ARMISelLowering.cpp revision 2f95461ee2edf896ef4a45dff40b9f20bcb31de3
1//===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "ARM.h" 16#include "ARMAddressingModes.h" 17#include "ARMConstantPoolValue.h" 18#include "ARMISelLowering.h" 19#include "ARMMachineFunctionInfo.h" 20#include "ARMRegisterInfo.h" 21#include "ARMSubtarget.h" 22#include "ARMTargetMachine.h" 23#include "llvm/CallingConv.h" 24#include "llvm/Constants.h" 25#include "llvm/Function.h" 26#include "llvm/Instruction.h" 27#include "llvm/Intrinsics.h" 28#include "llvm/GlobalValue.h" 29#include "llvm/CodeGen/CallingConvLower.h" 30#include "llvm/CodeGen/MachineBasicBlock.h" 31#include "llvm/CodeGen/MachineFrameInfo.h" 32#include "llvm/CodeGen/MachineFunction.h" 33#include "llvm/CodeGen/MachineInstrBuilder.h" 34#include "llvm/CodeGen/MachineRegisterInfo.h" 35#include "llvm/CodeGen/PseudoSourceValue.h" 36#include "llvm/CodeGen/SelectionDAG.h" 37#include "llvm/Target/TargetOptions.h" 38#include "llvm/ADT/VectorExtras.h" 39#include "llvm/Support/MathExtras.h" 40using namespace llvm; 41 42static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 43 CCValAssign::LocInfo &LocInfo, 44 ISD::ArgFlagsTy &ArgFlags, 45 CCState &State); 46static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 47 CCValAssign::LocInfo &LocInfo, 48 ISD::ArgFlagsTy &ArgFlags, 49 CCState &State); 50static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 51 CCValAssign::LocInfo &LocInfo, 52 ISD::ArgFlagsTy &ArgFlags, 53 CCState &State); 54static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 55 CCValAssign::LocInfo &LocInfo, 56 ISD::ArgFlagsTy &ArgFlags, 57 CCState &State); 58 59ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) 60 : TargetLowering(TM), ARMPCLabelIndex(0) { 61 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 62 63 if (Subtarget->isTargetDarwin()) { 64 // Uses VFP for Thumb libfuncs if available. 65 if (Subtarget->isThumb() && Subtarget->hasVFP2()) { 66 // Single-precision floating-point arithmetic. 67 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp"); 68 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp"); 69 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp"); 70 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp"); 71 72 // Double-precision floating-point arithmetic. 73 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp"); 74 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp"); 75 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp"); 76 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp"); 77 78 // Single-precision comparisons. 79 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp"); 80 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp"); 81 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp"); 82 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp"); 83 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp"); 84 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp"); 85 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp"); 86 setLibcallName(RTLIB::O_F32, "__unordsf2vfp"); 87 88 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 89 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE); 90 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 91 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 92 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 93 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 94 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 95 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 96 97 // Double-precision comparisons. 98 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp"); 99 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp"); 100 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp"); 101 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp"); 102 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp"); 103 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp"); 104 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp"); 105 setLibcallName(RTLIB::O_F64, "__unorddf2vfp"); 106 107 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 108 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE); 109 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 110 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 111 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 112 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 113 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 114 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 115 116 // Floating-point to integer conversions. 117 // i64 conversions are done via library routines even when generating VFP 118 // instructions, so use the same ones. 119 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp"); 120 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp"); 121 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp"); 122 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp"); 123 124 // Conversions between floating types. 125 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp"); 126 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp"); 127 128 // Integer to floating-point conversions. 129 // i64 conversions are done via library routines even when generating VFP 130 // instructions, so use the same ones. 131 // FIXME: There appears to be some naming inconsistency in ARM libgcc: 132 // e.g., __floatunsidf vs. __floatunssidfvfp. 133 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp"); 134 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp"); 135 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp"); 136 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp"); 137 } 138 } 139 140 // These libcalls are not available in 32-bit. 141 setLibcallName(RTLIB::SHL_I128, 0); 142 setLibcallName(RTLIB::SRL_I128, 0); 143 setLibcallName(RTLIB::SRA_I128, 0); 144 145 if (Subtarget->isThumb()) 146 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass); 147 else 148 addRegisterClass(MVT::i32, ARM::GPRRegisterClass); 149 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) { 150 addRegisterClass(MVT::f32, ARM::SPRRegisterClass); 151 addRegisterClass(MVT::f64, ARM::DPRRegisterClass); 152 153 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 154 } 155 computeRegisterProperties(); 156 157 // ARM does not have f32 extending load. 158 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 159 160 // ARM does not have i1 sign extending load. 161 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 162 163 // ARM supports all 4 flavors of integer indexed load / store. 164 for (unsigned im = (unsigned)ISD::PRE_INC; 165 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { 166 setIndexedLoadAction(im, MVT::i1, Legal); 167 setIndexedLoadAction(im, MVT::i8, Legal); 168 setIndexedLoadAction(im, MVT::i16, Legal); 169 setIndexedLoadAction(im, MVT::i32, Legal); 170 setIndexedStoreAction(im, MVT::i1, Legal); 171 setIndexedStoreAction(im, MVT::i8, Legal); 172 setIndexedStoreAction(im, MVT::i16, Legal); 173 setIndexedStoreAction(im, MVT::i32, Legal); 174 } 175 176 // i64 operation support. 177 if (Subtarget->isThumb()) { 178 setOperationAction(ISD::MUL, MVT::i64, Expand); 179 setOperationAction(ISD::MULHU, MVT::i32, Expand); 180 setOperationAction(ISD::MULHS, MVT::i32, Expand); 181 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 182 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 183 } else { 184 setOperationAction(ISD::MUL, MVT::i64, Expand); 185 setOperationAction(ISD::MULHU, MVT::i32, Expand); 186 if (!Subtarget->hasV6Ops()) 187 setOperationAction(ISD::MULHS, MVT::i32, Expand); 188 } 189 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 190 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 191 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 192 setOperationAction(ISD::SRL, MVT::i64, Custom); 193 setOperationAction(ISD::SRA, MVT::i64, Custom); 194 195 // ARM does not have ROTL. 196 setOperationAction(ISD::ROTL, MVT::i32, Expand); 197 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 198 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 199 if (!Subtarget->hasV5TOps() || Subtarget->isThumb()) 200 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 201 202 // Only ARMv6 has BSWAP. 203 if (!Subtarget->hasV6Ops()) 204 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 205 206 // These are expanded into libcalls. 207 setOperationAction(ISD::SDIV, MVT::i32, Expand); 208 setOperationAction(ISD::UDIV, MVT::i32, Expand); 209 setOperationAction(ISD::SREM, MVT::i32, Expand); 210 setOperationAction(ISD::UREM, MVT::i32, Expand); 211 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 212 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 213 214 // Support label based line numbers. 215 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); 216 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 217 218 setOperationAction(ISD::RET, MVT::Other, Custom); 219 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 220 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 221 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom); 222 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 223 224 // Use the default implementation. 225 setOperationAction(ISD::VASTART, MVT::Other, Custom); 226 setOperationAction(ISD::VAARG, MVT::Other, Expand); 227 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 228 setOperationAction(ISD::VAEND, MVT::Other, Expand); 229 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 230 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 231 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 232 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 233 234 if (!Subtarget->hasV6Ops()) { 235 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 236 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 237 } 238 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 239 240 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) 241 // Turn f64->i64 into FMRRD, i64 -> f64 to FMDRR iff target supports vfp2. 242 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom); 243 244 // We want to custom lower some of our intrinsics. 245 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 246 247 setOperationAction(ISD::SETCC, MVT::i32, Expand); 248 setOperationAction(ISD::SETCC, MVT::f32, Expand); 249 setOperationAction(ISD::SETCC, MVT::f64, Expand); 250 setOperationAction(ISD::SELECT, MVT::i32, Expand); 251 setOperationAction(ISD::SELECT, MVT::f32, Expand); 252 setOperationAction(ISD::SELECT, MVT::f64, Expand); 253 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 254 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 255 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 256 257 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 258 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 259 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 260 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 261 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 262 263 // We don't support sin/cos/fmod/copysign/pow 264 setOperationAction(ISD::FSIN, MVT::f64, Expand); 265 setOperationAction(ISD::FSIN, MVT::f32, Expand); 266 setOperationAction(ISD::FCOS, MVT::f32, Expand); 267 setOperationAction(ISD::FCOS, MVT::f64, Expand); 268 setOperationAction(ISD::FREM, MVT::f64, Expand); 269 setOperationAction(ISD::FREM, MVT::f32, Expand); 270 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) { 271 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 272 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 273 } 274 setOperationAction(ISD::FPOW, MVT::f64, Expand); 275 setOperationAction(ISD::FPOW, MVT::f32, Expand); 276 277 // int <-> fp are custom expanded into bit_convert + ARMISD ops. 278 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) { 279 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 280 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 281 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 282 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 283 } 284 285 // We have target-specific dag combine patterns for the following nodes: 286 // ARMISD::FMRRD - No need to call setTargetDAGCombine 287 setTargetDAGCombine(ISD::ADD); 288 setTargetDAGCombine(ISD::SUB); 289 290 setStackPointerRegisterToSaveRestore(ARM::SP); 291 setSchedulingPreference(SchedulingForRegPressure); 292 setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10); 293 setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2); 294 295 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type 296 // Do not enable CodePlacementOpt for now: it currently runs after the 297 // ARMConstantIslandPass and messes up branch relaxation and placement 298 // of constant islands. 299 // benefitFromCodePlacementOpt = true; 300} 301 302const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { 303 switch (Opcode) { 304 default: return 0; 305 case ARMISD::Wrapper: return "ARMISD::Wrapper"; 306 case ARMISD::WrapperJT: return "ARMISD::WrapperJT"; 307 case ARMISD::CALL: return "ARMISD::CALL"; 308 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED"; 309 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK"; 310 case ARMISD::tCALL: return "ARMISD::tCALL"; 311 case ARMISD::BRCOND: return "ARMISD::BRCOND"; 312 case ARMISD::BR_JT: return "ARMISD::BR_JT"; 313 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; 314 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD"; 315 case ARMISD::CMP: return "ARMISD::CMP"; 316 case ARMISD::CMPNZ: return "ARMISD::CMPNZ"; 317 case ARMISD::CMPFP: return "ARMISD::CMPFP"; 318 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0"; 319 case ARMISD::FMSTAT: return "ARMISD::FMSTAT"; 320 case ARMISD::CMOV: return "ARMISD::CMOV"; 321 case ARMISD::CNEG: return "ARMISD::CNEG"; 322 323 case ARMISD::FTOSI: return "ARMISD::FTOSI"; 324 case ARMISD::FTOUI: return "ARMISD::FTOUI"; 325 case ARMISD::SITOF: return "ARMISD::SITOF"; 326 case ARMISD::UITOF: return "ARMISD::UITOF"; 327 328 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG"; 329 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG"; 330 case ARMISD::RRX: return "ARMISD::RRX"; 331 332 case ARMISD::FMRRD: return "ARMISD::FMRRD"; 333 case ARMISD::FMDRR: return "ARMISD::FMDRR"; 334 335 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER"; 336 } 337} 338 339//===----------------------------------------------------------------------===// 340// Lowering Code 341//===----------------------------------------------------------------------===// 342 343/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC 344static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { 345 switch (CC) { 346 default: assert(0 && "Unknown condition code!"); 347 case ISD::SETNE: return ARMCC::NE; 348 case ISD::SETEQ: return ARMCC::EQ; 349 case ISD::SETGT: return ARMCC::GT; 350 case ISD::SETGE: return ARMCC::GE; 351 case ISD::SETLT: return ARMCC::LT; 352 case ISD::SETLE: return ARMCC::LE; 353 case ISD::SETUGT: return ARMCC::HI; 354 case ISD::SETUGE: return ARMCC::HS; 355 case ISD::SETULT: return ARMCC::LO; 356 case ISD::SETULE: return ARMCC::LS; 357 } 358} 359 360/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It 361/// returns true if the operands should be inverted to form the proper 362/// comparison. 363static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, 364 ARMCC::CondCodes &CondCode2) { 365 bool Invert = false; 366 CondCode2 = ARMCC::AL; 367 switch (CC) { 368 default: assert(0 && "Unknown FP condition!"); 369 case ISD::SETEQ: 370 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; 371 case ISD::SETGT: 372 case ISD::SETOGT: CondCode = ARMCC::GT; break; 373 case ISD::SETGE: 374 case ISD::SETOGE: CondCode = ARMCC::GE; break; 375 case ISD::SETOLT: CondCode = ARMCC::MI; break; 376 case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break; 377 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break; 378 case ISD::SETO: CondCode = ARMCC::VC; break; 379 case ISD::SETUO: CondCode = ARMCC::VS; break; 380 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break; 381 case ISD::SETUGT: CondCode = ARMCC::HI; break; 382 case ISD::SETUGE: CondCode = ARMCC::PL; break; 383 case ISD::SETLT: 384 case ISD::SETULT: CondCode = ARMCC::LT; break; 385 case ISD::SETLE: 386 case ISD::SETULE: CondCode = ARMCC::LE; break; 387 case ISD::SETNE: 388 case ISD::SETUNE: CondCode = ARMCC::NE; break; 389 } 390 return Invert; 391} 392 393//===----------------------------------------------------------------------===// 394// Calling Convention Implementation 395// 396// The lower operations present on calling convention works on this order: 397// LowerCALL (virt regs --> phys regs, virt regs --> stack) 398// LowerFORMAL_ARGUMENTS (phys --> virt regs, stack --> virt regs) 399// LowerRET (virt regs --> phys regs) 400// LowerCALL (phys regs --> virt regs) 401// 402//===----------------------------------------------------------------------===// 403 404#include "ARMGenCallingConv.inc" 405 406// APCS f64 is in register pairs, possibly split to stack 407static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 408 CCValAssign::LocInfo &LocInfo, 409 ISD::ArgFlagsTy &ArgFlags, 410 CCState &State) { 411 static const unsigned HiRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; 412 static const unsigned LoRegList[] = { ARM::R1, 413 ARM::R2, 414 ARM::R3, 415 ARM::NoRegister }; 416 417 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 4); 418 if (Reg == 0) 419 return false; // we didn't handle it 420 421 unsigned i; 422 for (i = 0; i < 4; ++i) 423 if (HiRegList[i] == Reg) 424 break; 425 426 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, MVT::i32, LocInfo)); 427 if (LoRegList[i] != ARM::NoRegister) 428 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], 429 MVT::i32, LocInfo)); 430 else 431 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 432 State.AllocateStack(4, 4), 433 MVT::i32, LocInfo)); 434 return true; // we handled it 435} 436 437// AAPCS f64 is in aligned register pairs 438static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 439 CCValAssign::LocInfo &LocInfo, 440 ISD::ArgFlagsTy &ArgFlags, 441 CCState &State) { 442 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; 443 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 }; 444 445 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2); 446 if (Reg == 0) 447 return false; // we didn't handle it 448 449 unsigned i; 450 for (i = 0; i < 2; ++i) 451 if (HiRegList[i] == Reg) 452 break; 453 454 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, MVT::i32, LocInfo)); 455 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], 456 MVT::i32, LocInfo)); 457 return true; // we handled it 458} 459 460static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 461 CCValAssign::LocInfo &LocInfo, 462 ISD::ArgFlagsTy &ArgFlags, 463 CCState &State) { 464 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; 465 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 }; 466 467 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2); 468 if (Reg == 0) 469 return false; // we didn't handle it 470 471 unsigned i; 472 for (i = 0; i < 2; ++i) 473 if (HiRegList[i] == Reg) 474 break; 475 476 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, MVT::i32, LocInfo)); 477 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i], 478 MVT::i32, LocInfo)); 479 return true; // we handled it 480} 481 482static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, 483 CCValAssign::LocInfo &LocInfo, 484 ISD::ArgFlagsTy &ArgFlags, 485 CCState &State) { 486 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, 487 State); 488} 489 490/// LowerCallResult - Lower the result values of an ISD::CALL into the 491/// appropriate copies out of appropriate physical registers. This assumes that 492/// Chain/InFlag are the input chain/flag to use, and that TheCall is the call 493/// being lowered. The returns a SDNode with the same number of values as the 494/// ISD::CALL. 495SDNode *ARMTargetLowering:: 496LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall, 497 unsigned CallingConv, SelectionDAG &DAG) { 498 499 DebugLoc dl = TheCall->getDebugLoc(); 500 // Assign locations to each value returned by this call. 501 SmallVector<CCValAssign, 16> RVLocs; 502 bool isVarArg = TheCall->isVarArg(); 503 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs); 504 CCInfo.AnalyzeCallResult(TheCall, RetCC_ARM); 505 506 SmallVector<SDValue, 8> ResultVals; 507 508 // Copy all of the result registers out of their specified physreg. 509 for (unsigned i = 0; i != RVLocs.size(); ++i) { 510 CCValAssign VA = RVLocs[i]; 511 512 SDValue Val; 513 if (VA.needsCustom()) { 514 // Handle f64 as custom. 515 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 516 InFlag); 517 Chain = Lo.getValue(1); 518 InFlag = Lo.getValue(2); 519 VA = RVLocs[++i]; // skip ahead to next loc 520 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 521 InFlag); 522 Chain = Hi.getValue(1); 523 InFlag = Hi.getValue(2); 524 Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi); 525 } else { 526 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), 527 InFlag); 528 Chain = Val.getValue(1); 529 InFlag = Val.getValue(2); 530 } 531 532 switch (VA.getLocInfo()) { 533 default: assert(0 && "Unknown loc info!"); 534 case CCValAssign::Full: break; 535 case CCValAssign::BCvt: 536 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val); 537 break; 538 } 539 540 ResultVals.push_back(Val); 541 } 542 543 // Merge everything together with a MERGE_VALUES node. 544 ResultVals.push_back(Chain); 545 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(), 546 &ResultVals[0], ResultVals.size()).getNode(); 547} 548 549/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 550/// by "Src" to address "Dst" of size "Size". Alignment information is 551/// specified by the specific parameter attribute. The copy will be passed as 552/// a byval function parameter. 553/// Sometimes what we are copying is the end of a larger object, the part that 554/// does not fit in registers. 555static SDValue 556CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 557 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 558 DebugLoc dl) { 559 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 560 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 561 /*AlwaysInline=*/false, NULL, 0, NULL, 0); 562} 563 564/// LowerMemOpCallTo - Store the argument to the stack. 565SDValue 566ARMTargetLowering::LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG, 567 const SDValue &StackPtr, 568 const CCValAssign &VA, SDValue Chain, 569 SDValue Arg, ISD::ArgFlagsTy Flags) { 570 DebugLoc dl = TheCall->getDebugLoc(); 571 unsigned LocMemOffset = VA.getLocMemOffset(); 572 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 573 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 574 if (Flags.isByVal()) { 575 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 576 } 577 return DAG.getStore(Chain, dl, Arg, PtrOff, 578 PseudoSourceValue::getStack(), LocMemOffset); 579} 580 581/// LowerCALL - Lowering a ISD::CALL node into a callseq_start <- 582/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter 583/// nodes. 584SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { 585 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode()); 586 MVT RetVT = TheCall->getRetValType(0); 587 SDValue Chain = TheCall->getChain(); 588 unsigned CC = TheCall->getCallingConv(); 589 assert((CC == CallingConv::C || 590 CC == CallingConv::Fast) && "unknown calling convention"); 591 bool isVarArg = TheCall->isVarArg(); 592 SDValue Callee = TheCall->getCallee(); 593 DebugLoc dl = TheCall->getDebugLoc(); 594 595 // Analyze operands of the call, assigning locations to each operand. 596 SmallVector<CCValAssign, 16> ArgLocs; 597 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs); 598 CCInfo.AnalyzeCallOperands(TheCall, CC_ARM); 599 600 // Get a count of how many bytes are to be pushed on the stack. 601 unsigned NumBytes = CCInfo.getNextStackOffset(); 602 603 // Adjust the stack pointer for the new arguments... 604 // These operations are automatically eliminated by the prolog/epilog pass 605 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 606 607 SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32); 608 609 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 610 SmallVector<SDValue, 8> MemOpChains; 611 612 // Walk the register/memloc assignments, inserting copies/loads. In the case 613 // of tail call optimization, arguments are handled later. 614 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); 615 i != e; 616 ++i, ++realArgIdx) { 617 CCValAssign &VA = ArgLocs[i]; 618 SDValue Arg = TheCall->getArg(realArgIdx); 619 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(realArgIdx); 620 621 // Promote the value if needed. 622 switch (VA.getLocInfo()) { 623 default: assert(0 && "Unknown loc info!"); 624 case CCValAssign::Full: break; 625 case CCValAssign::SExt: 626 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 627 break; 628 case CCValAssign::ZExt: 629 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 630 break; 631 case CCValAssign::AExt: 632 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 633 break; 634 case CCValAssign::BCvt: 635 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg); 636 break; 637 } 638 639 // f64 is passed in i32 pairs and must be combined 640 if (VA.needsCustom()) { 641 SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl, 642 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1); 643 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd)); 644 VA = ArgLocs[++i]; // skip ahead to next loc 645 if (VA.isRegLoc()) 646 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(1))); 647 else { 648 assert(VA.isMemLoc()); 649 if (StackPtr.getNode() == 0) 650 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); 651 652 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA, 653 Chain, fmrrd.getValue(1), 654 Flags)); 655 } 656 } else if (VA.isRegLoc()) { 657 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 658 } else { 659 assert(VA.isMemLoc()); 660 if (StackPtr.getNode() == 0) 661 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); 662 663 MemOpChains.push_back(LowerMemOpCallTo(TheCall, DAG, StackPtr, VA, 664 Chain, Arg, Flags)); 665 } 666 } 667 668 if (!MemOpChains.empty()) 669 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 670 &MemOpChains[0], MemOpChains.size()); 671 672 // Build a sequence of copy-to-reg nodes chained together with token chain 673 // and flag operands which copy the outgoing args into the appropriate regs. 674 SDValue InFlag; 675 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 676 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 677 RegsToPass[i].second, InFlag); 678 InFlag = Chain.getValue(1); 679 } 680 681 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 682 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 683 // node so that legalize doesn't hack it. 684 bool isDirect = false; 685 bool isARMFunc = false; 686 bool isLocalARMFunc = false; 687 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 688 GlobalValue *GV = G->getGlobal(); 689 isDirect = true; 690 bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() || 691 GV->hasLinkOnceLinkage()); 692 bool isStub = (isExt && Subtarget->isTargetDarwin()) && 693 getTargetMachine().getRelocationModel() != Reloc::Static; 694 isARMFunc = !Subtarget->isThumb() || isStub; 695 // ARM call to a local ARM function is predicable. 696 isLocalARMFunc = !Subtarget->isThumb() && !isExt; 697 // tBX takes a register source operand. 698 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) { 699 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex, 700 ARMCP::CPStub, 4); 701 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 702 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 703 Callee = DAG.getLoad(getPointerTy(), dl, 704 DAG.getEntryNode(), CPAddr, NULL, 0); 705 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 706 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, 707 getPointerTy(), Callee, PICLabel); 708 } else 709 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy()); 710 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 711 isDirect = true; 712 bool isStub = Subtarget->isTargetDarwin() && 713 getTargetMachine().getRelocationModel() != Reloc::Static; 714 isARMFunc = !Subtarget->isThumb() || isStub; 715 // tBX takes a register source operand. 716 const char *Sym = S->getSymbol(); 717 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) { 718 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex, 719 ARMCP::CPStub, 4); 720 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 721 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 722 Callee = DAG.getLoad(getPointerTy(), dl, 723 DAG.getEntryNode(), CPAddr, NULL, 0); 724 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 725 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, 726 getPointerTy(), Callee, PICLabel); 727 } else 728 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy()); 729 } 730 731 // FIXME: handle tail calls differently. 732 unsigned CallOpc; 733 if (Subtarget->isThumb()) { 734 if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc)) 735 CallOpc = ARMISD::CALL_NOLINK; 736 else 737 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL; 738 } else { 739 CallOpc = (isDirect || Subtarget->hasV5TOps()) 740 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL) 741 : ARMISD::CALL_NOLINK; 742 } 743 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) { 744 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK 745 Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag); 746 InFlag = Chain.getValue(1); 747 } 748 749 std::vector<SDValue> Ops; 750 Ops.push_back(Chain); 751 Ops.push_back(Callee); 752 753 // Add argument registers to the end of the list so that they are known live 754 // into the call. 755 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 756 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 757 RegsToPass[i].second.getValueType())); 758 759 if (InFlag.getNode()) 760 Ops.push_back(InFlag); 761 // Returns a chain and a flag for retval copy to use. 762 Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag), 763 &Ops[0], Ops.size()); 764 InFlag = Chain.getValue(1); 765 766 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 767 DAG.getIntPtrConstant(0, true), InFlag); 768 if (RetVT != MVT::Other) 769 InFlag = Chain.getValue(1); 770 771 // Handle result values, copying them out of physregs into vregs that we 772 // return. 773 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG), 774 Op.getResNo()); 775} 776 777SDValue ARMTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) { 778 // The chain is always operand #0 779 SDValue Chain = Op.getOperand(0); 780 DebugLoc dl = Op.getDebugLoc(); 781 782 // CCValAssign - represent the assignment of the return value to a location. 783 SmallVector<CCValAssign, 16> RVLocs; 784 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv(); 785 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 786 787 // CCState - Info about the registers and stack slots. 788 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs); 789 790 // Analyze return values of ISD::RET. 791 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_ARM); 792 793 // If this is the first return lowered for this function, add 794 // the regs to the liveout set for the function. 795 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 796 for (unsigned i = 0; i != RVLocs.size(); ++i) 797 if (RVLocs[i].isRegLoc()) 798 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 799 } 800 801 SDValue Flag; 802 803 // Copy the result values into the output registers. 804 for (unsigned i = 0, realRVLocIdx = 0; 805 i != RVLocs.size(); 806 ++i, ++realRVLocIdx) { 807 CCValAssign &VA = RVLocs[i]; 808 assert(VA.isRegLoc() && "Can only return in registers!"); 809 810 // ISD::RET => ret chain, (regnum1,val1), ... 811 // So i*2+1 index only the regnums 812 SDValue Arg = Op.getOperand(realRVLocIdx*2+1); 813 814 switch (VA.getLocInfo()) { 815 default: assert(0 && "Unknown loc info!"); 816 case CCValAssign::Full: break; 817 case CCValAssign::BCvt: 818 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg); 819 break; 820 } 821 822 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is 823 // available. 824 if (VA.needsCustom()) { 825 SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl, 826 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1); 827 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag); 828 Flag = Chain.getValue(1); 829 VA = RVLocs[++i]; // skip ahead to next loc 830 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1), 831 Flag); 832 } else 833 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); 834 835 // Guarantee that all emitted copies are 836 // stuck together, avoiding something bad. 837 Flag = Chain.getValue(1); 838 } 839 840 SDValue result; 841 if (Flag.getNode()) 842 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 843 else // Return Void 844 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain); 845 846 return result; 847} 848 849// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 850// their target countpart wrapped in the ARMISD::Wrapper node. Suppose N is 851// one of the above mentioned nodes. It has to be wrapped because otherwise 852// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 853// be used to form addressing mode. These wrapped nodes will be selected 854// into MOVi. 855static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) { 856 MVT PtrVT = Op.getValueType(); 857 // FIXME there is no actual debug info here 858 DebugLoc dl = Op.getDebugLoc(); 859 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 860 SDValue Res; 861 if (CP->isMachineConstantPoolEntry()) 862 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, 863 CP->getAlignment()); 864 else 865 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, 866 CP->getAlignment()); 867 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res); 868} 869 870// Lower ISD::GlobalTLSAddress using the "general dynamic" model 871SDValue 872ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 873 SelectionDAG &DAG) { 874 DebugLoc dl = GA->getDebugLoc(); 875 MVT PtrVT = getPointerTy(); 876 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 877 ARMConstantPoolValue *CPV = 878 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue, 879 PCAdj, "tlsgd", true); 880 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4); 881 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument); 882 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, NULL, 0); 883 SDValue Chain = Argument.getValue(1); 884 885 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 886 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel); 887 888 // call __tls_get_addr. 889 ArgListTy Args; 890 ArgListEntry Entry; 891 Entry.Node = Argument; 892 Entry.Ty = (const Type *) Type::Int32Ty; 893 Args.push_back(Entry); 894 // FIXME: is there useful debug info available here? 895 std::pair<SDValue, SDValue> CallResult = 896 LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false, false, 897 CallingConv::C, false, 898 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl); 899 return CallResult.first; 900} 901 902// Lower ISD::GlobalTLSAddress using the "initial exec" or 903// "local exec" model. 904SDValue 905ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, 906 SelectionDAG &DAG) { 907 GlobalValue *GV = GA->getGlobal(); 908 DebugLoc dl = GA->getDebugLoc(); 909 SDValue Offset; 910 SDValue Chain = DAG.getEntryNode(); 911 MVT PtrVT = getPointerTy(); 912 // Get the Thread Pointer 913 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); 914 915 if (GV->isDeclaration()){ 916 // initial exec model 917 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 918 ARMConstantPoolValue *CPV = 919 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue, 920 PCAdj, "gottpoff", true); 921 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); 922 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); 923 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0); 924 Chain = Offset.getValue(1); 925 926 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 927 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel); 928 929 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0); 930 } else { 931 // local exec model 932 ARMConstantPoolValue *CPV = 933 new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff"); 934 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); 935 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); 936 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0); 937 } 938 939 // The address of the thread local variable is the add of the thread 940 // pointer with the offset of the variable. 941 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 942} 943 944SDValue 945ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { 946 // TODO: implement the "local dynamic" model 947 assert(Subtarget->isTargetELF() && 948 "TLS not implemented for non-ELF targets"); 949 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 950 // If the relocation model is PIC, use the "General Dynamic" TLS Model, 951 // otherwise use the "Local Exec" TLS Model 952 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) 953 return LowerToTLSGeneralDynamicModel(GA, DAG); 954 else 955 return LowerToTLSExecModels(GA, DAG); 956} 957 958SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, 959 SelectionDAG &DAG) { 960 MVT PtrVT = getPointerTy(); 961 DebugLoc dl = Op.getDebugLoc(); 962 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 963 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 964 if (RelocM == Reloc::PIC_) { 965 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility(); 966 ARMConstantPoolValue *CPV = 967 new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT"); 968 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 969 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 970 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 971 CPAddr, NULL, 0); 972 SDValue Chain = Result.getValue(1); 973 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT); 974 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT); 975 if (!UseGOTOFF) 976 Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0); 977 return Result; 978 } else { 979 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); 980 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 981 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0); 982 } 983} 984 985/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol 986/// even in non-static mode. 987static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) { 988 // If symbol visibility is hidden, the extra load is not needed if 989 // the symbol is definitely defined in the current translation unit. 990 bool isDecl = GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode(); 991 if (GV->hasHiddenVisibility() && (!isDecl && !GV->hasCommonLinkage())) 992 return false; 993 return RelocM != Reloc::Static && (isDecl || GV->isWeakForLinker()); 994} 995 996SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op, 997 SelectionDAG &DAG) { 998 MVT PtrVT = getPointerTy(); 999 DebugLoc dl = Op.getDebugLoc(); 1000 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1001 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 1002 bool IsIndirect = GVIsIndirectSymbol(GV, RelocM); 1003 SDValue CPAddr; 1004 if (RelocM == Reloc::Static) 1005 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); 1006 else { 1007 unsigned PCAdj = (RelocM != Reloc::PIC_) 1008 ? 0 : (Subtarget->isThumb() ? 4 : 8); 1009 ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr 1010 : ARMCP::CPValue; 1011 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex, 1012 Kind, PCAdj); 1013 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1014 } 1015 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1016 1017 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0); 1018 SDValue Chain = Result.getValue(1); 1019 1020 if (RelocM == Reloc::PIC_) { 1021 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 1022 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 1023 } 1024 if (IsIndirect) 1025 Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0); 1026 1027 return Result; 1028} 1029 1030SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, 1031 SelectionDAG &DAG){ 1032 assert(Subtarget->isTargetELF() && 1033 "GLOBAL OFFSET TABLE not implemented for non-ELF targets"); 1034 MVT PtrVT = getPointerTy(); 1035 DebugLoc dl = Op.getDebugLoc(); 1036 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 1037 ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_", 1038 ARMPCLabelIndex, 1039 ARMCP::CPValue, PCAdj); 1040 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1041 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1042 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0); 1043 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 1044 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 1045} 1046 1047SDValue 1048ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { 1049 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1050 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 1051 DebugLoc dl = Op.getDebugLoc(); 1052 switch (IntNo) { 1053 default: return SDValue(); // Don't custom lower most intrinsics. 1054 case Intrinsic::arm_thread_pointer: 1055 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); 1056 case Intrinsic::eh_sjlj_setjmp: 1057 SDValue Res = DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, 1058 Op.getOperand(1)); 1059 return Res; 1060 } 1061} 1062 1063static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 1064 unsigned VarArgsFrameIndex) { 1065 // vastart just stores the address of the VarArgsFrameIndex slot into the 1066 // memory location argument. 1067 DebugLoc dl = Op.getDebugLoc(); 1068 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1069 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 1070 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1071 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0); 1072} 1073 1074SDValue 1075ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) { 1076 MachineFunction &MF = DAG.getMachineFunction(); 1077 MachineFrameInfo *MFI = MF.getFrameInfo(); 1078 1079 SDValue Root = Op.getOperand(0); 1080 DebugLoc dl = Op.getDebugLoc(); 1081 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0; 1082 unsigned CC = MF.getFunction()->getCallingConv(); 1083 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1084 1085 // Assign locations to all of the incoming arguments. 1086 SmallVector<CCValAssign, 16> ArgLocs; 1087 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs); 1088 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_ARM); 1089 1090 SmallVector<SDValue, 16> ArgValues; 1091 1092 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1093 CCValAssign &VA = ArgLocs[i]; 1094 1095 // Arguments stored in registers. 1096 if (VA.isRegLoc()) { 1097 MVT RegVT = VA.getLocVT(); 1098 TargetRegisterClass *RC; 1099 if (AFI->isThumbFunction()) 1100 RC = ARM::tGPRRegisterClass; 1101 else 1102 RC = ARM::GPRRegisterClass; 1103 1104 if (RegVT == MVT::f64) { 1105 // f64 is passed in pairs of GPRs and must be combined. 1106 RegVT = MVT::i32; 1107 } else if (!((RegVT == MVT::i32) || (RegVT == MVT::f32))) 1108 assert(0 && "RegVT not supported by FORMAL_ARGUMENTS Lowering"); 1109 1110 // Transform the arguments stored in physical registers into virtual ones. 1111 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1112 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT); 1113 1114 // f64 is passed in i32 pairs and must be combined. 1115 if (VA.needsCustom()) { 1116 SDValue ArgValue2; 1117 1118 VA = ArgLocs[++i]; // skip ahead to next loc 1119 if (VA.isMemLoc()) { 1120 // must be APCS to split like this 1121 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8; 1122 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset()); 1123 1124 // Create load node to retrieve arguments from the stack. 1125 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1126 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0); 1127 } else { 1128 Reg = MF.addLiveIn(VA.getLocReg(), RC); 1129 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); 1130 } 1131 1132 ArgValue = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, 1133 ArgValue, ArgValue2); 1134 } 1135 1136 // If this is an 8 or 16-bit value, it is really passed promoted 1137 // to 32 bits. Insert an assert[sz]ext to capture this, then 1138 // truncate to the right size. 1139 switch (VA.getLocInfo()) { 1140 default: assert(0 && "Unknown loc info!"); 1141 case CCValAssign::Full: break; 1142 case CCValAssign::BCvt: 1143 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); 1144 break; 1145 case CCValAssign::SExt: 1146 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1147 DAG.getValueType(VA.getValVT())); 1148 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1149 break; 1150 case CCValAssign::ZExt: 1151 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1152 DAG.getValueType(VA.getValVT())); 1153 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1154 break; 1155 } 1156 1157 ArgValues.push_back(ArgValue); 1158 1159 } else { // VA.isRegLoc() 1160 1161 // sanity check 1162 assert(VA.isMemLoc()); 1163 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered"); 1164 1165 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8; 1166 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset()); 1167 1168 // Create load nodes to retrieve arguments from the stack. 1169 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1170 ArgValues.push_back(DAG.getLoad(VA.getValVT(), dl, Root, FIN, NULL, 0)); 1171 } 1172 } 1173 1174 // varargs 1175 if (isVarArg) { 1176 static const unsigned GPRArgRegs[] = { 1177 ARM::R0, ARM::R1, ARM::R2, ARM::R3 1178 }; 1179 1180 unsigned NumGPRs = CCInfo.getFirstUnallocated 1181 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0])); 1182 1183 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 1184 unsigned VARegSize = (4 - NumGPRs) * 4; 1185 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1); 1186 unsigned ArgOffset = 0; 1187 if (VARegSaveSize) { 1188 // If this function is vararg, store any remaining integer argument regs 1189 // to their spots on the stack so that they may be loaded by deferencing 1190 // the result of va_next. 1191 AFI->setVarArgsRegSaveSize(VARegSaveSize); 1192 ArgOffset = CCInfo.getNextStackOffset(); 1193 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset + 1194 VARegSaveSize - VARegSize); 1195 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 1196 1197 SmallVector<SDValue, 4> MemOps; 1198 for (; NumGPRs < 4; ++NumGPRs) { 1199 TargetRegisterClass *RC; 1200 if (AFI->isThumbFunction()) 1201 RC = ARM::tGPRRegisterClass; 1202 else 1203 RC = ARM::GPRRegisterClass; 1204 1205 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC); 1206 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32); 1207 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0); 1208 MemOps.push_back(Store); 1209 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN, 1210 DAG.getConstant(4, getPointerTy())); 1211 } 1212 if (!MemOps.empty()) 1213 Root = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1214 &MemOps[0], MemOps.size()); 1215 } else 1216 // This will point to the next argument passed via stack. 1217 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset); 1218 } 1219 1220 ArgValues.push_back(Root); 1221 1222 // Return the new list of results. 1223 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(), 1224 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo()); 1225} 1226 1227/// isFloatingPointZero - Return true if this is +0.0. 1228static bool isFloatingPointZero(SDValue Op) { 1229 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 1230 return CFP->getValueAPF().isPosZero(); 1231 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 1232 // Maybe this has already been legalized into the constant pool? 1233 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) { 1234 SDValue WrapperOp = Op.getOperand(1).getOperand(0); 1235 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp)) 1236 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 1237 return CFP->getValueAPF().isPosZero(); 1238 } 1239 } 1240 return false; 1241} 1242 1243static bool isLegalCmpImmediate(unsigned C, bool isThumb) { 1244 return ( isThumb && (C & ~255U) == 0) || 1245 (!isThumb && ARM_AM::getSOImmVal(C) != -1); 1246} 1247 1248/// Returns appropriate ARM CMP (cmp) and corresponding condition code for 1249/// the given operands. 1250static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 1251 SDValue &ARMCC, SelectionDAG &DAG, bool isThumb, 1252 DebugLoc dl) { 1253 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) { 1254 unsigned C = RHSC->getZExtValue(); 1255 if (!isLegalCmpImmediate(C, isThumb)) { 1256 // Constant does not fit, try adjusting it by one? 1257 switch (CC) { 1258 default: break; 1259 case ISD::SETLT: 1260 case ISD::SETGE: 1261 if (isLegalCmpImmediate(C-1, isThumb)) { 1262 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 1263 RHS = DAG.getConstant(C-1, MVT::i32); 1264 } 1265 break; 1266 case ISD::SETULT: 1267 case ISD::SETUGE: 1268 if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) { 1269 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 1270 RHS = DAG.getConstant(C-1, MVT::i32); 1271 } 1272 break; 1273 case ISD::SETLE: 1274 case ISD::SETGT: 1275 if (isLegalCmpImmediate(C+1, isThumb)) { 1276 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; 1277 RHS = DAG.getConstant(C+1, MVT::i32); 1278 } 1279 break; 1280 case ISD::SETULE: 1281 case ISD::SETUGT: 1282 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb)) { 1283 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 1284 RHS = DAG.getConstant(C+1, MVT::i32); 1285 } 1286 break; 1287 } 1288 } 1289 } 1290 1291 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 1292 ARMISD::NodeType CompareType; 1293 switch (CondCode) { 1294 default: 1295 CompareType = ARMISD::CMP; 1296 break; 1297 case ARMCC::EQ: 1298 case ARMCC::NE: 1299 case ARMCC::MI: 1300 case ARMCC::PL: 1301 // Uses only N and Z Flags 1302 CompareType = ARMISD::CMPNZ; 1303 break; 1304 } 1305 ARMCC = DAG.getConstant(CondCode, MVT::i32); 1306 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS); 1307} 1308 1309/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands. 1310static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, 1311 DebugLoc dl) { 1312 SDValue Cmp; 1313 if (!isFloatingPointZero(RHS)) 1314 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS); 1315 else 1316 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS); 1317 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp); 1318} 1319 1320static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, 1321 const ARMSubtarget *ST) { 1322 MVT VT = Op.getValueType(); 1323 SDValue LHS = Op.getOperand(0); 1324 SDValue RHS = Op.getOperand(1); 1325 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 1326 SDValue TrueVal = Op.getOperand(2); 1327 SDValue FalseVal = Op.getOperand(3); 1328 DebugLoc dl = Op.getDebugLoc(); 1329 1330 if (LHS.getValueType() == MVT::i32) { 1331 SDValue ARMCC; 1332 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1333 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb(), dl); 1334 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp); 1335 } 1336 1337 ARMCC::CondCodes CondCode, CondCode2; 1338 if (FPCCToARMCC(CC, CondCode, CondCode2)) 1339 std::swap(TrueVal, FalseVal); 1340 1341 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32); 1342 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1343 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); 1344 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, 1345 ARMCC, CCR, Cmp); 1346 if (CondCode2 != ARMCC::AL) { 1347 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32); 1348 // FIXME: Needs another CMP because flag can have but one use. 1349 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl); 1350 Result = DAG.getNode(ARMISD::CMOV, dl, VT, 1351 Result, TrueVal, ARMCC2, CCR, Cmp2); 1352 } 1353 return Result; 1354} 1355 1356static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, 1357 const ARMSubtarget *ST) { 1358 SDValue Chain = Op.getOperand(0); 1359 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 1360 SDValue LHS = Op.getOperand(2); 1361 SDValue RHS = Op.getOperand(3); 1362 SDValue Dest = Op.getOperand(4); 1363 DebugLoc dl = Op.getDebugLoc(); 1364 1365 if (LHS.getValueType() == MVT::i32) { 1366 SDValue ARMCC; 1367 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1368 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb(), dl); 1369 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, 1370 Chain, Dest, ARMCC, CCR,Cmp); 1371 } 1372 1373 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); 1374 ARMCC::CondCodes CondCode, CondCode2; 1375 if (FPCCToARMCC(CC, CondCode, CondCode2)) 1376 // Swap the LHS/RHS of the comparison if needed. 1377 std::swap(LHS, RHS); 1378 1379 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); 1380 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32); 1381 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1382 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag); 1383 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp }; 1384 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); 1385 if (CondCode2 != ARMCC::AL) { 1386 ARMCC = DAG.getConstant(CondCode2, MVT::i32); 1387 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) }; 1388 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); 1389 } 1390 return Res; 1391} 1392 1393SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) { 1394 SDValue Chain = Op.getOperand(0); 1395 SDValue Table = Op.getOperand(1); 1396 SDValue Index = Op.getOperand(2); 1397 DebugLoc dl = Op.getDebugLoc(); 1398 1399 MVT PTy = getPointerTy(); 1400 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); 1401 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>(); 1402 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); 1403 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); 1404 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId); 1405 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy)); 1406 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 1407 bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1408 Addr = DAG.getLoad(isPIC ? (MVT)MVT::i32 : PTy, dl, 1409 Chain, Addr, NULL, 0); 1410 Chain = Addr.getValue(1); 1411 if (isPIC) 1412 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table); 1413 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); 1414} 1415 1416static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) { 1417 DebugLoc dl = Op.getDebugLoc(); 1418 unsigned Opc = 1419 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI; 1420 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0)); 1421 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); 1422} 1423 1424static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 1425 MVT VT = Op.getValueType(); 1426 DebugLoc dl = Op.getDebugLoc(); 1427 unsigned Opc = 1428 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF; 1429 1430 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0)); 1431 return DAG.getNode(Opc, dl, VT, Op); 1432} 1433 1434static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) { 1435 // Implement fcopysign with a fabs and a conditional fneg. 1436 SDValue Tmp0 = Op.getOperand(0); 1437 SDValue Tmp1 = Op.getOperand(1); 1438 DebugLoc dl = Op.getDebugLoc(); 1439 MVT VT = Op.getValueType(); 1440 MVT SrcVT = Tmp1.getValueType(); 1441 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0); 1442 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl); 1443 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32); 1444 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1445 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp); 1446} 1447 1448SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 1449 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1450 MFI->setFrameAddressIsTaken(true); 1451 MVT VT = Op.getValueType(); 1452 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 1453 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 1454 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->useThumbBacktraces()) 1455 ? ARM::R7 : ARM::R11; 1456 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 1457 while (Depth--) 1458 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0); 1459 return FrameAddr; 1460} 1461 1462SDValue 1463ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 1464 SDValue Chain, 1465 SDValue Dst, SDValue Src, 1466 SDValue Size, unsigned Align, 1467 bool AlwaysInline, 1468 const Value *DstSV, uint64_t DstSVOff, 1469 const Value *SrcSV, uint64_t SrcSVOff){ 1470 // Do repeated 4-byte loads and stores. To be improved. 1471 // This requires 4-byte alignment. 1472 if ((Align & 3) != 0) 1473 return SDValue(); 1474 // This requires the copy size to be a constant, preferrably 1475 // within a subtarget-specific limit. 1476 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 1477 if (!ConstantSize) 1478 return SDValue(); 1479 uint64_t SizeVal = ConstantSize->getZExtValue(); 1480 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold()) 1481 return SDValue(); 1482 1483 unsigned BytesLeft = SizeVal & 3; 1484 unsigned NumMemOps = SizeVal >> 2; 1485 unsigned EmittedNumMemOps = 0; 1486 MVT VT = MVT::i32; 1487 unsigned VTSize = 4; 1488 unsigned i = 0; 1489 const unsigned MAX_LOADS_IN_LDM = 6; 1490 SDValue TFOps[MAX_LOADS_IN_LDM]; 1491 SDValue Loads[MAX_LOADS_IN_LDM]; 1492 uint64_t SrcOff = 0, DstOff = 0; 1493 1494 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the 1495 // same number of stores. The loads and stores will get combined into 1496 // ldm/stm later on. 1497 while (EmittedNumMemOps < NumMemOps) { 1498 for (i = 0; 1499 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) { 1500 Loads[i] = DAG.getLoad(VT, dl, Chain, 1501 DAG.getNode(ISD::ADD, dl, MVT::i32, Src, 1502 DAG.getConstant(SrcOff, MVT::i32)), 1503 SrcSV, SrcSVOff + SrcOff); 1504 TFOps[i] = Loads[i].getValue(1); 1505 SrcOff += VTSize; 1506 } 1507 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); 1508 1509 for (i = 0; 1510 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) { 1511 TFOps[i] = DAG.getStore(Chain, dl, Loads[i], 1512 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, 1513 DAG.getConstant(DstOff, MVT::i32)), 1514 DstSV, DstSVOff + DstOff); 1515 DstOff += VTSize; 1516 } 1517 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); 1518 1519 EmittedNumMemOps += i; 1520 } 1521 1522 if (BytesLeft == 0) 1523 return Chain; 1524 1525 // Issue loads / stores for the trailing (1 - 3) bytes. 1526 unsigned BytesLeftSave = BytesLeft; 1527 i = 0; 1528 while (BytesLeft) { 1529 if (BytesLeft >= 2) { 1530 VT = MVT::i16; 1531 VTSize = 2; 1532 } else { 1533 VT = MVT::i8; 1534 VTSize = 1; 1535 } 1536 1537 Loads[i] = DAG.getLoad(VT, dl, Chain, 1538 DAG.getNode(ISD::ADD, dl, MVT::i32, Src, 1539 DAG.getConstant(SrcOff, MVT::i32)), 1540 SrcSV, SrcSVOff + SrcOff); 1541 TFOps[i] = Loads[i].getValue(1); 1542 ++i; 1543 SrcOff += VTSize; 1544 BytesLeft -= VTSize; 1545 } 1546 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); 1547 1548 i = 0; 1549 BytesLeft = BytesLeftSave; 1550 while (BytesLeft) { 1551 if (BytesLeft >= 2) { 1552 VT = MVT::i16; 1553 VTSize = 2; 1554 } else { 1555 VT = MVT::i8; 1556 VTSize = 1; 1557 } 1558 1559 TFOps[i] = DAG.getStore(Chain, dl, Loads[i], 1560 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, 1561 DAG.getConstant(DstOff, MVT::i32)), 1562 DstSV, DstSVOff + DstOff); 1563 ++i; 1564 DstOff += VTSize; 1565 BytesLeft -= VTSize; 1566 } 1567 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); 1568} 1569 1570static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) { 1571 SDValue Op = N->getOperand(0); 1572 DebugLoc dl = N->getDebugLoc(); 1573 if (N->getValueType(0) == MVT::f64) { 1574 // Turn i64->f64 into FMDRR. 1575 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, 1576 DAG.getConstant(0, MVT::i32)); 1577 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, 1578 DAG.getConstant(1, MVT::i32)); 1579 return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi); 1580 } 1581 1582 // Turn f64->i64 into FMRRD. 1583 SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl, 1584 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1); 1585 1586 // Merge the pieces into a single i64 value. 1587 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1)); 1588} 1589 1590static SDValue ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) { 1591 assert(N->getValueType(0) == MVT::i64 && 1592 (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && 1593 "Unknown shift to lower!"); 1594 1595 // We only lower SRA, SRL of 1 here, all others use generic lowering. 1596 if (!isa<ConstantSDNode>(N->getOperand(1)) || 1597 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1) 1598 return SDValue(); 1599 1600 // If we are in thumb mode, we don't have RRX. 1601 if (ST->isThumb()) return SDValue(); 1602 1603 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr. 1604 DebugLoc dl = N->getDebugLoc(); 1605 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), 1606 DAG.getConstant(0, MVT::i32)); 1607 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), 1608 DAG.getConstant(1, MVT::i32)); 1609 1610 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and 1611 // captures the result into a carry flag. 1612 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG; 1613 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1); 1614 1615 // The low part is an ARMISD::RRX operand, which shifts the carry in. 1616 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1)); 1617 1618 // Merge the pieces into a single i64 value. 1619 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 1620} 1621 1622SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 1623 switch (Op.getOpcode()) { 1624 default: assert(0 && "Don't know how to custom lower this!"); abort(); 1625 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 1626 case ISD::GlobalAddress: 1627 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) : 1628 LowerGlobalAddressELF(Op, DAG); 1629 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 1630 case ISD::CALL: return LowerCALL(Op, DAG); 1631 case ISD::RET: return LowerRET(Op, DAG); 1632 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget); 1633 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget); 1634 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 1635 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex); 1636 case ISD::SINT_TO_FP: 1637 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); 1638 case ISD::FP_TO_SINT: 1639 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG); 1640 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 1641 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG); 1642 case ISD::RETURNADDR: break; 1643 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 1644 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG); 1645 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 1646 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG); 1647 case ISD::SRL: 1648 case ISD::SRA: return ExpandSRx(Op.getNode(), DAG,Subtarget); 1649 } 1650 return SDValue(); 1651} 1652 1653/// ReplaceNodeResults - Replace the results of node with an illegal result 1654/// type with new values built out of custom code. 1655void ARMTargetLowering::ReplaceNodeResults(SDNode *N, 1656 SmallVectorImpl<SDValue>&Results, 1657 SelectionDAG &DAG) { 1658 switch (N->getOpcode()) { 1659 default: 1660 assert(0 && "Don't know how to custom expand this!"); 1661 return; 1662 case ISD::BIT_CONVERT: 1663 Results.push_back(ExpandBIT_CONVERT(N, DAG)); 1664 return; 1665 case ISD::SRL: 1666 case ISD::SRA: { 1667 SDValue Res = ExpandSRx(N, DAG, Subtarget); 1668 if (Res.getNode()) 1669 Results.push_back(Res); 1670 return; 1671 } 1672 } 1673} 1674 1675//===----------------------------------------------------------------------===// 1676// ARM Scheduler Hooks 1677//===----------------------------------------------------------------------===// 1678 1679MachineBasicBlock * 1680ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1681 MachineBasicBlock *BB) const { 1682 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1683 DebugLoc dl = MI->getDebugLoc(); 1684 switch (MI->getOpcode()) { 1685 default: assert(false && "Unexpected instr type to insert"); 1686 case ARM::tMOVCCr: { 1687 // To "insert" a SELECT_CC instruction, we actually have to insert the 1688 // diamond control-flow pattern. The incoming instruction knows the 1689 // destination vreg to set, the condition code register to branch on, the 1690 // true/false values to select between, and a branch opcode to use. 1691 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1692 MachineFunction::iterator It = BB; 1693 ++It; 1694 1695 // thisMBB: 1696 // ... 1697 // TrueVal = ... 1698 // cmpTY ccX, r1, r2 1699 // bCC copy1MBB 1700 // fallthrough --> copy0MBB 1701 MachineBasicBlock *thisMBB = BB; 1702 MachineFunction *F = BB->getParent(); 1703 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1704 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 1705 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB) 1706 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg()); 1707 F->insert(It, copy0MBB); 1708 F->insert(It, sinkMBB); 1709 // Update machine-CFG edges by first adding all successors of the current 1710 // block to the new block which will contain the Phi node for the select. 1711 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 1712 e = BB->succ_end(); i != e; ++i) 1713 sinkMBB->addSuccessor(*i); 1714 // Next, remove all successors of the current block, and add the true 1715 // and fallthrough blocks as its successors. 1716 while(!BB->succ_empty()) 1717 BB->removeSuccessor(BB->succ_begin()); 1718 BB->addSuccessor(copy0MBB); 1719 BB->addSuccessor(sinkMBB); 1720 1721 // copy0MBB: 1722 // %FalseValue = ... 1723 // # fallthrough to sinkMBB 1724 BB = copy0MBB; 1725 1726 // Update machine-CFG edges 1727 BB->addSuccessor(sinkMBB); 1728 1729 // sinkMBB: 1730 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1731 // ... 1732 BB = sinkMBB; 1733 BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg()) 1734 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 1735 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 1736 1737 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 1738 return BB; 1739 } 1740 } 1741} 1742 1743//===----------------------------------------------------------------------===// 1744// ARM Optimization Hooks 1745//===----------------------------------------------------------------------===// 1746 1747static 1748SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, 1749 TargetLowering::DAGCombinerInfo &DCI) { 1750 SelectionDAG &DAG = DCI.DAG; 1751 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 1752 MVT VT = N->getValueType(0); 1753 unsigned Opc = N->getOpcode(); 1754 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 1755 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 1756 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 1757 ISD::CondCode CC = ISD::SETCC_INVALID; 1758 1759 if (isSlctCC) { 1760 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 1761 } else { 1762 SDValue CCOp = Slct.getOperand(0); 1763 if (CCOp.getOpcode() == ISD::SETCC) 1764 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 1765 } 1766 1767 bool DoXform = false; 1768 bool InvCC = false; 1769 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 1770 "Bad input!"); 1771 1772 if (LHS.getOpcode() == ISD::Constant && 1773 cast<ConstantSDNode>(LHS)->isNullValue()) { 1774 DoXform = true; 1775 } else if (CC != ISD::SETCC_INVALID && 1776 RHS.getOpcode() == ISD::Constant && 1777 cast<ConstantSDNode>(RHS)->isNullValue()) { 1778 std::swap(LHS, RHS); 1779 SDValue Op0 = Slct.getOperand(0); 1780 MVT OpVT = isSlctCC ? Op0.getValueType() : 1781 Op0.getOperand(0).getValueType(); 1782 bool isInt = OpVT.isInteger(); 1783 CC = ISD::getSetCCInverse(CC, isInt); 1784 1785 if (!TLI.isCondCodeLegal(CC, OpVT)) 1786 return SDValue(); // Inverse operator isn't legal. 1787 1788 DoXform = true; 1789 InvCC = true; 1790 } 1791 1792 if (DoXform) { 1793 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS); 1794 if (isSlctCC) 1795 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result, 1796 Slct.getOperand(0), Slct.getOperand(1), CC); 1797 SDValue CCOp = Slct.getOperand(0); 1798 if (InvCC) 1799 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(), 1800 CCOp.getOperand(0), CCOp.getOperand(1), CC); 1801 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 1802 CCOp, OtherOp, Result); 1803 } 1804 return SDValue(); 1805} 1806 1807/// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD. 1808static SDValue PerformADDCombine(SDNode *N, 1809 TargetLowering::DAGCombinerInfo &DCI) { 1810 // added by evan in r37685 with no testcase. 1811 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1812 1813 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 1814 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) { 1815 SDValue Result = combineSelectAndUse(N, N0, N1, DCI); 1816 if (Result.getNode()) return Result; 1817 } 1818 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 1819 SDValue Result = combineSelectAndUse(N, N1, N0, DCI); 1820 if (Result.getNode()) return Result; 1821 } 1822 1823 return SDValue(); 1824} 1825 1826/// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB. 1827static SDValue PerformSUBCombine(SDNode *N, 1828 TargetLowering::DAGCombinerInfo &DCI) { 1829 // added by evan in r37685 with no testcase. 1830 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1831 1832 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1833 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 1834 SDValue Result = combineSelectAndUse(N, N1, N0, DCI); 1835 if (Result.getNode()) return Result; 1836 } 1837 1838 return SDValue(); 1839} 1840 1841 1842/// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD. 1843static SDValue PerformFMRRDCombine(SDNode *N, 1844 TargetLowering::DAGCombinerInfo &DCI) { 1845 // fmrrd(fmdrr x, y) -> x,y 1846 SDValue InDouble = N->getOperand(0); 1847 if (InDouble.getOpcode() == ARMISD::FMDRR) 1848 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1)); 1849 return SDValue(); 1850} 1851 1852SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N, 1853 DAGCombinerInfo &DCI) const { 1854 switch (N->getOpcode()) { 1855 default: break; 1856 case ISD::ADD: return PerformADDCombine(N, DCI); 1857 case ISD::SUB: return PerformSUBCombine(N, DCI); 1858 case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI); 1859 } 1860 1861 return SDValue(); 1862} 1863 1864/// isLegalAddressImmediate - Return true if the integer value can be used 1865/// as the offset of the target addressing mode for load / store of the 1866/// given type. 1867static bool isLegalAddressImmediate(int64_t V, MVT VT, 1868 const ARMSubtarget *Subtarget) { 1869 if (V == 0) 1870 return true; 1871 1872 if (!VT.isSimple()) 1873 return false; 1874 1875 if (Subtarget->isThumb()) { 1876 if (V < 0) 1877 return false; 1878 1879 unsigned Scale = 1; 1880 switch (VT.getSimpleVT()) { 1881 default: return false; 1882 case MVT::i1: 1883 case MVT::i8: 1884 // Scale == 1; 1885 break; 1886 case MVT::i16: 1887 // Scale == 2; 1888 Scale = 2; 1889 break; 1890 case MVT::i32: 1891 // Scale == 4; 1892 Scale = 4; 1893 break; 1894 } 1895 1896 if ((V & (Scale - 1)) != 0) 1897 return false; 1898 V /= Scale; 1899 return V == (V & ((1LL << 5) - 1)); 1900 } 1901 1902 if (V < 0) 1903 V = - V; 1904 switch (VT.getSimpleVT()) { 1905 default: return false; 1906 case MVT::i1: 1907 case MVT::i8: 1908 case MVT::i32: 1909 // +- imm12 1910 return V == (V & ((1LL << 12) - 1)); 1911 case MVT::i16: 1912 // +- imm8 1913 return V == (V & ((1LL << 8) - 1)); 1914 case MVT::f32: 1915 case MVT::f64: 1916 if (!Subtarget->hasVFP2()) 1917 return false; 1918 if ((V & 3) != 0) 1919 return false; 1920 V >>= 2; 1921 return V == (V & ((1LL << 8) - 1)); 1922 } 1923} 1924 1925/// isLegalAddressingMode - Return true if the addressing mode represented 1926/// by AM is legal for this target, for a load/store of the specified type. 1927bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM, 1928 const Type *Ty) const { 1929 MVT VT = getValueType(Ty, true); 1930 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget)) 1931 return false; 1932 1933 // Can never fold addr of global into load/store. 1934 if (AM.BaseGV) 1935 return false; 1936 1937 switch (AM.Scale) { 1938 case 0: // no scale reg, must be "r+i" or "r", or "i". 1939 break; 1940 case 1: 1941 if (Subtarget->isThumb()) 1942 return false; 1943 // FALL THROUGH. 1944 default: 1945 // ARM doesn't support any R+R*scale+imm addr modes. 1946 if (AM.BaseOffs) 1947 return false; 1948 1949 if (!VT.isSimple()) 1950 return false; 1951 1952 int Scale = AM.Scale; 1953 switch (VT.getSimpleVT()) { 1954 default: return false; 1955 case MVT::i1: 1956 case MVT::i8: 1957 case MVT::i32: 1958 case MVT::i64: 1959 // This assumes i64 is legalized to a pair of i32. If not (i.e. 1960 // ldrd / strd are used, then its address mode is same as i16. 1961 // r + r 1962 if (Scale < 0) Scale = -Scale; 1963 if (Scale == 1) 1964 return true; 1965 // r + r << imm 1966 return isPowerOf2_32(Scale & ~1); 1967 case MVT::i16: 1968 // r + r 1969 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 1970 return true; 1971 return false; 1972 1973 case MVT::isVoid: 1974 // Note, we allow "void" uses (basically, uses that aren't loads or 1975 // stores), because arm allows folding a scale into many arithmetic 1976 // operations. This should be made more precise and revisited later. 1977 1978 // Allow r << imm, but the imm has to be a multiple of two. 1979 if (AM.Scale & 1) return false; 1980 return isPowerOf2_32(AM.Scale); 1981 } 1982 break; 1983 } 1984 return true; 1985} 1986 1987static bool getIndexedAddressParts(SDNode *Ptr, MVT VT, 1988 bool isSEXTLoad, SDValue &Base, 1989 SDValue &Offset, bool &isInc, 1990 SelectionDAG &DAG) { 1991 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 1992 return false; 1993 1994 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { 1995 // AddressingMode 3 1996 Base = Ptr->getOperand(0); 1997 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 1998 int RHSC = (int)RHS->getZExtValue(); 1999 if (RHSC < 0 && RHSC > -256) { 2000 isInc = false; 2001 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 2002 return true; 2003 } 2004 } 2005 isInc = (Ptr->getOpcode() == ISD::ADD); 2006 Offset = Ptr->getOperand(1); 2007 return true; 2008 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) { 2009 // AddressingMode 2 2010 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 2011 int RHSC = (int)RHS->getZExtValue(); 2012 if (RHSC < 0 && RHSC > -0x1000) { 2013 isInc = false; 2014 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 2015 Base = Ptr->getOperand(0); 2016 return true; 2017 } 2018 } 2019 2020 if (Ptr->getOpcode() == ISD::ADD) { 2021 isInc = true; 2022 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0)); 2023 if (ShOpcVal != ARM_AM::no_shift) { 2024 Base = Ptr->getOperand(1); 2025 Offset = Ptr->getOperand(0); 2026 } else { 2027 Base = Ptr->getOperand(0); 2028 Offset = Ptr->getOperand(1); 2029 } 2030 return true; 2031 } 2032 2033 isInc = (Ptr->getOpcode() == ISD::ADD); 2034 Base = Ptr->getOperand(0); 2035 Offset = Ptr->getOperand(1); 2036 return true; 2037 } 2038 2039 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store. 2040 return false; 2041} 2042 2043/// getPreIndexedAddressParts - returns true by value, base pointer and 2044/// offset pointer and addressing mode by reference if the node's address 2045/// can be legally represented as pre-indexed load / store address. 2046bool 2047ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 2048 SDValue &Offset, 2049 ISD::MemIndexedMode &AM, 2050 SelectionDAG &DAG) const { 2051 if (Subtarget->isThumb()) 2052 return false; 2053 2054 MVT VT; 2055 SDValue Ptr; 2056 bool isSEXTLoad = false; 2057 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 2058 Ptr = LD->getBasePtr(); 2059 VT = LD->getMemoryVT(); 2060 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 2061 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 2062 Ptr = ST->getBasePtr(); 2063 VT = ST->getMemoryVT(); 2064 } else 2065 return false; 2066 2067 bool isInc; 2068 bool isLegal = getIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, Offset, 2069 isInc, DAG); 2070 if (isLegal) { 2071 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC; 2072 return true; 2073 } 2074 return false; 2075} 2076 2077/// getPostIndexedAddressParts - returns true by value, base pointer and 2078/// offset pointer and addressing mode by reference if this node can be 2079/// combined with a load / store to form a post-indexed load / store. 2080bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 2081 SDValue &Base, 2082 SDValue &Offset, 2083 ISD::MemIndexedMode &AM, 2084 SelectionDAG &DAG) const { 2085 if (Subtarget->isThumb()) 2086 return false; 2087 2088 MVT VT; 2089 SDValue Ptr; 2090 bool isSEXTLoad = false; 2091 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 2092 VT = LD->getMemoryVT(); 2093 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 2094 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 2095 VT = ST->getMemoryVT(); 2096 } else 2097 return false; 2098 2099 bool isInc; 2100 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 2101 isInc, DAG); 2102 if (isLegal) { 2103 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; 2104 return true; 2105 } 2106 return false; 2107} 2108 2109void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 2110 const APInt &Mask, 2111 APInt &KnownZero, 2112 APInt &KnownOne, 2113 const SelectionDAG &DAG, 2114 unsigned Depth) const { 2115 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 2116 switch (Op.getOpcode()) { 2117 default: break; 2118 case ARMISD::CMOV: { 2119 // Bits are known zero/one if known on the LHS and RHS. 2120 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 2121 if (KnownZero == 0 && KnownOne == 0) return; 2122 2123 APInt KnownZeroRHS, KnownOneRHS; 2124 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, 2125 KnownZeroRHS, KnownOneRHS, Depth+1); 2126 KnownZero &= KnownZeroRHS; 2127 KnownOne &= KnownOneRHS; 2128 return; 2129 } 2130 } 2131} 2132 2133//===----------------------------------------------------------------------===// 2134// ARM Inline Assembly Support 2135//===----------------------------------------------------------------------===// 2136 2137/// getConstraintType - Given a constraint letter, return the type of 2138/// constraint it is for this target. 2139ARMTargetLowering::ConstraintType 2140ARMTargetLowering::getConstraintType(const std::string &Constraint) const { 2141 if (Constraint.size() == 1) { 2142 switch (Constraint[0]) { 2143 default: break; 2144 case 'l': return C_RegisterClass; 2145 case 'w': return C_RegisterClass; 2146 } 2147 } 2148 return TargetLowering::getConstraintType(Constraint); 2149} 2150 2151std::pair<unsigned, const TargetRegisterClass*> 2152ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 2153 MVT VT) const { 2154 if (Constraint.size() == 1) { 2155 // GCC RS6000 Constraint Letters 2156 switch (Constraint[0]) { 2157 case 'l': 2158 if (Subtarget->isThumb()) 2159 return std::make_pair(0U, ARM::tGPRRegisterClass); 2160 else 2161 return std::make_pair(0U, ARM::GPRRegisterClass); 2162 case 'r': 2163 return std::make_pair(0U, ARM::GPRRegisterClass); 2164 case 'w': 2165 if (VT == MVT::f32) 2166 return std::make_pair(0U, ARM::SPRRegisterClass); 2167 if (VT == MVT::f64) 2168 return std::make_pair(0U, ARM::DPRRegisterClass); 2169 break; 2170 } 2171 } 2172 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 2173} 2174 2175std::vector<unsigned> ARMTargetLowering:: 2176getRegClassForInlineAsmConstraint(const std::string &Constraint, 2177 MVT VT) const { 2178 if (Constraint.size() != 1) 2179 return std::vector<unsigned>(); 2180 2181 switch (Constraint[0]) { // GCC ARM Constraint Letters 2182 default: break; 2183 case 'l': 2184 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3, 2185 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 2186 0); 2187 case 'r': 2188 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3, 2189 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 2190 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 2191 ARM::R12, ARM::LR, 0); 2192 case 'w': 2193 if (VT == MVT::f32) 2194 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3, 2195 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 2196 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 2197 ARM::S12,ARM::S13,ARM::S14,ARM::S15, 2198 ARM::S16,ARM::S17,ARM::S18,ARM::S19, 2199 ARM::S20,ARM::S21,ARM::S22,ARM::S23, 2200 ARM::S24,ARM::S25,ARM::S26,ARM::S27, 2201 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0); 2202 if (VT == MVT::f64) 2203 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3, 2204 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 2205 ARM::D8, ARM::D9, ARM::D10,ARM::D11, 2206 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0); 2207 break; 2208 } 2209 2210 return std::vector<unsigned>(); 2211} 2212 2213/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 2214/// vector. If it is invalid, don't add anything to Ops. 2215void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 2216 char Constraint, 2217 bool hasMemory, 2218 std::vector<SDValue>&Ops, 2219 SelectionDAG &DAG) const { 2220 SDValue Result(0, 0); 2221 2222 switch (Constraint) { 2223 default: break; 2224 case 'I': case 'J': case 'K': case 'L': 2225 case 'M': case 'N': case 'O': 2226 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 2227 if (!C) 2228 return; 2229 2230 int64_t CVal64 = C->getSExtValue(); 2231 int CVal = (int) CVal64; 2232 // None of these constraints allow values larger than 32 bits. Check 2233 // that the value fits in an int. 2234 if (CVal != CVal64) 2235 return; 2236 2237 switch (Constraint) { 2238 case 'I': 2239 if (Subtarget->isThumb()) { 2240 // This must be a constant between 0 and 255, for ADD immediates. 2241 if (CVal >= 0 && CVal <= 255) 2242 break; 2243 } else { 2244 // A constant that can be used as an immediate value in a 2245 // data-processing instruction. 2246 if (ARM_AM::getSOImmVal(CVal) != -1) 2247 break; 2248 } 2249 return; 2250 2251 case 'J': 2252 if (Subtarget->isThumb()) { 2253 // This must be a constant between -255 and -1, for negated ADD 2254 // immediates. This can be used in GCC with an "n" modifier that 2255 // prints the negated value, for use with SUB instructions. It is 2256 // not useful otherwise but is implemented for compatibility. 2257 if (CVal >= -255 && CVal <= -1) 2258 break; 2259 } else { 2260 // This must be a constant between -4095 and 4095. It is not clear 2261 // what this constraint is intended for. Implemented for 2262 // compatibility with GCC. 2263 if (CVal >= -4095 && CVal <= 4095) 2264 break; 2265 } 2266 return; 2267 2268 case 'K': 2269 if (Subtarget->isThumb()) { 2270 // A 32-bit value where only one byte has a nonzero value. Exclude 2271 // zero to match GCC. This constraint is used by GCC internally for 2272 // constants that can be loaded with a move/shift combination. 2273 // It is not useful otherwise but is implemented for compatibility. 2274 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal)) 2275 break; 2276 } else { 2277 // A constant whose bitwise inverse can be used as an immediate 2278 // value in a data-processing instruction. This can be used in GCC 2279 // with a "B" modifier that prints the inverted value, for use with 2280 // BIC and MVN instructions. It is not useful otherwise but is 2281 // implemented for compatibility. 2282 if (ARM_AM::getSOImmVal(~CVal) != -1) 2283 break; 2284 } 2285 return; 2286 2287 case 'L': 2288 if (Subtarget->isThumb()) { 2289 // This must be a constant between -7 and 7, 2290 // for 3-operand ADD/SUB immediate instructions. 2291 if (CVal >= -7 && CVal < 7) 2292 break; 2293 } else { 2294 // A constant whose negation can be used as an immediate value in a 2295 // data-processing instruction. This can be used in GCC with an "n" 2296 // modifier that prints the negated value, for use with SUB 2297 // instructions. It is not useful otherwise but is implemented for 2298 // compatibility. 2299 if (ARM_AM::getSOImmVal(-CVal) != -1) 2300 break; 2301 } 2302 return; 2303 2304 case 'M': 2305 if (Subtarget->isThumb()) { 2306 // This must be a multiple of 4 between 0 and 1020, for 2307 // ADD sp + immediate. 2308 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0)) 2309 break; 2310 } else { 2311 // A power of two or a constant between 0 and 32. This is used in 2312 // GCC for the shift amount on shifted register operands, but it is 2313 // useful in general for any shift amounts. 2314 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0)) 2315 break; 2316 } 2317 return; 2318 2319 case 'N': 2320 if (Subtarget->isThumb()) { 2321 // This must be a constant between 0 and 31, for shift amounts. 2322 if (CVal >= 0 && CVal <= 31) 2323 break; 2324 } 2325 return; 2326 2327 case 'O': 2328 if (Subtarget->isThumb()) { 2329 // This must be a multiple of 4 between -508 and 508, for 2330 // ADD/SUB sp = sp + immediate. 2331 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0)) 2332 break; 2333 } 2334 return; 2335 } 2336 Result = DAG.getTargetConstant(CVal, Op.getValueType()); 2337 break; 2338 } 2339 2340 if (Result.getNode()) { 2341 Ops.push_back(Result); 2342 return; 2343 } 2344 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory, 2345 Ops, DAG); 2346} 2347