ARMISelLowering.cpp revision 368f20fda4a1cb9afdc2788a754b9ffe59afd391 
1//===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Evan Cheng and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "ARM.h"
16#include "ARMAddressingModes.h"
17#include "ARMConstantPoolValue.h"
18#include "ARMISelLowering.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMRegisterInfo.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/CallingConv.h"
24#include "llvm/Constants.h"
25#include "llvm/Instruction.h"
26#include "llvm/CodeGen/MachineBasicBlock.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/SelectionDAG.h"
31#include "llvm/CodeGen/SSARegMap.h"
32#include "llvm/Target/TargetOptions.h"
33#include "llvm/ADT/VectorExtras.h"
34#include "llvm/Support/MathExtras.h"
35using namespace llvm;
36
37ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
38    : TargetLowering(TM), ARMPCLabelIndex(0) {
39  Subtarget = &TM.getSubtarget<ARMSubtarget>();
40
41  // Uses VFP for Thumb libfuncs if available.
42  if (!UseSoftFloat && Subtarget->isThumb() && Subtarget->hasVFP2()) {
43    // Single-precision floating-point arithmetic.
44    setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
45    setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
46    setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
47    setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
48
49    // Double-precision floating-point arithmetic.
50    setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
51    setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
52    setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
53    setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
54
55    // Single-precision comparisons.
56    setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
57    setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
58    setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
59    setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
60    setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
61    setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
62    setLibcallName(RTLIB::UO_F32,  "__unordsf2vfp");
63    setLibcallName(RTLIB::O_F32,   "__unordsf2vfp");
64
65    setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
66    setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
67    setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
68    setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
69    setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
70    setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
71    setCmpLibcallCC(RTLIB::UO_F32,  ISD::SETNE);
72    setCmpLibcallCC(RTLIB::O_F32,   ISD::SETEQ);
73
74    // Double-precision comparisons.
75    setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
76    setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
77    setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
78    setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
79    setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
80    setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
81    setLibcallName(RTLIB::UO_F64,  "__unorddf2vfp");
82    setLibcallName(RTLIB::O_F64,   "__unorddf2vfp");
83
84    setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
85    setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
86    setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
87    setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
88    setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
89    setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
90    setCmpLibcallCC(RTLIB::UO_F64,  ISD::SETNE);
91    setCmpLibcallCC(RTLIB::O_F64,   ISD::SETEQ);
92
93    // Floating-point to integer conversions.
94    // i64 conversions are done via library routines even when generating VFP
95    // instructions, so use the same ones.
96    setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
97    setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
98    setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
99    setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
100
101    // Conversions between floating types.
102    setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
103    setLibcallName(RTLIB::FPEXT_F32_F64,   "__extendsfdf2vfp");
104
105    // Integer to floating-point conversions.
106    // i64 conversions are done via library routines even when generating VFP
107    // instructions, so use the same ones.
108    // FIXME: There appears to be some naming inconsistency in ARM libgcc: e.g.
109    // __floatunsidf vs. __floatunssidfvfp.
110    setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
111    setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
112    setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
113    setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
114  }
115
116  addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
117  if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
118    addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
119    addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
120  }
121
122  // ARM does not have f32 extending load.
123  setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
124
125  // ARM supports all 4 flavors of integer indexed load / store.
126  for (unsigned im = (unsigned)ISD::PRE_INC;
127       im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
128    setIndexedLoadAction(im,  MVT::i1,  Legal);
129    setIndexedLoadAction(im,  MVT::i8,  Legal);
130    setIndexedLoadAction(im,  MVT::i16, Legal);
131    setIndexedLoadAction(im,  MVT::i32, Legal);
132    setIndexedStoreAction(im, MVT::i1,  Legal);
133    setIndexedStoreAction(im, MVT::i8,  Legal);
134    setIndexedStoreAction(im, MVT::i16, Legal);
135    setIndexedStoreAction(im, MVT::i32, Legal);
136  }
137
138  // i64 operation support.
139  if (Subtarget->isThumb()) {
140    setOperationAction(ISD::MUL,     MVT::i64, Expand);
141    setOperationAction(ISD::MULHU,   MVT::i32, Expand);
142    setOperationAction(ISD::MULHS,   MVT::i32, Expand);
143  } else {
144    setOperationAction(ISD::MUL,     MVT::i64, Custom);
145    setOperationAction(ISD::MULHU,   MVT::i32, Custom);
146    if (!Subtarget->hasV6Ops())
147      setOperationAction(ISD::MULHS, MVT::i32, Custom);
148  }
149  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
150  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
151  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
152  setOperationAction(ISD::SRL,       MVT::i64, Custom);
153  setOperationAction(ISD::SRA,       MVT::i64, Custom);
154
155  // ARM does not have ROTL.
156  setOperationAction(ISD::ROTL,  MVT::i32, Expand);
157  setOperationAction(ISD::CTTZ , MVT::i32, Expand);
158  setOperationAction(ISD::CTPOP, MVT::i32, Expand);
159  if (!Subtarget->hasV5TOps() || Subtarget->isThumb())
160    setOperationAction(ISD::CTLZ, MVT::i32, Expand);
161
162  // Only ARMv6 has BSWAP.
163  if (!Subtarget->hasV6Ops())
164      setOperationAction(ISD::BSWAP, MVT::i32, Expand);
165
166  // These are expanded into libcalls.
167  setOperationAction(ISD::SDIV,  MVT::i32, Expand);
168  setOperationAction(ISD::UDIV,  MVT::i32, Expand);
169  setOperationAction(ISD::SREM,  MVT::i32, Expand);
170  setOperationAction(ISD::UREM,  MVT::i32, Expand);
171
172  // Support label based line numbers.
173  setOperationAction(ISD::LOCATION, MVT::Other, Expand);
174  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
175  // FIXME - use subtarget debug flags
176  if (!Subtarget->isTargetDarwin())
177    setOperationAction(ISD::LABEL, MVT::Other, Expand);
178
179  setOperationAction(ISD::RET,           MVT::Other, Custom);
180  setOperationAction(ISD::GlobalAddress, MVT::i32,   Custom);
181  setOperationAction(ISD::ConstantPool,  MVT::i32,   Custom);
182
183  // Expand mem operations genericly.
184  setOperationAction(ISD::MEMSET          , MVT::Other, Expand);
185  setOperationAction(ISD::MEMCPY          , MVT::Other, Expand);
186  setOperationAction(ISD::MEMMOVE         , MVT::Other, Expand);
187
188  // Use the default implementation.
189  setOperationAction(ISD::VASTART           , MVT::Other, Expand);
190  setOperationAction(ISD::VAARG             , MVT::Other, Expand);
191  setOperationAction(ISD::VACOPY            , MVT::Other, Expand);
192  setOperationAction(ISD::VAEND             , MVT::Other, Expand);
193  setOperationAction(ISD::STACKSAVE,          MVT::Other, Expand);
194  setOperationAction(ISD::STACKRESTORE,       MVT::Other, Expand);
195  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Expand);
196
197  if (!Subtarget->hasV6Ops()) {
198    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
199    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8,  Expand);
200  }
201  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
202
203  if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb())
204    // Turn f64->i64 into FMRRD iff target supports vfp2.
205    setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
206
207  setOperationAction(ISD::SETCC    , MVT::i32, Expand);
208  setOperationAction(ISD::SETCC    , MVT::f32, Expand);
209  setOperationAction(ISD::SETCC    , MVT::f64, Expand);
210  setOperationAction(ISD::SELECT   , MVT::i32, Expand);
211  setOperationAction(ISD::SELECT   , MVT::f32, Expand);
212  setOperationAction(ISD::SELECT   , MVT::f64, Expand);
213  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
214  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
215  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
216
217  setOperationAction(ISD::BRCOND   , MVT::Other, Expand);
218  setOperationAction(ISD::BR_CC    , MVT::i32,   Custom);
219  setOperationAction(ISD::BR_CC    , MVT::f32,   Custom);
220  setOperationAction(ISD::BR_CC    , MVT::f64,   Custom);
221  setOperationAction(ISD::BR_JT    , MVT::Other, Custom);
222
223  setOperationAction(ISD::VASTART,       MVT::Other, Custom);
224  setOperationAction(ISD::VACOPY,        MVT::Other, Expand);
225  setOperationAction(ISD::VAEND,         MVT::Other, Expand);
226  setOperationAction(ISD::STACKSAVE,     MVT::Other, Expand);
227  setOperationAction(ISD::STACKRESTORE,  MVT::Other, Expand);
228
229  // FP Constants can't be immediates.
230  setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
231  setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
232
233  // We don't support sin/cos/fmod/copysign
234  setOperationAction(ISD::FSIN     , MVT::f64, Expand);
235  setOperationAction(ISD::FSIN     , MVT::f32, Expand);
236  setOperationAction(ISD::FCOS     , MVT::f32, Expand);
237  setOperationAction(ISD::FCOS     , MVT::f64, Expand);
238  setOperationAction(ISD::FREM     , MVT::f64, Expand);
239  setOperationAction(ISD::FREM     , MVT::f32, Expand);
240  setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
241  setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
242
243  // int <-> fp are custom expanded into bit_convert + ARMISD ops.
244  setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
245  setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
246  setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
247  setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
248
249  setStackPointerRegisterToSaveRestore(ARM::SP);
250
251  setSchedulingPreference(SchedulingForRegPressure);
252  computeRegisterProperties();
253}
254
255
256const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
257  switch (Opcode) {
258  default: return 0;
259  case ARMISD::Wrapper:       return "ARMISD::Wrapper";
260  case ARMISD::WrapperJT:     return "ARMISD::WrapperJT";
261  case ARMISD::CALL:          return "ARMISD::CALL";
262  case ARMISD::CALL_NOLINK:   return "ARMISD::CALL_NOLINK";
263  case ARMISD::tCALL:         return "ARMISD::tCALL";
264  case ARMISD::BRCOND:        return "ARMISD::BRCOND";
265  case ARMISD::BR_JT:         return "ARMISD::BR_JT";
266  case ARMISD::RET_FLAG:      return "ARMISD::RET_FLAG";
267  case ARMISD::PIC_ADD:       return "ARMISD::PIC_ADD";
268  case ARMISD::CMP:           return "ARMISD::CMP";
269  case ARMISD::CMPFP:         return "ARMISD::CMPFP";
270  case ARMISD::CMPFPw0:       return "ARMISD::CMPFPw0";
271  case ARMISD::FMSTAT:        return "ARMISD::FMSTAT";
272  case ARMISD::CMOV:          return "ARMISD::CMOV";
273  case ARMISD::CNEG:          return "ARMISD::CNEG";
274
275  case ARMISD::FTOSI:         return "ARMISD::FTOSI";
276  case ARMISD::FTOUI:         return "ARMISD::FTOUI";
277  case ARMISD::SITOF:         return "ARMISD::SITOF";
278  case ARMISD::UITOF:         return "ARMISD::UITOF";
279  case ARMISD::MULHILOU:      return "ARMISD::MULHILOU";
280  case ARMISD::MULHILOS:      return "ARMISD::MULHILOS";
281
282  case ARMISD::SRL_FLAG:      return "ARMISD::SRL_FLAG";
283  case ARMISD::SRA_FLAG:      return "ARMISD::SRA_FLAG";
284  case ARMISD::RRX:           return "ARMISD::RRX";
285
286  case ARMISD::FMRRD:         return "ARMISD::FMRRD";
287  case ARMISD::FMDRR:         return "ARMISD::FMDRR";
288  }
289}
290
291//===----------------------------------------------------------------------===//
292// Lowering Code
293//===----------------------------------------------------------------------===//
294
295
296/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
297static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
298  switch (CC) {
299  default: assert(0 && "Unknown condition code!");
300  case ISD::SETNE:  return ARMCC::NE;
301  case ISD::SETEQ:  return ARMCC::EQ;
302  case ISD::SETGT:  return ARMCC::GT;
303  case ISD::SETGE:  return ARMCC::GE;
304  case ISD::SETLT:  return ARMCC::LT;
305  case ISD::SETLE:  return ARMCC::LE;
306  case ISD::SETUGT: return ARMCC::HI;
307  case ISD::SETUGE: return ARMCC::HS;
308  case ISD::SETULT: return ARMCC::LO;
309  case ISD::SETULE: return ARMCC::LS;
310  }
311}
312
313/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It
314/// returns true if the operands should be inverted to form the proper
315/// comparison.
316static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
317                        ARMCC::CondCodes &CondCode2) {
318  bool Invert = false;
319  CondCode2 = ARMCC::AL;
320  switch (CC) {
321  default: assert(0 && "Unknown FP condition!");
322  case ISD::SETEQ:
323  case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
324  case ISD::SETGT:
325  case ISD::SETOGT: CondCode = ARMCC::GT; break;
326  case ISD::SETGE:
327  case ISD::SETOGE: CondCode = ARMCC::GE; break;
328  case ISD::SETOLT: CondCode = ARMCC::MI; break;
329  case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break;
330  case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
331  case ISD::SETO:   CondCode = ARMCC::VC; break;
332  case ISD::SETUO:  CondCode = ARMCC::VS; break;
333  case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
334  case ISD::SETUGT: CondCode = ARMCC::HI; break;
335  case ISD::SETUGE: CondCode = ARMCC::PL; break;
336  case ISD::SETLT:
337  case ISD::SETULT: CondCode = ARMCC::LT; break;
338  case ISD::SETLE:
339  case ISD::SETULE: CondCode = ARMCC::LE; break;
340  case ISD::SETNE:
341  case ISD::SETUNE: CondCode = ARMCC::NE; break;
342  }
343  return Invert;
344}
345
346static void
347HowToPassArgument(MVT::ValueType ObjectVT, unsigned NumGPRs,
348                  unsigned StackOffset, unsigned &NeededGPRs,
349                  unsigned &NeededStackSize, unsigned &GPRPad,
350                  unsigned &StackPad, unsigned Flags) {
351  NeededStackSize = 0;
352  NeededGPRs = 0;
353  StackPad = 0;
354  GPRPad = 0;
355  unsigned align = (Flags >> ISD::ParamFlags::OrigAlignmentOffs);
356  GPRPad = NumGPRs % ((align + 3)/4);
357  StackPad = StackOffset % align;
358  unsigned firstGPR = NumGPRs + GPRPad;
359  switch (ObjectVT) {
360  default: assert(0 && "Unhandled argument type!");
361  case MVT::i32:
362  case MVT::f32:
363    if (firstGPR < 4)
364      NeededGPRs = 1;
365    else
366      NeededStackSize = 4;
367    break;
368  case MVT::i64:
369  case MVT::f64:
370    if (firstGPR < 3)
371      NeededGPRs = 2;
372    else if (firstGPR == 3) {
373      NeededGPRs = 1;
374      NeededStackSize = 4;
375    } else
376      NeededStackSize = 8;
377  }
378}
379
380/// LowerCALL - Lowering a ISD::CALL node into a callseq_start <-
381/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
382/// nodes.
383SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
384  MVT::ValueType RetVT= Op.Val->getValueType(0);
385  SDOperand Chain    = Op.getOperand(0);
386  unsigned CallConv  = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
387  assert((CallConv == CallingConv::C ||
388          CallConv == CallingConv::Fast) && "unknown calling convention");
389  SDOperand Callee   = Op.getOperand(4);
390  unsigned NumOps    = (Op.getNumOperands() - 5) / 2;
391  unsigned ArgOffset = 0;   // Frame mechanisms handle retaddr slot
392  unsigned NumGPRs = 0;     // GPRs used for parameter passing.
393
394  // Count how many bytes are to be pushed on the stack.
395  unsigned NumBytes = 0;
396
397  // Add up all the space actually used.
398  for (unsigned i = 0; i < NumOps; ++i) {
399    unsigned ObjSize;
400    unsigned ObjGPRs;
401    unsigned StackPad;
402    unsigned GPRPad;
403    MVT::ValueType ObjectVT = Op.getOperand(5+2*i).getValueType();
404    unsigned Flags = Op.getConstantOperandVal(5+2*i+1);
405    HowToPassArgument(ObjectVT, NumGPRs, NumBytes, ObjGPRs, ObjSize,
406                      GPRPad, StackPad, Flags);
407    NumBytes += ObjSize + StackPad;
408    NumGPRs += ObjGPRs + GPRPad;
409  }
410
411  // Adjust the stack pointer for the new arguments...
412  // These operations are automatically eliminated by the prolog/epilog pass
413  Chain = DAG.getCALLSEQ_START(Chain,
414                               DAG.getConstant(NumBytes, MVT::i32));
415
416  SDOperand StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
417
418  static const unsigned GPRArgRegs[] = {
419    ARM::R0, ARM::R1, ARM::R2, ARM::R3
420  };
421
422  NumGPRs = 0;
423  std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
424  std::vector<SDOperand> MemOpChains;
425  for (unsigned i = 0; i != NumOps; ++i) {
426    SDOperand Arg = Op.getOperand(5+2*i);
427    unsigned Flags = Op.getConstantOperandVal(5+2*i+1);
428    MVT::ValueType ArgVT = Arg.getValueType();
429
430    unsigned ObjSize;
431    unsigned ObjGPRs;
432    unsigned GPRPad;
433    unsigned StackPad;
434    HowToPassArgument(ArgVT, NumGPRs, ArgOffset, ObjGPRs,
435                      ObjSize, GPRPad, StackPad, Flags);
436    NumGPRs += GPRPad;
437    ArgOffset += StackPad;
438    if (ObjGPRs > 0) {
439      switch (ArgVT) {
440      default: assert(0 && "Unexpected ValueType for argument!");
441      case MVT::i32:
442        RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Arg));
443        break;
444      case MVT::f32:
445        RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs],
446                                 DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg)));
447        break;
448      case MVT::i64: {
449        SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
450                                   DAG.getConstant(0, getPointerTy()));
451        SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
452                                   DAG.getConstant(1, getPointerTy()));
453        RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo));
454        if (ObjGPRs == 2)
455          RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi));
456        else {
457          SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
458          PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
459          MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0));
460        }
461        break;
462      }
463      case MVT::f64: {
464        SDOperand Cvt = DAG.getNode(ARMISD::FMRRD,
465                                    DAG.getVTList(MVT::i32, MVT::i32),
466                                    &Arg, 1);
467        RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Cvt));
468        if (ObjGPRs == 2)
469          RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1],
470                                              Cvt.getValue(1)));
471        else {
472          SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
473          PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
474          MemOpChains.push_back(DAG.getStore(Chain, Cvt.getValue(1), PtrOff,
475                                             NULL, 0));
476        }
477        break;
478      }
479      }
480    } else {
481      assert(ObjSize != 0);
482      SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
483      PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
484      MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
485    }
486
487    NumGPRs += ObjGPRs;
488    ArgOffset += ObjSize;
489  }
490
491  if (!MemOpChains.empty())
492    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
493                        &MemOpChains[0], MemOpChains.size());
494
495  // Build a sequence of copy-to-reg nodes chained together with token chain
496  // and flag operands which copy the outgoing args into the appropriate regs.
497  SDOperand InFlag;
498  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
499    Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
500                             InFlag);
501    InFlag = Chain.getValue(1);
502  }
503
504  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
505  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
506  // node so that legalize doesn't hack it.
507  bool isDirect = false;
508  bool isARMFunc = false;
509  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
510    GlobalValue *GV = G->getGlobal();
511    isDirect = true;
512    bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() ||
513                  GV->hasLinkOnceLinkage());
514    bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
515                   getTargetMachine().getRelocationModel() != Reloc::Static;
516    isARMFunc = !Subtarget->isThumb() || isStub;
517    // tBX takes a register source operand.
518    if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
519      ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
520                                                           ARMCP::CPStub, 4);
521      SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
522      CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
523      Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
524      SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
525      Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
526   } else
527      Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
528  } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
529    isDirect = true;
530    bool isStub = Subtarget->isTargetDarwin() &&
531                  getTargetMachine().getRelocationModel() != Reloc::Static;
532    isARMFunc = !Subtarget->isThumb() || isStub;
533    // tBX takes a register source operand.
534    const char *Sym = S->getSymbol();
535    if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
536      ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
537                                                           ARMCP::CPStub, 4);
538      SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
539      CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
540      Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
541      SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
542      Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
543    } else
544      Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
545  }
546
547  std::vector<MVT::ValueType> NodeTys;
548  NodeTys.push_back(MVT::Other);   // Returns a chain
549  NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
550
551  std::vector<SDOperand> Ops;
552  Ops.push_back(Chain);
553  Ops.push_back(Callee);
554
555  // Add argument registers to the end of the list so that they are known live
556  // into the call.
557  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
558    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
559                                  RegsToPass[i].second.getValueType()));
560
561  // FIXME: handle tail calls differently.
562  unsigned CallOpc;
563  if (Subtarget->isThumb()) {
564    if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc))
565      CallOpc = ARMISD::CALL_NOLINK;
566    else
567      CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
568  } else {
569    CallOpc = (isDirect || Subtarget->hasV5TOps())
570      ? ARMISD::CALL : ARMISD::CALL_NOLINK;
571  }
572  if (InFlag.Val)
573    Ops.push_back(InFlag);
574  Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
575  InFlag = Chain.getValue(1);
576
577  SDOperand CSOps[] = { Chain, DAG.getConstant(NumBytes, MVT::i32), InFlag };
578  Chain = DAG.getNode(ISD::CALLSEQ_END,
579                      DAG.getNodeValueTypes(MVT::Other, MVT::Flag),
580                      ((RetVT != MVT::Other) ? 2 : 1), CSOps, 3);
581  if (RetVT != MVT::Other)
582    InFlag = Chain.getValue(1);
583
584  std::vector<SDOperand> ResultVals;
585  NodeTys.clear();
586
587  // If the call has results, copy the values out of the ret val registers.
588  switch (RetVT) {
589  default: assert(0 && "Unexpected ret value!");
590  case MVT::Other:
591    break;
592  case MVT::i32:
593    Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
594    ResultVals.push_back(Chain.getValue(0));
595    if (Op.Val->getValueType(1) == MVT::i32) {
596      // Returns a i64 value.
597      Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32,
598                                 Chain.getValue(2)).getValue(1);
599      ResultVals.push_back(Chain.getValue(0));
600      NodeTys.push_back(MVT::i32);
601    }
602    NodeTys.push_back(MVT::i32);
603    break;
604  case MVT::f32:
605    Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
606    ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f32,
607                                     Chain.getValue(0)));
608    NodeTys.push_back(MVT::f32);
609    break;
610  case MVT::f64: {
611    SDOperand Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag);
612    SDOperand Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2));
613    ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi));
614    NodeTys.push_back(MVT::f64);
615    break;
616  }
617  }
618
619  NodeTys.push_back(MVT::Other);
620
621  if (ResultVals.empty())
622    return Chain;
623
624  ResultVals.push_back(Chain);
625  SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, &ResultVals[0],
626                              ResultVals.size());
627  return Res.getValue(Op.ResNo);
628}
629
630static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
631  SDOperand Copy;
632  SDOperand Chain = Op.getOperand(0);
633  switch(Op.getNumOperands()) {
634  default:
635    assert(0 && "Do not know how to return this many arguments!");
636    abort();
637  case 1: {
638    SDOperand LR = DAG.getRegister(ARM::LR, MVT::i32);
639    return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain);
640  }
641  case 3:
642    Op = Op.getOperand(1);
643    if (Op.getValueType() == MVT::f32) {
644      Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
645    } else if (Op.getValueType() == MVT::f64) {
646      // Recursively legalize f64 -> i64.
647      Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Op);
648      return DAG.getNode(ISD::RET, MVT::Other, Chain, Op,
649                         DAG.getConstant(0, MVT::i32));
650    }
651    Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDOperand());
652    if (DAG.getMachineFunction().liveout_empty())
653      DAG.getMachineFunction().addLiveOut(ARM::R0);
654    break;
655  case 5:
656    Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand());
657    Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1));
658    // If we haven't noted the R0+R1 are live out, do so now.
659    if (DAG.getMachineFunction().liveout_empty()) {
660      DAG.getMachineFunction().addLiveOut(ARM::R0);
661      DAG.getMachineFunction().addLiveOut(ARM::R1);
662    }
663    break;
664  }
665
666  //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag
667  return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
668}
669
670// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
671// their target countpart wrapped in the ARMISD::Wrapper node. Suppose N is
672// one of the above mentioned nodes. It has to be wrapped because otherwise
673// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
674// be used to form addressing mode. These wrapped nodes will be selected
675// into MOVri.
676static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
677  MVT::ValueType PtrVT = Op.getValueType();
678  ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
679  SDOperand Res;
680  if (CP->isMachineConstantPoolEntry())
681    Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
682                                    CP->getAlignment());
683  else
684    Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
685                                    CP->getAlignment());
686  return DAG.getNode(ARMISD::Wrapper, MVT::i32, Res);
687}
688
689/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol
690/// even in dynamic-no-pic mode.
691static bool GVIsIndirectSymbol(GlobalValue *GV) {
692  return (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
693          (GV->isDeclaration() && !GV->hasNotBeenReadFromBytecode()));
694}
695
696SDOperand ARMTargetLowering::LowerGlobalAddress(SDOperand Op,
697                                                SelectionDAG &DAG) {
698  MVT::ValueType PtrVT = getPointerTy();
699  GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
700  Reloc::Model RelocM = getTargetMachine().getRelocationModel();
701  bool IsIndirect = Subtarget->isTargetDarwin() && GVIsIndirectSymbol(GV);
702  SDOperand CPAddr;
703  if (RelocM == Reloc::Static)
704    CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
705  else {
706    unsigned PCAdj = (RelocM != Reloc::PIC_)
707      ? 0 : (Subtarget->isThumb() ? 4 : 8);
708    ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr
709      : ARMCP::CPValue;
710    ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
711                                                         Kind, PCAdj);
712    CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
713  }
714  CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
715
716  SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
717  SDOperand Chain = Result.getValue(1);
718
719  if (RelocM == Reloc::PIC_) {
720    SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
721    Result = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel);
722  }
723  if (IsIndirect)
724    Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0);
725
726  return Result;
727}
728
729static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
730                              unsigned VarArgsFrameIndex) {
731  // vastart just stores the address of the VarArgsFrameIndex slot into the
732  // memory location argument.
733  MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
734  SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
735  SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
736  return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(),
737                      SV->getOffset());
738}
739
740static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
741                                      unsigned *vRegs, unsigned ArgNo,
742                                      unsigned &NumGPRs, unsigned &ArgOffset) {
743  MachineFunction &MF = DAG.getMachineFunction();
744  MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
745  SDOperand Root = Op.getOperand(0);
746  std::vector<SDOperand> ArgValues;
747  SSARegMap *RegMap = MF.getSSARegMap();
748
749  static const unsigned GPRArgRegs[] = {
750    ARM::R0, ARM::R1, ARM::R2, ARM::R3
751  };
752
753  unsigned ObjSize;
754  unsigned ObjGPRs;
755  unsigned GPRPad;
756  unsigned StackPad;
757  unsigned Flags = Op.getConstantOperandVal(ArgNo + 3);
758  HowToPassArgument(ObjectVT, NumGPRs, ArgOffset, ObjGPRs,
759                    ObjSize, GPRPad, StackPad, Flags);
760  NumGPRs += GPRPad;
761  ArgOffset += StackPad;
762
763  SDOperand ArgValue;
764  if (ObjGPRs == 1) {
765    unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
766    MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
767    vRegs[NumGPRs] = VReg;
768    ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
769    if (ObjectVT == MVT::f32)
770      ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue);
771  } else if (ObjGPRs == 2) {
772    unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
773    MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
774    vRegs[NumGPRs] = VReg;
775    ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
776
777    VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
778    MF.addLiveIn(GPRArgRegs[NumGPRs+1], VReg);
779    vRegs[NumGPRs+1] = VReg;
780    SDOperand ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32);
781
782    if (ObjectVT == MVT::i64)
783      ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2);
784    else
785      ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
786  }
787  NumGPRs += ObjGPRs;
788
789  if (ObjSize) {
790    // If the argument is actually used, emit a load from the right stack
791    // slot.
792    if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
793      MachineFrameInfo *MFI = MF.getFrameInfo();
794      int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
795      SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
796      if (ObjGPRs == 0)
797        ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
798      else {
799        SDOperand ArgValue2 =
800          DAG.getLoad(MVT::i32, Root, FIN, NULL, 0);
801        if (ObjectVT == MVT::i64)
802          ArgValue= DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2);
803        else
804          ArgValue= DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
805      }
806    } else {
807      // Don't emit a dead load.
808      ArgValue = DAG.getNode(ISD::UNDEF, ObjectVT);
809    }
810
811    ArgOffset += ObjSize;   // Move on to the next argument.
812  }
813
814  return ArgValue;
815}
816
817SDOperand
818ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
819  std::vector<SDOperand> ArgValues;
820  SDOperand Root = Op.getOperand(0);
821  unsigned ArgOffset = 0;   // Frame mechanisms handle retaddr slot
822  unsigned NumGPRs = 0;     // GPRs used for parameter passing.
823  unsigned VRegs[4];
824
825  unsigned NumArgs = Op.Val->getNumValues()-1;
826  for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo)
827    ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, VRegs, ArgNo,
828                                             NumGPRs, ArgOffset));
829
830  bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
831  if (isVarArg) {
832    static const unsigned GPRArgRegs[] = {
833      ARM::R0, ARM::R1, ARM::R2, ARM::R3
834    };
835
836    MachineFunction &MF = DAG.getMachineFunction();
837    SSARegMap *RegMap = MF.getSSARegMap();
838    MachineFrameInfo *MFI = MF.getFrameInfo();
839    ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
840    unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
841    unsigned VARegSize = (4 - NumGPRs) * 4;
842    unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
843    if (VARegSaveSize) {
844      // If this function is vararg, store any remaining integer argument regs
845      // to their spots on the stack so that they may be loaded by deferencing
846      // the result of va_next.
847      AFI->setVarArgsRegSaveSize(VARegSaveSize);
848      VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
849                                                 VARegSaveSize - VARegSize);
850      SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
851
852      SmallVector<SDOperand, 4> MemOps;
853      for (; NumGPRs < 4; ++NumGPRs) {
854        unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
855        MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
856        SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
857        SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
858        MemOps.push_back(Store);
859        FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
860                          DAG.getConstant(4, getPointerTy()));
861      }
862      if (!MemOps.empty())
863        Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
864                           &MemOps[0], MemOps.size());
865    } else
866      // This will point to the next argument passed via stack.
867      VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
868  }
869
870  ArgValues.push_back(Root);
871
872  // Return the new list of results.
873  std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
874                                    Op.Val->value_end());
875  return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
876}
877
878/// isFloatingPointZero - Return true if this is +0.0.
879static bool isFloatingPointZero(SDOperand Op) {
880  if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
881    return CFP->isExactlyValue(0.0);
882  else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
883    // Maybe this has already been legalized into the constant pool?
884    if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
885      SDOperand WrapperOp = Op.getOperand(1).getOperand(0);
886      if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
887        if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
888          return CFP->isExactlyValue(0.0);
889    }
890  }
891  return false;
892}
893
894static bool isLegalCmpImmediate(unsigned C, bool isThumb) {
895  return ( isThumb && (C & ~255U) == 0) ||
896         (!isThumb && ARM_AM::getSOImmVal(C) != -1);
897}
898
899/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
900/// the given operands.
901static SDOperand getARMCmp(SDOperand LHS, SDOperand RHS, ISD::CondCode CC,
902                           SDOperand &ARMCC, SelectionDAG &DAG, bool isThumb) {
903  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.Val)) {
904    unsigned C = RHSC->getValue();
905    if (!isLegalCmpImmediate(C, isThumb)) {
906      // Constant does not fit, try adjusting it by one?
907      switch (CC) {
908      default: break;
909      case ISD::SETLT:
910      case ISD::SETGE:
911        if (isLegalCmpImmediate(C-1, isThumb)) {
912          CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
913          RHS = DAG.getConstant(C-1, MVT::i32);
914        }
915        break;
916      case ISD::SETULT:
917      case ISD::SETUGE:
918        if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) {
919          CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
920          RHS = DAG.getConstant(C-1, MVT::i32);
921        }
922        break;
923      case ISD::SETLE:
924      case ISD::SETGT:
925        if (isLegalCmpImmediate(C+1, isThumb)) {
926          CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
927          RHS = DAG.getConstant(C+1, MVT::i32);
928        }
929        break;
930      case ISD::SETULE:
931      case ISD::SETUGT:
932        if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb)) {
933          CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
934          RHS = DAG.getConstant(C+1, MVT::i32);
935        }
936        break;
937      }
938    }
939  }
940
941  ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
942  ARMCC = DAG.getConstant(CondCode, MVT::i32);
943  return DAG.getNode(ARMISD::CMP, MVT::Flag, LHS, RHS);
944}
945
946/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
947static SDOperand getVFPCmp(SDOperand LHS, SDOperand RHS, SelectionDAG &DAG) {
948  SDOperand Cmp;
949  if (!isFloatingPointZero(RHS))
950    Cmp = DAG.getNode(ARMISD::CMPFP, MVT::Flag, LHS, RHS);
951  else
952    Cmp = DAG.getNode(ARMISD::CMPFPw0, MVT::Flag, LHS);
953  return DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp);
954}
955
956static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG,
957                                const ARMSubtarget *ST) {
958  MVT::ValueType VT = Op.getValueType();
959  SDOperand LHS = Op.getOperand(0);
960  SDOperand RHS = Op.getOperand(1);
961  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
962  SDOperand TrueVal = Op.getOperand(2);
963  SDOperand FalseVal = Op.getOperand(3);
964
965  if (LHS.getValueType() == MVT::i32) {
966    SDOperand ARMCC;
967    SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
968    return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, Cmp);
969  }
970
971  ARMCC::CondCodes CondCode, CondCode2;
972  if (FPCCToARMCC(CC, CondCode, CondCode2))
973    std::swap(TrueVal, FalseVal);
974
975  SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
976  SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
977  SDOperand Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal,
978                                 ARMCC, Cmp);
979  if (CondCode2 != ARMCC::AL) {
980    SDOperand ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
981    // FIXME: Needs another CMP because flag can have but one use.
982    SDOperand Cmp2 = getVFPCmp(LHS, RHS, DAG);
983    Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, Cmp2);
984  }
985  return Result;
986}
987
988static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG,
989                            const ARMSubtarget *ST) {
990  SDOperand  Chain = Op.getOperand(0);
991  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
992  SDOperand    LHS = Op.getOperand(2);
993  SDOperand    RHS = Op.getOperand(3);
994  SDOperand   Dest = Op.getOperand(4);
995
996  if (LHS.getValueType() == MVT::i32) {
997    SDOperand ARMCC;
998    SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
999    return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, Cmp);
1000  }
1001
1002  assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1003  ARMCC::CondCodes CondCode, CondCode2;
1004  if (FPCCToARMCC(CC, CondCode, CondCode2))
1005    // Swap the LHS/RHS of the comparison if needed.
1006    std::swap(LHS, RHS);
1007
1008  SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
1009  SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
1010  SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1011  SDOperand Ops[] = { Chain, Dest, ARMCC, Cmp };
1012  SDOperand Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 4);
1013  if (CondCode2 != ARMCC::AL) {
1014    ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1015    SDOperand Ops[] = { Res, Dest, ARMCC, Res.getValue(1) };
1016    Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 4);
1017  }
1018  return Res;
1019}
1020
1021SDOperand ARMTargetLowering::LowerBR_JT(SDOperand Op, SelectionDAG &DAG) {
1022  SDOperand Chain = Op.getOperand(0);
1023  SDOperand Table = Op.getOperand(1);
1024  SDOperand Index = Op.getOperand(2);
1025
1026  MVT::ValueType PTy = getPointerTy();
1027  JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1028  ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1029  SDOperand UId =  DAG.getConstant(AFI->createJumpTableUId(), PTy);
1030  SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1031  Table = DAG.getNode(ARMISD::WrapperJT, MVT::i32, JTI, UId);
1032  Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy));
1033  SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1034  bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1035  Addr = DAG.getLoad(isPIC ? MVT::i32 : PTy, Chain, Addr, NULL, 0);
1036  Chain = Addr.getValue(1);
1037  if (isPIC)
1038    Addr = DAG.getNode(ISD::ADD, PTy, Addr, Table);
1039  return DAG.getNode(ARMISD::BR_JT, MVT::Other, Chain, Addr, JTI, UId);
1040}
1041
1042static SDOperand LowerFP_TO_INT(SDOperand Op, SelectionDAG &DAG) {
1043  unsigned Opc =
1044    Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1045  Op = DAG.getNode(Opc, MVT::f32, Op.getOperand(0));
1046  return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
1047}
1048
1049static SDOperand LowerINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
1050  MVT::ValueType VT = Op.getValueType();
1051  unsigned Opc =
1052    Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1053
1054  Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
1055  return DAG.getNode(Opc, VT, Op);
1056}
1057
1058static SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
1059  // Implement fcopysign with a fabs and a conditional fneg.
1060  SDOperand Tmp0 = Op.getOperand(0);
1061  SDOperand Tmp1 = Op.getOperand(1);
1062  MVT::ValueType VT = Op.getValueType();
1063  MVT::ValueType SrcVT = Tmp1.getValueType();
1064  SDOperand AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0);
1065  SDOperand Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG);
1066  SDOperand ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1067  return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, Cmp);
1068}
1069
1070static SDOperand LowerBIT_CONVERT(SDOperand Op, SelectionDAG &DAG) {
1071  // Turn f64->i64 into FMRRD.
1072  assert(Op.getValueType() == MVT::i64 &&
1073         Op.getOperand(0).getValueType() == MVT::f64);
1074
1075  Op = Op.getOperand(0);
1076  SDOperand Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32),
1077                              &Op, 1);
1078
1079  // Merge the pieces into a single i64 value.
1080  return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1));
1081}
1082
1083static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
1084  // FIXME: All this code is target-independent.  Create a new target-indep
1085  // MULHILO node and move this code to the legalizer.
1086  //
1087  assert(Op.getValueType() == MVT::i64 && "Only handles i64 expand right now!");
1088
1089  SDOperand LL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1090                             DAG.getConstant(0, MVT::i32));
1091  SDOperand RL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(1),
1092                             DAG.getConstant(0, MVT::i32));
1093
1094  const TargetLowering &TL = DAG.getTargetLoweringInfo();
1095  unsigned LHSSB = TL.ComputeNumSignBits(Op.getOperand(0));
1096  unsigned RHSSB = TL.ComputeNumSignBits(Op.getOperand(1));
1097
1098  SDOperand Lo, Hi;
1099  // Figure out how to lower this multiply.
1100  if (LHSSB >= 33 && RHSSB >= 33) {
1101    // If the input values are both sign extended, we can emit a mulhs+mul.
1102    Lo = DAG.getNode(ISD::MUL, MVT::i32, LL, RL);
1103    Hi = DAG.getNode(ISD::MULHS, MVT::i32, LL, RL);
1104  } else if (LHSSB == 32 && RHSSB == 32 &&
1105             TL.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) &&
1106             TL.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) {
1107    // If the inputs are zero extended, use mulhu.
1108    Lo = DAG.getNode(ISD::MUL, MVT::i32, LL, RL);
1109    Hi = DAG.getNode(ISD::MULHU, MVT::i32, LL, RL);
1110  } else {
1111    SDOperand LH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1112                               DAG.getConstant(1, MVT::i32));
1113    SDOperand RH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(1),
1114                               DAG.getConstant(1, MVT::i32));
1115
1116    // Lo,Hi = umul LHS, RHS.
1117    SDOperand Ops[] = { LL, RL };
1118    SDOperand UMul64 = DAG.getNode(ARMISD::MULHILOU,
1119                                   DAG.getVTList(MVT::i32, MVT::i32), Ops, 2);
1120    Lo = UMul64;
1121    Hi = UMul64.getValue(1);
1122    RH = DAG.getNode(ISD::MUL, MVT::i32, LL, RH);
1123    LH = DAG.getNode(ISD::MUL, MVT::i32, LH, RL);
1124    Hi = DAG.getNode(ISD::ADD, MVT::i32, Hi, RH);
1125    Hi = DAG.getNode(ISD::ADD, MVT::i32, Hi, LH);
1126  }
1127
1128  // Merge the pieces into a single i64 value.
1129  return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
1130}
1131
1132static SDOperand LowerMULHU(SDOperand Op, SelectionDAG &DAG) {
1133  SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1) };
1134  return DAG.getNode(ARMISD::MULHILOU,
1135                     DAG.getVTList(MVT::i32, MVT::i32), Ops, 2).getValue(1);
1136}
1137
1138static SDOperand LowerMULHS(SDOperand Op, SelectionDAG &DAG) {
1139  SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1) };
1140  return DAG.getNode(ARMISD::MULHILOS,
1141                     DAG.getVTList(MVT::i32, MVT::i32), Ops, 2).getValue(1);
1142}
1143
1144static SDOperand LowerSRx(SDOperand Op, SelectionDAG &DAG,
1145                          const ARMSubtarget *ST) {
1146  assert(Op.getValueType() == MVT::i64 &&
1147         (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) &&
1148         "Unknown shift to lower!");
1149
1150  // We only lower SRA, SRL of 1 here, all others use generic lowering.
1151  if (!isa<ConstantSDNode>(Op.getOperand(1)) ||
1152      cast<ConstantSDNode>(Op.getOperand(1))->getValue() != 1)
1153    return SDOperand();
1154
1155  // If we are in thumb mode, we don't have RRX.
1156  if (ST->isThumb()) return SDOperand();
1157
1158  // Okay, we have a 64-bit SRA or SRL of 1.  Lower this to an RRX expr.
1159  SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1160                             DAG.getConstant(0, MVT::i32));
1161  SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1162                             DAG.getConstant(1, MVT::i32));
1163
1164  // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
1165  // captures the result into a carry flag.
1166  unsigned Opc = Op.getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
1167  Hi = DAG.getNode(Opc, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
1168
1169  // The low part is an ARMISD::RRX operand, which shifts the carry in.
1170  Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1));
1171
1172  // Merge the pieces into a single i64 value.
1173  return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
1174}
1175
1176SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
1177  switch (Op.getOpcode()) {
1178  default: assert(0 && "Don't know how to custom lower this!"); abort();
1179  case ISD::ConstantPool:  return LowerConstantPool(Op, DAG);
1180  case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
1181  case ISD::CALL:          return LowerCALL(Op, DAG);
1182  case ISD::RET:           return LowerRET(Op, DAG);
1183  case ISD::SELECT_CC:     return LowerSELECT_CC(Op, DAG, Subtarget);
1184  case ISD::BR_CC:         return LowerBR_CC(Op, DAG, Subtarget);
1185  case ISD::BR_JT:         return LowerBR_JT(Op, DAG);
1186  case ISD::VASTART:       return LowerVASTART(Op, DAG, VarArgsFrameIndex);
1187  case ISD::SINT_TO_FP:
1188  case ISD::UINT_TO_FP:    return LowerINT_TO_FP(Op, DAG);
1189  case ISD::FP_TO_SINT:
1190  case ISD::FP_TO_UINT:    return LowerFP_TO_INT(Op, DAG);
1191  case ISD::FCOPYSIGN:     return LowerFCOPYSIGN(Op, DAG);
1192  case ISD::BIT_CONVERT:   return LowerBIT_CONVERT(Op, DAG);
1193  case ISD::MUL:           return LowerMUL(Op, DAG);
1194  case ISD::MULHU:         return LowerMULHU(Op, DAG);
1195  case ISD::MULHS:         return LowerMULHS(Op, DAG);
1196  case ISD::SRL:
1197  case ISD::SRA:           return LowerSRx(Op, DAG, Subtarget);
1198  case ISD::FORMAL_ARGUMENTS:
1199    return LowerFORMAL_ARGUMENTS(Op, DAG);
1200  case ISD::RETURNADDR:    break;
1201  case ISD::FRAMEADDR:     break;
1202  }
1203  return SDOperand();
1204}
1205
1206//===----------------------------------------------------------------------===//
1207//                           ARM Scheduler Hooks
1208//===----------------------------------------------------------------------===//
1209
1210MachineBasicBlock *
1211ARMTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
1212                                           MachineBasicBlock *BB) {
1213  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1214  switch (MI->getOpcode()) {
1215  default: assert(false && "Unexpected instr type to insert");
1216  case ARM::tMOVCCr: {
1217    // To "insert" a SELECT_CC instruction, we actually have to insert the
1218    // diamond control-flow pattern.  The incoming instruction knows the
1219    // destination vreg to set, the condition code register to branch on, the
1220    // true/false values to select between, and a branch opcode to use.
1221    const BasicBlock *LLVM_BB = BB->getBasicBlock();
1222    ilist<MachineBasicBlock>::iterator It = BB;
1223    ++It;
1224
1225    //  thisMBB:
1226    //  ...
1227    //   TrueVal = ...
1228    //   cmpTY ccX, r1, r2
1229    //   bCC copy1MBB
1230    //   fallthrough --> copy0MBB
1231    MachineBasicBlock *thisMBB  = BB;
1232    MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
1233    MachineBasicBlock *sinkMBB  = new MachineBasicBlock(LLVM_BB);
1234    BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB)
1235      .addImm(MI->getOperand(3).getImm());
1236    MachineFunction *F = BB->getParent();
1237    F->getBasicBlockList().insert(It, copy0MBB);
1238    F->getBasicBlockList().insert(It, sinkMBB);
1239    // Update machine-CFG edges by first adding all successors of the current
1240    // block to the new block which will contain the Phi node for the select.
1241    for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
1242        e = BB->succ_end(); i != e; ++i)
1243      sinkMBB->addSuccessor(*i);
1244    // Next, remove all successors of the current block, and add the true
1245    // and fallthrough blocks as its successors.
1246    while(!BB->succ_empty())
1247      BB->removeSuccessor(BB->succ_begin());
1248    BB->addSuccessor(copy0MBB);
1249    BB->addSuccessor(sinkMBB);
1250
1251    //  copy0MBB:
1252    //   %FalseValue = ...
1253    //   # fallthrough to sinkMBB
1254    BB = copy0MBB;
1255
1256    // Update machine-CFG edges
1257    BB->addSuccessor(sinkMBB);
1258
1259    //  sinkMBB:
1260    //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1261    //  ...
1262    BB = sinkMBB;
1263    BuildMI(BB, TII->get(ARM::PHI), MI->getOperand(0).getReg())
1264      .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
1265      .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1266
1267    delete MI;   // The pseudo instruction is gone now.
1268    return BB;
1269  }
1270  }
1271}
1272
1273//===----------------------------------------------------------------------===//
1274//                           ARM Optimization Hooks
1275//===----------------------------------------------------------------------===//
1276
1277/// isLegalAddressExpression - Return true if the binary expression made up of
1278/// specified opcode, operands, and type can be folded into target addressing
1279/// mode for load / store of the given type.
1280bool ARMTargetLowering::isLegalAddressExpression(unsigned Opc, Value *Op0,
1281                                             Value *Op1, const Type *Ty) const {
1282  if (ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) {
1283    if (Opc == Instruction::Add)
1284      return isLegalAddressImmediate(Op1C->getSExtValue(), Ty);
1285    if (Opc == Instruction::Sub)
1286      return isLegalAddressImmediate(-Op1C->getSExtValue(), Ty);
1287  }
1288  return false;
1289}
1290
1291/// isLegalAddressImmediate - Return true if the integer value can be used
1292/// as the offset of the target addressing mode for load / store of the
1293/// given type.
1294bool ARMTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
1295  if (V == 0)
1296    return true;
1297
1298  MVT::ValueType VT = getValueType(Ty);
1299  if (Subtarget->isThumb()) {
1300    if (V < 0)
1301      return false;
1302
1303    unsigned Scale = 1;
1304    switch (VT) {
1305    default: return false;
1306    case MVT::i1:
1307    case MVT::i8:
1308      // Scale == 1;
1309      break;
1310    case MVT::i16:
1311      // Scale == 2;
1312      Scale = 2;
1313      break;
1314    case MVT::i32:
1315      // Scale == 4;
1316      Scale = 4;
1317      break;
1318    }
1319
1320    if ((V & (Scale - 1)) != 0)
1321      return false;
1322    V /= Scale;
1323    return V == V & ((1LL << 5) - 1);
1324  }
1325
1326  if (V < 0)
1327    V = - V;
1328  switch (VT) {
1329  default: return false;
1330  case MVT::i1:
1331  case MVT::i8:
1332  case MVT::i32:
1333    // +- imm12
1334    return V == V & ((1LL << 12) - 1);
1335  case MVT::i16:
1336    // +- imm8
1337    return V == V & ((1LL << 8) - 1);
1338  case MVT::f32:
1339  case MVT::f64:
1340    if (!Subtarget->hasVFP2())
1341      return false;
1342    if ((V % 3) != 0)
1343      return false;
1344    V >>= 2;
1345    return V == V & ((1LL << 8) - 1);
1346  }
1347}
1348
1349bool ARMTargetLowering::isLegalAddressImmediate(GlobalValue *GV) const {
1350  return false;
1351}
1352
1353/// isLegalAddressScale - Return true if the integer value can be used as
1354/// the scale of the target addressing mode for load / store of the given
1355/// type.
1356bool ARMTargetLowering::isLegalAddressScale(int64_t S, const Type *Ty) const {
1357  if (Subtarget->isThumb())
1358    return false;
1359
1360  MVT::ValueType VT = getValueType(Ty);
1361  switch (VT) {
1362  default: return false;
1363  case MVT::i1:
1364  case MVT::i8:
1365  case MVT::i32:
1366    // r + r
1367    if (S == 2)
1368      return true;
1369    // r + r << imm
1370    S &= ~1;
1371    return isPowerOf2_32(S);
1372  }
1373}
1374
1375static bool getIndexedAddressParts(SDNode *Ptr, MVT::ValueType VT,
1376                                   bool isSEXTLoad, SDOperand &Base,
1377                                   SDOperand &Offset, bool &isInc,
1378                                   SelectionDAG &DAG) {
1379  if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
1380    return false;
1381
1382  if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
1383    // AddressingMode 3
1384    Base = Ptr->getOperand(0);
1385    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1386      int RHSC = (int)RHS->getValue();
1387      if (RHSC < 0 && RHSC > -256) {
1388        isInc = false;
1389        Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1390        return true;
1391      }
1392    }
1393    isInc = (Ptr->getOpcode() == ISD::ADD);
1394    Offset = Ptr->getOperand(1);
1395    return true;
1396  } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
1397    // AddressingMode 2
1398    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1399      int RHSC = (int)RHS->getValue();
1400      if (RHSC < 0 && RHSC > -0x1000) {
1401        isInc = false;
1402        Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1403        Base = Ptr->getOperand(0);
1404        return true;
1405      }
1406    }
1407
1408    if (Ptr->getOpcode() == ISD::ADD) {
1409      isInc = true;
1410      ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
1411      if (ShOpcVal != ARM_AM::no_shift) {
1412        Base = Ptr->getOperand(1);
1413        Offset = Ptr->getOperand(0);
1414      } else {
1415        Base = Ptr->getOperand(0);
1416        Offset = Ptr->getOperand(1);
1417      }
1418      return true;
1419    }
1420
1421    isInc = (Ptr->getOpcode() == ISD::ADD);
1422    Base = Ptr->getOperand(0);
1423    Offset = Ptr->getOperand(1);
1424    return true;
1425  }
1426
1427  // FIXME: Use FLDM / FSTM to emulate indexed FP load / store.
1428  return false;
1429}
1430
1431/// getPreIndexedAddressParts - returns true by value, base pointer and
1432/// offset pointer and addressing mode by reference if the node's address
1433/// can be legally represented as pre-indexed load / store address.
1434bool
1435ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
1436                                             SDOperand &Offset,
1437                                             ISD::MemIndexedMode &AM,
1438                                             SelectionDAG &DAG) {
1439  if (Subtarget->isThumb())
1440    return false;
1441
1442  MVT::ValueType VT;
1443  SDOperand Ptr;
1444  bool isSEXTLoad = false;
1445  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1446    Ptr = LD->getBasePtr();
1447    VT  = LD->getLoadedVT();
1448    isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1449  } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1450    Ptr = ST->getBasePtr();
1451    VT  = ST->getStoredVT();
1452  } else
1453    return false;
1454
1455  bool isInc;
1456  bool isLegal = getIndexedAddressParts(Ptr.Val, VT, isSEXTLoad, Base, Offset,
1457                                        isInc, DAG);
1458  if (isLegal) {
1459    AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
1460    return true;
1461  }
1462  return false;
1463}
1464
1465/// getPostIndexedAddressParts - returns true by value, base pointer and
1466/// offset pointer and addressing mode by reference if this node can be
1467/// combined with a load / store to form a post-indexed load / store.
1468bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1469                                                   SDOperand &Base,
1470                                                   SDOperand &Offset,
1471                                                   ISD::MemIndexedMode &AM,
1472                                                   SelectionDAG &DAG) {
1473  if (Subtarget->isThumb())
1474    return false;
1475
1476  MVT::ValueType VT;
1477  SDOperand Ptr;
1478  bool isSEXTLoad = false;
1479  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1480    VT  = LD->getLoadedVT();
1481    isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1482  } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1483    VT  = ST->getStoredVT();
1484  } else
1485    return false;
1486
1487  bool isInc;
1488  bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
1489                                        isInc, DAG);
1490  if (isLegal) {
1491    AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
1492    return true;
1493  }
1494  return false;
1495}
1496
1497void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
1498                                                       uint64_t Mask,
1499                                                       uint64_t &KnownZero,
1500                                                       uint64_t &KnownOne,
1501                                                       unsigned Depth) const {
1502  KnownZero = 0;
1503  KnownOne = 0;
1504  switch (Op.getOpcode()) {
1505  default: break;
1506  case ARMISD::CMOV: {
1507    // Bits are known zero/one if known on the LHS and RHS.
1508    ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
1509    if (KnownZero == 0 && KnownOne == 0) return;
1510
1511    uint64_t KnownZeroRHS, KnownOneRHS;
1512    ComputeMaskedBits(Op.getOperand(1), Mask,
1513                      KnownZeroRHS, KnownOneRHS, Depth+1);
1514    KnownZero &= KnownZeroRHS;
1515    KnownOne  &= KnownOneRHS;
1516    return;
1517  }
1518  }
1519}
1520
1521//===----------------------------------------------------------------------===//
1522//                           ARM Inline Assembly Support
1523//===----------------------------------------------------------------------===//
1524
1525/// getConstraintType - Given a constraint letter, return the type of
1526/// constraint it is for this target.
1527ARMTargetLowering::ConstraintType
1528ARMTargetLowering::getConstraintType(char ConstraintLetter) const {
1529  switch (ConstraintLetter) {
1530    case 'l':
1531      return C_RegisterClass;
1532    default: return TargetLowering::getConstraintType(ConstraintLetter);
1533  }
1534}
1535
1536std::pair<unsigned, const TargetRegisterClass*>
1537ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
1538                                                MVT::ValueType VT) const {
1539  if (Constraint.size() == 1) {
1540    // GCC RS6000 Constraint Letters
1541    switch (Constraint[0]) {
1542      case 'l':
1543      // FIXME: in thumb mode, 'l' is only low-regs.
1544      // FALL THROUGH.
1545      case 'r':
1546        return std::make_pair(0U, ARM::GPRRegisterClass);
1547        break;
1548    }
1549  }
1550  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1551}
1552
1553std::vector<unsigned> ARMTargetLowering::
1554getRegClassForInlineAsmConstraint(const std::string &Constraint,
1555                                  MVT::ValueType VT) const {
1556  if (Constraint.size() != 1)
1557    return std::vector<unsigned>();
1558
1559  switch (Constraint[0]) {      // GCC ARM Constraint Letters
1560  default: break;
1561  case 'l':
1562  case 'r':
1563    return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1564                                 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1565                                 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1566                                 ARM::R12, ARM::LR, 0);
1567  }
1568
1569  return std::vector<unsigned>();
1570}
1571