ARMISelLowering.cpp revision 5a3d40d88fbfe79ad7ed5802ff4fd1498c4c820b 
1//===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Evan Cheng and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "ARM.h"
16#include "ARMAddressingModes.h"
17#include "ARMConstantPoolValue.h"
18#include "ARMISelLowering.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMRegisterInfo.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/CallingConv.h"
24#include "llvm/Constants.h"
25#include "llvm/Instruction.h"
26#include "llvm/CodeGen/MachineBasicBlock.h"
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineFunction.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/SelectionDAG.h"
31#include "llvm/CodeGen/SSARegMap.h"
32#include "llvm/Target/TargetOptions.h"
33#include "llvm/ADT/VectorExtras.h"
34#include "llvm/Support/MathExtras.h"
35using namespace llvm;
36
37ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
38    : TargetLowering(TM), ARMPCLabelIndex(0) {
39  Subtarget = &TM.getSubtarget<ARMSubtarget>();
40
41  // Uses VFP for Thumb libfuncs if available.
42  if (!UseSoftFloat && Subtarget->isThumb() && Subtarget->hasVFP2()) {
43    // Single-precision floating-point arithmetic.
44    setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
45    setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
46    setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
47    setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
48
49    // Double-precision floating-point arithmetic.
50    setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
51    setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
52    setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
53    setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
54
55    // Single-precision comparisons.
56    setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
57    setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
58    setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
59    setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
60    setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
61    setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
62    setLibcallName(RTLIB::UO_F32,  "__unordsf2vfp");
63    setLibcallName(RTLIB::O_F32,   "__unordsf2vfp");
64
65    setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
66    setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
67    setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
68    setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
69    setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
70    setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
71    setCmpLibcallCC(RTLIB::UO_F32,  ISD::SETNE);
72    setCmpLibcallCC(RTLIB::O_F32,   ISD::SETEQ);
73
74    // Double-precision comparisons.
75    setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
76    setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
77    setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
78    setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
79    setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
80    setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
81    setLibcallName(RTLIB::UO_F64,  "__unorddf2vfp");
82    setLibcallName(RTLIB::O_F64,   "__unorddf2vfp");
83
84    setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
85    setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
86    setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
87    setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
88    setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
89    setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
90    setCmpLibcallCC(RTLIB::UO_F64,  ISD::SETNE);
91    setCmpLibcallCC(RTLIB::O_F64,   ISD::SETEQ);
92
93    // Floating-point to integer conversions.
94    // i64 conversions are done via library routines even when generating VFP
95    // instructions, so use the same ones.
96    setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
97    setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
98    setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
99    setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
100
101    // Conversions between floating types.
102    setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
103    setLibcallName(RTLIB::FPEXT_F32_F64,   "__extendsfdf2vfp");
104
105    // Integer to floating-point conversions.
106    // i64 conversions are done via library routines even when generating VFP
107    // instructions, so use the same ones.
108    // FIXME: There appears to be some naming inconsistency in ARM libgcc: e.g.
109    // __floatunsidf vs. __floatunssidfvfp.
110    setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
111    setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
112    setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
113    setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
114  }
115
116  addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
117  if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
118    addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
119    addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
120  }
121
122  // ARM does not have f32 extending load.
123  setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
124
125  // ARM supports all 4 flavors of integer indexed load / store.
126  for (unsigned im = (unsigned)ISD::PRE_INC;
127       im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
128    setIndexedLoadAction(im,  MVT::i1,  Legal);
129    setIndexedLoadAction(im,  MVT::i8,  Legal);
130    setIndexedLoadAction(im,  MVT::i16, Legal);
131    setIndexedLoadAction(im,  MVT::i32, Legal);
132    setIndexedStoreAction(im, MVT::i1,  Legal);
133    setIndexedStoreAction(im, MVT::i8,  Legal);
134    setIndexedStoreAction(im, MVT::i16, Legal);
135    setIndexedStoreAction(im, MVT::i32, Legal);
136  }
137
138  // i64 operation support.
139  if (Subtarget->isThumb()) {
140    setOperationAction(ISD::MUL,     MVT::i64, Expand);
141    setOperationAction(ISD::MULHU,   MVT::i32, Expand);
142    setOperationAction(ISD::MULHS,   MVT::i32, Expand);
143  } else {
144    setOperationAction(ISD::MUL,     MVT::i64, Custom);
145    setOperationAction(ISD::MULHU,   MVT::i32, Custom);
146    if (!Subtarget->hasV6Ops())
147      setOperationAction(ISD::MULHS, MVT::i32, Custom);
148  }
149  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
150  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
151  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
152  setOperationAction(ISD::SRL,       MVT::i64, Custom);
153  setOperationAction(ISD::SRA,       MVT::i64, Custom);
154
155  // ARM does not have ROTL.
156  setOperationAction(ISD::ROTL,  MVT::i32, Expand);
157  setOperationAction(ISD::CTTZ , MVT::i32, Expand);
158  setOperationAction(ISD::CTPOP, MVT::i32, Expand);
159  if (!Subtarget->hasV5TOps() || Subtarget->isThumb())
160    setOperationAction(ISD::CTLZ, MVT::i32, Expand);
161
162  // Only ARMv6 has BSWAP.
163  if (!Subtarget->hasV6Ops())
164    setOperationAction(ISD::BSWAP, MVT::i32, Expand);
165
166  // These are expanded into libcalls.
167  setOperationAction(ISD::SDIV,  MVT::i32, Expand);
168  setOperationAction(ISD::UDIV,  MVT::i32, Expand);
169  setOperationAction(ISD::SREM,  MVT::i32, Expand);
170  setOperationAction(ISD::UREM,  MVT::i32, Expand);
171
172  // Support label based line numbers.
173  setOperationAction(ISD::LOCATION, MVT::Other, Expand);
174  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
175  // FIXME - use subtarget debug flags
176  if (!Subtarget->isTargetDarwin())
177    setOperationAction(ISD::LABEL, MVT::Other, Expand);
178
179  setOperationAction(ISD::RET,           MVT::Other, Custom);
180  setOperationAction(ISD::GlobalAddress, MVT::i32,   Custom);
181  setOperationAction(ISD::ConstantPool,  MVT::i32,   Custom);
182
183  // Expand mem operations genericly.
184  setOperationAction(ISD::MEMSET          , MVT::Other, Expand);
185  setOperationAction(ISD::MEMCPY          , MVT::Other, Expand);
186  setOperationAction(ISD::MEMMOVE         , MVT::Other, Expand);
187
188  // Use the default implementation.
189  setOperationAction(ISD::VASTART           , MVT::Other, Expand);
190  setOperationAction(ISD::VAARG             , MVT::Other, Expand);
191  setOperationAction(ISD::VACOPY            , MVT::Other, Expand);
192  setOperationAction(ISD::VAEND             , MVT::Other, Expand);
193  setOperationAction(ISD::STACKSAVE,          MVT::Other, Expand);
194  setOperationAction(ISD::STACKRESTORE,       MVT::Other, Expand);
195  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Expand);
196
197  if (!Subtarget->hasV6Ops()) {
198    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
199    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8,  Expand);
200  }
201  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
202
203  if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb())
204    // Turn f64->i64 into FMRRD iff target supports vfp2.
205    setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
206
207  setOperationAction(ISD::SETCC    , MVT::i32, Expand);
208  setOperationAction(ISD::SETCC    , MVT::f32, Expand);
209  setOperationAction(ISD::SETCC    , MVT::f64, Expand);
210  setOperationAction(ISD::SELECT   , MVT::i32, Expand);
211  setOperationAction(ISD::SELECT   , MVT::f32, Expand);
212  setOperationAction(ISD::SELECT   , MVT::f64, Expand);
213  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
214  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
215  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
216
217  setOperationAction(ISD::BRCOND   , MVT::Other, Expand);
218  setOperationAction(ISD::BR_CC    , MVT::i32,   Custom);
219  setOperationAction(ISD::BR_CC    , MVT::f32,   Custom);
220  setOperationAction(ISD::BR_CC    , MVT::f64,   Custom);
221  setOperationAction(ISD::BR_JT    , MVT::Other, Custom);
222
223  setOperationAction(ISD::VASTART,       MVT::Other, Custom);
224  setOperationAction(ISD::VACOPY,        MVT::Other, Expand);
225  setOperationAction(ISD::VAEND,         MVT::Other, Expand);
226  setOperationAction(ISD::STACKSAVE,     MVT::Other, Expand);
227  setOperationAction(ISD::STACKRESTORE,  MVT::Other, Expand);
228
229  // FP Constants can't be immediates.
230  setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
231  setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
232
233  // We don't support sin/cos/fmod/copysign
234  setOperationAction(ISD::FSIN     , MVT::f64, Expand);
235  setOperationAction(ISD::FSIN     , MVT::f32, Expand);
236  setOperationAction(ISD::FCOS     , MVT::f32, Expand);
237  setOperationAction(ISD::FCOS     , MVT::f64, Expand);
238  setOperationAction(ISD::FREM     , MVT::f64, Expand);
239  setOperationAction(ISD::FREM     , MVT::f32, Expand);
240  setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
241  setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
242
243  // int <-> fp are custom expanded into bit_convert + ARMISD ops.
244  setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
245  setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
246  setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
247  setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
248
249  setStackPointerRegisterToSaveRestore(ARM::SP);
250
251  setSchedulingPreference(SchedulingForRegPressure);
252  computeRegisterProperties();
253}
254
255
256const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
257  switch (Opcode) {
258  default: return 0;
259  case ARMISD::Wrapper:       return "ARMISD::Wrapper";
260  case ARMISD::WrapperJT:     return "ARMISD::WrapperJT";
261  case ARMISD::CALL:          return "ARMISD::CALL";
262  case ARMISD::CALL_NOLINK:   return "ARMISD::CALL_NOLINK";
263  case ARMISD::tCALL:         return "ARMISD::tCALL";
264  case ARMISD::BRCOND:        return "ARMISD::BRCOND";
265  case ARMISD::BR_JT:         return "ARMISD::BR_JT";
266  case ARMISD::RET_FLAG:      return "ARMISD::RET_FLAG";
267  case ARMISD::PIC_ADD:       return "ARMISD::PIC_ADD";
268  case ARMISD::CMP:           return "ARMISD::CMP";
269  case ARMISD::CMPNZ:         return "ARMISD::CMPNZ";
270  case ARMISD::CMPFP:         return "ARMISD::CMPFP";
271  case ARMISD::CMPFPw0:       return "ARMISD::CMPFPw0";
272  case ARMISD::FMSTAT:        return "ARMISD::FMSTAT";
273  case ARMISD::CMOV:          return "ARMISD::CMOV";
274  case ARMISD::CNEG:          return "ARMISD::CNEG";
275
276  case ARMISD::FTOSI:         return "ARMISD::FTOSI";
277  case ARMISD::FTOUI:         return "ARMISD::FTOUI";
278  case ARMISD::SITOF:         return "ARMISD::SITOF";
279  case ARMISD::UITOF:         return "ARMISD::UITOF";
280  case ARMISD::MULHILOU:      return "ARMISD::MULHILOU";
281  case ARMISD::MULHILOS:      return "ARMISD::MULHILOS";
282
283  case ARMISD::SRL_FLAG:      return "ARMISD::SRL_FLAG";
284  case ARMISD::SRA_FLAG:      return "ARMISD::SRA_FLAG";
285  case ARMISD::RRX:           return "ARMISD::RRX";
286
287  case ARMISD::FMRRD:         return "ARMISD::FMRRD";
288  case ARMISD::FMDRR:         return "ARMISD::FMDRR";
289  }
290}
291
292//===----------------------------------------------------------------------===//
293// Lowering Code
294//===----------------------------------------------------------------------===//
295
296
297/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
298static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
299  switch (CC) {
300  default: assert(0 && "Unknown condition code!");
301  case ISD::SETNE:  return ARMCC::NE;
302  case ISD::SETEQ:  return ARMCC::EQ;
303  case ISD::SETGT:  return ARMCC::GT;
304  case ISD::SETGE:  return ARMCC::GE;
305  case ISD::SETLT:  return ARMCC::LT;
306  case ISD::SETLE:  return ARMCC::LE;
307  case ISD::SETUGT: return ARMCC::HI;
308  case ISD::SETUGE: return ARMCC::HS;
309  case ISD::SETULT: return ARMCC::LO;
310  case ISD::SETULE: return ARMCC::LS;
311  }
312}
313
314/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It
315/// returns true if the operands should be inverted to form the proper
316/// comparison.
317static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
318                        ARMCC::CondCodes &CondCode2) {
319  bool Invert = false;
320  CondCode2 = ARMCC::AL;
321  switch (CC) {
322  default: assert(0 && "Unknown FP condition!");
323  case ISD::SETEQ:
324  case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
325  case ISD::SETGT:
326  case ISD::SETOGT: CondCode = ARMCC::GT; break;
327  case ISD::SETGE:
328  case ISD::SETOGE: CondCode = ARMCC::GE; break;
329  case ISD::SETOLT: CondCode = ARMCC::MI; break;
330  case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break;
331  case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
332  case ISD::SETO:   CondCode = ARMCC::VC; break;
333  case ISD::SETUO:  CondCode = ARMCC::VS; break;
334  case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
335  case ISD::SETUGT: CondCode = ARMCC::HI; break;
336  case ISD::SETUGE: CondCode = ARMCC::PL; break;
337  case ISD::SETLT:
338  case ISD::SETULT: CondCode = ARMCC::LT; break;
339  case ISD::SETLE:
340  case ISD::SETULE: CondCode = ARMCC::LE; break;
341  case ISD::SETNE:
342  case ISD::SETUNE: CondCode = ARMCC::NE; break;
343  }
344  return Invert;
345}
346
347static void
348HowToPassArgument(MVT::ValueType ObjectVT, unsigned NumGPRs,
349                  unsigned StackOffset, unsigned &NeededGPRs,
350                  unsigned &NeededStackSize, unsigned &GPRPad,
351                  unsigned &StackPad, unsigned Flags) {
352  NeededStackSize = 0;
353  NeededGPRs = 0;
354  StackPad = 0;
355  GPRPad = 0;
356  unsigned align = (Flags >> ISD::ParamFlags::OrigAlignmentOffs);
357  GPRPad = NumGPRs % ((align + 3)/4);
358  StackPad = StackOffset % align;
359  unsigned firstGPR = NumGPRs + GPRPad;
360  switch (ObjectVT) {
361  default: assert(0 && "Unhandled argument type!");
362  case MVT::i32:
363  case MVT::f32:
364    if (firstGPR < 4)
365      NeededGPRs = 1;
366    else
367      NeededStackSize = 4;
368    break;
369  case MVT::i64:
370  case MVT::f64:
371    if (firstGPR < 3)
372      NeededGPRs = 2;
373    else if (firstGPR == 3) {
374      NeededGPRs = 1;
375      NeededStackSize = 4;
376    } else
377      NeededStackSize = 8;
378  }
379}
380
381/// LowerCALL - Lowering a ISD::CALL node into a callseq_start <-
382/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
383/// nodes.
384SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
385  MVT::ValueType RetVT= Op.Val->getValueType(0);
386  SDOperand Chain    = Op.getOperand(0);
387  unsigned CallConv  = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
388  assert((CallConv == CallingConv::C ||
389          CallConv == CallingConv::Fast) && "unknown calling convention");
390  SDOperand Callee   = Op.getOperand(4);
391  unsigned NumOps    = (Op.getNumOperands() - 5) / 2;
392  unsigned ArgOffset = 0;   // Frame mechanisms handle retaddr slot
393  unsigned NumGPRs = 0;     // GPRs used for parameter passing.
394
395  // Count how many bytes are to be pushed on the stack.
396  unsigned NumBytes = 0;
397
398  // Add up all the space actually used.
399  for (unsigned i = 0; i < NumOps; ++i) {
400    unsigned ObjSize;
401    unsigned ObjGPRs;
402    unsigned StackPad;
403    unsigned GPRPad;
404    MVT::ValueType ObjectVT = Op.getOperand(5+2*i).getValueType();
405    unsigned Flags = Op.getConstantOperandVal(5+2*i+1);
406    HowToPassArgument(ObjectVT, NumGPRs, NumBytes, ObjGPRs, ObjSize,
407                      GPRPad, StackPad, Flags);
408    NumBytes += ObjSize + StackPad;
409    NumGPRs += ObjGPRs + GPRPad;
410  }
411
412  // Adjust the stack pointer for the new arguments...
413  // These operations are automatically eliminated by the prolog/epilog pass
414  Chain = DAG.getCALLSEQ_START(Chain,
415                               DAG.getConstant(NumBytes, MVT::i32));
416
417  SDOperand StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
418
419  static const unsigned GPRArgRegs[] = {
420    ARM::R0, ARM::R1, ARM::R2, ARM::R3
421  };
422
423  NumGPRs = 0;
424  std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
425  std::vector<SDOperand> MemOpChains;
426  for (unsigned i = 0; i != NumOps; ++i) {
427    SDOperand Arg = Op.getOperand(5+2*i);
428    unsigned Flags = Op.getConstantOperandVal(5+2*i+1);
429    MVT::ValueType ArgVT = Arg.getValueType();
430
431    unsigned ObjSize;
432    unsigned ObjGPRs;
433    unsigned GPRPad;
434    unsigned StackPad;
435    HowToPassArgument(ArgVT, NumGPRs, ArgOffset, ObjGPRs,
436                      ObjSize, GPRPad, StackPad, Flags);
437    NumGPRs += GPRPad;
438    ArgOffset += StackPad;
439    if (ObjGPRs > 0) {
440      switch (ArgVT) {
441      default: assert(0 && "Unexpected ValueType for argument!");
442      case MVT::i32:
443        RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Arg));
444        break;
445      case MVT::f32:
446        RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs],
447                                 DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg)));
448        break;
449      case MVT::i64: {
450        SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
451                                   DAG.getConstant(0, getPointerTy()));
452        SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
453                                   DAG.getConstant(1, getPointerTy()));
454        RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo));
455        if (ObjGPRs == 2)
456          RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi));
457        else {
458          SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
459          PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
460          MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0));
461        }
462        break;
463      }
464      case MVT::f64: {
465        SDOperand Cvt = DAG.getNode(ARMISD::FMRRD,
466                                    DAG.getVTList(MVT::i32, MVT::i32),
467                                    &Arg, 1);
468        RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Cvt));
469        if (ObjGPRs == 2)
470          RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1],
471                                              Cvt.getValue(1)));
472        else {
473          SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
474          PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
475          MemOpChains.push_back(DAG.getStore(Chain, Cvt.getValue(1), PtrOff,
476                                             NULL, 0));
477        }
478        break;
479      }
480      }
481    } else {
482      assert(ObjSize != 0);
483      SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
484      PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
485      MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
486    }
487
488    NumGPRs += ObjGPRs;
489    ArgOffset += ObjSize;
490  }
491
492  if (!MemOpChains.empty())
493    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
494                        &MemOpChains[0], MemOpChains.size());
495
496  // Build a sequence of copy-to-reg nodes chained together with token chain
497  // and flag operands which copy the outgoing args into the appropriate regs.
498  SDOperand InFlag;
499  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
500    Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
501                             InFlag);
502    InFlag = Chain.getValue(1);
503  }
504
505  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
506  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
507  // node so that legalize doesn't hack it.
508  bool isDirect = false;
509  bool isARMFunc = false;
510  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
511    GlobalValue *GV = G->getGlobal();
512    isDirect = true;
513    bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() ||
514                  GV->hasLinkOnceLinkage());
515    bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
516                   getTargetMachine().getRelocationModel() != Reloc::Static;
517    isARMFunc = !Subtarget->isThumb() || isStub;
518    // tBX takes a register source operand.
519    if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
520      ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
521                                                           ARMCP::CPStub, 4);
522      SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
523      CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
524      Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
525      SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
526      Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
527   } else
528      Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
529  } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
530    isDirect = true;
531    bool isStub = Subtarget->isTargetDarwin() &&
532                  getTargetMachine().getRelocationModel() != Reloc::Static;
533    isARMFunc = !Subtarget->isThumb() || isStub;
534    // tBX takes a register source operand.
535    const char *Sym = S->getSymbol();
536    if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
537      ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
538                                                           ARMCP::CPStub, 4);
539      SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
540      CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
541      Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
542      SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
543      Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
544    } else
545      Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
546  }
547
548  // FIXME: handle tail calls differently.
549  unsigned CallOpc;
550  if (Subtarget->isThumb()) {
551    if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc))
552      CallOpc = ARMISD::CALL_NOLINK;
553    else
554      CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
555  } else {
556    CallOpc = (isDirect || Subtarget->hasV5TOps())
557      ? ARMISD::CALL : ARMISD::CALL_NOLINK;
558  }
559  if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) {
560    // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
561    Chain = DAG.getCopyToReg(Chain, ARM::LR,
562                             DAG.getNode(ISD::UNDEF, MVT::i32), InFlag);
563    InFlag = Chain.getValue(1);
564  }
565
566  std::vector<MVT::ValueType> NodeTys;
567  NodeTys.push_back(MVT::Other);   // Returns a chain
568  NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
569
570  std::vector<SDOperand> Ops;
571  Ops.push_back(Chain);
572  Ops.push_back(Callee);
573
574  // Add argument registers to the end of the list so that they are known live
575  // into the call.
576  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
577    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
578                                  RegsToPass[i].second.getValueType()));
579
580  if (InFlag.Val)
581    Ops.push_back(InFlag);
582  Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
583  InFlag = Chain.getValue(1);
584
585  SDOperand CSOps[] = { Chain, DAG.getConstant(NumBytes, MVT::i32), InFlag };
586  Chain = DAG.getNode(ISD::CALLSEQ_END,
587                      DAG.getNodeValueTypes(MVT::Other, MVT::Flag),
588                      ((RetVT != MVT::Other) ? 2 : 1), CSOps, 3);
589  if (RetVT != MVT::Other)
590    InFlag = Chain.getValue(1);
591
592  std::vector<SDOperand> ResultVals;
593  NodeTys.clear();
594
595  // If the call has results, copy the values out of the ret val registers.
596  switch (RetVT) {
597  default: assert(0 && "Unexpected ret value!");
598  case MVT::Other:
599    break;
600  case MVT::i32:
601    Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
602    ResultVals.push_back(Chain.getValue(0));
603    if (Op.Val->getValueType(1) == MVT::i32) {
604      // Returns a i64 value.
605      Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32,
606                                 Chain.getValue(2)).getValue(1);
607      ResultVals.push_back(Chain.getValue(0));
608      NodeTys.push_back(MVT::i32);
609    }
610    NodeTys.push_back(MVT::i32);
611    break;
612  case MVT::f32:
613    Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
614    ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f32,
615                                     Chain.getValue(0)));
616    NodeTys.push_back(MVT::f32);
617    break;
618  case MVT::f64: {
619    SDOperand Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag);
620    SDOperand Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2));
621    ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi));
622    NodeTys.push_back(MVT::f64);
623    break;
624  }
625  }
626
627  NodeTys.push_back(MVT::Other);
628
629  if (ResultVals.empty())
630    return Chain;
631
632  ResultVals.push_back(Chain);
633  SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, &ResultVals[0],
634                              ResultVals.size());
635  return Res.getValue(Op.ResNo);
636}
637
638static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
639  SDOperand Copy;
640  SDOperand Chain = Op.getOperand(0);
641  switch(Op.getNumOperands()) {
642  default:
643    assert(0 && "Do not know how to return this many arguments!");
644    abort();
645  case 1: {
646    SDOperand LR = DAG.getRegister(ARM::LR, MVT::i32);
647    return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain);
648  }
649  case 3:
650    Op = Op.getOperand(1);
651    if (Op.getValueType() == MVT::f32) {
652      Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
653    } else if (Op.getValueType() == MVT::f64) {
654      // Recursively legalize f64 -> i64.
655      Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Op);
656      return DAG.getNode(ISD::RET, MVT::Other, Chain, Op,
657                         DAG.getConstant(0, MVT::i32));
658    }
659    Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDOperand());
660    if (DAG.getMachineFunction().liveout_empty())
661      DAG.getMachineFunction().addLiveOut(ARM::R0);
662    break;
663  case 5:
664    Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand());
665    Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1));
666    // If we haven't noted the R0+R1 are live out, do so now.
667    if (DAG.getMachineFunction().liveout_empty()) {
668      DAG.getMachineFunction().addLiveOut(ARM::R0);
669      DAG.getMachineFunction().addLiveOut(ARM::R1);
670    }
671    break;
672  }
673
674  //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag
675  return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
676}
677
678// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
679// their target countpart wrapped in the ARMISD::Wrapper node. Suppose N is
680// one of the above mentioned nodes. It has to be wrapped because otherwise
681// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
682// be used to form addressing mode. These wrapped nodes will be selected
683// into MOVi.
684static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
685  MVT::ValueType PtrVT = Op.getValueType();
686  ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
687  SDOperand Res;
688  if (CP->isMachineConstantPoolEntry())
689    Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
690                                    CP->getAlignment());
691  else
692    Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
693                                    CP->getAlignment());
694  return DAG.getNode(ARMISD::Wrapper, MVT::i32, Res);
695}
696
697/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol
698/// even in dynamic-no-pic mode.
699static bool GVIsIndirectSymbol(GlobalValue *GV) {
700  return (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
701          (GV->isDeclaration() && !GV->hasNotBeenReadFromBytecode()));
702}
703
704SDOperand ARMTargetLowering::LowerGlobalAddress(SDOperand Op,
705                                                SelectionDAG &DAG) {
706  MVT::ValueType PtrVT = getPointerTy();
707  GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
708  Reloc::Model RelocM = getTargetMachine().getRelocationModel();
709  bool IsIndirect = Subtarget->isTargetDarwin() && GVIsIndirectSymbol(GV);
710  SDOperand CPAddr;
711  if (RelocM == Reloc::Static)
712    CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
713  else {
714    unsigned PCAdj = (RelocM != Reloc::PIC_)
715      ? 0 : (Subtarget->isThumb() ? 4 : 8);
716    ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr
717      : ARMCP::CPValue;
718    ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
719                                                         Kind, PCAdj);
720    CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
721  }
722  CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
723
724  SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
725  SDOperand Chain = Result.getValue(1);
726
727  if (RelocM == Reloc::PIC_) {
728    SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
729    Result = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel);
730  }
731  if (IsIndirect)
732    Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0);
733
734  return Result;
735}
736
737static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
738                              unsigned VarArgsFrameIndex) {
739  // vastart just stores the address of the VarArgsFrameIndex slot into the
740  // memory location argument.
741  MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
742  SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
743  SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
744  return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(),
745                      SV->getOffset());
746}
747
748static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
749                                      unsigned *vRegs, unsigned ArgNo,
750                                      unsigned &NumGPRs, unsigned &ArgOffset) {
751  MachineFunction &MF = DAG.getMachineFunction();
752  MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
753  SDOperand Root = Op.getOperand(0);
754  std::vector<SDOperand> ArgValues;
755  SSARegMap *RegMap = MF.getSSARegMap();
756
757  static const unsigned GPRArgRegs[] = {
758    ARM::R0, ARM::R1, ARM::R2, ARM::R3
759  };
760
761  unsigned ObjSize;
762  unsigned ObjGPRs;
763  unsigned GPRPad;
764  unsigned StackPad;
765  unsigned Flags = Op.getConstantOperandVal(ArgNo + 3);
766  HowToPassArgument(ObjectVT, NumGPRs, ArgOffset, ObjGPRs,
767                    ObjSize, GPRPad, StackPad, Flags);
768  NumGPRs += GPRPad;
769  ArgOffset += StackPad;
770
771  SDOperand ArgValue;
772  if (ObjGPRs == 1) {
773    unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
774    MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
775    vRegs[NumGPRs] = VReg;
776    ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
777    if (ObjectVT == MVT::f32)
778      ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue);
779  } else if (ObjGPRs == 2) {
780    unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
781    MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
782    vRegs[NumGPRs] = VReg;
783    ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
784
785    VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
786    MF.addLiveIn(GPRArgRegs[NumGPRs+1], VReg);
787    vRegs[NumGPRs+1] = VReg;
788    SDOperand ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32);
789
790    if (ObjectVT == MVT::i64)
791      ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2);
792    else
793      ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
794  }
795  NumGPRs += ObjGPRs;
796
797  if (ObjSize) {
798    // If the argument is actually used, emit a load from the right stack
799    // slot.
800    if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
801      MachineFrameInfo *MFI = MF.getFrameInfo();
802      int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
803      SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
804      if (ObjGPRs == 0)
805        ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
806      else {
807        SDOperand ArgValue2 =
808          DAG.getLoad(MVT::i32, Root, FIN, NULL, 0);
809        if (ObjectVT == MVT::i64)
810          ArgValue= DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2);
811        else
812          ArgValue= DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
813      }
814    } else {
815      // Don't emit a dead load.
816      ArgValue = DAG.getNode(ISD::UNDEF, ObjectVT);
817    }
818
819    ArgOffset += ObjSize;   // Move on to the next argument.
820  }
821
822  return ArgValue;
823}
824
825SDOperand
826ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
827  std::vector<SDOperand> ArgValues;
828  SDOperand Root = Op.getOperand(0);
829  unsigned ArgOffset = 0;   // Frame mechanisms handle retaddr slot
830  unsigned NumGPRs = 0;     // GPRs used for parameter passing.
831  unsigned VRegs[4];
832
833  unsigned NumArgs = Op.Val->getNumValues()-1;
834  for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo)
835    ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, VRegs, ArgNo,
836                                             NumGPRs, ArgOffset));
837
838  bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
839  if (isVarArg) {
840    static const unsigned GPRArgRegs[] = {
841      ARM::R0, ARM::R1, ARM::R2, ARM::R3
842    };
843
844    MachineFunction &MF = DAG.getMachineFunction();
845    SSARegMap *RegMap = MF.getSSARegMap();
846    MachineFrameInfo *MFI = MF.getFrameInfo();
847    ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
848    unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
849    unsigned VARegSize = (4 - NumGPRs) * 4;
850    unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
851    if (VARegSaveSize) {
852      // If this function is vararg, store any remaining integer argument regs
853      // to their spots on the stack so that they may be loaded by deferencing
854      // the result of va_next.
855      AFI->setVarArgsRegSaveSize(VARegSaveSize);
856      VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
857                                                 VARegSaveSize - VARegSize);
858      SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
859
860      SmallVector<SDOperand, 4> MemOps;
861      for (; NumGPRs < 4; ++NumGPRs) {
862        unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
863        MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
864        SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
865        SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
866        MemOps.push_back(Store);
867        FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
868                          DAG.getConstant(4, getPointerTy()));
869      }
870      if (!MemOps.empty())
871        Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
872                           &MemOps[0], MemOps.size());
873    } else
874      // This will point to the next argument passed via stack.
875      VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
876  }
877
878  ArgValues.push_back(Root);
879
880  // Return the new list of results.
881  std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
882                                    Op.Val->value_end());
883  return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
884}
885
886/// isFloatingPointZero - Return true if this is +0.0.
887static bool isFloatingPointZero(SDOperand Op) {
888  if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
889    return CFP->isExactlyValue(0.0);
890  else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
891    // Maybe this has already been legalized into the constant pool?
892    if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
893      SDOperand WrapperOp = Op.getOperand(1).getOperand(0);
894      if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
895        if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
896          return CFP->isExactlyValue(0.0);
897    }
898  }
899  return false;
900}
901
902static bool isLegalCmpImmediate(unsigned C, bool isThumb) {
903  return ( isThumb && (C & ~255U) == 0) ||
904         (!isThumb && ARM_AM::getSOImmVal(C) != -1);
905}
906
907/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
908/// the given operands.
909static SDOperand getARMCmp(SDOperand LHS, SDOperand RHS, ISD::CondCode CC,
910                           SDOperand &ARMCC, SelectionDAG &DAG, bool isThumb) {
911  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.Val)) {
912    unsigned C = RHSC->getValue();
913    if (!isLegalCmpImmediate(C, isThumb)) {
914      // Constant does not fit, try adjusting it by one?
915      switch (CC) {
916      default: break;
917      case ISD::SETLT:
918      case ISD::SETGE:
919        if (isLegalCmpImmediate(C-1, isThumb)) {
920          CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
921          RHS = DAG.getConstant(C-1, MVT::i32);
922        }
923        break;
924      case ISD::SETULT:
925      case ISD::SETUGE:
926        if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) {
927          CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
928          RHS = DAG.getConstant(C-1, MVT::i32);
929        }
930        break;
931      case ISD::SETLE:
932      case ISD::SETGT:
933        if (isLegalCmpImmediate(C+1, isThumb)) {
934          CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
935          RHS = DAG.getConstant(C+1, MVT::i32);
936        }
937        break;
938      case ISD::SETULE:
939      case ISD::SETUGT:
940        if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb)) {
941          CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
942          RHS = DAG.getConstant(C+1, MVT::i32);
943        }
944        break;
945      }
946    }
947  }
948
949  ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
950  ARMISD::NodeType CompareType;
951  switch (CondCode) {
952  default:
953    CompareType = ARMISD::CMP;
954    break;
955  case ARMCC::EQ:
956  case ARMCC::NE:
957  case ARMCC::MI:
958  case ARMCC::PL:
959    // Uses only N and Z Flags
960    CompareType = ARMISD::CMPNZ;
961    break;
962  }
963  ARMCC = DAG.getConstant(CondCode, MVT::i32);
964  return DAG.getNode(CompareType, MVT::Flag, LHS, RHS);
965}
966
967/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
968static SDOperand getVFPCmp(SDOperand LHS, SDOperand RHS, SelectionDAG &DAG) {
969  SDOperand Cmp;
970  if (!isFloatingPointZero(RHS))
971    Cmp = DAG.getNode(ARMISD::CMPFP, MVT::Flag, LHS, RHS);
972  else
973    Cmp = DAG.getNode(ARMISD::CMPFPw0, MVT::Flag, LHS);
974  return DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp);
975}
976
977static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG,
978                                const ARMSubtarget *ST) {
979  MVT::ValueType VT = Op.getValueType();
980  SDOperand LHS = Op.getOperand(0);
981  SDOperand RHS = Op.getOperand(1);
982  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
983  SDOperand TrueVal = Op.getOperand(2);
984  SDOperand FalseVal = Op.getOperand(3);
985
986  if (LHS.getValueType() == MVT::i32) {
987    SDOperand ARMCC;
988    SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
989    return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, Cmp);
990  }
991
992  ARMCC::CondCodes CondCode, CondCode2;
993  if (FPCCToARMCC(CC, CondCode, CondCode2))
994    std::swap(TrueVal, FalseVal);
995
996  SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
997  SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
998  SDOperand Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal,
999                                 ARMCC, Cmp);
1000  if (CondCode2 != ARMCC::AL) {
1001    SDOperand ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
1002    // FIXME: Needs another CMP because flag can have but one use.
1003    SDOperand Cmp2 = getVFPCmp(LHS, RHS, DAG);
1004    Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, Cmp2);
1005  }
1006  return Result;
1007}
1008
1009static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG,
1010                            const ARMSubtarget *ST) {
1011  SDOperand  Chain = Op.getOperand(0);
1012  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1013  SDOperand    LHS = Op.getOperand(2);
1014  SDOperand    RHS = Op.getOperand(3);
1015  SDOperand   Dest = Op.getOperand(4);
1016
1017  if (LHS.getValueType() == MVT::i32) {
1018    SDOperand ARMCC;
1019    SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
1020    return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, Cmp);
1021  }
1022
1023  assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1024  ARMCC::CondCodes CondCode, CondCode2;
1025  if (FPCCToARMCC(CC, CondCode, CondCode2))
1026    // Swap the LHS/RHS of the comparison if needed.
1027    std::swap(LHS, RHS);
1028
1029  SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
1030  SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
1031  SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1032  SDOperand Ops[] = { Chain, Dest, ARMCC, Cmp };
1033  SDOperand Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 4);
1034  if (CondCode2 != ARMCC::AL) {
1035    ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1036    SDOperand Ops[] = { Res, Dest, ARMCC, Res.getValue(1) };
1037    Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 4);
1038  }
1039  return Res;
1040}
1041
1042SDOperand ARMTargetLowering::LowerBR_JT(SDOperand Op, SelectionDAG &DAG) {
1043  SDOperand Chain = Op.getOperand(0);
1044  SDOperand Table = Op.getOperand(1);
1045  SDOperand Index = Op.getOperand(2);
1046
1047  MVT::ValueType PTy = getPointerTy();
1048  JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1049  ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1050  SDOperand UId =  DAG.getConstant(AFI->createJumpTableUId(), PTy);
1051  SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1052  Table = DAG.getNode(ARMISD::WrapperJT, MVT::i32, JTI, UId);
1053  Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy));
1054  SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1055  bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1056  Addr = DAG.getLoad(isPIC ? MVT::i32 : PTy, Chain, Addr, NULL, 0);
1057  Chain = Addr.getValue(1);
1058  if (isPIC)
1059    Addr = DAG.getNode(ISD::ADD, PTy, Addr, Table);
1060  return DAG.getNode(ARMISD::BR_JT, MVT::Other, Chain, Addr, JTI, UId);
1061}
1062
1063static SDOperand LowerFP_TO_INT(SDOperand Op, SelectionDAG &DAG) {
1064  unsigned Opc =
1065    Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1066  Op = DAG.getNode(Opc, MVT::f32, Op.getOperand(0));
1067  return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
1068}
1069
1070static SDOperand LowerINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
1071  MVT::ValueType VT = Op.getValueType();
1072  unsigned Opc =
1073    Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1074
1075  Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
1076  return DAG.getNode(Opc, VT, Op);
1077}
1078
1079static SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
1080  // Implement fcopysign with a fabs and a conditional fneg.
1081  SDOperand Tmp0 = Op.getOperand(0);
1082  SDOperand Tmp1 = Op.getOperand(1);
1083  MVT::ValueType VT = Op.getValueType();
1084  MVT::ValueType SrcVT = Tmp1.getValueType();
1085  SDOperand AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0);
1086  SDOperand Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG);
1087  SDOperand ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1088  return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, Cmp);
1089}
1090
1091static SDOperand LowerBIT_CONVERT(SDOperand Op, SelectionDAG &DAG) {
1092  // Turn f64->i64 into FMRRD.
1093  assert(Op.getValueType() == MVT::i64 &&
1094         Op.getOperand(0).getValueType() == MVT::f64);
1095
1096  Op = Op.getOperand(0);
1097  SDOperand Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32),
1098                              &Op, 1);
1099
1100  // Merge the pieces into a single i64 value.
1101  return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1));
1102}
1103
1104static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
1105  // FIXME: All this code is target-independent.  Create a new target-indep
1106  // MULHILO node and move this code to the legalizer.
1107  //
1108  assert(Op.getValueType() == MVT::i64 && "Only handles i64 expand right now!");
1109
1110  SDOperand LL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1111                             DAG.getConstant(0, MVT::i32));
1112  SDOperand RL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(1),
1113                             DAG.getConstant(0, MVT::i32));
1114
1115  const TargetLowering &TL = DAG.getTargetLoweringInfo();
1116  unsigned LHSSB = TL.ComputeNumSignBits(Op.getOperand(0));
1117  unsigned RHSSB = TL.ComputeNumSignBits(Op.getOperand(1));
1118
1119  SDOperand Lo, Hi;
1120  // Figure out how to lower this multiply.
1121  if (LHSSB >= 33 && RHSSB >= 33) {
1122    // If the input values are both sign extended, we can emit a mulhs+mul.
1123    Lo = DAG.getNode(ISD::MUL, MVT::i32, LL, RL);
1124    Hi = DAG.getNode(ISD::MULHS, MVT::i32, LL, RL);
1125  } else if (LHSSB == 32 && RHSSB == 32 &&
1126             TL.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) &&
1127             TL.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) {
1128    // If the inputs are zero extended, use mulhu.
1129    Lo = DAG.getNode(ISD::MUL, MVT::i32, LL, RL);
1130    Hi = DAG.getNode(ISD::MULHU, MVT::i32, LL, RL);
1131  } else {
1132    SDOperand LH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1133                               DAG.getConstant(1, MVT::i32));
1134    SDOperand RH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(1),
1135                               DAG.getConstant(1, MVT::i32));
1136
1137    // Lo,Hi = umul LHS, RHS.
1138    SDOperand Ops[] = { LL, RL };
1139    SDOperand UMul64 = DAG.getNode(ARMISD::MULHILOU,
1140                                   DAG.getVTList(MVT::i32, MVT::i32), Ops, 2);
1141    Lo = UMul64;
1142    Hi = UMul64.getValue(1);
1143    RH = DAG.getNode(ISD::MUL, MVT::i32, LL, RH);
1144    LH = DAG.getNode(ISD::MUL, MVT::i32, LH, RL);
1145    Hi = DAG.getNode(ISD::ADD, MVT::i32, Hi, RH);
1146    Hi = DAG.getNode(ISD::ADD, MVT::i32, Hi, LH);
1147  }
1148
1149  // Merge the pieces into a single i64 value.
1150  return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
1151}
1152
1153static SDOperand LowerMULHU(SDOperand Op, SelectionDAG &DAG) {
1154  SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1) };
1155  return DAG.getNode(ARMISD::MULHILOU,
1156                     DAG.getVTList(MVT::i32, MVT::i32), Ops, 2).getValue(1);
1157}
1158
1159static SDOperand LowerMULHS(SDOperand Op, SelectionDAG &DAG) {
1160  SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1) };
1161  return DAG.getNode(ARMISD::MULHILOS,
1162                     DAG.getVTList(MVT::i32, MVT::i32), Ops, 2).getValue(1);
1163}
1164
1165static SDOperand LowerSRx(SDOperand Op, SelectionDAG &DAG,
1166                          const ARMSubtarget *ST) {
1167  assert(Op.getValueType() == MVT::i64 &&
1168         (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) &&
1169         "Unknown shift to lower!");
1170
1171  // We only lower SRA, SRL of 1 here, all others use generic lowering.
1172  if (!isa<ConstantSDNode>(Op.getOperand(1)) ||
1173      cast<ConstantSDNode>(Op.getOperand(1))->getValue() != 1)
1174    return SDOperand();
1175
1176  // If we are in thumb mode, we don't have RRX.
1177  if (ST->isThumb()) return SDOperand();
1178
1179  // Okay, we have a 64-bit SRA or SRL of 1.  Lower this to an RRX expr.
1180  SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1181                             DAG.getConstant(0, MVT::i32));
1182  SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1183                             DAG.getConstant(1, MVT::i32));
1184
1185  // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
1186  // captures the result into a carry flag.
1187  unsigned Opc = Op.getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
1188  Hi = DAG.getNode(Opc, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
1189
1190  // The low part is an ARMISD::RRX operand, which shifts the carry in.
1191  Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1));
1192
1193  // Merge the pieces into a single i64 value.
1194  return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
1195}
1196
1197SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
1198  switch (Op.getOpcode()) {
1199  default: assert(0 && "Don't know how to custom lower this!"); abort();
1200  case ISD::ConstantPool:  return LowerConstantPool(Op, DAG);
1201  case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
1202  case ISD::CALL:          return LowerCALL(Op, DAG);
1203  case ISD::RET:           return LowerRET(Op, DAG);
1204  case ISD::SELECT_CC:     return LowerSELECT_CC(Op, DAG, Subtarget);
1205  case ISD::BR_CC:         return LowerBR_CC(Op, DAG, Subtarget);
1206  case ISD::BR_JT:         return LowerBR_JT(Op, DAG);
1207  case ISD::VASTART:       return LowerVASTART(Op, DAG, VarArgsFrameIndex);
1208  case ISD::SINT_TO_FP:
1209  case ISD::UINT_TO_FP:    return LowerINT_TO_FP(Op, DAG);
1210  case ISD::FP_TO_SINT:
1211  case ISD::FP_TO_UINT:    return LowerFP_TO_INT(Op, DAG);
1212  case ISD::FCOPYSIGN:     return LowerFCOPYSIGN(Op, DAG);
1213  case ISD::BIT_CONVERT:   return LowerBIT_CONVERT(Op, DAG);
1214  case ISD::MUL:           return LowerMUL(Op, DAG);
1215  case ISD::MULHU:         return LowerMULHU(Op, DAG);
1216  case ISD::MULHS:         return LowerMULHS(Op, DAG);
1217  case ISD::SRL:
1218  case ISD::SRA:           return LowerSRx(Op, DAG, Subtarget);
1219  case ISD::FORMAL_ARGUMENTS:
1220    return LowerFORMAL_ARGUMENTS(Op, DAG);
1221  case ISD::RETURNADDR:    break;
1222  case ISD::FRAMEADDR:     break;
1223  }
1224  return SDOperand();
1225}
1226
1227//===----------------------------------------------------------------------===//
1228//                           ARM Scheduler Hooks
1229//===----------------------------------------------------------------------===//
1230
1231MachineBasicBlock *
1232ARMTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
1233                                           MachineBasicBlock *BB) {
1234  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1235  switch (MI->getOpcode()) {
1236  default: assert(false && "Unexpected instr type to insert");
1237  case ARM::tMOVCCr: {
1238    // To "insert" a SELECT_CC instruction, we actually have to insert the
1239    // diamond control-flow pattern.  The incoming instruction knows the
1240    // destination vreg to set, the condition code register to branch on, the
1241    // true/false values to select between, and a branch opcode to use.
1242    const BasicBlock *LLVM_BB = BB->getBasicBlock();
1243    ilist<MachineBasicBlock>::iterator It = BB;
1244    ++It;
1245
1246    //  thisMBB:
1247    //  ...
1248    //   TrueVal = ...
1249    //   cmpTY ccX, r1, r2
1250    //   bCC copy1MBB
1251    //   fallthrough --> copy0MBB
1252    MachineBasicBlock *thisMBB  = BB;
1253    MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
1254    MachineBasicBlock *sinkMBB  = new MachineBasicBlock(LLVM_BB);
1255    BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB)
1256      .addImm(MI->getOperand(3).getImm());
1257    MachineFunction *F = BB->getParent();
1258    F->getBasicBlockList().insert(It, copy0MBB);
1259    F->getBasicBlockList().insert(It, sinkMBB);
1260    // Update machine-CFG edges by first adding all successors of the current
1261    // block to the new block which will contain the Phi node for the select.
1262    for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
1263        e = BB->succ_end(); i != e; ++i)
1264      sinkMBB->addSuccessor(*i);
1265    // Next, remove all successors of the current block, and add the true
1266    // and fallthrough blocks as its successors.
1267    while(!BB->succ_empty())
1268      BB->removeSuccessor(BB->succ_begin());
1269    BB->addSuccessor(copy0MBB);
1270    BB->addSuccessor(sinkMBB);
1271
1272    //  copy0MBB:
1273    //   %FalseValue = ...
1274    //   # fallthrough to sinkMBB
1275    BB = copy0MBB;
1276
1277    // Update machine-CFG edges
1278    BB->addSuccessor(sinkMBB);
1279
1280    //  sinkMBB:
1281    //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1282    //  ...
1283    BB = sinkMBB;
1284    BuildMI(BB, TII->get(ARM::PHI), MI->getOperand(0).getReg())
1285      .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
1286      .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1287
1288    delete MI;   // The pseudo instruction is gone now.
1289    return BB;
1290  }
1291  }
1292}
1293
1294//===----------------------------------------------------------------------===//
1295//                           ARM Optimization Hooks
1296//===----------------------------------------------------------------------===//
1297
1298/// isLegalAddressImmediate - Return true if the integer value can be used
1299/// as the offset of the target addressing mode for load / store of the
1300/// given type.
1301static bool isLegalAddressImmediate(int64_t V, MVT::ValueType VT,
1302                                    const ARMSubtarget *Subtarget) {
1303  if (V == 0)
1304    return true;
1305
1306  if (Subtarget->isThumb()) {
1307    if (V < 0)
1308      return false;
1309
1310    unsigned Scale = 1;
1311    switch (VT) {
1312    default: return false;
1313    case MVT::i1:
1314    case MVT::i8:
1315      // Scale == 1;
1316      break;
1317    case MVT::i16:
1318      // Scale == 2;
1319      Scale = 2;
1320      break;
1321    case MVT::i32:
1322      // Scale == 4;
1323      Scale = 4;
1324      break;
1325    }
1326
1327    if ((V & (Scale - 1)) != 0)
1328      return false;
1329    V /= Scale;
1330    return V == V & ((1LL << 5) - 1);
1331  }
1332
1333  if (V < 0)
1334    V = - V;
1335  switch (VT) {
1336  default: return false;
1337  case MVT::i1:
1338  case MVT::i8:
1339  case MVT::i32:
1340    // +- imm12
1341    return V == V & ((1LL << 12) - 1);
1342  case MVT::i16:
1343    // +- imm8
1344    return V == V & ((1LL << 8) - 1);
1345  case MVT::f32:
1346  case MVT::f64:
1347    if (!Subtarget->hasVFP2())
1348      return false;
1349    if ((V % 3) != 0)
1350      return false;
1351    V >>= 2;
1352    return V == V & ((1LL << 8) - 1);
1353  }
1354}
1355
1356/// isLegalAddressingMode - Return true if the addressing mode represented
1357/// by AM is legal for this target, for a load/store of the specified type.
1358bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
1359                                              const Type *Ty) const {
1360  if (!isLegalAddressImmediate(AM.BaseOffs, getValueType(Ty), Subtarget))
1361    return false;
1362
1363  // Can never fold addr of global into load/store.
1364  if (AM.BaseGV)
1365    return false;
1366
1367  switch (AM.Scale) {
1368  case 0:  // no scale reg, must be "r+i" or "r", or "i".
1369    break;
1370  case 1:
1371    if (Subtarget->isThumb())
1372      return false;
1373    // FALL THROUGH.
1374  default:
1375    // ARM doesn't support any R+R*scale+imm addr modes.
1376    if (AM.BaseOffs)
1377      return false;
1378
1379    int Scale = AM.Scale;
1380    switch (getValueType(Ty)) {
1381    default: return false;
1382    case MVT::i1:
1383    case MVT::i8:
1384    case MVT::i32:
1385    case MVT::i64:
1386      // This assumes i64 is legalized to a pair of i32. If not (i.e.
1387      // ldrd / strd are used, then its address mode is same as i16.
1388      // r + r
1389      if (Scale < 0) Scale = -Scale;
1390      if (Scale == 1)
1391        return true;
1392      // r + r << imm
1393      return isPowerOf2_32(Scale & ~1);
1394    case MVT::i16:
1395      // r + r
1396      if (((unsigned)AM.HasBaseReg + Scale) <= 2)
1397        return true;
1398      return false;
1399
1400    case MVT::isVoid:
1401      // Note, we allow "void" uses (basically, uses that aren't loads or
1402      // stores), because arm allows folding a scale into many arithmetic
1403      // operations.  This should be made more precise and revisited later.
1404
1405      // Allow r << imm, but the imm has to be a multiple of two.
1406      if (AM.Scale & 1) return false;
1407      return isPowerOf2_32(AM.Scale);
1408    }
1409    break;
1410  }
1411  return true;
1412}
1413
1414
1415static bool getIndexedAddressParts(SDNode *Ptr, MVT::ValueType VT,
1416                                   bool isSEXTLoad, SDOperand &Base,
1417                                   SDOperand &Offset, bool &isInc,
1418                                   SelectionDAG &DAG) {
1419  if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
1420    return false;
1421
1422  if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
1423    // AddressingMode 3
1424    Base = Ptr->getOperand(0);
1425    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1426      int RHSC = (int)RHS->getValue();
1427      if (RHSC < 0 && RHSC > -256) {
1428        isInc = false;
1429        Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1430        return true;
1431      }
1432    }
1433    isInc = (Ptr->getOpcode() == ISD::ADD);
1434    Offset = Ptr->getOperand(1);
1435    return true;
1436  } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
1437    // AddressingMode 2
1438    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1439      int RHSC = (int)RHS->getValue();
1440      if (RHSC < 0 && RHSC > -0x1000) {
1441        isInc = false;
1442        Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1443        Base = Ptr->getOperand(0);
1444        return true;
1445      }
1446    }
1447
1448    if (Ptr->getOpcode() == ISD::ADD) {
1449      isInc = true;
1450      ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
1451      if (ShOpcVal != ARM_AM::no_shift) {
1452        Base = Ptr->getOperand(1);
1453        Offset = Ptr->getOperand(0);
1454      } else {
1455        Base = Ptr->getOperand(0);
1456        Offset = Ptr->getOperand(1);
1457      }
1458      return true;
1459    }
1460
1461    isInc = (Ptr->getOpcode() == ISD::ADD);
1462    Base = Ptr->getOperand(0);
1463    Offset = Ptr->getOperand(1);
1464    return true;
1465  }
1466
1467  // FIXME: Use FLDM / FSTM to emulate indexed FP load / store.
1468  return false;
1469}
1470
1471/// getPreIndexedAddressParts - returns true by value, base pointer and
1472/// offset pointer and addressing mode by reference if the node's address
1473/// can be legally represented as pre-indexed load / store address.
1474bool
1475ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
1476                                             SDOperand &Offset,
1477                                             ISD::MemIndexedMode &AM,
1478                                             SelectionDAG &DAG) {
1479  if (Subtarget->isThumb())
1480    return false;
1481
1482  MVT::ValueType VT;
1483  SDOperand Ptr;
1484  bool isSEXTLoad = false;
1485  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1486    Ptr = LD->getBasePtr();
1487    VT  = LD->getLoadedVT();
1488    isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1489  } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1490    Ptr = ST->getBasePtr();
1491    VT  = ST->getStoredVT();
1492  } else
1493    return false;
1494
1495  bool isInc;
1496  bool isLegal = getIndexedAddressParts(Ptr.Val, VT, isSEXTLoad, Base, Offset,
1497                                        isInc, DAG);
1498  if (isLegal) {
1499    AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
1500    return true;
1501  }
1502  return false;
1503}
1504
1505/// getPostIndexedAddressParts - returns true by value, base pointer and
1506/// offset pointer and addressing mode by reference if this node can be
1507/// combined with a load / store to form a post-indexed load / store.
1508bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1509                                                   SDOperand &Base,
1510                                                   SDOperand &Offset,
1511                                                   ISD::MemIndexedMode &AM,
1512                                                   SelectionDAG &DAG) {
1513  if (Subtarget->isThumb())
1514    return false;
1515
1516  MVT::ValueType VT;
1517  SDOperand Ptr;
1518  bool isSEXTLoad = false;
1519  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1520    VT  = LD->getLoadedVT();
1521    isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1522  } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1523    VT  = ST->getStoredVT();
1524  } else
1525    return false;
1526
1527  bool isInc;
1528  bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
1529                                        isInc, DAG);
1530  if (isLegal) {
1531    AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
1532    return true;
1533  }
1534  return false;
1535}
1536
1537void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
1538                                                       uint64_t Mask,
1539                                                       uint64_t &KnownZero,
1540                                                       uint64_t &KnownOne,
1541                                                       unsigned Depth) const {
1542  KnownZero = 0;
1543  KnownOne = 0;
1544  switch (Op.getOpcode()) {
1545  default: break;
1546  case ARMISD::CMOV: {
1547    // Bits are known zero/one if known on the LHS and RHS.
1548    ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
1549    if (KnownZero == 0 && KnownOne == 0) return;
1550
1551    uint64_t KnownZeroRHS, KnownOneRHS;
1552    ComputeMaskedBits(Op.getOperand(1), Mask,
1553                      KnownZeroRHS, KnownOneRHS, Depth+1);
1554    KnownZero &= KnownZeroRHS;
1555    KnownOne  &= KnownOneRHS;
1556    return;
1557  }
1558  }
1559}
1560
1561//===----------------------------------------------------------------------===//
1562//                           ARM Inline Assembly Support
1563//===----------------------------------------------------------------------===//
1564
1565/// getConstraintType - Given a constraint letter, return the type of
1566/// constraint it is for this target.
1567ARMTargetLowering::ConstraintType
1568ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
1569  if (Constraint.size() == 1) {
1570    switch (Constraint[0]) {
1571    default:  break;
1572    case 'l': return C_RegisterClass;
1573    case 'w': return C_RegisterClass;
1574    }
1575  }
1576  return TargetLowering::getConstraintType(Constraint);
1577}
1578
1579std::pair<unsigned, const TargetRegisterClass*>
1580ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
1581                                                MVT::ValueType VT) const {
1582  if (Constraint.size() == 1) {
1583    // GCC RS6000 Constraint Letters
1584    switch (Constraint[0]) {
1585    case 'l':
1586    // FIXME: in thumb mode, 'l' is only low-regs.
1587    // FALL THROUGH.
1588    case 'r':
1589      return std::make_pair(0U, ARM::GPRRegisterClass);
1590    case 'w':
1591      if (VT == MVT::f32)
1592        return std::make_pair(0U, ARM::SPRRegisterClass);
1593      if (VT == MVT::f64)
1594        return std::make_pair(0U, ARM::DPRRegisterClass);
1595      break;
1596    }
1597  }
1598  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1599}
1600
1601std::vector<unsigned> ARMTargetLowering::
1602getRegClassForInlineAsmConstraint(const std::string &Constraint,
1603                                  MVT::ValueType VT) const {
1604  if (Constraint.size() != 1)
1605    return std::vector<unsigned>();
1606
1607  switch (Constraint[0]) {      // GCC ARM Constraint Letters
1608  default: break;
1609  case 'l':
1610  case 'r':
1611    return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1612                                 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1613                                 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1614                                 ARM::R12, ARM::LR, 0);
1615  case 'w':
1616    if (VT == MVT::f32)
1617      return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1618                                   ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1619                                   ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1620                                   ARM::S12,ARM::S13,ARM::S14,ARM::S15,
1621                                   ARM::S16,ARM::S17,ARM::S18,ARM::S19,
1622                                   ARM::S20,ARM::S21,ARM::S22,ARM::S23,
1623                                   ARM::S24,ARM::S25,ARM::S26,ARM::S27,
1624                                   ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
1625    if (VT == MVT::f64)
1626      return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1627                                   ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1628                                   ARM::D8, ARM::D9, ARM::D10,ARM::D11,
1629                                   ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
1630      break;
1631  }
1632
1633  return std::vector<unsigned>();
1634}
1635