ARMISelLowering.cpp revision 969c9ef0dd271905136f21a6c51dd0839ef01cce
1//===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "arm-isel" 16#include "ARM.h" 17#include "ARMCallingConv.h" 18#include "ARMConstantPoolValue.h" 19#include "ARMISelLowering.h" 20#include "ARMMachineFunctionInfo.h" 21#include "ARMPerfectShuffle.h" 22#include "ARMRegisterInfo.h" 23#include "ARMSubtarget.h" 24#include "ARMTargetMachine.h" 25#include "ARMTargetObjectFile.h" 26#include "MCTargetDesc/ARMAddressingModes.h" 27#include "llvm/CallingConv.h" 28#include "llvm/Constants.h" 29#include "llvm/Function.h" 30#include "llvm/GlobalValue.h" 31#include "llvm/Instruction.h" 32#include "llvm/Instructions.h" 33#include "llvm/Intrinsics.h" 34#include "llvm/Type.h" 35#include "llvm/CodeGen/CallingConvLower.h" 36#include "llvm/CodeGen/IntrinsicLowering.h" 37#include "llvm/CodeGen/MachineBasicBlock.h" 38#include "llvm/CodeGen/MachineFrameInfo.h" 39#include "llvm/CodeGen/MachineFunction.h" 40#include "llvm/CodeGen/MachineInstrBuilder.h" 41#include "llvm/CodeGen/MachineModuleInfo.h" 42#include "llvm/CodeGen/MachineRegisterInfo.h" 43#include "llvm/CodeGen/PseudoSourceValue.h" 44#include "llvm/CodeGen/SelectionDAG.h" 45#include "llvm/MC/MCSectionMachO.h" 46#include "llvm/Target/TargetOptions.h" 47#include "llvm/ADT/VectorExtras.h" 48#include "llvm/ADT/StringExtras.h" 49#include "llvm/ADT/Statistic.h" 50#include "llvm/Support/CommandLine.h" 51#include "llvm/Support/ErrorHandling.h" 52#include "llvm/Support/MathExtras.h" 53#include "llvm/Support/raw_ostream.h" 54#include <sstream> 55using namespace llvm; 56 57STATISTIC(NumTailCalls, "Number of tail calls"); 58STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt"); 59 60// This option should go away when tail calls fully work. 61static cl::opt<bool> 62EnableARMTailCalls("arm-tail-calls", cl::Hidden, 63 cl::desc("Generate tail calls (TEMPORARY OPTION)."), 64 cl::init(false)); 65 66cl::opt<bool> 67EnableARMLongCalls("arm-long-calls", cl::Hidden, 68 cl::desc("Generate calls via indirect call instructions"), 69 cl::init(false)); 70 71static cl::opt<bool> 72ARMInterworking("arm-interworking", cl::Hidden, 73 cl::desc("Enable / disable ARM interworking (for debugging only)"), 74 cl::init(true)); 75 76namespace llvm { 77 class ARMCCState : public CCState { 78 public: 79 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF, 80 const TargetMachine &TM, SmallVector<CCValAssign, 16> &locs, 81 LLVMContext &C, ParmContext PC) 82 : CCState(CC, isVarArg, MF, TM, locs, C) { 83 assert(((PC == Call) || (PC == Prologue)) && 84 "ARMCCState users must specify whether their context is call" 85 "or prologue generation."); 86 CallOrPrologue = PC; 87 } 88 }; 89} 90 91// The APCS parameter registers. 92static const unsigned GPRArgRegs[] = { 93 ARM::R0, ARM::R1, ARM::R2, ARM::R3 94}; 95 96void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT, 97 EVT PromotedBitwiseVT) { 98 if (VT != PromotedLdStVT) { 99 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote); 100 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(), 101 PromotedLdStVT.getSimpleVT()); 102 103 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote); 104 AddPromotedToType (ISD::STORE, VT.getSimpleVT(), 105 PromotedLdStVT.getSimpleVT()); 106 } 107 108 EVT ElemTy = VT.getVectorElementType(); 109 if (ElemTy != MVT::i64 && ElemTy != MVT::f64) 110 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom); 111 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom); 112 if (ElemTy != MVT::i32) { 113 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand); 114 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand); 115 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand); 116 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand); 117 } 118 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom); 119 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom); 120 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal); 121 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Legal); 122 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand); 123 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand); 124 if (VT.isInteger()) { 125 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom); 126 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom); 127 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom); 128 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand); 129 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand); 130 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 131 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 132 setTruncStoreAction(VT.getSimpleVT(), 133 (MVT::SimpleValueType)InnerVT, Expand); 134 } 135 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand); 136 137 // Promote all bit-wise operations. 138 if (VT.isInteger() && VT != PromotedBitwiseVT) { 139 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote); 140 AddPromotedToType (ISD::AND, VT.getSimpleVT(), 141 PromotedBitwiseVT.getSimpleVT()); 142 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote); 143 AddPromotedToType (ISD::OR, VT.getSimpleVT(), 144 PromotedBitwiseVT.getSimpleVT()); 145 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote); 146 AddPromotedToType (ISD::XOR, VT.getSimpleVT(), 147 PromotedBitwiseVT.getSimpleVT()); 148 } 149 150 // Neon does not support vector divide/remainder operations. 151 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand); 152 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand); 153 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand); 154 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand); 155 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand); 156 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand); 157} 158 159void ARMTargetLowering::addDRTypeForNEON(EVT VT) { 160 addRegisterClass(VT, ARM::DPRRegisterClass); 161 addTypeForNEON(VT, MVT::f64, MVT::v2i32); 162} 163 164void ARMTargetLowering::addQRTypeForNEON(EVT VT) { 165 addRegisterClass(VT, ARM::QPRRegisterClass); 166 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32); 167} 168 169static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) { 170 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin()) 171 return new TargetLoweringObjectFileMachO(); 172 173 return new ARMElfTargetObjectFile(); 174} 175 176ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) 177 : TargetLowering(TM, createTLOF(TM)) { 178 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 179 RegInfo = TM.getRegisterInfo(); 180 Itins = TM.getInstrItineraryData(); 181 182 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 183 184 if (Subtarget->isTargetDarwin()) { 185 // Uses VFP for Thumb libfuncs if available. 186 if (Subtarget->isThumb() && Subtarget->hasVFP2()) { 187 // Single-precision floating-point arithmetic. 188 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp"); 189 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp"); 190 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp"); 191 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp"); 192 193 // Double-precision floating-point arithmetic. 194 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp"); 195 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp"); 196 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp"); 197 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp"); 198 199 // Single-precision comparisons. 200 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp"); 201 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp"); 202 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp"); 203 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp"); 204 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp"); 205 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp"); 206 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp"); 207 setLibcallName(RTLIB::O_F32, "__unordsf2vfp"); 208 209 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 210 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE); 211 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 212 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 213 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 214 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 215 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 216 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 217 218 // Double-precision comparisons. 219 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp"); 220 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp"); 221 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp"); 222 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp"); 223 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp"); 224 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp"); 225 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp"); 226 setLibcallName(RTLIB::O_F64, "__unorddf2vfp"); 227 228 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 229 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE); 230 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 231 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 232 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 233 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 234 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 235 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 236 237 // Floating-point to integer conversions. 238 // i64 conversions are done via library routines even when generating VFP 239 // instructions, so use the same ones. 240 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp"); 241 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp"); 242 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp"); 243 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp"); 244 245 // Conversions between floating types. 246 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp"); 247 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp"); 248 249 // Integer to floating-point conversions. 250 // i64 conversions are done via library routines even when generating VFP 251 // instructions, so use the same ones. 252 // FIXME: There appears to be some naming inconsistency in ARM libgcc: 253 // e.g., __floatunsidf vs. __floatunssidfvfp. 254 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp"); 255 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp"); 256 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp"); 257 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp"); 258 } 259 } 260 261 // These libcalls are not available in 32-bit. 262 setLibcallName(RTLIB::SHL_I128, 0); 263 setLibcallName(RTLIB::SRL_I128, 0); 264 setLibcallName(RTLIB::SRA_I128, 0); 265 266 if (Subtarget->isAAPCS_ABI()) { 267 // Double-precision floating-point arithmetic helper functions 268 // RTABI chapter 4.1.2, Table 2 269 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd"); 270 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv"); 271 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul"); 272 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub"); 273 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS); 274 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS); 275 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS); 276 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS); 277 278 // Double-precision floating-point comparison helper functions 279 // RTABI chapter 4.1.2, Table 3 280 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq"); 281 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 282 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq"); 283 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ); 284 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt"); 285 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 286 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple"); 287 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 288 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge"); 289 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 290 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt"); 291 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 292 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun"); 293 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 294 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun"); 295 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 296 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS); 297 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS); 298 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS); 299 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS); 300 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS); 301 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS); 302 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS); 303 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS); 304 305 // Single-precision floating-point arithmetic helper functions 306 // RTABI chapter 4.1.2, Table 4 307 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd"); 308 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv"); 309 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul"); 310 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub"); 311 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS); 312 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS); 313 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS); 314 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS); 315 316 // Single-precision floating-point comparison helper functions 317 // RTABI chapter 4.1.2, Table 5 318 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq"); 319 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 320 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq"); 321 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ); 322 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt"); 323 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 324 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple"); 325 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 326 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge"); 327 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 328 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt"); 329 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 330 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun"); 331 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 332 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun"); 333 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 334 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS); 335 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS); 336 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS); 337 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS); 338 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS); 339 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS); 340 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS); 341 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS); 342 343 // Floating-point to integer conversions. 344 // RTABI chapter 4.1.2, Table 6 345 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz"); 346 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz"); 347 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz"); 348 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz"); 349 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz"); 350 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz"); 351 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz"); 352 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz"); 353 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS); 354 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS); 355 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS); 356 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS); 357 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS); 358 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS); 359 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS); 360 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS); 361 362 // Conversions between floating types. 363 // RTABI chapter 4.1.2, Table 7 364 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f"); 365 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d"); 366 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS); 367 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS); 368 369 // Integer to floating-point conversions. 370 // RTABI chapter 4.1.2, Table 8 371 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d"); 372 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d"); 373 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d"); 374 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d"); 375 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f"); 376 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f"); 377 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f"); 378 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f"); 379 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS); 380 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS); 381 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS); 382 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS); 383 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS); 384 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS); 385 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS); 386 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS); 387 388 // Long long helper functions 389 // RTABI chapter 4.2, Table 9 390 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul"); 391 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod"); 392 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod"); 393 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl"); 394 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr"); 395 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr"); 396 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS); 397 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS); 398 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS); 399 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS); 400 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS); 401 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS); 402 403 // Integer division functions 404 // RTABI chapter 4.3.1 405 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv"); 406 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv"); 407 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv"); 408 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv"); 409 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv"); 410 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv"); 411 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS); 412 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS); 413 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS); 414 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS); 415 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS); 416 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS); 417 418 // Memory operations 419 // RTABI chapter 4.3.4 420 setLibcallName(RTLIB::MEMCPY, "__aeabi_memcpy"); 421 setLibcallName(RTLIB::MEMMOVE, "__aeabi_memmove"); 422 setLibcallName(RTLIB::MEMSET, "__aeabi_memset"); 423 } 424 425 // Use divmod compiler-rt calls for iOS 5.0 and later. 426 if (Subtarget->getTargetTriple().getOS() == Triple::IOS && 427 !Subtarget->getTargetTriple().isOSVersionLT(5, 0)) { 428 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4"); 429 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4"); 430 } 431 432 if (Subtarget->isThumb1Only()) 433 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass); 434 else 435 addRegisterClass(MVT::i32, ARM::GPRRegisterClass); 436 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { 437 addRegisterClass(MVT::f32, ARM::SPRRegisterClass); 438 if (!Subtarget->isFPOnlySP()) 439 addRegisterClass(MVT::f64, ARM::DPRRegisterClass); 440 441 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 442 } 443 444 if (Subtarget->hasNEON()) { 445 addDRTypeForNEON(MVT::v2f32); 446 addDRTypeForNEON(MVT::v8i8); 447 addDRTypeForNEON(MVT::v4i16); 448 addDRTypeForNEON(MVT::v2i32); 449 addDRTypeForNEON(MVT::v1i64); 450 451 addQRTypeForNEON(MVT::v4f32); 452 addQRTypeForNEON(MVT::v2f64); 453 addQRTypeForNEON(MVT::v16i8); 454 addQRTypeForNEON(MVT::v8i16); 455 addQRTypeForNEON(MVT::v4i32); 456 addQRTypeForNEON(MVT::v2i64); 457 458 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but 459 // neither Neon nor VFP support any arithmetic operations on it. 460 setOperationAction(ISD::FADD, MVT::v2f64, Expand); 461 setOperationAction(ISD::FSUB, MVT::v2f64, Expand); 462 setOperationAction(ISD::FMUL, MVT::v2f64, Expand); 463 setOperationAction(ISD::FDIV, MVT::v2f64, Expand); 464 setOperationAction(ISD::FREM, MVT::v2f64, Expand); 465 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand); 466 setOperationAction(ISD::SETCC, MVT::v2f64, Expand); 467 setOperationAction(ISD::FNEG, MVT::v2f64, Expand); 468 setOperationAction(ISD::FABS, MVT::v2f64, Expand); 469 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand); 470 setOperationAction(ISD::FSIN, MVT::v2f64, Expand); 471 setOperationAction(ISD::FCOS, MVT::v2f64, Expand); 472 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand); 473 setOperationAction(ISD::FPOW, MVT::v2f64, Expand); 474 setOperationAction(ISD::FLOG, MVT::v2f64, Expand); 475 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand); 476 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand); 477 setOperationAction(ISD::FEXP, MVT::v2f64, Expand); 478 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand); 479 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand); 480 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand); 481 setOperationAction(ISD::FRINT, MVT::v2f64, Expand); 482 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand); 483 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand); 484 485 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand); 486 487 // Neon does not support some operations on v1i64 and v2i64 types. 488 setOperationAction(ISD::MUL, MVT::v1i64, Expand); 489 // Custom handling for some quad-vector types to detect VMULL. 490 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 491 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 492 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 493 // Custom handling for some vector types to avoid expensive expansions 494 setOperationAction(ISD::SDIV, MVT::v4i16, Custom); 495 setOperationAction(ISD::SDIV, MVT::v8i8, Custom); 496 setOperationAction(ISD::UDIV, MVT::v4i16, Custom); 497 setOperationAction(ISD::UDIV, MVT::v8i8, Custom); 498 setOperationAction(ISD::SETCC, MVT::v1i64, Expand); 499 setOperationAction(ISD::SETCC, MVT::v2i64, Expand); 500 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with 501 // a destination type that is wider than the source. 502 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom); 503 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom); 504 505 setTargetDAGCombine(ISD::INTRINSIC_VOID); 506 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN); 507 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); 508 setTargetDAGCombine(ISD::SHL); 509 setTargetDAGCombine(ISD::SRL); 510 setTargetDAGCombine(ISD::SRA); 511 setTargetDAGCombine(ISD::SIGN_EXTEND); 512 setTargetDAGCombine(ISD::ZERO_EXTEND); 513 setTargetDAGCombine(ISD::ANY_EXTEND); 514 setTargetDAGCombine(ISD::SELECT_CC); 515 setTargetDAGCombine(ISD::BUILD_VECTOR); 516 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 517 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); 518 setTargetDAGCombine(ISD::STORE); 519 setTargetDAGCombine(ISD::FP_TO_SINT); 520 setTargetDAGCombine(ISD::FP_TO_UINT); 521 setTargetDAGCombine(ISD::FDIV); 522 } 523 524 computeRegisterProperties(); 525 526 // ARM does not have f32 extending load. 527 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 528 529 // ARM does not have i1 sign extending load. 530 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 531 532 // ARM supports all 4 flavors of integer indexed load / store. 533 if (!Subtarget->isThumb1Only()) { 534 for (unsigned im = (unsigned)ISD::PRE_INC; 535 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { 536 setIndexedLoadAction(im, MVT::i1, Legal); 537 setIndexedLoadAction(im, MVT::i8, Legal); 538 setIndexedLoadAction(im, MVT::i16, Legal); 539 setIndexedLoadAction(im, MVT::i32, Legal); 540 setIndexedStoreAction(im, MVT::i1, Legal); 541 setIndexedStoreAction(im, MVT::i8, Legal); 542 setIndexedStoreAction(im, MVT::i16, Legal); 543 setIndexedStoreAction(im, MVT::i32, Legal); 544 } 545 } 546 547 // i64 operation support. 548 setOperationAction(ISD::MUL, MVT::i64, Expand); 549 setOperationAction(ISD::MULHU, MVT::i32, Expand); 550 if (Subtarget->isThumb1Only()) { 551 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 552 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 553 } 554 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops() 555 || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP())) 556 setOperationAction(ISD::MULHS, MVT::i32, Expand); 557 558 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 559 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 560 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 561 setOperationAction(ISD::SRL, MVT::i64, Custom); 562 setOperationAction(ISD::SRA, MVT::i64, Custom); 563 564 if (!Subtarget->isThumb1Only()) { 565 // FIXME: We should do this for Thumb1 as well. 566 setOperationAction(ISD::ADDC, MVT::i32, Custom); 567 setOperationAction(ISD::ADDE, MVT::i32, Custom); 568 setOperationAction(ISD::SUBC, MVT::i32, Custom); 569 setOperationAction(ISD::SUBE, MVT::i32, Custom); 570 } 571 572 // ARM does not have ROTL. 573 setOperationAction(ISD::ROTL, MVT::i32, Expand); 574 setOperationAction(ISD::CTTZ, MVT::i32, Custom); 575 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 576 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) 577 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 578 579 // Only ARMv6 has BSWAP. 580 if (!Subtarget->hasV6Ops()) 581 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 582 583 // These are expanded into libcalls. 584 if (!Subtarget->hasDivide() || !Subtarget->isThumb2()) { 585 // v7M has a hardware divider 586 setOperationAction(ISD::SDIV, MVT::i32, Expand); 587 setOperationAction(ISD::UDIV, MVT::i32, Expand); 588 } 589 setOperationAction(ISD::SREM, MVT::i32, Expand); 590 setOperationAction(ISD::UREM, MVT::i32, Expand); 591 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 592 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 593 594 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 595 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 596 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom); 597 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 598 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 599 600 setOperationAction(ISD::TRAP, MVT::Other, Legal); 601 602 // Use the default implementation. 603 setOperationAction(ISD::VASTART, MVT::Other, Custom); 604 setOperationAction(ISD::VAARG, MVT::Other, Expand); 605 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 606 setOperationAction(ISD::VAEND, MVT::Other, Expand); 607 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 608 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 609 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 610 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 611 setExceptionPointerRegister(ARM::R0); 612 setExceptionSelectorRegister(ARM::R1); 613 614 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 615 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use 616 // the default expansion. 617 // FIXME: This should be checking for v6k, not just v6. 618 if (Subtarget->hasDataBarrier() || 619 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) { 620 // membarrier needs custom lowering; the rest are legal and handled 621 // normally. 622 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); 623 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 624 // Custom lowering for 64-bit ops 625 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 626 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 627 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 628 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 629 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 630 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 631 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom); 632 // Automatically insert fences (dmb ist) around ATOMIC_SWAP etc. 633 setInsertFencesForAtomic(true); 634 } else { 635 // Set them all for expansion, which will force libcalls. 636 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 637 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); 638 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand); 639 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand); 640 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand); 641 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand); 642 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand); 643 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand); 644 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand); 645 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand); 646 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand); 647 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand); 648 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand); 649 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand); 650 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the 651 // Unordered/Monotonic case. 652 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom); 653 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom); 654 // Since the libcalls include locking, fold in the fences 655 setShouldFoldAtomicFences(true); 656 } 657 658 setOperationAction(ISD::PREFETCH, MVT::Other, Custom); 659 660 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes. 661 if (!Subtarget->hasV6Ops()) { 662 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 663 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 664 } 665 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 666 667 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { 668 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR 669 // iff target supports vfp2. 670 setOperationAction(ISD::BITCAST, MVT::i64, Custom); 671 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); 672 } 673 674 // We want to custom lower some of our intrinsics. 675 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 676 if (Subtarget->isTargetDarwin()) { 677 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom); 678 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom); 679 setOperationAction(ISD::EH_SJLJ_DISPATCHSETUP, MVT::Other, Custom); 680 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume"); 681 } 682 683 setOperationAction(ISD::SETCC, MVT::i32, Expand); 684 setOperationAction(ISD::SETCC, MVT::f32, Expand); 685 setOperationAction(ISD::SETCC, MVT::f64, Expand); 686 setOperationAction(ISD::SELECT, MVT::i32, Custom); 687 setOperationAction(ISD::SELECT, MVT::f32, Custom); 688 setOperationAction(ISD::SELECT, MVT::f64, Custom); 689 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 690 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 691 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 692 693 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 694 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 695 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 696 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 697 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 698 699 // We don't support sin/cos/fmod/copysign/pow 700 setOperationAction(ISD::FSIN, MVT::f64, Expand); 701 setOperationAction(ISD::FSIN, MVT::f32, Expand); 702 setOperationAction(ISD::FCOS, MVT::f32, Expand); 703 setOperationAction(ISD::FCOS, MVT::f64, Expand); 704 setOperationAction(ISD::FREM, MVT::f64, Expand); 705 setOperationAction(ISD::FREM, MVT::f32, Expand); 706 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { 707 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 708 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 709 } 710 setOperationAction(ISD::FPOW, MVT::f64, Expand); 711 setOperationAction(ISD::FPOW, MVT::f32, Expand); 712 713 setOperationAction(ISD::FMA, MVT::f64, Expand); 714 setOperationAction(ISD::FMA, MVT::f32, Expand); 715 716 // Various VFP goodness 717 if (!UseSoftFloat && !Subtarget->isThumb1Only()) { 718 // int <-> fp are custom expanded into bit_convert + ARMISD ops. 719 if (Subtarget->hasVFP2()) { 720 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 721 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 722 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 723 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 724 } 725 // Special handling for half-precision FP. 726 if (!Subtarget->hasFP16()) { 727 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand); 728 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand); 729 } 730 } 731 732 // We have target-specific dag combine patterns for the following nodes: 733 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine 734 setTargetDAGCombine(ISD::ADD); 735 setTargetDAGCombine(ISD::SUB); 736 setTargetDAGCombine(ISD::MUL); 737 738 if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON()) 739 setTargetDAGCombine(ISD::OR); 740 if (Subtarget->hasNEON()) 741 setTargetDAGCombine(ISD::AND); 742 743 setStackPointerRegisterToSaveRestore(ARM::SP); 744 745 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2()) 746 setSchedulingPreference(Sched::RegPressure); 747 else 748 setSchedulingPreference(Sched::Hybrid); 749 750 //// temporary - rewrite interface to use type 751 maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 1; 752 753 // On ARM arguments smaller than 4 bytes are extended, so all arguments 754 // are at least 4 bytes aligned. 755 setMinStackArgumentAlignment(4); 756 757 benefitFromCodePlacementOpt = true; 758 759 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2); 760} 761 762// FIXME: It might make sense to define the representative register class as the 763// nearest super-register that has a non-null superset. For example, DPR_VFP2 is 764// a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently, 765// SPR's representative would be DPR_VFP2. This should work well if register 766// pressure tracking were modified such that a register use would increment the 767// pressure of the register class's representative and all of it's super 768// classes' representatives transitively. We have not implemented this because 769// of the difficulty prior to coalescing of modeling operand register classes 770// due to the common occurrence of cross class copies and subregister insertions 771// and extractions. 772std::pair<const TargetRegisterClass*, uint8_t> 773ARMTargetLowering::findRepresentativeClass(EVT VT) const{ 774 const TargetRegisterClass *RRC = 0; 775 uint8_t Cost = 1; 776 switch (VT.getSimpleVT().SimpleTy) { 777 default: 778 return TargetLowering::findRepresentativeClass(VT); 779 // Use DPR as representative register class for all floating point 780 // and vector types. Since there are 32 SPR registers and 32 DPR registers so 781 // the cost is 1 for both f32 and f64. 782 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16: 783 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32: 784 RRC = ARM::DPRRegisterClass; 785 // When NEON is used for SP, only half of the register file is available 786 // because operations that define both SP and DP results will be constrained 787 // to the VFP2 class (D0-D15). We currently model this constraint prior to 788 // coalescing by double-counting the SP regs. See the FIXME above. 789 if (Subtarget->useNEONForSinglePrecisionFP()) 790 Cost = 2; 791 break; 792 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 793 case MVT::v4f32: case MVT::v2f64: 794 RRC = ARM::DPRRegisterClass; 795 Cost = 2; 796 break; 797 case MVT::v4i64: 798 RRC = ARM::DPRRegisterClass; 799 Cost = 4; 800 break; 801 case MVT::v8i64: 802 RRC = ARM::DPRRegisterClass; 803 Cost = 8; 804 break; 805 } 806 return std::make_pair(RRC, Cost); 807} 808 809const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { 810 switch (Opcode) { 811 default: return 0; 812 case ARMISD::Wrapper: return "ARMISD::Wrapper"; 813 case ARMISD::WrapperDYN: return "ARMISD::WrapperDYN"; 814 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC"; 815 case ARMISD::WrapperJT: return "ARMISD::WrapperJT"; 816 case ARMISD::CALL: return "ARMISD::CALL"; 817 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED"; 818 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK"; 819 case ARMISD::tCALL: return "ARMISD::tCALL"; 820 case ARMISD::BRCOND: return "ARMISD::BRCOND"; 821 case ARMISD::BR_JT: return "ARMISD::BR_JT"; 822 case ARMISD::BR2_JT: return "ARMISD::BR2_JT"; 823 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; 824 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD"; 825 case ARMISD::CMP: return "ARMISD::CMP"; 826 case ARMISD::CMPZ: return "ARMISD::CMPZ"; 827 case ARMISD::CMPFP: return "ARMISD::CMPFP"; 828 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0"; 829 case ARMISD::BCC_i64: return "ARMISD::BCC_i64"; 830 case ARMISD::FMSTAT: return "ARMISD::FMSTAT"; 831 case ARMISD::CMOV: return "ARMISD::CMOV"; 832 833 case ARMISD::RBIT: return "ARMISD::RBIT"; 834 835 case ARMISD::FTOSI: return "ARMISD::FTOSI"; 836 case ARMISD::FTOUI: return "ARMISD::FTOUI"; 837 case ARMISD::SITOF: return "ARMISD::SITOF"; 838 case ARMISD::UITOF: return "ARMISD::UITOF"; 839 840 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG"; 841 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG"; 842 case ARMISD::RRX: return "ARMISD::RRX"; 843 844 case ARMISD::ADDC: return "ARMISD::ADDC"; 845 case ARMISD::ADDE: return "ARMISD::ADDE"; 846 case ARMISD::SUBC: return "ARMISD::SUBC"; 847 case ARMISD::SUBE: return "ARMISD::SUBE"; 848 849 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD"; 850 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR"; 851 852 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP"; 853 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP"; 854 case ARMISD::EH_SJLJ_DISPATCHSETUP:return "ARMISD::EH_SJLJ_DISPATCHSETUP"; 855 856 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN"; 857 858 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER"; 859 860 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC"; 861 862 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER"; 863 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR"; 864 865 case ARMISD::PRELOAD: return "ARMISD::PRELOAD"; 866 867 case ARMISD::VCEQ: return "ARMISD::VCEQ"; 868 case ARMISD::VCEQZ: return "ARMISD::VCEQZ"; 869 case ARMISD::VCGE: return "ARMISD::VCGE"; 870 case ARMISD::VCGEZ: return "ARMISD::VCGEZ"; 871 case ARMISD::VCLEZ: return "ARMISD::VCLEZ"; 872 case ARMISD::VCGEU: return "ARMISD::VCGEU"; 873 case ARMISD::VCGT: return "ARMISD::VCGT"; 874 case ARMISD::VCGTZ: return "ARMISD::VCGTZ"; 875 case ARMISD::VCLTZ: return "ARMISD::VCLTZ"; 876 case ARMISD::VCGTU: return "ARMISD::VCGTU"; 877 case ARMISD::VTST: return "ARMISD::VTST"; 878 879 case ARMISD::VSHL: return "ARMISD::VSHL"; 880 case ARMISD::VSHRs: return "ARMISD::VSHRs"; 881 case ARMISD::VSHRu: return "ARMISD::VSHRu"; 882 case ARMISD::VSHLLs: return "ARMISD::VSHLLs"; 883 case ARMISD::VSHLLu: return "ARMISD::VSHLLu"; 884 case ARMISD::VSHLLi: return "ARMISD::VSHLLi"; 885 case ARMISD::VSHRN: return "ARMISD::VSHRN"; 886 case ARMISD::VRSHRs: return "ARMISD::VRSHRs"; 887 case ARMISD::VRSHRu: return "ARMISD::VRSHRu"; 888 case ARMISD::VRSHRN: return "ARMISD::VRSHRN"; 889 case ARMISD::VQSHLs: return "ARMISD::VQSHLs"; 890 case ARMISD::VQSHLu: return "ARMISD::VQSHLu"; 891 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu"; 892 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs"; 893 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu"; 894 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu"; 895 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs"; 896 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu"; 897 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu"; 898 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu"; 899 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs"; 900 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM"; 901 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM"; 902 case ARMISD::VDUP: return "ARMISD::VDUP"; 903 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE"; 904 case ARMISD::VEXT: return "ARMISD::VEXT"; 905 case ARMISD::VREV64: return "ARMISD::VREV64"; 906 case ARMISD::VREV32: return "ARMISD::VREV32"; 907 case ARMISD::VREV16: return "ARMISD::VREV16"; 908 case ARMISD::VZIP: return "ARMISD::VZIP"; 909 case ARMISD::VUZP: return "ARMISD::VUZP"; 910 case ARMISD::VTRN: return "ARMISD::VTRN"; 911 case ARMISD::VTBL1: return "ARMISD::VTBL1"; 912 case ARMISD::VTBL2: return "ARMISD::VTBL2"; 913 case ARMISD::VMULLs: return "ARMISD::VMULLs"; 914 case ARMISD::VMULLu: return "ARMISD::VMULLu"; 915 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR"; 916 case ARMISD::FMAX: return "ARMISD::FMAX"; 917 case ARMISD::FMIN: return "ARMISD::FMIN"; 918 case ARMISD::BFI: return "ARMISD::BFI"; 919 case ARMISD::VORRIMM: return "ARMISD::VORRIMM"; 920 case ARMISD::VBICIMM: return "ARMISD::VBICIMM"; 921 case ARMISD::VBSL: return "ARMISD::VBSL"; 922 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP"; 923 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP"; 924 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP"; 925 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD"; 926 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD"; 927 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD"; 928 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD"; 929 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD"; 930 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD"; 931 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD"; 932 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD"; 933 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD"; 934 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD"; 935 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD"; 936 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD"; 937 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD"; 938 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD"; 939 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD"; 940 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD"; 941 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD"; 942 } 943} 944 945EVT ARMTargetLowering::getSetCCResultType(EVT VT) const { 946 if (!VT.isVector()) return getPointerTy(); 947 return VT.changeVectorElementTypeToInteger(); 948} 949 950/// getRegClassFor - Return the register class that should be used for the 951/// specified value type. 952TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const { 953 // Map v4i64 to QQ registers but do not make the type legal. Similarly map 954 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to 955 // load / store 4 to 8 consecutive D registers. 956 if (Subtarget->hasNEON()) { 957 if (VT == MVT::v4i64) 958 return ARM::QQPRRegisterClass; 959 else if (VT == MVT::v8i64) 960 return ARM::QQQQPRRegisterClass; 961 } 962 return TargetLowering::getRegClassFor(VT); 963} 964 965// Create a fast isel object. 966FastISel * 967ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 968 return ARM::createFastISel(funcInfo); 969} 970 971/// getMaximalGlobalOffset - Returns the maximal possible offset which can 972/// be used for loads / stores from the global. 973unsigned ARMTargetLowering::getMaximalGlobalOffset() const { 974 return (Subtarget->isThumb1Only() ? 127 : 4095); 975} 976 977Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const { 978 unsigned NumVals = N->getNumValues(); 979 if (!NumVals) 980 return Sched::RegPressure; 981 982 for (unsigned i = 0; i != NumVals; ++i) { 983 EVT VT = N->getValueType(i); 984 if (VT == MVT::Glue || VT == MVT::Other) 985 continue; 986 if (VT.isFloatingPoint() || VT.isVector()) 987 return Sched::Latency; 988 } 989 990 if (!N->isMachineOpcode()) 991 return Sched::RegPressure; 992 993 // Load are scheduled for latency even if there instruction itinerary 994 // is not available. 995 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 996 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); 997 998 if (MCID.getNumDefs() == 0) 999 return Sched::RegPressure; 1000 if (!Itins->isEmpty() && 1001 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2) 1002 return Sched::Latency; 1003 1004 return Sched::RegPressure; 1005} 1006 1007//===----------------------------------------------------------------------===// 1008// Lowering Code 1009//===----------------------------------------------------------------------===// 1010 1011/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC 1012static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { 1013 switch (CC) { 1014 default: llvm_unreachable("Unknown condition code!"); 1015 case ISD::SETNE: return ARMCC::NE; 1016 case ISD::SETEQ: return ARMCC::EQ; 1017 case ISD::SETGT: return ARMCC::GT; 1018 case ISD::SETGE: return ARMCC::GE; 1019 case ISD::SETLT: return ARMCC::LT; 1020 case ISD::SETLE: return ARMCC::LE; 1021 case ISD::SETUGT: return ARMCC::HI; 1022 case ISD::SETUGE: return ARMCC::HS; 1023 case ISD::SETULT: return ARMCC::LO; 1024 case ISD::SETULE: return ARMCC::LS; 1025 } 1026} 1027 1028/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. 1029static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, 1030 ARMCC::CondCodes &CondCode2) { 1031 CondCode2 = ARMCC::AL; 1032 switch (CC) { 1033 default: llvm_unreachable("Unknown FP condition!"); 1034 case ISD::SETEQ: 1035 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; 1036 case ISD::SETGT: 1037 case ISD::SETOGT: CondCode = ARMCC::GT; break; 1038 case ISD::SETGE: 1039 case ISD::SETOGE: CondCode = ARMCC::GE; break; 1040 case ISD::SETOLT: CondCode = ARMCC::MI; break; 1041 case ISD::SETOLE: CondCode = ARMCC::LS; break; 1042 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break; 1043 case ISD::SETO: CondCode = ARMCC::VC; break; 1044 case ISD::SETUO: CondCode = ARMCC::VS; break; 1045 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break; 1046 case ISD::SETUGT: CondCode = ARMCC::HI; break; 1047 case ISD::SETUGE: CondCode = ARMCC::PL; break; 1048 case ISD::SETLT: 1049 case ISD::SETULT: CondCode = ARMCC::LT; break; 1050 case ISD::SETLE: 1051 case ISD::SETULE: CondCode = ARMCC::LE; break; 1052 case ISD::SETNE: 1053 case ISD::SETUNE: CondCode = ARMCC::NE; break; 1054 } 1055} 1056 1057//===----------------------------------------------------------------------===// 1058// Calling Convention Implementation 1059//===----------------------------------------------------------------------===// 1060 1061#include "ARMGenCallingConv.inc" 1062 1063/// CCAssignFnForNode - Selects the correct CCAssignFn for a the 1064/// given CallingConvention value. 1065CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC, 1066 bool Return, 1067 bool isVarArg) const { 1068 switch (CC) { 1069 default: 1070 llvm_unreachable("Unsupported calling convention"); 1071 case CallingConv::Fast: 1072 if (Subtarget->hasVFP2() && !isVarArg) { 1073 if (!Subtarget->isAAPCS_ABI()) 1074 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS); 1075 // For AAPCS ABI targets, just use VFP variant of the calling convention. 1076 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP); 1077 } 1078 // Fallthrough 1079 case CallingConv::C: { 1080 // Use target triple & subtarget features to do actual dispatch. 1081 if (!Subtarget->isAAPCS_ABI()) 1082 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS); 1083 else if (Subtarget->hasVFP2() && 1084 FloatABIType == FloatABI::Hard && !isVarArg) 1085 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP); 1086 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS); 1087 } 1088 case CallingConv::ARM_AAPCS_VFP: 1089 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP); 1090 case CallingConv::ARM_AAPCS: 1091 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS); 1092 case CallingConv::ARM_APCS: 1093 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS); 1094 } 1095} 1096 1097/// LowerCallResult - Lower the result values of a call into the 1098/// appropriate copies out of appropriate physical registers. 1099SDValue 1100ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1101 CallingConv::ID CallConv, bool isVarArg, 1102 const SmallVectorImpl<ISD::InputArg> &Ins, 1103 DebugLoc dl, SelectionDAG &DAG, 1104 SmallVectorImpl<SDValue> &InVals) const { 1105 1106 // Assign locations to each value returned by this call. 1107 SmallVector<CCValAssign, 16> RVLocs; 1108 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1109 getTargetMachine(), RVLocs, *DAG.getContext(), Call); 1110 CCInfo.AnalyzeCallResult(Ins, 1111 CCAssignFnForNode(CallConv, /* Return*/ true, 1112 isVarArg)); 1113 1114 // Copy all of the result registers out of their specified physreg. 1115 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1116 CCValAssign VA = RVLocs[i]; 1117 1118 SDValue Val; 1119 if (VA.needsCustom()) { 1120 // Handle f64 or half of a v2f64. 1121 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 1122 InFlag); 1123 Chain = Lo.getValue(1); 1124 InFlag = Lo.getValue(2); 1125 VA = RVLocs[++i]; // skip ahead to next loc 1126 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 1127 InFlag); 1128 Chain = Hi.getValue(1); 1129 InFlag = Hi.getValue(2); 1130 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); 1131 1132 if (VA.getLocVT() == MVT::v2f64) { 1133 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); 1134 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 1135 DAG.getConstant(0, MVT::i32)); 1136 1137 VA = RVLocs[++i]; // skip ahead to next loc 1138 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); 1139 Chain = Lo.getValue(1); 1140 InFlag = Lo.getValue(2); 1141 VA = RVLocs[++i]; // skip ahead to next loc 1142 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); 1143 Chain = Hi.getValue(1); 1144 InFlag = Hi.getValue(2); 1145 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); 1146 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 1147 DAG.getConstant(1, MVT::i32)); 1148 } 1149 } else { 1150 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), 1151 InFlag); 1152 Chain = Val.getValue(1); 1153 InFlag = Val.getValue(2); 1154 } 1155 1156 switch (VA.getLocInfo()) { 1157 default: llvm_unreachable("Unknown loc info!"); 1158 case CCValAssign::Full: break; 1159 case CCValAssign::BCvt: 1160 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val); 1161 break; 1162 } 1163 1164 InVals.push_back(Val); 1165 } 1166 1167 return Chain; 1168} 1169 1170/// LowerMemOpCallTo - Store the argument to the stack. 1171SDValue 1172ARMTargetLowering::LowerMemOpCallTo(SDValue Chain, 1173 SDValue StackPtr, SDValue Arg, 1174 DebugLoc dl, SelectionDAG &DAG, 1175 const CCValAssign &VA, 1176 ISD::ArgFlagsTy Flags) const { 1177 unsigned LocMemOffset = VA.getLocMemOffset(); 1178 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1179 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1180 return DAG.getStore(Chain, dl, Arg, PtrOff, 1181 MachinePointerInfo::getStack(LocMemOffset), 1182 false, false, 0); 1183} 1184 1185void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, 1186 SDValue Chain, SDValue &Arg, 1187 RegsToPassVector &RegsToPass, 1188 CCValAssign &VA, CCValAssign &NextVA, 1189 SDValue &StackPtr, 1190 SmallVector<SDValue, 8> &MemOpChains, 1191 ISD::ArgFlagsTy Flags) const { 1192 1193 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, 1194 DAG.getVTList(MVT::i32, MVT::i32), Arg); 1195 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd)); 1196 1197 if (NextVA.isRegLoc()) 1198 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1))); 1199 else { 1200 assert(NextVA.isMemLoc()); 1201 if (StackPtr.getNode() == 0) 1202 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); 1203 1204 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1), 1205 dl, DAG, NextVA, 1206 Flags)); 1207 } 1208} 1209 1210/// LowerCall - Lowering a call into a callseq_start <- 1211/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter 1212/// nodes. 1213SDValue 1214ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 1215 CallingConv::ID CallConv, bool isVarArg, 1216 bool &isTailCall, 1217 const SmallVectorImpl<ISD::OutputArg> &Outs, 1218 const SmallVectorImpl<SDValue> &OutVals, 1219 const SmallVectorImpl<ISD::InputArg> &Ins, 1220 DebugLoc dl, SelectionDAG &DAG, 1221 SmallVectorImpl<SDValue> &InVals) const { 1222 MachineFunction &MF = DAG.getMachineFunction(); 1223 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet(); 1224 bool IsSibCall = false; 1225 // Disable tail calls if they're not supported. 1226 if (!EnableARMTailCalls && !Subtarget->supportsTailCall()) 1227 isTailCall = false; 1228 if (isTailCall) { 1229 // Check if it's really possible to do a tail call. 1230 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 1231 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 1232 Outs, OutVals, Ins, DAG); 1233 // We don't support GuaranteedTailCallOpt for ARM, only automatically 1234 // detected sibcalls. 1235 if (isTailCall) { 1236 ++NumTailCalls; 1237 IsSibCall = true; 1238 } 1239 } 1240 1241 // Analyze operands of the call, assigning locations to each operand. 1242 SmallVector<CCValAssign, 16> ArgLocs; 1243 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1244 getTargetMachine(), ArgLocs, *DAG.getContext(), Call); 1245 CCInfo.AnalyzeCallOperands(Outs, 1246 CCAssignFnForNode(CallConv, /* Return*/ false, 1247 isVarArg)); 1248 1249 // Get a count of how many bytes are to be pushed on the stack. 1250 unsigned NumBytes = CCInfo.getNextStackOffset(); 1251 1252 // For tail calls, memory operands are available in our caller's stack. 1253 if (IsSibCall) 1254 NumBytes = 0; 1255 1256 // Adjust the stack pointer for the new arguments... 1257 // These operations are automatically eliminated by the prolog/epilog pass 1258 if (!IsSibCall) 1259 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 1260 1261 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); 1262 1263 RegsToPassVector RegsToPass; 1264 SmallVector<SDValue, 8> MemOpChains; 1265 1266 // Walk the register/memloc assignments, inserting copies/loads. In the case 1267 // of tail call optimization, arguments are handled later. 1268 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); 1269 i != e; 1270 ++i, ++realArgIdx) { 1271 CCValAssign &VA = ArgLocs[i]; 1272 SDValue Arg = OutVals[realArgIdx]; 1273 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 1274 bool isByVal = Flags.isByVal(); 1275 1276 // Promote the value if needed. 1277 switch (VA.getLocInfo()) { 1278 default: llvm_unreachable("Unknown loc info!"); 1279 case CCValAssign::Full: break; 1280 case CCValAssign::SExt: 1281 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 1282 break; 1283 case CCValAssign::ZExt: 1284 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 1285 break; 1286 case CCValAssign::AExt: 1287 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 1288 break; 1289 case CCValAssign::BCvt: 1290 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 1291 break; 1292 } 1293 1294 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces 1295 if (VA.needsCustom()) { 1296 if (VA.getLocVT() == MVT::v2f64) { 1297 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1298 DAG.getConstant(0, MVT::i32)); 1299 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1300 DAG.getConstant(1, MVT::i32)); 1301 1302 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass, 1303 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); 1304 1305 VA = ArgLocs[++i]; // skip ahead to next loc 1306 if (VA.isRegLoc()) { 1307 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass, 1308 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); 1309 } else { 1310 assert(VA.isMemLoc()); 1311 1312 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1, 1313 dl, DAG, VA, Flags)); 1314 } 1315 } else { 1316 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i], 1317 StackPtr, MemOpChains, Flags); 1318 } 1319 } else if (VA.isRegLoc()) { 1320 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1321 } else if (isByVal) { 1322 assert(VA.isMemLoc()); 1323 unsigned offset = 0; 1324 1325 // True if this byval aggregate will be split between registers 1326 // and memory. 1327 if (CCInfo.isFirstByValRegValid()) { 1328 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1329 unsigned int i, j; 1330 for (i = 0, j = CCInfo.getFirstByValReg(); j < ARM::R4; i++, j++) { 1331 SDValue Const = DAG.getConstant(4*i, MVT::i32); 1332 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 1333 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, 1334 MachinePointerInfo(), 1335 false, false, 0); 1336 MemOpChains.push_back(Load.getValue(1)); 1337 RegsToPass.push_back(std::make_pair(j, Load)); 1338 } 1339 offset = ARM::R4 - CCInfo.getFirstByValReg(); 1340 CCInfo.clearFirstByValReg(); 1341 } 1342 1343 unsigned LocMemOffset = VA.getLocMemOffset(); 1344 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset); 1345 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, 1346 StkPtrOff); 1347 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset); 1348 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset); 1349 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, 1350 MVT::i32); 1351 // TODO: Disable AlwaysInline when it becomes possible 1352 // to emit a nested call sequence. 1353 MemOpChains.push_back(DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, 1354 Flags.getByValAlign(), 1355 /*isVolatile=*/false, 1356 /*AlwaysInline=*/true, 1357 MachinePointerInfo(0), 1358 MachinePointerInfo(0))); 1359 1360 } else if (!IsSibCall) { 1361 assert(VA.isMemLoc()); 1362 1363 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 1364 dl, DAG, VA, Flags)); 1365 } 1366 } 1367 1368 if (!MemOpChains.empty()) 1369 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1370 &MemOpChains[0], MemOpChains.size()); 1371 1372 // Build a sequence of copy-to-reg nodes chained together with token chain 1373 // and flag operands which copy the outgoing args into the appropriate regs. 1374 SDValue InFlag; 1375 // Tail call byval lowering might overwrite argument registers so in case of 1376 // tail call optimization the copies to registers are lowered later. 1377 if (!isTailCall) 1378 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1379 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1380 RegsToPass[i].second, InFlag); 1381 InFlag = Chain.getValue(1); 1382 } 1383 1384 // For tail calls lower the arguments to the 'real' stack slot. 1385 if (isTailCall) { 1386 // Force all the incoming stack arguments to be loaded from the stack 1387 // before any new outgoing arguments are stored to the stack, because the 1388 // outgoing stack slots may alias the incoming argument stack slots, and 1389 // the alias isn't otherwise explicit. This is slightly more conservative 1390 // than necessary, because it means that each store effectively depends 1391 // on every argument instead of just those arguments it would clobber. 1392 1393 // Do not flag preceding copytoreg stuff together with the following stuff. 1394 InFlag = SDValue(); 1395 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1396 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1397 RegsToPass[i].second, InFlag); 1398 InFlag = Chain.getValue(1); 1399 } 1400 InFlag =SDValue(); 1401 } 1402 1403 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 1404 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 1405 // node so that legalize doesn't hack it. 1406 bool isDirect = false; 1407 bool isARMFunc = false; 1408 bool isLocalARMFunc = false; 1409 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1410 1411 if (EnableARMLongCalls) { 1412 assert (getTargetMachine().getRelocationModel() == Reloc::Static 1413 && "long-calls with non-static relocation model!"); 1414 // Handle a global address or an external symbol. If it's not one of 1415 // those, the target's already in a register, so we don't need to do 1416 // anything extra. 1417 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1418 const GlobalValue *GV = G->getGlobal(); 1419 // Create a constant pool entry for the callee address 1420 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1421 ARMConstantPoolValue *CPV = 1422 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0); 1423 1424 // Get the address of the callee into a register 1425 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1426 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1427 Callee = DAG.getLoad(getPointerTy(), dl, 1428 DAG.getEntryNode(), CPAddr, 1429 MachinePointerInfo::getConstantPool(), 1430 false, false, 0); 1431 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) { 1432 const char *Sym = S->getSymbol(); 1433 1434 // Create a constant pool entry for the callee address 1435 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1436 ARMConstantPoolValue *CPV = 1437 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym, 1438 ARMPCLabelIndex, 0); 1439 // Get the address of the callee into a register 1440 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1441 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1442 Callee = DAG.getLoad(getPointerTy(), dl, 1443 DAG.getEntryNode(), CPAddr, 1444 MachinePointerInfo::getConstantPool(), 1445 false, false, 0); 1446 } 1447 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1448 const GlobalValue *GV = G->getGlobal(); 1449 isDirect = true; 1450 bool isExt = GV->isDeclaration() || GV->isWeakForLinker(); 1451 bool isStub = (isExt && Subtarget->isTargetDarwin()) && 1452 getTargetMachine().getRelocationModel() != Reloc::Static; 1453 isARMFunc = !Subtarget->isThumb() || isStub; 1454 // ARM call to a local ARM function is predicable. 1455 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking); 1456 // tBX takes a register source operand. 1457 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { 1458 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1459 ARMConstantPoolValue *CPV = 1460 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 4); 1461 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1462 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1463 Callee = DAG.getLoad(getPointerTy(), dl, 1464 DAG.getEntryNode(), CPAddr, 1465 MachinePointerInfo::getConstantPool(), 1466 false, false, 0); 1467 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1468 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, 1469 getPointerTy(), Callee, PICLabel); 1470 } else { 1471 // On ELF targets for PIC code, direct calls should go through the PLT 1472 unsigned OpFlags = 0; 1473 if (Subtarget->isTargetELF() && 1474 getTargetMachine().getRelocationModel() == Reloc::PIC_) 1475 OpFlags = ARMII::MO_PLT; 1476 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 1477 } 1478 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 1479 isDirect = true; 1480 bool isStub = Subtarget->isTargetDarwin() && 1481 getTargetMachine().getRelocationModel() != Reloc::Static; 1482 isARMFunc = !Subtarget->isThumb() || isStub; 1483 // tBX takes a register source operand. 1484 const char *Sym = S->getSymbol(); 1485 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { 1486 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1487 ARMConstantPoolValue *CPV = 1488 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym, 1489 ARMPCLabelIndex, 4); 1490 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1491 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1492 Callee = DAG.getLoad(getPointerTy(), dl, 1493 DAG.getEntryNode(), CPAddr, 1494 MachinePointerInfo::getConstantPool(), 1495 false, false, 0); 1496 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1497 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, 1498 getPointerTy(), Callee, PICLabel); 1499 } else { 1500 unsigned OpFlags = 0; 1501 // On ELF targets for PIC code, direct calls should go through the PLT 1502 if (Subtarget->isTargetELF() && 1503 getTargetMachine().getRelocationModel() == Reloc::PIC_) 1504 OpFlags = ARMII::MO_PLT; 1505 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags); 1506 } 1507 } 1508 1509 // FIXME: handle tail calls differently. 1510 unsigned CallOpc; 1511 if (Subtarget->isThumb()) { 1512 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps()) 1513 CallOpc = ARMISD::CALL_NOLINK; 1514 else 1515 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL; 1516 } else { 1517 CallOpc = (isDirect || Subtarget->hasV5TOps()) 1518 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL) 1519 : ARMISD::CALL_NOLINK; 1520 } 1521 1522 std::vector<SDValue> Ops; 1523 Ops.push_back(Chain); 1524 Ops.push_back(Callee); 1525 1526 // Add argument registers to the end of the list so that they are known live 1527 // into the call. 1528 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1529 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1530 RegsToPass[i].second.getValueType())); 1531 1532 if (InFlag.getNode()) 1533 Ops.push_back(InFlag); 1534 1535 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 1536 if (isTailCall) 1537 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size()); 1538 1539 // Returns a chain and a flag for retval copy to use. 1540 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); 1541 InFlag = Chain.getValue(1); 1542 1543 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 1544 DAG.getIntPtrConstant(0, true), InFlag); 1545 if (!Ins.empty()) 1546 InFlag = Chain.getValue(1); 1547 1548 // Handle result values, copying them out of physregs into vregs that we 1549 // return. 1550 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, 1551 dl, DAG, InVals); 1552} 1553 1554/// HandleByVal - Every parameter *after* a byval parameter is passed 1555/// on the stack. Remember the next parameter register to allocate, 1556/// and then confiscate the rest of the parameter registers to insure 1557/// this. 1558void 1559llvm::ARMTargetLowering::HandleByVal(CCState *State, unsigned &size) const { 1560 unsigned reg = State->AllocateReg(GPRArgRegs, 4); 1561 assert((State->getCallOrPrologue() == Prologue || 1562 State->getCallOrPrologue() == Call) && 1563 "unhandled ParmContext"); 1564 if ((!State->isFirstByValRegValid()) && 1565 (ARM::R0 <= reg) && (reg <= ARM::R3)) { 1566 State->setFirstByValReg(reg); 1567 // At a call site, a byval parameter that is split between 1568 // registers and memory needs its size truncated here. In a 1569 // function prologue, such byval parameters are reassembled in 1570 // memory, and are not truncated. 1571 if (State->getCallOrPrologue() == Call) { 1572 unsigned excess = 4 * (ARM::R4 - reg); 1573 assert(size >= excess && "expected larger existing stack allocation"); 1574 size -= excess; 1575 } 1576 } 1577 // Confiscate any remaining parameter registers to preclude their 1578 // assignment to subsequent parameters. 1579 while (State->AllocateReg(GPRArgRegs, 4)) 1580 ; 1581} 1582 1583/// MatchingStackOffset - Return true if the given stack call argument is 1584/// already available in the same position (relatively) of the caller's 1585/// incoming argument stack. 1586static 1587bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 1588 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 1589 const ARMInstrInfo *TII) { 1590 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 1591 int FI = INT_MAX; 1592 if (Arg.getOpcode() == ISD::CopyFromReg) { 1593 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 1594 if (!TargetRegisterInfo::isVirtualRegister(VR)) 1595 return false; 1596 MachineInstr *Def = MRI->getVRegDef(VR); 1597 if (!Def) 1598 return false; 1599 if (!Flags.isByVal()) { 1600 if (!TII->isLoadFromStackSlot(Def, FI)) 1601 return false; 1602 } else { 1603 return false; 1604 } 1605 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 1606 if (Flags.isByVal()) 1607 // ByVal argument is passed in as a pointer but it's now being 1608 // dereferenced. e.g. 1609 // define @foo(%struct.X* %A) { 1610 // tail call @bar(%struct.X* byval %A) 1611 // } 1612 return false; 1613 SDValue Ptr = Ld->getBasePtr(); 1614 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 1615 if (!FINode) 1616 return false; 1617 FI = FINode->getIndex(); 1618 } else 1619 return false; 1620 1621 assert(FI != INT_MAX); 1622 if (!MFI->isFixedObjectIndex(FI)) 1623 return false; 1624 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 1625} 1626 1627/// IsEligibleForTailCallOptimization - Check whether the call is eligible 1628/// for tail call optimization. Targets which want to do tail call 1629/// optimization should implement this function. 1630bool 1631ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 1632 CallingConv::ID CalleeCC, 1633 bool isVarArg, 1634 bool isCalleeStructRet, 1635 bool isCallerStructRet, 1636 const SmallVectorImpl<ISD::OutputArg> &Outs, 1637 const SmallVectorImpl<SDValue> &OutVals, 1638 const SmallVectorImpl<ISD::InputArg> &Ins, 1639 SelectionDAG& DAG) const { 1640 const Function *CallerF = DAG.getMachineFunction().getFunction(); 1641 CallingConv::ID CallerCC = CallerF->getCallingConv(); 1642 bool CCMatch = CallerCC == CalleeCC; 1643 1644 // Look for obvious safe cases to perform tail call optimization that do not 1645 // require ABI changes. This is what gcc calls sibcall. 1646 1647 // Do not sibcall optimize vararg calls unless the call site is not passing 1648 // any arguments. 1649 if (isVarArg && !Outs.empty()) 1650 return false; 1651 1652 // Also avoid sibcall optimization if either caller or callee uses struct 1653 // return semantics. 1654 if (isCalleeStructRet || isCallerStructRet) 1655 return false; 1656 1657 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo:: 1658 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as 1659 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation 1660 // support in the assembler and linker to be used. This would need to be 1661 // fixed to fully support tail calls in Thumb1. 1662 // 1663 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take 1664 // LR. This means if we need to reload LR, it takes an extra instructions, 1665 // which outweighs the value of the tail call; but here we don't know yet 1666 // whether LR is going to be used. Probably the right approach is to 1667 // generate the tail call here and turn it back into CALL/RET in 1668 // emitEpilogue if LR is used. 1669 1670 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls, 1671 // but we need to make sure there are enough registers; the only valid 1672 // registers are the 4 used for parameters. We don't currently do this 1673 // case. 1674 if (Subtarget->isThumb1Only()) 1675 return false; 1676 1677 // If the calling conventions do not match, then we'd better make sure the 1678 // results are returned in the same way as what the caller expects. 1679 if (!CCMatch) { 1680 SmallVector<CCValAssign, 16> RVLocs1; 1681 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 1682 getTargetMachine(), RVLocs1, *DAG.getContext(), Call); 1683 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg)); 1684 1685 SmallVector<CCValAssign, 16> RVLocs2; 1686 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 1687 getTargetMachine(), RVLocs2, *DAG.getContext(), Call); 1688 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg)); 1689 1690 if (RVLocs1.size() != RVLocs2.size()) 1691 return false; 1692 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 1693 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 1694 return false; 1695 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 1696 return false; 1697 if (RVLocs1[i].isRegLoc()) { 1698 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 1699 return false; 1700 } else { 1701 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 1702 return false; 1703 } 1704 } 1705 } 1706 1707 // If the callee takes no arguments then go on to check the results of the 1708 // call. 1709 if (!Outs.empty()) { 1710 // Check if stack adjustment is needed. For now, do not do this if any 1711 // argument is passed on the stack. 1712 SmallVector<CCValAssign, 16> ArgLocs; 1713 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 1714 getTargetMachine(), ArgLocs, *DAG.getContext(), Call); 1715 CCInfo.AnalyzeCallOperands(Outs, 1716 CCAssignFnForNode(CalleeCC, false, isVarArg)); 1717 if (CCInfo.getNextStackOffset()) { 1718 MachineFunction &MF = DAG.getMachineFunction(); 1719 1720 // Check if the arguments are already laid out in the right way as 1721 // the caller's fixed stack objects. 1722 MachineFrameInfo *MFI = MF.getFrameInfo(); 1723 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 1724 const ARMInstrInfo *TII = 1725 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo(); 1726 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); 1727 i != e; 1728 ++i, ++realArgIdx) { 1729 CCValAssign &VA = ArgLocs[i]; 1730 EVT RegVT = VA.getLocVT(); 1731 SDValue Arg = OutVals[realArgIdx]; 1732 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 1733 if (VA.getLocInfo() == CCValAssign::Indirect) 1734 return false; 1735 if (VA.needsCustom()) { 1736 // f64 and vector types are split into multiple registers or 1737 // register/stack-slot combinations. The types will not match 1738 // the registers; give up on memory f64 refs until we figure 1739 // out what to do about this. 1740 if (!VA.isRegLoc()) 1741 return false; 1742 if (!ArgLocs[++i].isRegLoc()) 1743 return false; 1744 if (RegVT == MVT::v2f64) { 1745 if (!ArgLocs[++i].isRegLoc()) 1746 return false; 1747 if (!ArgLocs[++i].isRegLoc()) 1748 return false; 1749 } 1750 } else if (!VA.isRegLoc()) { 1751 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 1752 MFI, MRI, TII)) 1753 return false; 1754 } 1755 } 1756 } 1757 } 1758 1759 return true; 1760} 1761 1762SDValue 1763ARMTargetLowering::LowerReturn(SDValue Chain, 1764 CallingConv::ID CallConv, bool isVarArg, 1765 const SmallVectorImpl<ISD::OutputArg> &Outs, 1766 const SmallVectorImpl<SDValue> &OutVals, 1767 DebugLoc dl, SelectionDAG &DAG) const { 1768 1769 // CCValAssign - represent the assignment of the return value to a location. 1770 SmallVector<CCValAssign, 16> RVLocs; 1771 1772 // CCState - Info about the registers and stack slots. 1773 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1774 getTargetMachine(), RVLocs, *DAG.getContext(), Call); 1775 1776 // Analyze outgoing return values. 1777 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true, 1778 isVarArg)); 1779 1780 // If this is the first return lowered for this function, add 1781 // the regs to the liveout set for the function. 1782 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 1783 for (unsigned i = 0; i != RVLocs.size(); ++i) 1784 if (RVLocs[i].isRegLoc()) 1785 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 1786 } 1787 1788 SDValue Flag; 1789 1790 // Copy the result values into the output registers. 1791 for (unsigned i = 0, realRVLocIdx = 0; 1792 i != RVLocs.size(); 1793 ++i, ++realRVLocIdx) { 1794 CCValAssign &VA = RVLocs[i]; 1795 assert(VA.isRegLoc() && "Can only return in registers!"); 1796 1797 SDValue Arg = OutVals[realRVLocIdx]; 1798 1799 switch (VA.getLocInfo()) { 1800 default: llvm_unreachable("Unknown loc info!"); 1801 case CCValAssign::Full: break; 1802 case CCValAssign::BCvt: 1803 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 1804 break; 1805 } 1806 1807 if (VA.needsCustom()) { 1808 if (VA.getLocVT() == MVT::v2f64) { 1809 // Extract the first half and return it in two registers. 1810 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1811 DAG.getConstant(0, MVT::i32)); 1812 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl, 1813 DAG.getVTList(MVT::i32, MVT::i32), Half); 1814 1815 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag); 1816 Flag = Chain.getValue(1); 1817 VA = RVLocs[++i]; // skip ahead to next loc 1818 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 1819 HalfGPRs.getValue(1), Flag); 1820 Flag = Chain.getValue(1); 1821 VA = RVLocs[++i]; // skip ahead to next loc 1822 1823 // Extract the 2nd half and fall through to handle it as an f64 value. 1824 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1825 DAG.getConstant(1, MVT::i32)); 1826 } 1827 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is 1828 // available. 1829 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, 1830 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1); 1831 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag); 1832 Flag = Chain.getValue(1); 1833 VA = RVLocs[++i]; // skip ahead to next loc 1834 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1), 1835 Flag); 1836 } else 1837 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); 1838 1839 // Guarantee that all emitted copies are 1840 // stuck together, avoiding something bad. 1841 Flag = Chain.getValue(1); 1842 } 1843 1844 SDValue result; 1845 if (Flag.getNode()) 1846 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 1847 else // Return Void 1848 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain); 1849 1850 return result; 1851} 1852 1853bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N) const { 1854 if (N->getNumValues() != 1) 1855 return false; 1856 if (!N->hasNUsesOfValue(1, 0)) 1857 return false; 1858 1859 unsigned NumCopies = 0; 1860 SDNode* Copies[2]; 1861 SDNode *Use = *N->use_begin(); 1862 if (Use->getOpcode() == ISD::CopyToReg) { 1863 Copies[NumCopies++] = Use; 1864 } else if (Use->getOpcode() == ARMISD::VMOVRRD) { 1865 // f64 returned in a pair of GPRs. 1866 for (SDNode::use_iterator UI = Use->use_begin(), UE = Use->use_end(); 1867 UI != UE; ++UI) { 1868 if (UI->getOpcode() != ISD::CopyToReg) 1869 return false; 1870 Copies[UI.getUse().getResNo()] = *UI; 1871 ++NumCopies; 1872 } 1873 } else if (Use->getOpcode() == ISD::BITCAST) { 1874 // f32 returned in a single GPR. 1875 if (!Use->hasNUsesOfValue(1, 0)) 1876 return false; 1877 Use = *Use->use_begin(); 1878 if (Use->getOpcode() != ISD::CopyToReg || !Use->hasNUsesOfValue(1, 0)) 1879 return false; 1880 Copies[NumCopies++] = Use; 1881 } else { 1882 return false; 1883 } 1884 1885 if (NumCopies != 1 && NumCopies != 2) 1886 return false; 1887 1888 bool HasRet = false; 1889 for (unsigned i = 0; i < NumCopies; ++i) { 1890 SDNode *Copy = Copies[i]; 1891 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1892 UI != UE; ++UI) { 1893 if (UI->getOpcode() == ISD::CopyToReg) { 1894 SDNode *Use = *UI; 1895 if (Use == Copies[0] || Use == Copies[1]) 1896 continue; 1897 return false; 1898 } 1899 if (UI->getOpcode() != ARMISD::RET_FLAG) 1900 return false; 1901 HasRet = true; 1902 } 1903 } 1904 1905 return HasRet; 1906} 1907 1908bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1909 if (!EnableARMTailCalls) 1910 return false; 1911 1912 if (!CI->isTailCall()) 1913 return false; 1914 1915 return !Subtarget->isThumb1Only(); 1916} 1917 1918// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 1919// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is 1920// one of the above mentioned nodes. It has to be wrapped because otherwise 1921// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 1922// be used to form addressing mode. These wrapped nodes will be selected 1923// into MOVi. 1924static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) { 1925 EVT PtrVT = Op.getValueType(); 1926 // FIXME there is no actual debug info here 1927 DebugLoc dl = Op.getDebugLoc(); 1928 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1929 SDValue Res; 1930 if (CP->isMachineConstantPoolEntry()) 1931 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, 1932 CP->getAlignment()); 1933 else 1934 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, 1935 CP->getAlignment()); 1936 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res); 1937} 1938 1939unsigned ARMTargetLowering::getJumpTableEncoding() const { 1940 return MachineJumpTableInfo::EK_Inline; 1941} 1942 1943SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op, 1944 SelectionDAG &DAG) const { 1945 MachineFunction &MF = DAG.getMachineFunction(); 1946 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1947 unsigned ARMPCLabelIndex = 0; 1948 DebugLoc DL = Op.getDebugLoc(); 1949 EVT PtrVT = getPointerTy(); 1950 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1951 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 1952 SDValue CPAddr; 1953 if (RelocM == Reloc::Static) { 1954 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4); 1955 } else { 1956 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 1957 ARMPCLabelIndex = AFI->createPICLabelUId(); 1958 ARMConstantPoolValue *CPV = 1959 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex, 1960 ARMCP::CPBlockAddress, PCAdj); 1961 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1962 } 1963 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr); 1964 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr, 1965 MachinePointerInfo::getConstantPool(), 1966 false, false, 0); 1967 if (RelocM == Reloc::Static) 1968 return Result; 1969 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1970 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel); 1971} 1972 1973// Lower ISD::GlobalTLSAddress using the "general dynamic" model 1974SDValue 1975ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 1976 SelectionDAG &DAG) const { 1977 DebugLoc dl = GA->getDebugLoc(); 1978 EVT PtrVT = getPointerTy(); 1979 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 1980 MachineFunction &MF = DAG.getMachineFunction(); 1981 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1982 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1983 ARMConstantPoolValue *CPV = 1984 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex, 1985 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true); 1986 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1987 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument); 1988 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, 1989 MachinePointerInfo::getConstantPool(), 1990 false, false, 0); 1991 SDValue Chain = Argument.getValue(1); 1992 1993 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1994 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel); 1995 1996 // call __tls_get_addr. 1997 ArgListTy Args; 1998 ArgListEntry Entry; 1999 Entry.Node = Argument; 2000 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext()); 2001 Args.push_back(Entry); 2002 // FIXME: is there useful debug info available here? 2003 std::pair<SDValue, SDValue> CallResult = 2004 LowerCallTo(Chain, (Type *) Type::getInt32Ty(*DAG.getContext()), 2005 false, false, false, false, 2006 0, CallingConv::C, false, /*isReturnValueUsed=*/true, 2007 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl); 2008 return CallResult.first; 2009} 2010 2011// Lower ISD::GlobalTLSAddress using the "initial exec" or 2012// "local exec" model. 2013SDValue 2014ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, 2015 SelectionDAG &DAG) const { 2016 const GlobalValue *GV = GA->getGlobal(); 2017 DebugLoc dl = GA->getDebugLoc(); 2018 SDValue Offset; 2019 SDValue Chain = DAG.getEntryNode(); 2020 EVT PtrVT = getPointerTy(); 2021 // Get the Thread Pointer 2022 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); 2023 2024 if (GV->isDeclaration()) { 2025 MachineFunction &MF = DAG.getMachineFunction(); 2026 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2027 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 2028 // Initial exec model. 2029 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 2030 ARMConstantPoolValue *CPV = 2031 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex, 2032 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF, 2033 true); 2034 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2035 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); 2036 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 2037 MachinePointerInfo::getConstantPool(), 2038 false, false, 0); 2039 Chain = Offset.getValue(1); 2040 2041 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2042 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel); 2043 2044 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 2045 MachinePointerInfo::getConstantPool(), 2046 false, false, 0); 2047 } else { 2048 // local exec model 2049 ARMConstantPoolValue *CPV = 2050 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF); 2051 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2052 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); 2053 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 2054 MachinePointerInfo::getConstantPool(), 2055 false, false, 0); 2056 } 2057 2058 // The address of the thread local variable is the add of the thread 2059 // pointer with the offset of the variable. 2060 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 2061} 2062 2063SDValue 2064ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 2065 // TODO: implement the "local dynamic" model 2066 assert(Subtarget->isTargetELF() && 2067 "TLS not implemented for non-ELF targets"); 2068 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 2069 // If the relocation model is PIC, use the "General Dynamic" TLS Model, 2070 // otherwise use the "Local Exec" TLS Model 2071 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) 2072 return LowerToTLSGeneralDynamicModel(GA, DAG); 2073 else 2074 return LowerToTLSExecModels(GA, DAG); 2075} 2076 2077SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, 2078 SelectionDAG &DAG) const { 2079 EVT PtrVT = getPointerTy(); 2080 DebugLoc dl = Op.getDebugLoc(); 2081 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 2082 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 2083 if (RelocM == Reloc::PIC_) { 2084 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility(); 2085 ARMConstantPoolValue *CPV = 2086 ARMConstantPoolConstant::Create(GV, 2087 UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT); 2088 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2089 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2090 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 2091 CPAddr, 2092 MachinePointerInfo::getConstantPool(), 2093 false, false, 0); 2094 SDValue Chain = Result.getValue(1); 2095 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT); 2096 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT); 2097 if (!UseGOTOFF) 2098 Result = DAG.getLoad(PtrVT, dl, Chain, Result, 2099 MachinePointerInfo::getGOT(), false, false, 0); 2100 return Result; 2101 } 2102 2103 // If we have T2 ops, we can materialize the address directly via movt/movw 2104 // pair. This is always cheaper. 2105 if (Subtarget->useMovt()) { 2106 ++NumMovwMovt; 2107 // FIXME: Once remat is capable of dealing with instructions with register 2108 // operands, expand this into two nodes. 2109 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT, 2110 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); 2111 } else { 2112 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); 2113 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2114 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2115 MachinePointerInfo::getConstantPool(), 2116 false, false, 0); 2117 } 2118} 2119 2120SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op, 2121 SelectionDAG &DAG) const { 2122 EVT PtrVT = getPointerTy(); 2123 DebugLoc dl = Op.getDebugLoc(); 2124 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 2125 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 2126 MachineFunction &MF = DAG.getMachineFunction(); 2127 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2128 2129 // FIXME: Enable this for static codegen when tool issues are fixed. 2130 if (Subtarget->useMovt() && RelocM != Reloc::Static) { 2131 ++NumMovwMovt; 2132 // FIXME: Once remat is capable of dealing with instructions with register 2133 // operands, expand this into two nodes. 2134 if (RelocM == Reloc::Static) 2135 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT, 2136 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); 2137 2138 unsigned Wrapper = (RelocM == Reloc::PIC_) 2139 ? ARMISD::WrapperPIC : ARMISD::WrapperDYN; 2140 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, 2141 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); 2142 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) 2143 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result, 2144 MachinePointerInfo::getGOT(), false, false, 0); 2145 return Result; 2146 } 2147 2148 unsigned ARMPCLabelIndex = 0; 2149 SDValue CPAddr; 2150 if (RelocM == Reloc::Static) { 2151 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); 2152 } else { 2153 ARMPCLabelIndex = AFI->createPICLabelUId(); 2154 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8); 2155 ARMConstantPoolValue *CPV = 2156 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 2157 PCAdj); 2158 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2159 } 2160 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2161 2162 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2163 MachinePointerInfo::getConstantPool(), 2164 false, false, 0); 2165 SDValue Chain = Result.getValue(1); 2166 2167 if (RelocM == Reloc::PIC_) { 2168 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2169 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 2170 } 2171 2172 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) 2173 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(), 2174 false, false, 0); 2175 2176 return Result; 2177} 2178 2179SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, 2180 SelectionDAG &DAG) const { 2181 assert(Subtarget->isTargetELF() && 2182 "GLOBAL OFFSET TABLE not implemented for non-ELF targets"); 2183 MachineFunction &MF = DAG.getMachineFunction(); 2184 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2185 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 2186 EVT PtrVT = getPointerTy(); 2187 DebugLoc dl = Op.getDebugLoc(); 2188 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 2189 ARMConstantPoolValue *CPV = 2190 ARMConstantPoolSymbol::Create(*DAG.getContext(), "_GLOBAL_OFFSET_TABLE_", 2191 ARMPCLabelIndex, PCAdj); 2192 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2193 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2194 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2195 MachinePointerInfo::getConstantPool(), 2196 false, false, 0); 2197 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2198 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 2199} 2200 2201SDValue 2202ARMTargetLowering::LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG) 2203 const { 2204 DebugLoc dl = Op.getDebugLoc(); 2205 return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other, 2206 Op.getOperand(0), Op.getOperand(1)); 2207} 2208 2209SDValue 2210ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const { 2211 DebugLoc dl = Op.getDebugLoc(); 2212 SDValue Val = DAG.getConstant(0, MVT::i32); 2213 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, 2214 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0), 2215 Op.getOperand(1), Val); 2216} 2217 2218SDValue 2219ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const { 2220 DebugLoc dl = Op.getDebugLoc(); 2221 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0), 2222 Op.getOperand(1), DAG.getConstant(0, MVT::i32)); 2223} 2224 2225SDValue 2226ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 2227 const ARMSubtarget *Subtarget) const { 2228 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 2229 DebugLoc dl = Op.getDebugLoc(); 2230 switch (IntNo) { 2231 default: return SDValue(); // Don't custom lower most intrinsics. 2232 case Intrinsic::arm_thread_pointer: { 2233 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2234 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); 2235 } 2236 case Intrinsic::eh_sjlj_lsda: { 2237 MachineFunction &MF = DAG.getMachineFunction(); 2238 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2239 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 2240 EVT PtrVT = getPointerTy(); 2241 DebugLoc dl = Op.getDebugLoc(); 2242 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 2243 SDValue CPAddr; 2244 unsigned PCAdj = (RelocM != Reloc::PIC_) 2245 ? 0 : (Subtarget->isThumb() ? 4 : 8); 2246 ARMConstantPoolValue *CPV = 2247 ARMConstantPoolConstant::Create(MF.getFunction(), ARMPCLabelIndex, 2248 ARMCP::CPLSDA, PCAdj); 2249 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2250 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2251 SDValue Result = 2252 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2253 MachinePointerInfo::getConstantPool(), 2254 false, false, 0); 2255 2256 if (RelocM == Reloc::PIC_) { 2257 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2258 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 2259 } 2260 return Result; 2261 } 2262 case Intrinsic::arm_neon_vmulls: 2263 case Intrinsic::arm_neon_vmullu: { 2264 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls) 2265 ? ARMISD::VMULLs : ARMISD::VMULLu; 2266 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(), 2267 Op.getOperand(1), Op.getOperand(2)); 2268 } 2269 } 2270} 2271 2272static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG, 2273 const ARMSubtarget *Subtarget) { 2274 DebugLoc dl = Op.getDebugLoc(); 2275 if (!Subtarget->hasDataBarrier()) { 2276 // Some ARMv6 cpus can support data barriers with an mcr instruction. 2277 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get 2278 // here. 2279 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() && 2280 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!"); 2281 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0), 2282 DAG.getConstant(0, MVT::i32)); 2283 } 2284 2285 SDValue Op5 = Op.getOperand(5); 2286 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0; 2287 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 2288 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 2289 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0); 2290 2291 ARM_MB::MemBOpt DMBOpt; 2292 if (isDeviceBarrier) 2293 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY; 2294 else 2295 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH; 2296 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0), 2297 DAG.getConstant(DMBOpt, MVT::i32)); 2298} 2299 2300 2301static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, 2302 const ARMSubtarget *Subtarget) { 2303 // FIXME: handle "fence singlethread" more efficiently. 2304 DebugLoc dl = Op.getDebugLoc(); 2305 if (!Subtarget->hasDataBarrier()) { 2306 // Some ARMv6 cpus can support data barriers with an mcr instruction. 2307 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get 2308 // here. 2309 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() && 2310 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!"); 2311 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0), 2312 DAG.getConstant(0, MVT::i32)); 2313 } 2314 2315 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0), 2316 DAG.getConstant(ARM_MB::ISH, MVT::i32)); 2317} 2318 2319static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG, 2320 const ARMSubtarget *Subtarget) { 2321 // ARM pre v5TE and Thumb1 does not have preload instructions. 2322 if (!(Subtarget->isThumb2() || 2323 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps()))) 2324 // Just preserve the chain. 2325 return Op.getOperand(0); 2326 2327 DebugLoc dl = Op.getDebugLoc(); 2328 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1; 2329 if (!isRead && 2330 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension())) 2331 // ARMv7 with MP extension has PLDW. 2332 return Op.getOperand(0); 2333 2334 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 2335 if (Subtarget->isThumb()) { 2336 // Invert the bits. 2337 isRead = ~isRead & 1; 2338 isData = ~isData & 1; 2339 } 2340 2341 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0), 2342 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32), 2343 DAG.getConstant(isData, MVT::i32)); 2344} 2345 2346static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) { 2347 MachineFunction &MF = DAG.getMachineFunction(); 2348 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>(); 2349 2350 // vastart just stores the address of the VarArgsFrameIndex slot into the 2351 // memory location argument. 2352 DebugLoc dl = Op.getDebugLoc(); 2353 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2354 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2355 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 2356 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), 2357 MachinePointerInfo(SV), false, false, 0); 2358} 2359 2360SDValue 2361ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 2362 SDValue &Root, SelectionDAG &DAG, 2363 DebugLoc dl) const { 2364 MachineFunction &MF = DAG.getMachineFunction(); 2365 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2366 2367 TargetRegisterClass *RC; 2368 if (AFI->isThumb1OnlyFunction()) 2369 RC = ARM::tGPRRegisterClass; 2370 else 2371 RC = ARM::GPRRegisterClass; 2372 2373 // Transform the arguments stored in physical registers into virtual ones. 2374 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 2375 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); 2376 2377 SDValue ArgValue2; 2378 if (NextVA.isMemLoc()) { 2379 MachineFrameInfo *MFI = MF.getFrameInfo(); 2380 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true); 2381 2382 // Create load node to retrieve arguments from the stack. 2383 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2384 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, 2385 MachinePointerInfo::getFixedStack(FI), 2386 false, false, 0); 2387 } else { 2388 Reg = MF.addLiveIn(NextVA.getLocReg(), RC); 2389 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); 2390 } 2391 2392 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2); 2393} 2394 2395void 2396ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF, 2397 unsigned &VARegSize, unsigned &VARegSaveSize) 2398 const { 2399 unsigned NumGPRs; 2400 if (CCInfo.isFirstByValRegValid()) 2401 NumGPRs = ARM::R4 - CCInfo.getFirstByValReg(); 2402 else { 2403 unsigned int firstUnalloced; 2404 firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs, 2405 sizeof(GPRArgRegs) / 2406 sizeof(GPRArgRegs[0])); 2407 NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0; 2408 } 2409 2410 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment(); 2411 VARegSize = NumGPRs * 4; 2412 VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1); 2413} 2414 2415// The remaining GPRs hold either the beginning of variable-argument 2416// data, or the beginning of an aggregate passed by value (usuall 2417// byval). Either way, we allocate stack slots adjacent to the data 2418// provided by our caller, and store the unallocated registers there. 2419// If this is a variadic function, the va_list pointer will begin with 2420// these values; otherwise, this reassembles a (byval) structure that 2421// was split between registers and memory. 2422void 2423ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, 2424 DebugLoc dl, SDValue &Chain, 2425 unsigned ArgOffset) const { 2426 MachineFunction &MF = DAG.getMachineFunction(); 2427 MachineFrameInfo *MFI = MF.getFrameInfo(); 2428 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2429 unsigned firstRegToSaveIndex; 2430 if (CCInfo.isFirstByValRegValid()) 2431 firstRegToSaveIndex = CCInfo.getFirstByValReg() - ARM::R0; 2432 else { 2433 firstRegToSaveIndex = CCInfo.getFirstUnallocated 2434 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0])); 2435 } 2436 2437 unsigned VARegSize, VARegSaveSize; 2438 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize); 2439 if (VARegSaveSize) { 2440 // If this function is vararg, store any remaining integer argument regs 2441 // to their spots on the stack so that they may be loaded by deferencing 2442 // the result of va_next. 2443 AFI->setVarArgsRegSaveSize(VARegSaveSize); 2444 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(VARegSaveSize, 2445 ArgOffset + VARegSaveSize 2446 - VARegSize, 2447 false)); 2448 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), 2449 getPointerTy()); 2450 2451 SmallVector<SDValue, 4> MemOps; 2452 for (; firstRegToSaveIndex < 4; ++firstRegToSaveIndex) { 2453 TargetRegisterClass *RC; 2454 if (AFI->isThumb1OnlyFunction()) 2455 RC = ARM::tGPRRegisterClass; 2456 else 2457 RC = ARM::GPRRegisterClass; 2458 2459 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC); 2460 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 2461 SDValue Store = 2462 DAG.getStore(Val.getValue(1), dl, Val, FIN, 2463 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()), 2464 false, false, 0); 2465 MemOps.push_back(Store); 2466 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN, 2467 DAG.getConstant(4, getPointerTy())); 2468 } 2469 if (!MemOps.empty()) 2470 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2471 &MemOps[0], MemOps.size()); 2472 } else 2473 // This will point to the next argument passed via stack. 2474 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true)); 2475} 2476 2477SDValue 2478ARMTargetLowering::LowerFormalArguments(SDValue Chain, 2479 CallingConv::ID CallConv, bool isVarArg, 2480 const SmallVectorImpl<ISD::InputArg> 2481 &Ins, 2482 DebugLoc dl, SelectionDAG &DAG, 2483 SmallVectorImpl<SDValue> &InVals) 2484 const { 2485 MachineFunction &MF = DAG.getMachineFunction(); 2486 MachineFrameInfo *MFI = MF.getFrameInfo(); 2487 2488 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2489 2490 // Assign locations to all of the incoming arguments. 2491 SmallVector<CCValAssign, 16> ArgLocs; 2492 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2493 getTargetMachine(), ArgLocs, *DAG.getContext(), Prologue); 2494 CCInfo.AnalyzeFormalArguments(Ins, 2495 CCAssignFnForNode(CallConv, /* Return*/ false, 2496 isVarArg)); 2497 2498 SmallVector<SDValue, 16> ArgValues; 2499 int lastInsIndex = -1; 2500 2501 SDValue ArgValue; 2502 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2503 CCValAssign &VA = ArgLocs[i]; 2504 2505 // Arguments stored in registers. 2506 if (VA.isRegLoc()) { 2507 EVT RegVT = VA.getLocVT(); 2508 2509 if (VA.needsCustom()) { 2510 // f64 and vector types are split up into multiple registers or 2511 // combinations of registers and stack slots. 2512 if (VA.getLocVT() == MVT::v2f64) { 2513 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i], 2514 Chain, DAG, dl); 2515 VA = ArgLocs[++i]; // skip ahead to next loc 2516 SDValue ArgValue2; 2517 if (VA.isMemLoc()) { 2518 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true); 2519 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2520 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN, 2521 MachinePointerInfo::getFixedStack(FI), 2522 false, false, 0); 2523 } else { 2524 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], 2525 Chain, DAG, dl); 2526 } 2527 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); 2528 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, 2529 ArgValue, ArgValue1, DAG.getIntPtrConstant(0)); 2530 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, 2531 ArgValue, ArgValue2, DAG.getIntPtrConstant(1)); 2532 } else 2533 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl); 2534 2535 } else { 2536 TargetRegisterClass *RC; 2537 2538 if (RegVT == MVT::f32) 2539 RC = ARM::SPRRegisterClass; 2540 else if (RegVT == MVT::f64) 2541 RC = ARM::DPRRegisterClass; 2542 else if (RegVT == MVT::v2f64) 2543 RC = ARM::QPRRegisterClass; 2544 else if (RegVT == MVT::i32) 2545 RC = (AFI->isThumb1OnlyFunction() ? 2546 ARM::tGPRRegisterClass : ARM::GPRRegisterClass); 2547 else 2548 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering"); 2549 2550 // Transform the arguments in physical registers into virtual ones. 2551 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 2552 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 2553 } 2554 2555 // If this is an 8 or 16-bit value, it is really passed promoted 2556 // to 32 bits. Insert an assert[sz]ext to capture this, then 2557 // truncate to the right size. 2558 switch (VA.getLocInfo()) { 2559 default: llvm_unreachable("Unknown loc info!"); 2560 case CCValAssign::Full: break; 2561 case CCValAssign::BCvt: 2562 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 2563 break; 2564 case CCValAssign::SExt: 2565 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 2566 DAG.getValueType(VA.getValVT())); 2567 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2568 break; 2569 case CCValAssign::ZExt: 2570 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 2571 DAG.getValueType(VA.getValVT())); 2572 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2573 break; 2574 } 2575 2576 InVals.push_back(ArgValue); 2577 2578 } else { // VA.isRegLoc() 2579 2580 // sanity check 2581 assert(VA.isMemLoc()); 2582 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered"); 2583 2584 int index = ArgLocs[i].getValNo(); 2585 2586 // Some Ins[] entries become multiple ArgLoc[] entries. 2587 // Process them only once. 2588 if (index != lastInsIndex) 2589 { 2590 ISD::ArgFlagsTy Flags = Ins[index].Flags; 2591 // FIXME: For now, all byval parameter objects are marked mutable. 2592 // This can be changed with more analysis. 2593 // In case of tail call optimization mark all arguments mutable. 2594 // Since they could be overwritten by lowering of arguments in case of 2595 // a tail call. 2596 if (Flags.isByVal()) { 2597 unsigned VARegSize, VARegSaveSize; 2598 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize); 2599 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, 0); 2600 unsigned Bytes = Flags.getByValSize() - VARegSize; 2601 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 2602 int FI = MFI->CreateFixedObject(Bytes, 2603 VA.getLocMemOffset(), false); 2604 InVals.push_back(DAG.getFrameIndex(FI, getPointerTy())); 2605 } else { 2606 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8, 2607 VA.getLocMemOffset(), true); 2608 2609 // Create load nodes to retrieve arguments from the stack. 2610 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2611 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 2612 MachinePointerInfo::getFixedStack(FI), 2613 false, false, 0)); 2614 } 2615 lastInsIndex = index; 2616 } 2617 } 2618 } 2619 2620 // varargs 2621 if (isVarArg) 2622 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, CCInfo.getNextStackOffset()); 2623 2624 return Chain; 2625} 2626 2627/// isFloatingPointZero - Return true if this is +0.0. 2628static bool isFloatingPointZero(SDValue Op) { 2629 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 2630 return CFP->getValueAPF().isPosZero(); 2631 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 2632 // Maybe this has already been legalized into the constant pool? 2633 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) { 2634 SDValue WrapperOp = Op.getOperand(1).getOperand(0); 2635 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp)) 2636 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 2637 return CFP->getValueAPF().isPosZero(); 2638 } 2639 } 2640 return false; 2641} 2642 2643/// Returns appropriate ARM CMP (cmp) and corresponding condition code for 2644/// the given operands. 2645SDValue 2646ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 2647 SDValue &ARMcc, SelectionDAG &DAG, 2648 DebugLoc dl) const { 2649 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) { 2650 unsigned C = RHSC->getZExtValue(); 2651 if (!isLegalICmpImmediate(C)) { 2652 // Constant does not fit, try adjusting it by one? 2653 switch (CC) { 2654 default: break; 2655 case ISD::SETLT: 2656 case ISD::SETGE: 2657 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) { 2658 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 2659 RHS = DAG.getConstant(C-1, MVT::i32); 2660 } 2661 break; 2662 case ISD::SETULT: 2663 case ISD::SETUGE: 2664 if (C != 0 && isLegalICmpImmediate(C-1)) { 2665 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 2666 RHS = DAG.getConstant(C-1, MVT::i32); 2667 } 2668 break; 2669 case ISD::SETLE: 2670 case ISD::SETGT: 2671 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) { 2672 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; 2673 RHS = DAG.getConstant(C+1, MVT::i32); 2674 } 2675 break; 2676 case ISD::SETULE: 2677 case ISD::SETUGT: 2678 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) { 2679 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 2680 RHS = DAG.getConstant(C+1, MVT::i32); 2681 } 2682 break; 2683 } 2684 } 2685 } 2686 2687 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 2688 ARMISD::NodeType CompareType; 2689 switch (CondCode) { 2690 default: 2691 CompareType = ARMISD::CMP; 2692 break; 2693 case ARMCC::EQ: 2694 case ARMCC::NE: 2695 // Uses only Z Flag 2696 CompareType = ARMISD::CMPZ; 2697 break; 2698 } 2699 ARMcc = DAG.getConstant(CondCode, MVT::i32); 2700 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS); 2701} 2702 2703/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands. 2704SDValue 2705ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, 2706 DebugLoc dl) const { 2707 SDValue Cmp; 2708 if (!isFloatingPointZero(RHS)) 2709 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS); 2710 else 2711 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS); 2712 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp); 2713} 2714 2715/// duplicateCmp - Glue values can have only one use, so this function 2716/// duplicates a comparison node. 2717SDValue 2718ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const { 2719 unsigned Opc = Cmp.getOpcode(); 2720 DebugLoc DL = Cmp.getDebugLoc(); 2721 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ) 2722 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1)); 2723 2724 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation"); 2725 Cmp = Cmp.getOperand(0); 2726 Opc = Cmp.getOpcode(); 2727 if (Opc == ARMISD::CMPFP) 2728 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1)); 2729 else { 2730 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT"); 2731 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0)); 2732 } 2733 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp); 2734} 2735 2736SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 2737 SDValue Cond = Op.getOperand(0); 2738 SDValue SelectTrue = Op.getOperand(1); 2739 SDValue SelectFalse = Op.getOperand(2); 2740 DebugLoc dl = Op.getDebugLoc(); 2741 2742 // Convert: 2743 // 2744 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond) 2745 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond) 2746 // 2747 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) { 2748 const ConstantSDNode *CMOVTrue = 2749 dyn_cast<ConstantSDNode>(Cond.getOperand(0)); 2750 const ConstantSDNode *CMOVFalse = 2751 dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 2752 2753 if (CMOVTrue && CMOVFalse) { 2754 unsigned CMOVTrueVal = CMOVTrue->getZExtValue(); 2755 unsigned CMOVFalseVal = CMOVFalse->getZExtValue(); 2756 2757 SDValue True; 2758 SDValue False; 2759 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) { 2760 True = SelectTrue; 2761 False = SelectFalse; 2762 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) { 2763 True = SelectFalse; 2764 False = SelectTrue; 2765 } 2766 2767 if (True.getNode() && False.getNode()) { 2768 EVT VT = Op.getValueType(); 2769 SDValue ARMcc = Cond.getOperand(2); 2770 SDValue CCR = Cond.getOperand(3); 2771 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG); 2772 assert(True.getValueType() == VT); 2773 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp); 2774 } 2775 } 2776 } 2777 2778 return DAG.getSelectCC(dl, Cond, 2779 DAG.getConstant(0, Cond.getValueType()), 2780 SelectTrue, SelectFalse, ISD::SETNE); 2781} 2782 2783SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 2784 EVT VT = Op.getValueType(); 2785 SDValue LHS = Op.getOperand(0); 2786 SDValue RHS = Op.getOperand(1); 2787 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 2788 SDValue TrueVal = Op.getOperand(2); 2789 SDValue FalseVal = Op.getOperand(3); 2790 DebugLoc dl = Op.getDebugLoc(); 2791 2792 if (LHS.getValueType() == MVT::i32) { 2793 SDValue ARMcc; 2794 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2795 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); 2796 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp); 2797 } 2798 2799 ARMCC::CondCodes CondCode, CondCode2; 2800 FPCCToARMCC(CC, CondCode, CondCode2); 2801 2802 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32); 2803 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); 2804 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2805 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, 2806 ARMcc, CCR, Cmp); 2807 if (CondCode2 != ARMCC::AL) { 2808 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32); 2809 // FIXME: Needs another CMP because flag can have but one use. 2810 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl); 2811 Result = DAG.getNode(ARMISD::CMOV, dl, VT, 2812 Result, TrueVal, ARMcc2, CCR, Cmp2); 2813 } 2814 return Result; 2815} 2816 2817/// canChangeToInt - Given the fp compare operand, return true if it is suitable 2818/// to morph to an integer compare sequence. 2819static bool canChangeToInt(SDValue Op, bool &SeenZero, 2820 const ARMSubtarget *Subtarget) { 2821 SDNode *N = Op.getNode(); 2822 if (!N->hasOneUse()) 2823 // Otherwise it requires moving the value from fp to integer registers. 2824 return false; 2825 if (!N->getNumValues()) 2826 return false; 2827 EVT VT = Op.getValueType(); 2828 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow()) 2829 // f32 case is generally profitable. f64 case only makes sense when vcmpe + 2830 // vmrs are very slow, e.g. cortex-a8. 2831 return false; 2832 2833 if (isFloatingPointZero(Op)) { 2834 SeenZero = true; 2835 return true; 2836 } 2837 return ISD::isNormalLoad(N); 2838} 2839 2840static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) { 2841 if (isFloatingPointZero(Op)) 2842 return DAG.getConstant(0, MVT::i32); 2843 2844 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) 2845 return DAG.getLoad(MVT::i32, Op.getDebugLoc(), 2846 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(), 2847 Ld->isVolatile(), Ld->isNonTemporal(), 2848 Ld->getAlignment()); 2849 2850 llvm_unreachable("Unknown VFP cmp argument!"); 2851} 2852 2853static void expandf64Toi32(SDValue Op, SelectionDAG &DAG, 2854 SDValue &RetVal1, SDValue &RetVal2) { 2855 if (isFloatingPointZero(Op)) { 2856 RetVal1 = DAG.getConstant(0, MVT::i32); 2857 RetVal2 = DAG.getConstant(0, MVT::i32); 2858 return; 2859 } 2860 2861 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) { 2862 SDValue Ptr = Ld->getBasePtr(); 2863 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(), 2864 Ld->getChain(), Ptr, 2865 Ld->getPointerInfo(), 2866 Ld->isVolatile(), Ld->isNonTemporal(), 2867 Ld->getAlignment()); 2868 2869 EVT PtrType = Ptr.getValueType(); 2870 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4); 2871 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(), 2872 PtrType, Ptr, DAG.getConstant(4, PtrType)); 2873 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(), 2874 Ld->getChain(), NewPtr, 2875 Ld->getPointerInfo().getWithOffset(4), 2876 Ld->isVolatile(), Ld->isNonTemporal(), 2877 NewAlign); 2878 return; 2879 } 2880 2881 llvm_unreachable("Unknown VFP cmp argument!"); 2882} 2883 2884/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some 2885/// f32 and even f64 comparisons to integer ones. 2886SDValue 2887ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const { 2888 SDValue Chain = Op.getOperand(0); 2889 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 2890 SDValue LHS = Op.getOperand(2); 2891 SDValue RHS = Op.getOperand(3); 2892 SDValue Dest = Op.getOperand(4); 2893 DebugLoc dl = Op.getDebugLoc(); 2894 2895 bool SeenZero = false; 2896 if (canChangeToInt(LHS, SeenZero, Subtarget) && 2897 canChangeToInt(RHS, SeenZero, Subtarget) && 2898 // If one of the operand is zero, it's safe to ignore the NaN case since 2899 // we only care about equality comparisons. 2900 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) { 2901 // If unsafe fp math optimization is enabled and there are no other uses of 2902 // the CMP operands, and the condition code is EQ or NE, we can optimize it 2903 // to an integer comparison. 2904 if (CC == ISD::SETOEQ) 2905 CC = ISD::SETEQ; 2906 else if (CC == ISD::SETUNE) 2907 CC = ISD::SETNE; 2908 2909 SDValue ARMcc; 2910 if (LHS.getValueType() == MVT::f32) { 2911 LHS = bitcastf32Toi32(LHS, DAG); 2912 RHS = bitcastf32Toi32(RHS, DAG); 2913 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); 2914 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2915 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, 2916 Chain, Dest, ARMcc, CCR, Cmp); 2917 } 2918 2919 SDValue LHS1, LHS2; 2920 SDValue RHS1, RHS2; 2921 expandf64Toi32(LHS, DAG, LHS1, LHS2); 2922 expandf64Toi32(RHS, DAG, RHS1, RHS2); 2923 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 2924 ARMcc = DAG.getConstant(CondCode, MVT::i32); 2925 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); 2926 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; 2927 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7); 2928 } 2929 2930 return SDValue(); 2931} 2932 2933SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 2934 SDValue Chain = Op.getOperand(0); 2935 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 2936 SDValue LHS = Op.getOperand(2); 2937 SDValue RHS = Op.getOperand(3); 2938 SDValue Dest = Op.getOperand(4); 2939 DebugLoc dl = Op.getDebugLoc(); 2940 2941 if (LHS.getValueType() == MVT::i32) { 2942 SDValue ARMcc; 2943 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); 2944 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2945 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, 2946 Chain, Dest, ARMcc, CCR, Cmp); 2947 } 2948 2949 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); 2950 2951 if (UnsafeFPMath && 2952 (CC == ISD::SETEQ || CC == ISD::SETOEQ || 2953 CC == ISD::SETNE || CC == ISD::SETUNE)) { 2954 SDValue Result = OptimizeVFPBrcond(Op, DAG); 2955 if (Result.getNode()) 2956 return Result; 2957 } 2958 2959 ARMCC::CondCodes CondCode, CondCode2; 2960 FPCCToARMCC(CC, CondCode, CondCode2); 2961 2962 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32); 2963 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); 2964 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2965 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); 2966 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp }; 2967 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); 2968 if (CondCode2 != ARMCC::AL) { 2969 ARMcc = DAG.getConstant(CondCode2, MVT::i32); 2970 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) }; 2971 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); 2972 } 2973 return Res; 2974} 2975 2976SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const { 2977 SDValue Chain = Op.getOperand(0); 2978 SDValue Table = Op.getOperand(1); 2979 SDValue Index = Op.getOperand(2); 2980 DebugLoc dl = Op.getDebugLoc(); 2981 2982 EVT PTy = getPointerTy(); 2983 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); 2984 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>(); 2985 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); 2986 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); 2987 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId); 2988 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy)); 2989 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 2990 if (Subtarget->isThumb2()) { 2991 // Thumb2 uses a two-level jump. That is, it jumps into the jump table 2992 // which does another jump to the destination. This also makes it easier 2993 // to translate it to TBB / TBH later. 2994 // FIXME: This might not work if the function is extremely large. 2995 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain, 2996 Addr, Op.getOperand(2), JTI, UId); 2997 } 2998 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2999 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr, 3000 MachinePointerInfo::getJumpTable(), 3001 false, false, 0); 3002 Chain = Addr.getValue(1); 3003 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table); 3004 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); 3005 } else { 3006 Addr = DAG.getLoad(PTy, dl, Chain, Addr, 3007 MachinePointerInfo::getJumpTable(), false, false, 0); 3008 Chain = Addr.getValue(1); 3009 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); 3010 } 3011} 3012 3013static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) { 3014 DebugLoc dl = Op.getDebugLoc(); 3015 unsigned Opc; 3016 3017 switch (Op.getOpcode()) { 3018 default: 3019 assert(0 && "Invalid opcode!"); 3020 case ISD::FP_TO_SINT: 3021 Opc = ARMISD::FTOSI; 3022 break; 3023 case ISD::FP_TO_UINT: 3024 Opc = ARMISD::FTOUI; 3025 break; 3026 } 3027 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0)); 3028 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3029} 3030 3031static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 3032 EVT VT = Op.getValueType(); 3033 DebugLoc dl = Op.getDebugLoc(); 3034 3035 assert(Op.getOperand(0).getValueType() == MVT::v4i16 && 3036 "Invalid type for custom lowering!"); 3037 if (VT != MVT::v4f32) 3038 return DAG.UnrollVectorOp(Op.getNode()); 3039 3040 unsigned CastOpc; 3041 unsigned Opc; 3042 switch (Op.getOpcode()) { 3043 default: 3044 assert(0 && "Invalid opcode!"); 3045 case ISD::SINT_TO_FP: 3046 CastOpc = ISD::SIGN_EXTEND; 3047 Opc = ISD::SINT_TO_FP; 3048 break; 3049 case ISD::UINT_TO_FP: 3050 CastOpc = ISD::ZERO_EXTEND; 3051 Opc = ISD::UINT_TO_FP; 3052 break; 3053 } 3054 3055 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0)); 3056 return DAG.getNode(Opc, dl, VT, Op); 3057} 3058 3059static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 3060 EVT VT = Op.getValueType(); 3061 if (VT.isVector()) 3062 return LowerVectorINT_TO_FP(Op, DAG); 3063 3064 DebugLoc dl = Op.getDebugLoc(); 3065 unsigned Opc; 3066 3067 switch (Op.getOpcode()) { 3068 default: 3069 assert(0 && "Invalid opcode!"); 3070 case ISD::SINT_TO_FP: 3071 Opc = ARMISD::SITOF; 3072 break; 3073 case ISD::UINT_TO_FP: 3074 Opc = ARMISD::UITOF; 3075 break; 3076 } 3077 3078 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0)); 3079 return DAG.getNode(Opc, dl, VT, Op); 3080} 3081 3082SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 3083 // Implement fcopysign with a fabs and a conditional fneg. 3084 SDValue Tmp0 = Op.getOperand(0); 3085 SDValue Tmp1 = Op.getOperand(1); 3086 DebugLoc dl = Op.getDebugLoc(); 3087 EVT VT = Op.getValueType(); 3088 EVT SrcVT = Tmp1.getValueType(); 3089 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST || 3090 Tmp0.getOpcode() == ARMISD::VMOVDRR; 3091 bool UseNEON = !InGPR && Subtarget->hasNEON(); 3092 3093 if (UseNEON) { 3094 // Use VBSL to copy the sign bit. 3095 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80); 3096 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32, 3097 DAG.getTargetConstant(EncodedVal, MVT::i32)); 3098 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64; 3099 if (VT == MVT::f64) 3100 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT, 3101 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask), 3102 DAG.getConstant(32, MVT::i32)); 3103 else /*if (VT == MVT::f32)*/ 3104 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0); 3105 if (SrcVT == MVT::f32) { 3106 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1); 3107 if (VT == MVT::f64) 3108 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT, 3109 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1), 3110 DAG.getConstant(32, MVT::i32)); 3111 } else if (VT == MVT::f32) 3112 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64, 3113 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1), 3114 DAG.getConstant(32, MVT::i32)); 3115 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0); 3116 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1); 3117 3118 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff), 3119 MVT::i32); 3120 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes); 3121 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask, 3122 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes)); 3123 3124 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT, 3125 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask), 3126 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot)); 3127 if (VT == MVT::f32) { 3128 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res); 3129 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res, 3130 DAG.getConstant(0, MVT::i32)); 3131 } else { 3132 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res); 3133 } 3134 3135 return Res; 3136 } 3137 3138 // Bitcast operand 1 to i32. 3139 if (SrcVT == MVT::f64) 3140 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), 3141 &Tmp1, 1).getValue(1); 3142 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1); 3143 3144 // Or in the signbit with integer operations. 3145 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32); 3146 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32); 3147 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1); 3148 if (VT == MVT::f32) { 3149 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32, 3150 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2); 3151 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, 3152 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1)); 3153 } 3154 3155 // f64: Or the high part with signbit and then combine two parts. 3156 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), 3157 &Tmp0, 1); 3158 SDValue Lo = Tmp0.getValue(0); 3159 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2); 3160 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1); 3161 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); 3162} 3163 3164SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{ 3165 MachineFunction &MF = DAG.getMachineFunction(); 3166 MachineFrameInfo *MFI = MF.getFrameInfo(); 3167 MFI->setReturnAddressIsTaken(true); 3168 3169 EVT VT = Op.getValueType(); 3170 DebugLoc dl = Op.getDebugLoc(); 3171 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 3172 if (Depth) { 3173 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 3174 SDValue Offset = DAG.getConstant(4, MVT::i32); 3175 return DAG.getLoad(VT, dl, DAG.getEntryNode(), 3176 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset), 3177 MachinePointerInfo(), false, false, 0); 3178 } 3179 3180 // Return LR, which contains the return address. Mark it an implicit live-in. 3181 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32)); 3182 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT); 3183} 3184 3185SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 3186 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3187 MFI->setFrameAddressIsTaken(true); 3188 3189 EVT VT = Op.getValueType(); 3190 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 3191 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 3192 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin()) 3193 ? ARM::R7 : ARM::R11; 3194 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 3195 while (Depth--) 3196 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 3197 MachinePointerInfo(), 3198 false, false, 0); 3199 return FrameAddr; 3200} 3201 3202/// ExpandBITCAST - If the target supports VFP, this function is called to 3203/// expand a bit convert where either the source or destination type is i64 to 3204/// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64 3205/// operand type is illegal (e.g., v2f32 for a target that doesn't support 3206/// vectors), since the legalizer won't know what to do with that. 3207static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) { 3208 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3209 DebugLoc dl = N->getDebugLoc(); 3210 SDValue Op = N->getOperand(0); 3211 3212 // This function is only supposed to be called for i64 types, either as the 3213 // source or destination of the bit convert. 3214 EVT SrcVT = Op.getValueType(); 3215 EVT DstVT = N->getValueType(0); 3216 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) && 3217 "ExpandBITCAST called for non-i64 type"); 3218 3219 // Turn i64->f64 into VMOVDRR. 3220 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) { 3221 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, 3222 DAG.getConstant(0, MVT::i32)); 3223 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, 3224 DAG.getConstant(1, MVT::i32)); 3225 return DAG.getNode(ISD::BITCAST, dl, DstVT, 3226 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi)); 3227 } 3228 3229 // Turn f64->i64 into VMOVRRD. 3230 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) { 3231 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, 3232 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1); 3233 // Merge the pieces into a single i64 value. 3234 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1)); 3235 } 3236 3237 return SDValue(); 3238} 3239 3240/// getZeroVector - Returns a vector of specified type with all zero elements. 3241/// Zero vectors are used to represent vector negation and in those cases 3242/// will be implemented with the NEON VNEG instruction. However, VNEG does 3243/// not support i64 elements, so sometimes the zero vectors will need to be 3244/// explicitly constructed. Regardless, use a canonical VMOV to create the 3245/// zero vector. 3246static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 3247 assert(VT.isVector() && "Expected a vector type"); 3248 // The canonical modified immediate encoding of a zero vector is....0! 3249 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32); 3250 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32; 3251 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal); 3252 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); 3253} 3254 3255/// LowerShiftRightParts - Lower SRA_PARTS, which returns two 3256/// i32 values and take a 2 x i32 value to shift plus a shift amount. 3257SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op, 3258 SelectionDAG &DAG) const { 3259 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 3260 EVT VT = Op.getValueType(); 3261 unsigned VTBits = VT.getSizeInBits(); 3262 DebugLoc dl = Op.getDebugLoc(); 3263 SDValue ShOpLo = Op.getOperand(0); 3264 SDValue ShOpHi = Op.getOperand(1); 3265 SDValue ShAmt = Op.getOperand(2); 3266 SDValue ARMcc; 3267 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL; 3268 3269 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS); 3270 3271 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, 3272 DAG.getConstant(VTBits, MVT::i32), ShAmt); 3273 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); 3274 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, 3275 DAG.getConstant(VTBits, MVT::i32)); 3276 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); 3277 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 3278 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt); 3279 3280 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 3281 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, 3282 ARMcc, DAG, dl); 3283 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt); 3284 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, 3285 CCR, Cmp); 3286 3287 SDValue Ops[2] = { Lo, Hi }; 3288 return DAG.getMergeValues(Ops, 2, dl); 3289} 3290 3291/// LowerShiftLeftParts - Lower SHL_PARTS, which returns two 3292/// i32 values and take a 2 x i32 value to shift plus a shift amount. 3293SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op, 3294 SelectionDAG &DAG) const { 3295 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 3296 EVT VT = Op.getValueType(); 3297 unsigned VTBits = VT.getSizeInBits(); 3298 DebugLoc dl = Op.getDebugLoc(); 3299 SDValue ShOpLo = Op.getOperand(0); 3300 SDValue ShOpHi = Op.getOperand(1); 3301 SDValue ShAmt = Op.getOperand(2); 3302 SDValue ARMcc; 3303 3304 assert(Op.getOpcode() == ISD::SHL_PARTS); 3305 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, 3306 DAG.getConstant(VTBits, MVT::i32), ShAmt); 3307 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); 3308 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, 3309 DAG.getConstant(VTBits, MVT::i32)); 3310 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); 3311 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); 3312 3313 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 3314 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 3315 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, 3316 ARMcc, DAG, dl); 3317 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 3318 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc, 3319 CCR, Cmp); 3320 3321 SDValue Ops[2] = { Lo, Hi }; 3322 return DAG.getMergeValues(Ops, 2, dl); 3323} 3324 3325SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op, 3326 SelectionDAG &DAG) const { 3327 // The rounding mode is in bits 23:22 of the FPSCR. 3328 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0 3329 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3) 3330 // so that the shift + and get folded into a bitfield extract. 3331 DebugLoc dl = Op.getDebugLoc(); 3332 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32, 3333 DAG.getConstant(Intrinsic::arm_get_fpscr, 3334 MVT::i32)); 3335 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR, 3336 DAG.getConstant(1U << 22, MVT::i32)); 3337 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds, 3338 DAG.getConstant(22, MVT::i32)); 3339 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE, 3340 DAG.getConstant(3, MVT::i32)); 3341} 3342 3343static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG, 3344 const ARMSubtarget *ST) { 3345 EVT VT = N->getValueType(0); 3346 DebugLoc dl = N->getDebugLoc(); 3347 3348 if (!ST->hasV6T2Ops()) 3349 return SDValue(); 3350 3351 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0)); 3352 return DAG.getNode(ISD::CTLZ, dl, VT, rbit); 3353} 3354 3355static SDValue LowerShift(SDNode *N, SelectionDAG &DAG, 3356 const ARMSubtarget *ST) { 3357 EVT VT = N->getValueType(0); 3358 DebugLoc dl = N->getDebugLoc(); 3359 3360 if (!VT.isVector()) 3361 return SDValue(); 3362 3363 // Lower vector shifts on NEON to use VSHL. 3364 assert(ST->hasNEON() && "unexpected vector shift"); 3365 3366 // Left shifts translate directly to the vshiftu intrinsic. 3367 if (N->getOpcode() == ISD::SHL) 3368 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 3369 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32), 3370 N->getOperand(0), N->getOperand(1)); 3371 3372 assert((N->getOpcode() == ISD::SRA || 3373 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode"); 3374 3375 // NEON uses the same intrinsics for both left and right shifts. For 3376 // right shifts, the shift amounts are negative, so negate the vector of 3377 // shift amounts. 3378 EVT ShiftVT = N->getOperand(1).getValueType(); 3379 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT, 3380 getZeroVector(ShiftVT, DAG, dl), 3381 N->getOperand(1)); 3382 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ? 3383 Intrinsic::arm_neon_vshifts : 3384 Intrinsic::arm_neon_vshiftu); 3385 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 3386 DAG.getConstant(vshiftInt, MVT::i32), 3387 N->getOperand(0), NegatedCount); 3388} 3389 3390static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG, 3391 const ARMSubtarget *ST) { 3392 EVT VT = N->getValueType(0); 3393 DebugLoc dl = N->getDebugLoc(); 3394 3395 // We can get here for a node like i32 = ISD::SHL i32, i64 3396 if (VT != MVT::i64) 3397 return SDValue(); 3398 3399 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && 3400 "Unknown shift to lower!"); 3401 3402 // We only lower SRA, SRL of 1 here, all others use generic lowering. 3403 if (!isa<ConstantSDNode>(N->getOperand(1)) || 3404 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1) 3405 return SDValue(); 3406 3407 // If we are in thumb mode, we don't have RRX. 3408 if (ST->isThumb1Only()) return SDValue(); 3409 3410 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr. 3411 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), 3412 DAG.getConstant(0, MVT::i32)); 3413 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), 3414 DAG.getConstant(1, MVT::i32)); 3415 3416 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and 3417 // captures the result into a carry flag. 3418 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG; 3419 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1); 3420 3421 // The low part is an ARMISD::RRX operand, which shifts the carry in. 3422 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1)); 3423 3424 // Merge the pieces into a single i64 value. 3425 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 3426} 3427 3428static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { 3429 SDValue TmpOp0, TmpOp1; 3430 bool Invert = false; 3431 bool Swap = false; 3432 unsigned Opc = 0; 3433 3434 SDValue Op0 = Op.getOperand(0); 3435 SDValue Op1 = Op.getOperand(1); 3436 SDValue CC = Op.getOperand(2); 3437 EVT VT = Op.getValueType(); 3438 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 3439 DebugLoc dl = Op.getDebugLoc(); 3440 3441 if (Op.getOperand(1).getValueType().isFloatingPoint()) { 3442 switch (SetCCOpcode) { 3443 default: llvm_unreachable("Illegal FP comparison"); break; 3444 case ISD::SETUNE: 3445 case ISD::SETNE: Invert = true; // Fallthrough 3446 case ISD::SETOEQ: 3447 case ISD::SETEQ: Opc = ARMISD::VCEQ; break; 3448 case ISD::SETOLT: 3449 case ISD::SETLT: Swap = true; // Fallthrough 3450 case ISD::SETOGT: 3451 case ISD::SETGT: Opc = ARMISD::VCGT; break; 3452 case ISD::SETOLE: 3453 case ISD::SETLE: Swap = true; // Fallthrough 3454 case ISD::SETOGE: 3455 case ISD::SETGE: Opc = ARMISD::VCGE; break; 3456 case ISD::SETUGE: Swap = true; // Fallthrough 3457 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break; 3458 case ISD::SETUGT: Swap = true; // Fallthrough 3459 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break; 3460 case ISD::SETUEQ: Invert = true; // Fallthrough 3461 case ISD::SETONE: 3462 // Expand this to (OLT | OGT). 3463 TmpOp0 = Op0; 3464 TmpOp1 = Op1; 3465 Opc = ISD::OR; 3466 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0); 3467 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1); 3468 break; 3469 case ISD::SETUO: Invert = true; // Fallthrough 3470 case ISD::SETO: 3471 // Expand this to (OLT | OGE). 3472 TmpOp0 = Op0; 3473 TmpOp1 = Op1; 3474 Opc = ISD::OR; 3475 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0); 3476 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1); 3477 break; 3478 } 3479 } else { 3480 // Integer comparisons. 3481 switch (SetCCOpcode) { 3482 default: llvm_unreachable("Illegal integer comparison"); break; 3483 case ISD::SETNE: Invert = true; 3484 case ISD::SETEQ: Opc = ARMISD::VCEQ; break; 3485 case ISD::SETLT: Swap = true; 3486 case ISD::SETGT: Opc = ARMISD::VCGT; break; 3487 case ISD::SETLE: Swap = true; 3488 case ISD::SETGE: Opc = ARMISD::VCGE; break; 3489 case ISD::SETULT: Swap = true; 3490 case ISD::SETUGT: Opc = ARMISD::VCGTU; break; 3491 case ISD::SETULE: Swap = true; 3492 case ISD::SETUGE: Opc = ARMISD::VCGEU; break; 3493 } 3494 3495 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero). 3496 if (Opc == ARMISD::VCEQ) { 3497 3498 SDValue AndOp; 3499 if (ISD::isBuildVectorAllZeros(Op1.getNode())) 3500 AndOp = Op0; 3501 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) 3502 AndOp = Op1; 3503 3504 // Ignore bitconvert. 3505 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST) 3506 AndOp = AndOp.getOperand(0); 3507 3508 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) { 3509 Opc = ARMISD::VTST; 3510 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0)); 3511 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1)); 3512 Invert = !Invert; 3513 } 3514 } 3515 } 3516 3517 if (Swap) 3518 std::swap(Op0, Op1); 3519 3520 // If one of the operands is a constant vector zero, attempt to fold the 3521 // comparison to a specialized compare-against-zero form. 3522 SDValue SingleOp; 3523 if (ISD::isBuildVectorAllZeros(Op1.getNode())) 3524 SingleOp = Op0; 3525 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) { 3526 if (Opc == ARMISD::VCGE) 3527 Opc = ARMISD::VCLEZ; 3528 else if (Opc == ARMISD::VCGT) 3529 Opc = ARMISD::VCLTZ; 3530 SingleOp = Op1; 3531 } 3532 3533 SDValue Result; 3534 if (SingleOp.getNode()) { 3535 switch (Opc) { 3536 case ARMISD::VCEQ: 3537 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break; 3538 case ARMISD::VCGE: 3539 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break; 3540 case ARMISD::VCLEZ: 3541 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break; 3542 case ARMISD::VCGT: 3543 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break; 3544 case ARMISD::VCLTZ: 3545 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break; 3546 default: 3547 Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 3548 } 3549 } else { 3550 Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 3551 } 3552 3553 if (Invert) 3554 Result = DAG.getNOT(dl, Result, VT); 3555 3556 return Result; 3557} 3558 3559/// isNEONModifiedImm - Check if the specified splat value corresponds to a 3560/// valid vector constant for a NEON instruction with a "modified immediate" 3561/// operand (e.g., VMOV). If so, return the encoded value. 3562static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef, 3563 unsigned SplatBitSize, SelectionDAG &DAG, 3564 EVT &VT, bool is128Bits, NEONModImmType type) { 3565 unsigned OpCmode, Imm; 3566 3567 // SplatBitSize is set to the smallest size that splats the vector, so a 3568 // zero vector will always have SplatBitSize == 8. However, NEON modified 3569 // immediate instructions others than VMOV do not support the 8-bit encoding 3570 // of a zero vector, and the default encoding of zero is supposed to be the 3571 // 32-bit version. 3572 if (SplatBits == 0) 3573 SplatBitSize = 32; 3574 3575 switch (SplatBitSize) { 3576 case 8: 3577 if (type != VMOVModImm) 3578 return SDValue(); 3579 // Any 1-byte value is OK. Op=0, Cmode=1110. 3580 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big"); 3581 OpCmode = 0xe; 3582 Imm = SplatBits; 3583 VT = is128Bits ? MVT::v16i8 : MVT::v8i8; 3584 break; 3585 3586 case 16: 3587 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero. 3588 VT = is128Bits ? MVT::v8i16 : MVT::v4i16; 3589 if ((SplatBits & ~0xff) == 0) { 3590 // Value = 0x00nn: Op=x, Cmode=100x. 3591 OpCmode = 0x8; 3592 Imm = SplatBits; 3593 break; 3594 } 3595 if ((SplatBits & ~0xff00) == 0) { 3596 // Value = 0xnn00: Op=x, Cmode=101x. 3597 OpCmode = 0xa; 3598 Imm = SplatBits >> 8; 3599 break; 3600 } 3601 return SDValue(); 3602 3603 case 32: 3604 // NEON's 32-bit VMOV supports splat values where: 3605 // * only one byte is nonzero, or 3606 // * the least significant byte is 0xff and the second byte is nonzero, or 3607 // * the least significant 2 bytes are 0xff and the third is nonzero. 3608 VT = is128Bits ? MVT::v4i32 : MVT::v2i32; 3609 if ((SplatBits & ~0xff) == 0) { 3610 // Value = 0x000000nn: Op=x, Cmode=000x. 3611 OpCmode = 0; 3612 Imm = SplatBits; 3613 break; 3614 } 3615 if ((SplatBits & ~0xff00) == 0) { 3616 // Value = 0x0000nn00: Op=x, Cmode=001x. 3617 OpCmode = 0x2; 3618 Imm = SplatBits >> 8; 3619 break; 3620 } 3621 if ((SplatBits & ~0xff0000) == 0) { 3622 // Value = 0x00nn0000: Op=x, Cmode=010x. 3623 OpCmode = 0x4; 3624 Imm = SplatBits >> 16; 3625 break; 3626 } 3627 if ((SplatBits & ~0xff000000) == 0) { 3628 // Value = 0xnn000000: Op=x, Cmode=011x. 3629 OpCmode = 0x6; 3630 Imm = SplatBits >> 24; 3631 break; 3632 } 3633 3634 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC 3635 if (type == OtherModImm) return SDValue(); 3636 3637 if ((SplatBits & ~0xffff) == 0 && 3638 ((SplatBits | SplatUndef) & 0xff) == 0xff) { 3639 // Value = 0x0000nnff: Op=x, Cmode=1100. 3640 OpCmode = 0xc; 3641 Imm = SplatBits >> 8; 3642 SplatBits |= 0xff; 3643 break; 3644 } 3645 3646 if ((SplatBits & ~0xffffff) == 0 && 3647 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) { 3648 // Value = 0x00nnffff: Op=x, Cmode=1101. 3649 OpCmode = 0xd; 3650 Imm = SplatBits >> 16; 3651 SplatBits |= 0xffff; 3652 break; 3653 } 3654 3655 // Note: there are a few 32-bit splat values (specifically: 00ffff00, 3656 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not 3657 // VMOV.I32. A (very) minor optimization would be to replicate the value 3658 // and fall through here to test for a valid 64-bit splat. But, then the 3659 // caller would also need to check and handle the change in size. 3660 return SDValue(); 3661 3662 case 64: { 3663 if (type != VMOVModImm) 3664 return SDValue(); 3665 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff. 3666 uint64_t BitMask = 0xff; 3667 uint64_t Val = 0; 3668 unsigned ImmMask = 1; 3669 Imm = 0; 3670 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) { 3671 if (((SplatBits | SplatUndef) & BitMask) == BitMask) { 3672 Val |= BitMask; 3673 Imm |= ImmMask; 3674 } else if ((SplatBits & BitMask) != 0) { 3675 return SDValue(); 3676 } 3677 BitMask <<= 8; 3678 ImmMask <<= 1; 3679 } 3680 // Op=1, Cmode=1110. 3681 OpCmode = 0x1e; 3682 SplatBits = Val; 3683 VT = is128Bits ? MVT::v2i64 : MVT::v1i64; 3684 break; 3685 } 3686 3687 default: 3688 llvm_unreachable("unexpected size for isNEONModifiedImm"); 3689 return SDValue(); 3690 } 3691 3692 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm); 3693 return DAG.getTargetConstant(EncodedVal, MVT::i32); 3694} 3695 3696static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT, 3697 bool &ReverseVEXT, unsigned &Imm) { 3698 unsigned NumElts = VT.getVectorNumElements(); 3699 ReverseVEXT = false; 3700 3701 // Assume that the first shuffle index is not UNDEF. Fail if it is. 3702 if (M[0] < 0) 3703 return false; 3704 3705 Imm = M[0]; 3706 3707 // If this is a VEXT shuffle, the immediate value is the index of the first 3708 // element. The other shuffle indices must be the successive elements after 3709 // the first one. 3710 unsigned ExpectedElt = Imm; 3711 for (unsigned i = 1; i < NumElts; ++i) { 3712 // Increment the expected index. If it wraps around, it may still be 3713 // a VEXT but the source vectors must be swapped. 3714 ExpectedElt += 1; 3715 if (ExpectedElt == NumElts * 2) { 3716 ExpectedElt = 0; 3717 ReverseVEXT = true; 3718 } 3719 3720 if (M[i] < 0) continue; // ignore UNDEF indices 3721 if (ExpectedElt != static_cast<unsigned>(M[i])) 3722 return false; 3723 } 3724 3725 // Adjust the index value if the source operands will be swapped. 3726 if (ReverseVEXT) 3727 Imm -= NumElts; 3728 3729 return true; 3730} 3731 3732/// isVREVMask - Check if a vector shuffle corresponds to a VREV 3733/// instruction with the specified blocksize. (The order of the elements 3734/// within each block of the vector is reversed.) 3735static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT, 3736 unsigned BlockSize) { 3737 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) && 3738 "Only possible block sizes for VREV are: 16, 32, 64"); 3739 3740 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3741 if (EltSz == 64) 3742 return false; 3743 3744 unsigned NumElts = VT.getVectorNumElements(); 3745 unsigned BlockElts = M[0] + 1; 3746 // If the first shuffle index is UNDEF, be optimistic. 3747 if (M[0] < 0) 3748 BlockElts = BlockSize / EltSz; 3749 3750 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz) 3751 return false; 3752 3753 for (unsigned i = 0; i < NumElts; ++i) { 3754 if (M[i] < 0) continue; // ignore UNDEF indices 3755 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts)) 3756 return false; 3757 } 3758 3759 return true; 3760} 3761 3762static bool isVTBLMask(const SmallVectorImpl<int> &M, EVT VT) { 3763 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of 3764 // range, then 0 is placed into the resulting vector. So pretty much any mask 3765 // of 8 elements can work here. 3766 return VT == MVT::v8i8 && M.size() == 8; 3767} 3768 3769static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT, 3770 unsigned &WhichResult) { 3771 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3772 if (EltSz == 64) 3773 return false; 3774 3775 unsigned NumElts = VT.getVectorNumElements(); 3776 WhichResult = (M[0] == 0 ? 0 : 1); 3777 for (unsigned i = 0; i < NumElts; i += 2) { 3778 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) || 3779 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult)) 3780 return false; 3781 } 3782 return true; 3783} 3784 3785/// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of 3786/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 3787/// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>. 3788static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT, 3789 unsigned &WhichResult) { 3790 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3791 if (EltSz == 64) 3792 return false; 3793 3794 unsigned NumElts = VT.getVectorNumElements(); 3795 WhichResult = (M[0] == 0 ? 0 : 1); 3796 for (unsigned i = 0; i < NumElts; i += 2) { 3797 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) || 3798 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult)) 3799 return false; 3800 } 3801 return true; 3802} 3803 3804static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT, 3805 unsigned &WhichResult) { 3806 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3807 if (EltSz == 64) 3808 return false; 3809 3810 unsigned NumElts = VT.getVectorNumElements(); 3811 WhichResult = (M[0] == 0 ? 0 : 1); 3812 for (unsigned i = 0; i != NumElts; ++i) { 3813 if (M[i] < 0) continue; // ignore UNDEF indices 3814 if ((unsigned) M[i] != 2 * i + WhichResult) 3815 return false; 3816 } 3817 3818 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3819 if (VT.is64BitVector() && EltSz == 32) 3820 return false; 3821 3822 return true; 3823} 3824 3825/// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of 3826/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 3827/// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>, 3828static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT, 3829 unsigned &WhichResult) { 3830 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3831 if (EltSz == 64) 3832 return false; 3833 3834 unsigned Half = VT.getVectorNumElements() / 2; 3835 WhichResult = (M[0] == 0 ? 0 : 1); 3836 for (unsigned j = 0; j != 2; ++j) { 3837 unsigned Idx = WhichResult; 3838 for (unsigned i = 0; i != Half; ++i) { 3839 int MIdx = M[i + j * Half]; 3840 if (MIdx >= 0 && (unsigned) MIdx != Idx) 3841 return false; 3842 Idx += 2; 3843 } 3844 } 3845 3846 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3847 if (VT.is64BitVector() && EltSz == 32) 3848 return false; 3849 3850 return true; 3851} 3852 3853static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT, 3854 unsigned &WhichResult) { 3855 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3856 if (EltSz == 64) 3857 return false; 3858 3859 unsigned NumElts = VT.getVectorNumElements(); 3860 WhichResult = (M[0] == 0 ? 0 : 1); 3861 unsigned Idx = WhichResult * NumElts / 2; 3862 for (unsigned i = 0; i != NumElts; i += 2) { 3863 if ((M[i] >= 0 && (unsigned) M[i] != Idx) || 3864 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts)) 3865 return false; 3866 Idx += 1; 3867 } 3868 3869 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3870 if (VT.is64BitVector() && EltSz == 32) 3871 return false; 3872 3873 return true; 3874} 3875 3876/// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of 3877/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 3878/// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>. 3879static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT, 3880 unsigned &WhichResult) { 3881 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3882 if (EltSz == 64) 3883 return false; 3884 3885 unsigned NumElts = VT.getVectorNumElements(); 3886 WhichResult = (M[0] == 0 ? 0 : 1); 3887 unsigned Idx = WhichResult * NumElts / 2; 3888 for (unsigned i = 0; i != NumElts; i += 2) { 3889 if ((M[i] >= 0 && (unsigned) M[i] != Idx) || 3890 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx)) 3891 return false; 3892 Idx += 1; 3893 } 3894 3895 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3896 if (VT.is64BitVector() && EltSz == 32) 3897 return false; 3898 3899 return true; 3900} 3901 3902// If N is an integer constant that can be moved into a register in one 3903// instruction, return an SDValue of such a constant (will become a MOV 3904// instruction). Otherwise return null. 3905static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG, 3906 const ARMSubtarget *ST, DebugLoc dl) { 3907 uint64_t Val; 3908 if (!isa<ConstantSDNode>(N)) 3909 return SDValue(); 3910 Val = cast<ConstantSDNode>(N)->getZExtValue(); 3911 3912 if (ST->isThumb1Only()) { 3913 if (Val <= 255 || ~Val <= 255) 3914 return DAG.getConstant(Val, MVT::i32); 3915 } else { 3916 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1) 3917 return DAG.getConstant(Val, MVT::i32); 3918 } 3919 return SDValue(); 3920} 3921 3922// If this is a case we can't handle, return null and let the default 3923// expansion code take care of it. 3924SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, 3925 const ARMSubtarget *ST) const { 3926 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode()); 3927 DebugLoc dl = Op.getDebugLoc(); 3928 EVT VT = Op.getValueType(); 3929 3930 APInt SplatBits, SplatUndef; 3931 unsigned SplatBitSize; 3932 bool HasAnyUndefs; 3933 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { 3934 if (SplatBitSize <= 64) { 3935 // Check if an immediate VMOV works. 3936 EVT VmovVT; 3937 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(), 3938 SplatUndef.getZExtValue(), SplatBitSize, 3939 DAG, VmovVT, VT.is128BitVector(), 3940 VMOVModImm); 3941 if (Val.getNode()) { 3942 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val); 3943 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); 3944 } 3945 3946 // Try an immediate VMVN. 3947 uint64_t NegatedImm = (~SplatBits).getZExtValue(); 3948 Val = isNEONModifiedImm(NegatedImm, 3949 SplatUndef.getZExtValue(), SplatBitSize, 3950 DAG, VmovVT, VT.is128BitVector(), 3951 VMVNModImm); 3952 if (Val.getNode()) { 3953 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val); 3954 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); 3955 } 3956 } 3957 } 3958 3959 // Scan through the operands to see if only one value is used. 3960 unsigned NumElts = VT.getVectorNumElements(); 3961 bool isOnlyLowElement = true; 3962 bool usesOnlyOneValue = true; 3963 bool isConstant = true; 3964 SDValue Value; 3965 for (unsigned i = 0; i < NumElts; ++i) { 3966 SDValue V = Op.getOperand(i); 3967 if (V.getOpcode() == ISD::UNDEF) 3968 continue; 3969 if (i > 0) 3970 isOnlyLowElement = false; 3971 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 3972 isConstant = false; 3973 3974 if (!Value.getNode()) 3975 Value = V; 3976 else if (V != Value) 3977 usesOnlyOneValue = false; 3978 } 3979 3980 if (!Value.getNode()) 3981 return DAG.getUNDEF(VT); 3982 3983 if (isOnlyLowElement) 3984 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value); 3985 3986 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 3987 3988 // Use VDUP for non-constant splats. For f32 constant splats, reduce to 3989 // i32 and try again. 3990 if (usesOnlyOneValue && EltSize <= 32) { 3991 if (!isConstant) 3992 return DAG.getNode(ARMISD::VDUP, dl, VT, Value); 3993 if (VT.getVectorElementType().isFloatingPoint()) { 3994 SmallVector<SDValue, 8> Ops; 3995 for (unsigned i = 0; i < NumElts; ++i) 3996 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32, 3997 Op.getOperand(i))); 3998 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts); 3999 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts); 4000 Val = LowerBUILD_VECTOR(Val, DAG, ST); 4001 if (Val.getNode()) 4002 return DAG.getNode(ISD::BITCAST, dl, VT, Val); 4003 } 4004 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl); 4005 if (Val.getNode()) 4006 return DAG.getNode(ARMISD::VDUP, dl, VT, Val); 4007 } 4008 4009 // If all elements are constants and the case above didn't get hit, fall back 4010 // to the default expansion, which will generate a load from the constant 4011 // pool. 4012 if (isConstant) 4013 return SDValue(); 4014 4015 // Empirical tests suggest this is rarely worth it for vectors of length <= 2. 4016 if (NumElts >= 4) { 4017 SDValue shuffle = ReconstructShuffle(Op, DAG); 4018 if (shuffle != SDValue()) 4019 return shuffle; 4020 } 4021 4022 // Vectors with 32- or 64-bit elements can be built by directly assigning 4023 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands 4024 // will be legalized. 4025 if (EltSize >= 32) { 4026 // Do the expansion with floating-point types, since that is what the VFP 4027 // registers are defined to use, and since i64 is not legal. 4028 EVT EltVT = EVT::getFloatingPointVT(EltSize); 4029 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); 4030 SmallVector<SDValue, 8> Ops; 4031 for (unsigned i = 0; i < NumElts; ++i) 4032 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i))); 4033 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts); 4034 return DAG.getNode(ISD::BITCAST, dl, VT, Val); 4035 } 4036 4037 return SDValue(); 4038} 4039 4040// Gather data to see if the operation can be modelled as a 4041// shuffle in combination with VEXTs. 4042SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op, 4043 SelectionDAG &DAG) const { 4044 DebugLoc dl = Op.getDebugLoc(); 4045 EVT VT = Op.getValueType(); 4046 unsigned NumElts = VT.getVectorNumElements(); 4047 4048 SmallVector<SDValue, 2> SourceVecs; 4049 SmallVector<unsigned, 2> MinElts; 4050 SmallVector<unsigned, 2> MaxElts; 4051 4052 for (unsigned i = 0; i < NumElts; ++i) { 4053 SDValue V = Op.getOperand(i); 4054 if (V.getOpcode() == ISD::UNDEF) 4055 continue; 4056 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) { 4057 // A shuffle can only come from building a vector from various 4058 // elements of other vectors. 4059 return SDValue(); 4060 } 4061 4062 // Record this extraction against the appropriate vector if possible... 4063 SDValue SourceVec = V.getOperand(0); 4064 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue(); 4065 bool FoundSource = false; 4066 for (unsigned j = 0; j < SourceVecs.size(); ++j) { 4067 if (SourceVecs[j] == SourceVec) { 4068 if (MinElts[j] > EltNo) 4069 MinElts[j] = EltNo; 4070 if (MaxElts[j] < EltNo) 4071 MaxElts[j] = EltNo; 4072 FoundSource = true; 4073 break; 4074 } 4075 } 4076 4077 // Or record a new source if not... 4078 if (!FoundSource) { 4079 SourceVecs.push_back(SourceVec); 4080 MinElts.push_back(EltNo); 4081 MaxElts.push_back(EltNo); 4082 } 4083 } 4084 4085 // Currently only do something sane when at most two source vectors 4086 // involved. 4087 if (SourceVecs.size() > 2) 4088 return SDValue(); 4089 4090 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) }; 4091 int VEXTOffsets[2] = {0, 0}; 4092 4093 // This loop extracts the usage patterns of the source vectors 4094 // and prepares appropriate SDValues for a shuffle if possible. 4095 for (unsigned i = 0; i < SourceVecs.size(); ++i) { 4096 if (SourceVecs[i].getValueType() == VT) { 4097 // No VEXT necessary 4098 ShuffleSrcs[i] = SourceVecs[i]; 4099 VEXTOffsets[i] = 0; 4100 continue; 4101 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) { 4102 // It probably isn't worth padding out a smaller vector just to 4103 // break it down again in a shuffle. 4104 return SDValue(); 4105 } 4106 4107 // Since only 64-bit and 128-bit vectors are legal on ARM and 4108 // we've eliminated the other cases... 4109 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts && 4110 "unexpected vector sizes in ReconstructShuffle"); 4111 4112 if (MaxElts[i] - MinElts[i] >= NumElts) { 4113 // Span too large for a VEXT to cope 4114 return SDValue(); 4115 } 4116 4117 if (MinElts[i] >= NumElts) { 4118 // The extraction can just take the second half 4119 VEXTOffsets[i] = NumElts; 4120 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4121 SourceVecs[i], 4122 DAG.getIntPtrConstant(NumElts)); 4123 } else if (MaxElts[i] < NumElts) { 4124 // The extraction can just take the first half 4125 VEXTOffsets[i] = 0; 4126 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4127 SourceVecs[i], 4128 DAG.getIntPtrConstant(0)); 4129 } else { 4130 // An actual VEXT is needed 4131 VEXTOffsets[i] = MinElts[i]; 4132 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4133 SourceVecs[i], 4134 DAG.getIntPtrConstant(0)); 4135 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4136 SourceVecs[i], 4137 DAG.getIntPtrConstant(NumElts)); 4138 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2, 4139 DAG.getConstant(VEXTOffsets[i], MVT::i32)); 4140 } 4141 } 4142 4143 SmallVector<int, 8> Mask; 4144 4145 for (unsigned i = 0; i < NumElts; ++i) { 4146 SDValue Entry = Op.getOperand(i); 4147 if (Entry.getOpcode() == ISD::UNDEF) { 4148 Mask.push_back(-1); 4149 continue; 4150 } 4151 4152 SDValue ExtractVec = Entry.getOperand(0); 4153 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i) 4154 .getOperand(1))->getSExtValue(); 4155 if (ExtractVec == SourceVecs[0]) { 4156 Mask.push_back(ExtractElt - VEXTOffsets[0]); 4157 } else { 4158 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]); 4159 } 4160 } 4161 4162 // Final check before we try to produce nonsense... 4163 if (isShuffleMaskLegal(Mask, VT)) 4164 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1], 4165 &Mask[0]); 4166 4167 return SDValue(); 4168} 4169 4170/// isShuffleMaskLegal - Targets can use this to indicate that they only 4171/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 4172/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 4173/// are assumed to be legal. 4174bool 4175ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 4176 EVT VT) const { 4177 if (VT.getVectorNumElements() == 4 && 4178 (VT.is128BitVector() || VT.is64BitVector())) { 4179 unsigned PFIndexes[4]; 4180 for (unsigned i = 0; i != 4; ++i) { 4181 if (M[i] < 0) 4182 PFIndexes[i] = 8; 4183 else 4184 PFIndexes[i] = M[i]; 4185 } 4186 4187 // Compute the index in the perfect shuffle table. 4188 unsigned PFTableIndex = 4189 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 4190 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 4191 unsigned Cost = (PFEntry >> 30); 4192 4193 if (Cost <= 4) 4194 return true; 4195 } 4196 4197 bool ReverseVEXT; 4198 unsigned Imm, WhichResult; 4199 4200 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 4201 return (EltSize >= 32 || 4202 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 4203 isVREVMask(M, VT, 64) || 4204 isVREVMask(M, VT, 32) || 4205 isVREVMask(M, VT, 16) || 4206 isVEXTMask(M, VT, ReverseVEXT, Imm) || 4207 isVTBLMask(M, VT) || 4208 isVTRNMask(M, VT, WhichResult) || 4209 isVUZPMask(M, VT, WhichResult) || 4210 isVZIPMask(M, VT, WhichResult) || 4211 isVTRN_v_undef_Mask(M, VT, WhichResult) || 4212 isVUZP_v_undef_Mask(M, VT, WhichResult) || 4213 isVZIP_v_undef_Mask(M, VT, WhichResult)); 4214} 4215 4216/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 4217/// the specified operations to build the shuffle. 4218static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 4219 SDValue RHS, SelectionDAG &DAG, 4220 DebugLoc dl) { 4221 unsigned OpNum = (PFEntry >> 26) & 0x0F; 4222 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 4223 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 4224 4225 enum { 4226 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 4227 OP_VREV, 4228 OP_VDUP0, 4229 OP_VDUP1, 4230 OP_VDUP2, 4231 OP_VDUP3, 4232 OP_VEXT1, 4233 OP_VEXT2, 4234 OP_VEXT3, 4235 OP_VUZPL, // VUZP, left result 4236 OP_VUZPR, // VUZP, right result 4237 OP_VZIPL, // VZIP, left result 4238 OP_VZIPR, // VZIP, right result 4239 OP_VTRNL, // VTRN, left result 4240 OP_VTRNR // VTRN, right result 4241 }; 4242 4243 if (OpNum == OP_COPY) { 4244 if (LHSID == (1*9+2)*9+3) return LHS; 4245 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 4246 return RHS; 4247 } 4248 4249 SDValue OpLHS, OpRHS; 4250 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); 4251 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); 4252 EVT VT = OpLHS.getValueType(); 4253 4254 switch (OpNum) { 4255 default: llvm_unreachable("Unknown shuffle opcode!"); 4256 case OP_VREV: 4257 // VREV divides the vector in half and swaps within the half. 4258 if (VT.getVectorElementType() == MVT::i32 || 4259 VT.getVectorElementType() == MVT::f32) 4260 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); 4261 // vrev <4 x i16> -> VREV32 4262 if (VT.getVectorElementType() == MVT::i16) 4263 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS); 4264 // vrev <4 x i8> -> VREV16 4265 assert(VT.getVectorElementType() == MVT::i8); 4266 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS); 4267 case OP_VDUP0: 4268 case OP_VDUP1: 4269 case OP_VDUP2: 4270 case OP_VDUP3: 4271 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, 4272 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32)); 4273 case OP_VEXT1: 4274 case OP_VEXT2: 4275 case OP_VEXT3: 4276 return DAG.getNode(ARMISD::VEXT, dl, VT, 4277 OpLHS, OpRHS, 4278 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32)); 4279 case OP_VUZPL: 4280 case OP_VUZPR: 4281 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 4282 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL); 4283 case OP_VZIPL: 4284 case OP_VZIPR: 4285 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 4286 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL); 4287 case OP_VTRNL: 4288 case OP_VTRNR: 4289 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 4290 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL); 4291 } 4292} 4293 4294static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op, 4295 SmallVectorImpl<int> &ShuffleMask, 4296 SelectionDAG &DAG) { 4297 // Check to see if we can use the VTBL instruction. 4298 SDValue V1 = Op.getOperand(0); 4299 SDValue V2 = Op.getOperand(1); 4300 DebugLoc DL = Op.getDebugLoc(); 4301 4302 SmallVector<SDValue, 8> VTBLMask; 4303 for (SmallVectorImpl<int>::iterator 4304 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I) 4305 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32)); 4306 4307 if (V2.getNode()->getOpcode() == ISD::UNDEF) 4308 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1, 4309 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, 4310 &VTBLMask[0], 8)); 4311 4312 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2, 4313 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, 4314 &VTBLMask[0], 8)); 4315} 4316 4317static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { 4318 SDValue V1 = Op.getOperand(0); 4319 SDValue V2 = Op.getOperand(1); 4320 DebugLoc dl = Op.getDebugLoc(); 4321 EVT VT = Op.getValueType(); 4322 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode()); 4323 SmallVector<int, 8> ShuffleMask; 4324 4325 // Convert shuffles that are directly supported on NEON to target-specific 4326 // DAG nodes, instead of keeping them as shuffles and matching them again 4327 // during code selection. This is more efficient and avoids the possibility 4328 // of inconsistencies between legalization and selection. 4329 // FIXME: floating-point vectors should be canonicalized to integer vectors 4330 // of the same time so that they get CSEd properly. 4331 SVN->getMask(ShuffleMask); 4332 4333 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 4334 if (EltSize <= 32) { 4335 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) { 4336 int Lane = SVN->getSplatIndex(); 4337 // If this is undef splat, generate it via "just" vdup, if possible. 4338 if (Lane == -1) Lane = 0; 4339 4340 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) { 4341 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0)); 4342 } 4343 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1, 4344 DAG.getConstant(Lane, MVT::i32)); 4345 } 4346 4347 bool ReverseVEXT; 4348 unsigned Imm; 4349 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) { 4350 if (ReverseVEXT) 4351 std::swap(V1, V2); 4352 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2, 4353 DAG.getConstant(Imm, MVT::i32)); 4354 } 4355 4356 if (isVREVMask(ShuffleMask, VT, 64)) 4357 return DAG.getNode(ARMISD::VREV64, dl, VT, V1); 4358 if (isVREVMask(ShuffleMask, VT, 32)) 4359 return DAG.getNode(ARMISD::VREV32, dl, VT, V1); 4360 if (isVREVMask(ShuffleMask, VT, 16)) 4361 return DAG.getNode(ARMISD::VREV16, dl, VT, V1); 4362 4363 // Check for Neon shuffles that modify both input vectors in place. 4364 // If both results are used, i.e., if there are two shuffles with the same 4365 // source operands and with masks corresponding to both results of one of 4366 // these operations, DAG memoization will ensure that a single node is 4367 // used for both shuffles. 4368 unsigned WhichResult; 4369 if (isVTRNMask(ShuffleMask, VT, WhichResult)) 4370 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 4371 V1, V2).getValue(WhichResult); 4372 if (isVUZPMask(ShuffleMask, VT, WhichResult)) 4373 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 4374 V1, V2).getValue(WhichResult); 4375 if (isVZIPMask(ShuffleMask, VT, WhichResult)) 4376 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 4377 V1, V2).getValue(WhichResult); 4378 4379 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) 4380 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 4381 V1, V1).getValue(WhichResult); 4382 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) 4383 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 4384 V1, V1).getValue(WhichResult); 4385 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) 4386 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 4387 V1, V1).getValue(WhichResult); 4388 } 4389 4390 // If the shuffle is not directly supported and it has 4 elements, use 4391 // the PerfectShuffle-generated table to synthesize it from other shuffles. 4392 unsigned NumElts = VT.getVectorNumElements(); 4393 if (NumElts == 4) { 4394 unsigned PFIndexes[4]; 4395 for (unsigned i = 0; i != 4; ++i) { 4396 if (ShuffleMask[i] < 0) 4397 PFIndexes[i] = 8; 4398 else 4399 PFIndexes[i] = ShuffleMask[i]; 4400 } 4401 4402 // Compute the index in the perfect shuffle table. 4403 unsigned PFTableIndex = 4404 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 4405 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 4406 unsigned Cost = (PFEntry >> 30); 4407 4408 if (Cost <= 4) 4409 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); 4410 } 4411 4412 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs. 4413 if (EltSize >= 32) { 4414 // Do the expansion with floating-point types, since that is what the VFP 4415 // registers are defined to use, and since i64 is not legal. 4416 EVT EltVT = EVT::getFloatingPointVT(EltSize); 4417 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); 4418 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1); 4419 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2); 4420 SmallVector<SDValue, 8> Ops; 4421 for (unsigned i = 0; i < NumElts; ++i) { 4422 if (ShuffleMask[i] < 0) 4423 Ops.push_back(DAG.getUNDEF(EltVT)); 4424 else 4425 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 4426 ShuffleMask[i] < (int)NumElts ? V1 : V2, 4427 DAG.getConstant(ShuffleMask[i] & (NumElts-1), 4428 MVT::i32))); 4429 } 4430 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts); 4431 return DAG.getNode(ISD::BITCAST, dl, VT, Val); 4432 } 4433 4434 if (VT == MVT::v8i8) { 4435 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG); 4436 if (NewOp.getNode()) 4437 return NewOp; 4438 } 4439 4440 return SDValue(); 4441} 4442 4443static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4444 // EXTRACT_VECTOR_ELT is legal only for immediate indexes. 4445 SDValue Lane = Op.getOperand(1); 4446 if (!isa<ConstantSDNode>(Lane)) 4447 return SDValue(); 4448 4449 SDValue Vec = Op.getOperand(0); 4450 if (Op.getValueType() == MVT::i32 && 4451 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) { 4452 DebugLoc dl = Op.getDebugLoc(); 4453 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane); 4454 } 4455 4456 return Op; 4457} 4458 4459static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 4460 // The only time a CONCAT_VECTORS operation can have legal types is when 4461 // two 64-bit vectors are concatenated to a 128-bit vector. 4462 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 && 4463 "unexpected CONCAT_VECTORS"); 4464 DebugLoc dl = Op.getDebugLoc(); 4465 SDValue Val = DAG.getUNDEF(MVT::v2f64); 4466 SDValue Op0 = Op.getOperand(0); 4467 SDValue Op1 = Op.getOperand(1); 4468 if (Op0.getOpcode() != ISD::UNDEF) 4469 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, 4470 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0), 4471 DAG.getIntPtrConstant(0)); 4472 if (Op1.getOpcode() != ISD::UNDEF) 4473 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, 4474 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1), 4475 DAG.getIntPtrConstant(1)); 4476 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val); 4477} 4478 4479/// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each 4480/// element has been zero/sign-extended, depending on the isSigned parameter, 4481/// from an integer type half its size. 4482static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG, 4483 bool isSigned) { 4484 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32. 4485 EVT VT = N->getValueType(0); 4486 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) { 4487 SDNode *BVN = N->getOperand(0).getNode(); 4488 if (BVN->getValueType(0) != MVT::v4i32 || 4489 BVN->getOpcode() != ISD::BUILD_VECTOR) 4490 return false; 4491 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0; 4492 unsigned HiElt = 1 - LoElt; 4493 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt)); 4494 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt)); 4495 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2)); 4496 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2)); 4497 if (!Lo0 || !Hi0 || !Lo1 || !Hi1) 4498 return false; 4499 if (isSigned) { 4500 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 && 4501 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32) 4502 return true; 4503 } else { 4504 if (Hi0->isNullValue() && Hi1->isNullValue()) 4505 return true; 4506 } 4507 return false; 4508 } 4509 4510 if (N->getOpcode() != ISD::BUILD_VECTOR) 4511 return false; 4512 4513 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 4514 SDNode *Elt = N->getOperand(i).getNode(); 4515 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) { 4516 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 4517 unsigned HalfSize = EltSize / 2; 4518 if (isSigned) { 4519 int64_t SExtVal = C->getSExtValue(); 4520 if ((SExtVal >> HalfSize) != (SExtVal >> EltSize)) 4521 return false; 4522 } else { 4523 if ((C->getZExtValue() >> HalfSize) != 0) 4524 return false; 4525 } 4526 continue; 4527 } 4528 return false; 4529 } 4530 4531 return true; 4532} 4533 4534/// isSignExtended - Check if a node is a vector value that is sign-extended 4535/// or a constant BUILD_VECTOR with sign-extended elements. 4536static bool isSignExtended(SDNode *N, SelectionDAG &DAG) { 4537 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N)) 4538 return true; 4539 if (isExtendedBUILD_VECTOR(N, DAG, true)) 4540 return true; 4541 return false; 4542} 4543 4544/// isZeroExtended - Check if a node is a vector value that is zero-extended 4545/// or a constant BUILD_VECTOR with zero-extended elements. 4546static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) { 4547 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N)) 4548 return true; 4549 if (isExtendedBUILD_VECTOR(N, DAG, false)) 4550 return true; 4551 return false; 4552} 4553 4554/// SkipExtension - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending 4555/// load, or BUILD_VECTOR with extended elements, return the unextended value. 4556static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) { 4557 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND) 4558 return N->getOperand(0); 4559 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) 4560 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(), 4561 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(), 4562 LD->isNonTemporal(), LD->getAlignment()); 4563 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will 4564 // have been legalized as a BITCAST from v4i32. 4565 if (N->getOpcode() == ISD::BITCAST) { 4566 SDNode *BVN = N->getOperand(0).getNode(); 4567 assert(BVN->getOpcode() == ISD::BUILD_VECTOR && 4568 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR"); 4569 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0; 4570 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32, 4571 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2)); 4572 } 4573 // Construct a new BUILD_VECTOR with elements truncated to half the size. 4574 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR"); 4575 EVT VT = N->getValueType(0); 4576 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2; 4577 unsigned NumElts = VT.getVectorNumElements(); 4578 MVT TruncVT = MVT::getIntegerVT(EltSize); 4579 SmallVector<SDValue, 8> Ops; 4580 for (unsigned i = 0; i != NumElts; ++i) { 4581 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i)); 4582 const APInt &CInt = C->getAPIntValue(); 4583 Ops.push_back(DAG.getConstant(CInt.trunc(EltSize), TruncVT)); 4584 } 4585 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 4586 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts); 4587} 4588 4589static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) { 4590 unsigned Opcode = N->getOpcode(); 4591 if (Opcode == ISD::ADD || Opcode == ISD::SUB) { 4592 SDNode *N0 = N->getOperand(0).getNode(); 4593 SDNode *N1 = N->getOperand(1).getNode(); 4594 return N0->hasOneUse() && N1->hasOneUse() && 4595 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); 4596 } 4597 return false; 4598} 4599 4600static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) { 4601 unsigned Opcode = N->getOpcode(); 4602 if (Opcode == ISD::ADD || Opcode == ISD::SUB) { 4603 SDNode *N0 = N->getOperand(0).getNode(); 4604 SDNode *N1 = N->getOperand(1).getNode(); 4605 return N0->hasOneUse() && N1->hasOneUse() && 4606 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); 4607 } 4608 return false; 4609} 4610 4611static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) { 4612 // Multiplications are only custom-lowered for 128-bit vectors so that 4613 // VMULL can be detected. Otherwise v2i64 multiplications are not legal. 4614 EVT VT = Op.getValueType(); 4615 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL"); 4616 SDNode *N0 = Op.getOperand(0).getNode(); 4617 SDNode *N1 = Op.getOperand(1).getNode(); 4618 unsigned NewOpc = 0; 4619 bool isMLA = false; 4620 bool isN0SExt = isSignExtended(N0, DAG); 4621 bool isN1SExt = isSignExtended(N1, DAG); 4622 if (isN0SExt && isN1SExt) 4623 NewOpc = ARMISD::VMULLs; 4624 else { 4625 bool isN0ZExt = isZeroExtended(N0, DAG); 4626 bool isN1ZExt = isZeroExtended(N1, DAG); 4627 if (isN0ZExt && isN1ZExt) 4628 NewOpc = ARMISD::VMULLu; 4629 else if (isN1SExt || isN1ZExt) { 4630 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these 4631 // into (s/zext A * s/zext C) + (s/zext B * s/zext C) 4632 if (isN1SExt && isAddSubSExt(N0, DAG)) { 4633 NewOpc = ARMISD::VMULLs; 4634 isMLA = true; 4635 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) { 4636 NewOpc = ARMISD::VMULLu; 4637 isMLA = true; 4638 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) { 4639 std::swap(N0, N1); 4640 NewOpc = ARMISD::VMULLu; 4641 isMLA = true; 4642 } 4643 } 4644 4645 if (!NewOpc) { 4646 if (VT == MVT::v2i64) 4647 // Fall through to expand this. It is not legal. 4648 return SDValue(); 4649 else 4650 // Other vector multiplications are legal. 4651 return Op; 4652 } 4653 } 4654 4655 // Legalize to a VMULL instruction. 4656 DebugLoc DL = Op.getDebugLoc(); 4657 SDValue Op0; 4658 SDValue Op1 = SkipExtension(N1, DAG); 4659 if (!isMLA) { 4660 Op0 = SkipExtension(N0, DAG); 4661 assert(Op0.getValueType().is64BitVector() && 4662 Op1.getValueType().is64BitVector() && 4663 "unexpected types for extended operands to VMULL"); 4664 return DAG.getNode(NewOpc, DL, VT, Op0, Op1); 4665 } 4666 4667 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during 4668 // isel lowering to take advantage of no-stall back to back vmul + vmla. 4669 // vmull q0, d4, d6 4670 // vmlal q0, d5, d6 4671 // is faster than 4672 // vaddl q0, d4, d5 4673 // vmovl q1, d6 4674 // vmul q0, q0, q1 4675 SDValue N00 = SkipExtension(N0->getOperand(0).getNode(), DAG); 4676 SDValue N01 = SkipExtension(N0->getOperand(1).getNode(), DAG); 4677 EVT Op1VT = Op1.getValueType(); 4678 return DAG.getNode(N0->getOpcode(), DL, VT, 4679 DAG.getNode(NewOpc, DL, VT, 4680 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1), 4681 DAG.getNode(NewOpc, DL, VT, 4682 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); 4683} 4684 4685static SDValue 4686LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) { 4687 // Convert to float 4688 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo)); 4689 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo)); 4690 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X); 4691 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y); 4692 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X); 4693 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y); 4694 // Get reciprocal estimate. 4695 // float4 recip = vrecpeq_f32(yf); 4696 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4697 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y); 4698 // Because char has a smaller range than uchar, we can actually get away 4699 // without any newton steps. This requires that we use a weird bias 4700 // of 0xb000, however (again, this has been exhaustively tested). 4701 // float4 result = as_float4(as_int4(xf*recip) + 0xb000); 4702 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y); 4703 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X); 4704 Y = DAG.getConstant(0xb000, MVT::i32); 4705 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y); 4706 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y); 4707 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X); 4708 // Convert back to short. 4709 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X); 4710 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X); 4711 return X; 4712} 4713 4714static SDValue 4715LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) { 4716 SDValue N2; 4717 // Convert to float. 4718 // float4 yf = vcvt_f32_s32(vmovl_s16(y)); 4719 // float4 xf = vcvt_f32_s32(vmovl_s16(x)); 4720 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0); 4721 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1); 4722 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); 4723 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1); 4724 4725 // Use reciprocal estimate and one refinement step. 4726 // float4 recip = vrecpeq_f32(yf); 4727 // recip *= vrecpsq_f32(yf, recip); 4728 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4729 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1); 4730 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4731 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32), 4732 N1, N2); 4733 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); 4734 // Because short has a smaller range than ushort, we can actually get away 4735 // with only a single newton step. This requires that we use a weird bias 4736 // of 89, however (again, this has been exhaustively tested). 4737 // float4 result = as_float4(as_int4(xf*recip) + 0x89); 4738 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); 4739 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); 4740 N1 = DAG.getConstant(0x89, MVT::i32); 4741 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1); 4742 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); 4743 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); 4744 // Convert back to integer and return. 4745 // return vmovn_s32(vcvt_s32_f32(result)); 4746 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); 4747 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); 4748 return N0; 4749} 4750 4751static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) { 4752 EVT VT = Op.getValueType(); 4753 assert((VT == MVT::v4i16 || VT == MVT::v8i8) && 4754 "unexpected type for custom-lowering ISD::SDIV"); 4755 4756 DebugLoc dl = Op.getDebugLoc(); 4757 SDValue N0 = Op.getOperand(0); 4758 SDValue N1 = Op.getOperand(1); 4759 SDValue N2, N3; 4760 4761 if (VT == MVT::v8i8) { 4762 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0); 4763 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1); 4764 4765 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, 4766 DAG.getIntPtrConstant(4)); 4767 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, 4768 DAG.getIntPtrConstant(4)); 4769 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, 4770 DAG.getIntPtrConstant(0)); 4771 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, 4772 DAG.getIntPtrConstant(0)); 4773 4774 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16 4775 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16 4776 4777 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); 4778 N0 = LowerCONCAT_VECTORS(N0, DAG); 4779 4780 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0); 4781 return N0; 4782 } 4783 return LowerSDIV_v4i16(N0, N1, dl, DAG); 4784} 4785 4786static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) { 4787 EVT VT = Op.getValueType(); 4788 assert((VT == MVT::v4i16 || VT == MVT::v8i8) && 4789 "unexpected type for custom-lowering ISD::UDIV"); 4790 4791 DebugLoc dl = Op.getDebugLoc(); 4792 SDValue N0 = Op.getOperand(0); 4793 SDValue N1 = Op.getOperand(1); 4794 SDValue N2, N3; 4795 4796 if (VT == MVT::v8i8) { 4797 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0); 4798 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1); 4799 4800 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, 4801 DAG.getIntPtrConstant(4)); 4802 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, 4803 DAG.getIntPtrConstant(4)); 4804 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, 4805 DAG.getIntPtrConstant(0)); 4806 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, 4807 DAG.getIntPtrConstant(0)); 4808 4809 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16 4810 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16 4811 4812 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); 4813 N0 = LowerCONCAT_VECTORS(N0, DAG); 4814 4815 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8, 4816 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32), 4817 N0); 4818 return N0; 4819 } 4820 4821 // v4i16 sdiv ... Convert to float. 4822 // float4 yf = vcvt_f32_s32(vmovl_u16(y)); 4823 // float4 xf = vcvt_f32_s32(vmovl_u16(x)); 4824 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0); 4825 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1); 4826 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); 4827 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1); 4828 4829 // Use reciprocal estimate and two refinement steps. 4830 // float4 recip = vrecpeq_f32(yf); 4831 // recip *= vrecpsq_f32(yf, recip); 4832 // recip *= vrecpsq_f32(yf, recip); 4833 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4834 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1); 4835 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4836 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32), 4837 BN1, N2); 4838 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); 4839 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4840 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32), 4841 BN1, N2); 4842 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); 4843 // Simply multiplying by the reciprocal estimate can leave us a few ulps 4844 // too low, so we add 2 ulps (exhaustive testing shows that this is enough, 4845 // and that it will never cause us to return an answer too large). 4846 // float4 result = as_float4(as_int4(xf*recip) + 2); 4847 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); 4848 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); 4849 N1 = DAG.getConstant(2, MVT::i32); 4850 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1); 4851 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); 4852 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); 4853 // Convert back to integer and return. 4854 // return vmovn_u32(vcvt_s32_f32(result)); 4855 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); 4856 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); 4857 return N0; 4858} 4859 4860static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 4861 EVT VT = Op.getNode()->getValueType(0); 4862 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 4863 4864 unsigned Opc; 4865 bool ExtraOp = false; 4866 switch (Op.getOpcode()) { 4867 default: assert(0 && "Invalid code"); 4868 case ISD::ADDC: Opc = ARMISD::ADDC; break; 4869 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break; 4870 case ISD::SUBC: Opc = ARMISD::SUBC; break; 4871 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break; 4872 } 4873 4874 if (!ExtraOp) 4875 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 4876 Op.getOperand(1)); 4877 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 4878 Op.getOperand(1), Op.getOperand(2)); 4879} 4880 4881static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) { 4882 // Monotonic load/store is legal for all targets 4883 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic) 4884 return Op; 4885 4886 // Aquire/Release load/store is not legal for targets without a 4887 // dmb or equivalent available. 4888 return SDValue(); 4889} 4890 4891 4892static void 4893ReplaceATOMIC_OP_64(SDNode *Node, SmallVectorImpl<SDValue>& Results, 4894 SelectionDAG &DAG, unsigned NewOp) { 4895 EVT T = Node->getValueType(0); 4896 DebugLoc dl = Node->getDebugLoc(); 4897 assert (T == MVT::i64 && "Only know how to expand i64 atomics"); 4898 4899 SmallVector<SDValue, 6> Ops; 4900 Ops.push_back(Node->getOperand(0)); // Chain 4901 Ops.push_back(Node->getOperand(1)); // Ptr 4902 // Low part of Val1 4903 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 4904 Node->getOperand(2), DAG.getIntPtrConstant(0))); 4905 // High part of Val1 4906 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 4907 Node->getOperand(2), DAG.getIntPtrConstant(1))); 4908 if (NewOp == ARMISD::ATOMCMPXCHG64_DAG) { 4909 // High part of Val1 4910 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 4911 Node->getOperand(3), DAG.getIntPtrConstant(0))); 4912 // High part of Val2 4913 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 4914 Node->getOperand(3), DAG.getIntPtrConstant(1))); 4915 } 4916 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 4917 SDValue Result = 4918 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops.data(), Ops.size(), MVT::i64, 4919 cast<MemSDNode>(Node)->getMemOperand()); 4920 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1) }; 4921 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 4922 Results.push_back(Result.getValue(2)); 4923} 4924 4925SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 4926 switch (Op.getOpcode()) { 4927 default: llvm_unreachable("Don't know how to custom lower this!"); 4928 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 4929 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 4930 case ISD::GlobalAddress: 4931 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) : 4932 LowerGlobalAddressELF(Op, DAG); 4933 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 4934 case ISD::SELECT: return LowerSELECT(Op, DAG); 4935 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 4936 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 4937 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 4938 case ISD::VASTART: return LowerVASTART(Op, DAG); 4939 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget); 4940 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget); 4941 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget); 4942 case ISD::SINT_TO_FP: 4943 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); 4944 case ISD::FP_TO_SINT: 4945 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG); 4946 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 4947 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 4948 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 4949 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG); 4950 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG); 4951 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG); 4952 case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG); 4953 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG, 4954 Subtarget); 4955 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG); 4956 case ISD::SHL: 4957 case ISD::SRL: 4958 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget); 4959 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG); 4960 case ISD::SRL_PARTS: 4961 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG); 4962 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget); 4963 case ISD::SETCC: return LowerVSETCC(Op, DAG); 4964 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget); 4965 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 4966 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 4967 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 4968 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 4969 case ISD::MUL: return LowerMUL(Op, DAG); 4970 case ISD::SDIV: return LowerSDIV(Op, DAG); 4971 case ISD::UDIV: return LowerUDIV(Op, DAG); 4972 case ISD::ADDC: 4973 case ISD::ADDE: 4974 case ISD::SUBC: 4975 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 4976 case ISD::ATOMIC_LOAD: 4977 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG); 4978 } 4979 return SDValue(); 4980} 4981 4982/// ReplaceNodeResults - Replace the results of node with an illegal result 4983/// type with new values built out of custom code. 4984void ARMTargetLowering::ReplaceNodeResults(SDNode *N, 4985 SmallVectorImpl<SDValue>&Results, 4986 SelectionDAG &DAG) const { 4987 SDValue Res; 4988 switch (N->getOpcode()) { 4989 default: 4990 llvm_unreachable("Don't know how to custom expand this!"); 4991 break; 4992 case ISD::BITCAST: 4993 Res = ExpandBITCAST(N, DAG); 4994 break; 4995 case ISD::SRL: 4996 case ISD::SRA: 4997 Res = Expand64BitShift(N, DAG, Subtarget); 4998 break; 4999 case ISD::ATOMIC_LOAD_ADD: 5000 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMADD64_DAG); 5001 return; 5002 case ISD::ATOMIC_LOAD_AND: 5003 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMAND64_DAG); 5004 return; 5005 case ISD::ATOMIC_LOAD_NAND: 5006 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMNAND64_DAG); 5007 return; 5008 case ISD::ATOMIC_LOAD_OR: 5009 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMOR64_DAG); 5010 return; 5011 case ISD::ATOMIC_LOAD_SUB: 5012 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSUB64_DAG); 5013 return; 5014 case ISD::ATOMIC_LOAD_XOR: 5015 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMXOR64_DAG); 5016 return; 5017 case ISD::ATOMIC_SWAP: 5018 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSWAP64_DAG); 5019 return; 5020 case ISD::ATOMIC_CMP_SWAP: 5021 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMCMPXCHG64_DAG); 5022 return; 5023 } 5024 if (Res.getNode()) 5025 Results.push_back(Res); 5026} 5027 5028//===----------------------------------------------------------------------===// 5029// ARM Scheduler Hooks 5030//===----------------------------------------------------------------------===// 5031 5032MachineBasicBlock * 5033ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, 5034 MachineBasicBlock *BB, 5035 unsigned Size) const { 5036 unsigned dest = MI->getOperand(0).getReg(); 5037 unsigned ptr = MI->getOperand(1).getReg(); 5038 unsigned oldval = MI->getOperand(2).getReg(); 5039 unsigned newval = MI->getOperand(3).getReg(); 5040 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5041 DebugLoc dl = MI->getDebugLoc(); 5042 bool isThumb2 = Subtarget->isThumb2(); 5043 5044 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 5045 unsigned scratch = 5046 MRI.createVirtualRegister(isThumb2 ? ARM::rGPRRegisterClass 5047 : ARM::GPRRegisterClass); 5048 5049 if (isThumb2) { 5050 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass); 5051 MRI.constrainRegClass(oldval, ARM::rGPRRegisterClass); 5052 MRI.constrainRegClass(newval, ARM::rGPRRegisterClass); 5053 } 5054 5055 unsigned ldrOpc, strOpc; 5056 switch (Size) { 5057 default: llvm_unreachable("unsupported size for AtomicCmpSwap!"); 5058 case 1: 5059 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB; 5060 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB; 5061 break; 5062 case 2: 5063 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH; 5064 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH; 5065 break; 5066 case 4: 5067 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX; 5068 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX; 5069 break; 5070 } 5071 5072 MachineFunction *MF = BB->getParent(); 5073 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5074 MachineFunction::iterator It = BB; 5075 ++It; // insert the new blocks after the current block 5076 5077 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 5078 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 5079 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5080 MF->insert(It, loop1MBB); 5081 MF->insert(It, loop2MBB); 5082 MF->insert(It, exitMBB); 5083 5084 // Transfer the remainder of BB and its successor edges to exitMBB. 5085 exitMBB->splice(exitMBB->begin(), BB, 5086 llvm::next(MachineBasicBlock::iterator(MI)), 5087 BB->end()); 5088 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5089 5090 // thisMBB: 5091 // ... 5092 // fallthrough --> loop1MBB 5093 BB->addSuccessor(loop1MBB); 5094 5095 // loop1MBB: 5096 // ldrex dest, [ptr] 5097 // cmp dest, oldval 5098 // bne exitMBB 5099 BB = loop1MBB; 5100 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); 5101 if (ldrOpc == ARM::t2LDREX) 5102 MIB.addImm(0); 5103 AddDefaultPred(MIB); 5104 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 5105 .addReg(dest).addReg(oldval)); 5106 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5107 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5108 BB->addSuccessor(loop2MBB); 5109 BB->addSuccessor(exitMBB); 5110 5111 // loop2MBB: 5112 // strex scratch, newval, [ptr] 5113 // cmp scratch, #0 5114 // bne loop1MBB 5115 BB = loop2MBB; 5116 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval).addReg(ptr); 5117 if (strOpc == ARM::t2STREX) 5118 MIB.addImm(0); 5119 AddDefaultPred(MIB); 5120 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5121 .addReg(scratch).addImm(0)); 5122 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5123 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5124 BB->addSuccessor(loop1MBB); 5125 BB->addSuccessor(exitMBB); 5126 5127 // exitMBB: 5128 // ... 5129 BB = exitMBB; 5130 5131 MI->eraseFromParent(); // The instruction is gone now. 5132 5133 return BB; 5134} 5135 5136MachineBasicBlock * 5137ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 5138 unsigned Size, unsigned BinOpcode) const { 5139 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 5140 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5141 5142 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5143 MachineFunction *MF = BB->getParent(); 5144 MachineFunction::iterator It = BB; 5145 ++It; 5146 5147 unsigned dest = MI->getOperand(0).getReg(); 5148 unsigned ptr = MI->getOperand(1).getReg(); 5149 unsigned incr = MI->getOperand(2).getReg(); 5150 DebugLoc dl = MI->getDebugLoc(); 5151 bool isThumb2 = Subtarget->isThumb2(); 5152 5153 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 5154 if (isThumb2) { 5155 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass); 5156 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass); 5157 } 5158 5159 unsigned ldrOpc, strOpc; 5160 switch (Size) { 5161 default: llvm_unreachable("unsupported size for AtomicCmpSwap!"); 5162 case 1: 5163 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB; 5164 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB; 5165 break; 5166 case 2: 5167 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH; 5168 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH; 5169 break; 5170 case 4: 5171 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX; 5172 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX; 5173 break; 5174 } 5175 5176 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5177 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5178 MF->insert(It, loopMBB); 5179 MF->insert(It, exitMBB); 5180 5181 // Transfer the remainder of BB and its successor edges to exitMBB. 5182 exitMBB->splice(exitMBB->begin(), BB, 5183 llvm::next(MachineBasicBlock::iterator(MI)), 5184 BB->end()); 5185 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5186 5187 TargetRegisterClass *TRC = 5188 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; 5189 unsigned scratch = MRI.createVirtualRegister(TRC); 5190 unsigned scratch2 = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC); 5191 5192 // thisMBB: 5193 // ... 5194 // fallthrough --> loopMBB 5195 BB->addSuccessor(loopMBB); 5196 5197 // loopMBB: 5198 // ldrex dest, ptr 5199 // <binop> scratch2, dest, incr 5200 // strex scratch, scratch2, ptr 5201 // cmp scratch, #0 5202 // bne- loopMBB 5203 // fallthrough --> exitMBB 5204 BB = loopMBB; 5205 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); 5206 if (ldrOpc == ARM::t2LDREX) 5207 MIB.addImm(0); 5208 AddDefaultPred(MIB); 5209 if (BinOpcode) { 5210 // operand order needs to go the other way for NAND 5211 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr) 5212 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2). 5213 addReg(incr).addReg(dest)).addReg(0); 5214 else 5215 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2). 5216 addReg(dest).addReg(incr)).addReg(0); 5217 } 5218 5219 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr); 5220 if (strOpc == ARM::t2STREX) 5221 MIB.addImm(0); 5222 AddDefaultPred(MIB); 5223 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5224 .addReg(scratch).addImm(0)); 5225 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5226 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5227 5228 BB->addSuccessor(loopMBB); 5229 BB->addSuccessor(exitMBB); 5230 5231 // exitMBB: 5232 // ... 5233 BB = exitMBB; 5234 5235 MI->eraseFromParent(); // The instruction is gone now. 5236 5237 return BB; 5238} 5239 5240MachineBasicBlock * 5241ARMTargetLowering::EmitAtomicBinaryMinMax(MachineInstr *MI, 5242 MachineBasicBlock *BB, 5243 unsigned Size, 5244 bool signExtend, 5245 ARMCC::CondCodes Cond) const { 5246 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5247 5248 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5249 MachineFunction *MF = BB->getParent(); 5250 MachineFunction::iterator It = BB; 5251 ++It; 5252 5253 unsigned dest = MI->getOperand(0).getReg(); 5254 unsigned ptr = MI->getOperand(1).getReg(); 5255 unsigned incr = MI->getOperand(2).getReg(); 5256 unsigned oldval = dest; 5257 DebugLoc dl = MI->getDebugLoc(); 5258 bool isThumb2 = Subtarget->isThumb2(); 5259 5260 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 5261 if (isThumb2) { 5262 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass); 5263 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass); 5264 } 5265 5266 unsigned ldrOpc, strOpc, extendOpc; 5267 switch (Size) { 5268 default: llvm_unreachable("unsupported size for AtomicCmpSwap!"); 5269 case 1: 5270 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB; 5271 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB; 5272 extendOpc = isThumb2 ? ARM::t2SXTB : ARM::SXTB; 5273 break; 5274 case 2: 5275 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH; 5276 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH; 5277 extendOpc = isThumb2 ? ARM::t2SXTH : ARM::SXTH; 5278 break; 5279 case 4: 5280 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX; 5281 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX; 5282 extendOpc = 0; 5283 break; 5284 } 5285 5286 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5287 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5288 MF->insert(It, loopMBB); 5289 MF->insert(It, exitMBB); 5290 5291 // Transfer the remainder of BB and its successor edges to exitMBB. 5292 exitMBB->splice(exitMBB->begin(), BB, 5293 llvm::next(MachineBasicBlock::iterator(MI)), 5294 BB->end()); 5295 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5296 5297 TargetRegisterClass *TRC = 5298 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; 5299 unsigned scratch = MRI.createVirtualRegister(TRC); 5300 unsigned scratch2 = MRI.createVirtualRegister(TRC); 5301 5302 // thisMBB: 5303 // ... 5304 // fallthrough --> loopMBB 5305 BB->addSuccessor(loopMBB); 5306 5307 // loopMBB: 5308 // ldrex dest, ptr 5309 // (sign extend dest, if required) 5310 // cmp dest, incr 5311 // cmov.cond scratch2, dest, incr 5312 // strex scratch, scratch2, ptr 5313 // cmp scratch, #0 5314 // bne- loopMBB 5315 // fallthrough --> exitMBB 5316 BB = loopMBB; 5317 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); 5318 if (ldrOpc == ARM::t2LDREX) 5319 MIB.addImm(0); 5320 AddDefaultPred(MIB); 5321 5322 // Sign extend the value, if necessary. 5323 if (signExtend && extendOpc) { 5324 oldval = MRI.createVirtualRegister(ARM::GPRRegisterClass); 5325 AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval) 5326 .addReg(dest) 5327 .addImm(0)); 5328 } 5329 5330 // Build compare and cmov instructions. 5331 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 5332 .addReg(oldval).addReg(incr)); 5333 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr), scratch2) 5334 .addReg(oldval).addReg(incr).addImm(Cond).addReg(ARM::CPSR); 5335 5336 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr); 5337 if (strOpc == ARM::t2STREX) 5338 MIB.addImm(0); 5339 AddDefaultPred(MIB); 5340 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5341 .addReg(scratch).addImm(0)); 5342 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5343 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5344 5345 BB->addSuccessor(loopMBB); 5346 BB->addSuccessor(exitMBB); 5347 5348 // exitMBB: 5349 // ... 5350 BB = exitMBB; 5351 5352 MI->eraseFromParent(); // The instruction is gone now. 5353 5354 return BB; 5355} 5356 5357MachineBasicBlock * 5358ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB, 5359 unsigned Op1, unsigned Op2, 5360 bool NeedsCarry, bool IsCmpxchg) const { 5361 // This also handles ATOMIC_SWAP, indicated by Op1==0. 5362 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5363 5364 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5365 MachineFunction *MF = BB->getParent(); 5366 MachineFunction::iterator It = BB; 5367 ++It; 5368 5369 unsigned destlo = MI->getOperand(0).getReg(); 5370 unsigned desthi = MI->getOperand(1).getReg(); 5371 unsigned ptr = MI->getOperand(2).getReg(); 5372 unsigned vallo = MI->getOperand(3).getReg(); 5373 unsigned valhi = MI->getOperand(4).getReg(); 5374 DebugLoc dl = MI->getDebugLoc(); 5375 bool isThumb2 = Subtarget->isThumb2(); 5376 5377 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 5378 if (isThumb2) { 5379 MRI.constrainRegClass(destlo, ARM::rGPRRegisterClass); 5380 MRI.constrainRegClass(desthi, ARM::rGPRRegisterClass); 5381 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass); 5382 } 5383 5384 unsigned ldrOpc = isThumb2 ? ARM::t2LDREXD : ARM::LDREXD; 5385 unsigned strOpc = isThumb2 ? ARM::t2STREXD : ARM::STREXD; 5386 5387 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5388 MachineBasicBlock *contBB = 0, *cont2BB = 0; 5389 if (IsCmpxchg) { 5390 contBB = MF->CreateMachineBasicBlock(LLVM_BB); 5391 cont2BB = MF->CreateMachineBasicBlock(LLVM_BB); 5392 } 5393 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5394 MF->insert(It, loopMBB); 5395 if (IsCmpxchg) { 5396 MF->insert(It, contBB); 5397 MF->insert(It, cont2BB); 5398 } 5399 MF->insert(It, exitMBB); 5400 5401 // Transfer the remainder of BB and its successor edges to exitMBB. 5402 exitMBB->splice(exitMBB->begin(), BB, 5403 llvm::next(MachineBasicBlock::iterator(MI)), 5404 BB->end()); 5405 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5406 5407 TargetRegisterClass *TRC = 5408 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; 5409 unsigned storesuccess = MRI.createVirtualRegister(TRC); 5410 5411 // thisMBB: 5412 // ... 5413 // fallthrough --> loopMBB 5414 BB->addSuccessor(loopMBB); 5415 5416 // loopMBB: 5417 // ldrexd r2, r3, ptr 5418 // <binopa> r0, r2, incr 5419 // <binopb> r1, r3, incr 5420 // strexd storesuccess, r0, r1, ptr 5421 // cmp storesuccess, #0 5422 // bne- loopMBB 5423 // fallthrough --> exitMBB 5424 // 5425 // Note that the registers are explicitly specified because there is not any 5426 // way to force the register allocator to allocate a register pair. 5427 // 5428 // FIXME: The hardcoded registers are not necessary for Thumb2, but we 5429 // need to properly enforce the restriction that the two output registers 5430 // for ldrexd must be different. 5431 BB = loopMBB; 5432 // Load 5433 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc)) 5434 .addReg(ARM::R2, RegState::Define) 5435 .addReg(ARM::R3, RegState::Define).addReg(ptr)); 5436 // Copy r2/r3 into dest. (This copy will normally be coalesced.) 5437 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), destlo).addReg(ARM::R2); 5438 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), desthi).addReg(ARM::R3); 5439 5440 if (IsCmpxchg) { 5441 // Add early exit 5442 for (unsigned i = 0; i < 2; i++) { 5443 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : 5444 ARM::CMPrr)) 5445 .addReg(i == 0 ? destlo : desthi) 5446 .addReg(i == 0 ? vallo : valhi)); 5447 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5448 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5449 BB->addSuccessor(exitMBB); 5450 BB->addSuccessor(i == 0 ? contBB : cont2BB); 5451 BB = (i == 0 ? contBB : cont2BB); 5452 } 5453 5454 // Copy to physregs for strexd 5455 unsigned setlo = MI->getOperand(5).getReg(); 5456 unsigned sethi = MI->getOperand(6).getReg(); 5457 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(setlo); 5458 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(sethi); 5459 } else if (Op1) { 5460 // Perform binary operation 5461 AddDefaultPred(BuildMI(BB, dl, TII->get(Op1), ARM::R0) 5462 .addReg(destlo).addReg(vallo)) 5463 .addReg(NeedsCarry ? ARM::CPSR : 0, getDefRegState(NeedsCarry)); 5464 AddDefaultPred(BuildMI(BB, dl, TII->get(Op2), ARM::R1) 5465 .addReg(desthi).addReg(valhi)).addReg(0); 5466 } else { 5467 // Copy to physregs for strexd 5468 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(vallo); 5469 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(valhi); 5470 } 5471 5472 // Store 5473 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), storesuccess) 5474 .addReg(ARM::R0).addReg(ARM::R1).addReg(ptr)); 5475 // Cmp+jump 5476 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5477 .addReg(storesuccess).addImm(0)); 5478 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5479 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5480 5481 BB->addSuccessor(loopMBB); 5482 BB->addSuccessor(exitMBB); 5483 5484 // exitMBB: 5485 // ... 5486 BB = exitMBB; 5487 5488 MI->eraseFromParent(); // The instruction is gone now. 5489 5490 return BB; 5491} 5492 5493/// EmitBasePointerRecalculation - For functions using a base pointer, we 5494/// rematerialize it (via the frame pointer). 5495void ARMTargetLowering:: 5496EmitBasePointerRecalculation(MachineInstr *MI, MachineBasicBlock *MBB, 5497 MachineBasicBlock *DispatchBB) const { 5498 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5499 const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII); 5500 MachineFunction &MF = *MI->getParent()->getParent(); 5501 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 5502 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo(); 5503 5504 if (!RI.hasBasePointer(MF)) return; 5505 5506 MachineBasicBlock::iterator MBBI = MI; 5507 5508 int32_t NumBytes = AFI->getFramePtrSpillOffset(); 5509 unsigned FramePtr = RI.getFrameRegister(MF); 5510 assert(MF.getTarget().getFrameLowering()->hasFP(MF) && 5511 "Base pointer without frame pointer?"); 5512 5513 if (AFI->isThumb2Function()) 5514 llvm::emitT2RegPlusImmediate(*MBB, MBBI, MI->getDebugLoc(), ARM::R6, 5515 FramePtr, -NumBytes, ARMCC::AL, 0, *AII); 5516 else if (AFI->isThumbFunction()) 5517 llvm::emitThumbRegPlusImmediate(*MBB, MBBI, MI->getDebugLoc(), ARM::R6, 5518 FramePtr, -NumBytes, *AII, RI); 5519 else 5520 llvm::emitARMRegPlusImmediate(*MBB, MBBI, MI->getDebugLoc(), ARM::R6, 5521 FramePtr, -NumBytes, ARMCC::AL, 0, *AII); 5522 5523 if (!RI.needsStackRealignment(MF)) return; 5524 5525 // If there's dynamic realignment, adjust for it. 5526 MachineFrameInfo *MFI = MF.getFrameInfo(); 5527 unsigned MaxAlign = MFI->getMaxAlignment(); 5528 assert(!AFI->isThumb1OnlyFunction()); 5529 5530 // Emit bic r6, r6, MaxAlign 5531 unsigned bicOpc = AFI->isThumbFunction() ? ARM::t2BICri : ARM::BICri; 5532 AddDefaultCC( 5533 AddDefaultPred( 5534 BuildMI(*MBB, MBBI, MI->getDebugLoc(), TII->get(bicOpc), ARM::R6) 5535 .addReg(ARM::R6, RegState::Kill) 5536 .addImm(MaxAlign - 1))); 5537} 5538 5539/// SetupEntryBlockForSjLj - Insert code into the entry block that creates and 5540/// registers the function context. 5541void ARMTargetLowering:: 5542SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB, 5543 MachineBasicBlock *DispatchBB, int FI) const { 5544 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5545 DebugLoc dl = MI->getDebugLoc(); 5546 MachineFunction *MF = MBB->getParent(); 5547 MachineRegisterInfo *MRI = &MF->getRegInfo(); 5548 MachineConstantPool *MCP = MF->getConstantPool(); 5549 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>(); 5550 const Function *F = MF->getFunction(); 5551 5552 bool isThumb = Subtarget->isThumb(); 5553 bool isThumb2 = Subtarget->isThumb2(); 5554 5555 unsigned PCLabelId = AFI->createPICLabelUId(); 5556 unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8; 5557 ARMConstantPoolValue *CPV = 5558 ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj); 5559 unsigned CPI = MCP->getConstantPoolIndex(CPV, 4); 5560 5561 const TargetRegisterClass *TRC = 5562 isThumb ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; 5563 5564 // Grab constant pool and fixed stack memory operands. 5565 MachineMemOperand *CPMMO = 5566 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(), 5567 MachineMemOperand::MOLoad, 4, 4); 5568 5569 MachineMemOperand *FIMMOSt = 5570 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 5571 MachineMemOperand::MOStore, 4, 4); 5572 5573 EmitBasePointerRecalculation(MI, MBB, DispatchBB); 5574 5575 // Load the address of the dispatch MBB into the jump buffer. 5576 if (isThumb2) { 5577 // Incoming value: jbuf 5578 // ldr.n r5, LCPI1_1 5579 // orr r5, r5, #1 5580 // add r5, pc 5581 // str r5, [$jbuf, #+4] ; &jbuf[1] 5582 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5583 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1) 5584 .addConstantPoolIndex(CPI) 5585 .addMemOperand(CPMMO)); 5586 // Set the low bit because of thumb mode. 5587 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5588 AddDefaultCC( 5589 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2) 5590 .addReg(NewVReg1, RegState::Kill) 5591 .addImm(0x01))); 5592 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 5593 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3) 5594 .addReg(NewVReg2, RegState::Kill) 5595 .addImm(PCLabelId); 5596 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12)) 5597 .addReg(NewVReg3, RegState::Kill) 5598 .addFrameIndex(FI) 5599 .addImm(36) // &jbuf[1] :: pc 5600 .addMemOperand(FIMMOSt)); 5601 } else if (isThumb) { 5602 // Incoming value: jbuf 5603 // ldr.n r1, LCPI1_4 5604 // add r1, pc 5605 // mov r2, #1 5606 // orrs r1, r2 5607 // add r2, $jbuf, #+4 ; &jbuf[1] 5608 // str r1, [r2] 5609 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5610 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1) 5611 .addConstantPoolIndex(CPI) 5612 .addMemOperand(CPMMO)); 5613 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5614 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2) 5615 .addReg(NewVReg1, RegState::Kill) 5616 .addImm(PCLabelId); 5617 // Set the low bit because of thumb mode. 5618 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 5619 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3) 5620 .addReg(ARM::CPSR, RegState::Define) 5621 .addImm(1)); 5622 unsigned NewVReg4 = MRI->createVirtualRegister(TRC); 5623 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4) 5624 .addReg(ARM::CPSR, RegState::Define) 5625 .addReg(NewVReg2, RegState::Kill) 5626 .addReg(NewVReg3, RegState::Kill)); 5627 unsigned NewVReg5 = MRI->createVirtualRegister(TRC); 5628 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tADDrSPi), NewVReg5) 5629 .addFrameIndex(FI) 5630 .addImm(36)); // &jbuf[1] :: pc 5631 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi)) 5632 .addReg(NewVReg4, RegState::Kill) 5633 .addReg(NewVReg5, RegState::Kill) 5634 .addImm(0) 5635 .addMemOperand(FIMMOSt)); 5636 } else { 5637 // Incoming value: jbuf 5638 // ldr r1, LCPI1_1 5639 // add r1, pc, r1 5640 // str r1, [$jbuf, #+4] ; &jbuf[1] 5641 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5642 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1) 5643 .addConstantPoolIndex(CPI) 5644 .addImm(0) 5645 .addMemOperand(CPMMO)); 5646 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5647 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2) 5648 .addReg(NewVReg1, RegState::Kill) 5649 .addImm(PCLabelId)); 5650 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12)) 5651 .addReg(NewVReg2, RegState::Kill) 5652 .addFrameIndex(FI) 5653 .addImm(36) // &jbuf[1] :: pc 5654 .addMemOperand(FIMMOSt)); 5655 } 5656} 5657 5658MachineBasicBlock *ARMTargetLowering:: 5659EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const { 5660 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5661 DebugLoc dl = MI->getDebugLoc(); 5662 MachineFunction *MF = MBB->getParent(); 5663 MachineRegisterInfo *MRI = &MF->getRegInfo(); 5664 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>(); 5665 MachineFrameInfo *MFI = MF->getFrameInfo(); 5666 int FI = MFI->getFunctionContextIndex(); 5667 5668 const TargetRegisterClass *TRC = 5669 Subtarget->isThumb() ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; 5670 5671 // Get a mapping of the call site numbers to all of the landing pads they're 5672 // associated with. 5673 DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2> > CallSiteNumToLPad; 5674 unsigned MaxCSNum = 0; 5675 MachineModuleInfo &MMI = MF->getMMI(); 5676 for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E; ++BB) { 5677 if (!BB->isLandingPad()) continue; 5678 5679 // FIXME: We should assert that the EH_LABEL is the first MI in the landing 5680 // pad. 5681 for (MachineBasicBlock::iterator 5682 II = BB->begin(), IE = BB->end(); II != IE; ++II) { 5683 if (!II->isEHLabel()) continue; 5684 5685 MCSymbol *Sym = II->getOperand(0).getMCSymbol(); 5686 if (!MMI.hasCallSiteLandingPad(Sym)) continue; 5687 5688 SmallVectorImpl<unsigned> &CallSiteIdxs = MMI.getCallSiteLandingPad(Sym); 5689 for (SmallVectorImpl<unsigned>::iterator 5690 CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end(); 5691 CSI != CSE; ++CSI) { 5692 CallSiteNumToLPad[*CSI].push_back(BB); 5693 MaxCSNum = std::max(MaxCSNum, *CSI); 5694 } 5695 break; 5696 } 5697 } 5698 5699 // Get an ordered list of the machine basic blocks for the jump table. 5700 std::vector<MachineBasicBlock*> LPadList; 5701 SmallPtrSet<MachineBasicBlock*, 64> InvokeBBs; 5702 LPadList.reserve(CallSiteNumToLPad.size()); 5703 for (unsigned I = 1; I <= MaxCSNum; ++I) { 5704 SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I]; 5705 for (SmallVectorImpl<MachineBasicBlock*>::iterator 5706 II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) { 5707 LPadList.push_back(*II); 5708 InvokeBBs.insert((*II)->pred_begin(), (*II)->pred_end()); 5709 } 5710 } 5711 5712 assert(!LPadList.empty() && 5713 "No landing pad destinations for the dispatch jump table!"); 5714 5715 // Create the jump table and associated information. 5716 MachineJumpTableInfo *JTI = 5717 MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline); 5718 unsigned MJTI = JTI->createJumpTableIndex(LPadList); 5719 unsigned UId = AFI->createJumpTableUId(); 5720 5721 // Create the MBBs for the dispatch code. 5722 5723 // Shove the dispatch's address into the return slot in the function context. 5724 MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock(); 5725 DispatchBB->setIsLandingPad(); 5726 5727 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock(); 5728 BuildMI(TrapBB, dl, TII->get(Subtarget->isThumb() ? ARM::tTRAP : ARM::TRAP)); 5729 DispatchBB->addSuccessor(TrapBB); 5730 5731 MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock(); 5732 DispatchBB->addSuccessor(DispContBB); 5733 5734 // Insert and renumber MBBs. 5735 MachineBasicBlock *Last = &MF->back(); 5736 MF->insert(MF->end(), DispatchBB); 5737 MF->insert(MF->end(), DispContBB); 5738 MF->insert(MF->end(), TrapBB); 5739 MF->RenumberBlocks(Last); 5740 5741 // Insert code into the entry block that creates and registers the function 5742 // context. 5743 SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI); 5744 5745 MachineMemOperand *FIMMOLd = 5746 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 5747 MachineMemOperand::MOLoad | 5748 MachineMemOperand::MOVolatile, 4, 4); 5749 5750 if (Subtarget->isThumb2()) { 5751 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5752 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1) 5753 .addFrameIndex(FI) 5754 .addImm(4) 5755 .addMemOperand(FIMMOLd)); 5756 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri)) 5757 .addReg(NewVReg1) 5758 .addImm(LPadList.size())); 5759 BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc)) 5760 .addMBB(TrapBB) 5761 .addImm(ARMCC::HI) 5762 .addReg(ARM::CPSR); 5763 5764 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5765 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg2) 5766 .addJumpTableIndex(MJTI) 5767 .addImm(UId)); 5768 5769 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 5770 AddDefaultCC( 5771 AddDefaultPred( 5772 BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg3) 5773 .addReg(NewVReg2, RegState::Kill) 5774 .addReg(NewVReg1) 5775 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2)))); 5776 5777 BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT)) 5778 .addReg(NewVReg3, RegState::Kill) 5779 .addReg(NewVReg1) 5780 .addJumpTableIndex(MJTI) 5781 .addImm(UId); 5782 } else if (Subtarget->isThumb()) { 5783 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5784 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1) 5785 .addFrameIndex(FI) 5786 .addImm(1) 5787 .addMemOperand(FIMMOLd)); 5788 5789 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8)) 5790 .addReg(NewVReg1) 5791 .addImm(LPadList.size())); 5792 BuildMI(DispatchBB, dl, TII->get(ARM::tBcc)) 5793 .addMBB(TrapBB) 5794 .addImm(ARMCC::HI) 5795 .addReg(ARM::CPSR); 5796 5797 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5798 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2) 5799 .addReg(ARM::CPSR, RegState::Define) 5800 .addReg(NewVReg1) 5801 .addImm(2)); 5802 5803 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 5804 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3) 5805 .addJumpTableIndex(MJTI) 5806 .addImm(UId)); 5807 5808 unsigned NewVReg4 = MRI->createVirtualRegister(TRC); 5809 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4) 5810 .addReg(ARM::CPSR, RegState::Define) 5811 .addReg(NewVReg2, RegState::Kill) 5812 .addReg(NewVReg3)); 5813 5814 MachineMemOperand *JTMMOLd = 5815 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(), 5816 MachineMemOperand::MOLoad, 4, 4); 5817 5818 unsigned NewVReg5 = MRI->createVirtualRegister(TRC); 5819 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5) 5820 .addReg(NewVReg4, RegState::Kill) 5821 .addImm(0) 5822 .addMemOperand(JTMMOLd)); 5823 5824 unsigned NewVReg6 = MRI->createVirtualRegister(TRC); 5825 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6) 5826 .addReg(ARM::CPSR, RegState::Define) 5827 .addReg(NewVReg5, RegState::Kill) 5828 .addReg(NewVReg3)); 5829 5830 BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr)) 5831 .addReg(NewVReg6, RegState::Kill) 5832 .addJumpTableIndex(MJTI) 5833 .addImm(UId); 5834 } else { 5835 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5836 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1) 5837 .addFrameIndex(FI) 5838 .addImm(4) 5839 .addMemOperand(FIMMOLd)); 5840 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri)) 5841 .addReg(NewVReg1) 5842 .addImm(LPadList.size())); 5843 BuildMI(DispatchBB, dl, TII->get(ARM::Bcc)) 5844 .addMBB(TrapBB) 5845 .addImm(ARMCC::HI) 5846 .addReg(ARM::CPSR); 5847 5848 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5849 AddDefaultCC( 5850 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg2) 5851 .addReg(NewVReg1) 5852 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2)))); 5853 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 5854 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg3) 5855 .addJumpTableIndex(MJTI) 5856 .addImm(UId)); 5857 5858 MachineMemOperand *JTMMOLd = 5859 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(), 5860 MachineMemOperand::MOLoad, 4, 4); 5861 unsigned NewVReg4 = MRI->createVirtualRegister(TRC); 5862 AddDefaultPred( 5863 BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg4) 5864 .addReg(NewVReg2, RegState::Kill) 5865 .addReg(NewVReg3) 5866 .addImm(0) 5867 .addMemOperand(JTMMOLd)); 5868 5869 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd)) 5870 .addReg(NewVReg4, RegState::Kill) 5871 .addReg(NewVReg3) 5872 .addJumpTableIndex(MJTI) 5873 .addImm(UId); 5874 } 5875 5876 // Add the jump table entries as successors to the MBB. 5877 MachineBasicBlock *PrevMBB = 0; 5878 for (std::vector<MachineBasicBlock*>::iterator 5879 I = LPadList.begin(), E = LPadList.end(); I != E; ++I) { 5880 MachineBasicBlock *CurMBB = *I; 5881 if (PrevMBB != CurMBB) 5882 DispContBB->addSuccessor(CurMBB); 5883 PrevMBB = CurMBB; 5884 } 5885 5886 const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII); 5887 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo(); 5888 const unsigned *SavedRegs = RI.getCalleeSavedRegs(MF); 5889 for (SmallPtrSet<MachineBasicBlock*, 64>::iterator 5890 I = InvokeBBs.begin(), E = InvokeBBs.end(); I != E; ++I) { 5891 MachineBasicBlock *BB = *I; 5892 5893 // Remove the landing pad successor from the invoke block and replace it 5894 // with the new dispatch block. 5895 for (MachineBasicBlock::succ_iterator 5896 SI = BB->succ_begin(), SE = BB->succ_end(); SI != SE; ++SI) { 5897 MachineBasicBlock *SMBB = *SI; 5898 if (SMBB->isLandingPad()) { 5899 BB->removeSuccessor(SMBB); 5900 SMBB->setIsLandingPad(false); 5901 } 5902 } 5903 5904 BB->addSuccessor(DispatchBB); 5905 5906 // Find the invoke call and mark all of the callee-saved registers as 5907 // 'implicit defined' so that they're spilled. This prevents code from 5908 // moving instructions to before the EH block, where they will never be 5909 // executed. 5910 for (MachineBasicBlock::reverse_iterator 5911 II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) { 5912 if (!II->getDesc().isCall()) continue; 5913 5914 DenseMap<unsigned, bool> DefRegs; 5915 for (MachineInstr::mop_iterator 5916 OI = II->operands_begin(), OE = II->operands_end(); 5917 OI != OE; ++OI) { 5918 if (!OI->isReg()) continue; 5919 DefRegs[OI->getReg()] = true; 5920 } 5921 5922 MachineInstrBuilder MIB(&*II); 5923 5924 for (unsigned i = 0; SavedRegs[i] != 0; ++i) 5925 if (!DefRegs[SavedRegs[i]]) 5926 MIB.addReg(SavedRegs[i], RegState::Implicit | RegState::Define); 5927 5928 break; 5929 } 5930 } 5931 5932 // The instruction is gone now. 5933 MI->eraseFromParent(); 5934 5935 return MBB; 5936} 5937 5938static 5939MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) { 5940 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(), 5941 E = MBB->succ_end(); I != E; ++I) 5942 if (*I != Succ) 5943 return *I; 5944 llvm_unreachable("Expecting a BB with two successors!"); 5945} 5946 5947MachineBasicBlock * 5948ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 5949 MachineBasicBlock *BB) const { 5950 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5951 DebugLoc dl = MI->getDebugLoc(); 5952 bool isThumb2 = Subtarget->isThumb2(); 5953 switch (MI->getOpcode()) { 5954 default: { 5955 MI->dump(); 5956 llvm_unreachable("Unexpected instr type to insert"); 5957 } 5958 // The Thumb2 pre-indexed stores have the same MI operands, they just 5959 // define them differently in the .td files from the isel patterns, so 5960 // they need pseudos. 5961 case ARM::t2STR_preidx: 5962 MI->setDesc(TII->get(ARM::t2STR_PRE)); 5963 return BB; 5964 case ARM::t2STRB_preidx: 5965 MI->setDesc(TII->get(ARM::t2STRB_PRE)); 5966 return BB; 5967 case ARM::t2STRH_preidx: 5968 MI->setDesc(TII->get(ARM::t2STRH_PRE)); 5969 return BB; 5970 5971 case ARM::STRi_preidx: 5972 case ARM::STRBi_preidx: { 5973 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ? 5974 ARM::STR_PRE_IMM : ARM::STRB_PRE_IMM; 5975 // Decode the offset. 5976 unsigned Offset = MI->getOperand(4).getImm(); 5977 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub; 5978 Offset = ARM_AM::getAM2Offset(Offset); 5979 if (isSub) 5980 Offset = -Offset; 5981 5982 MachineMemOperand *MMO = *MI->memoperands_begin(); 5983 BuildMI(*BB, MI, dl, TII->get(NewOpc)) 5984 .addOperand(MI->getOperand(0)) // Rn_wb 5985 .addOperand(MI->getOperand(1)) // Rt 5986 .addOperand(MI->getOperand(2)) // Rn 5987 .addImm(Offset) // offset (skip GPR==zero_reg) 5988 .addOperand(MI->getOperand(5)) // pred 5989 .addOperand(MI->getOperand(6)) 5990 .addMemOperand(MMO); 5991 MI->eraseFromParent(); 5992 return BB; 5993 } 5994 case ARM::STRr_preidx: 5995 case ARM::STRBr_preidx: 5996 case ARM::STRH_preidx: { 5997 unsigned NewOpc; 5998 switch (MI->getOpcode()) { 5999 default: llvm_unreachable("unexpected opcode!"); 6000 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break; 6001 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break; 6002 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break; 6003 } 6004 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc)); 6005 for (unsigned i = 0; i < MI->getNumOperands(); ++i) 6006 MIB.addOperand(MI->getOperand(i)); 6007 MI->eraseFromParent(); 6008 return BB; 6009 } 6010 case ARM::ATOMIC_LOAD_ADD_I8: 6011 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 6012 case ARM::ATOMIC_LOAD_ADD_I16: 6013 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 6014 case ARM::ATOMIC_LOAD_ADD_I32: 6015 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 6016 6017 case ARM::ATOMIC_LOAD_AND_I8: 6018 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 6019 case ARM::ATOMIC_LOAD_AND_I16: 6020 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 6021 case ARM::ATOMIC_LOAD_AND_I32: 6022 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 6023 6024 case ARM::ATOMIC_LOAD_OR_I8: 6025 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 6026 case ARM::ATOMIC_LOAD_OR_I16: 6027 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 6028 case ARM::ATOMIC_LOAD_OR_I32: 6029 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 6030 6031 case ARM::ATOMIC_LOAD_XOR_I8: 6032 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 6033 case ARM::ATOMIC_LOAD_XOR_I16: 6034 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 6035 case ARM::ATOMIC_LOAD_XOR_I32: 6036 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 6037 6038 case ARM::ATOMIC_LOAD_NAND_I8: 6039 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 6040 case ARM::ATOMIC_LOAD_NAND_I16: 6041 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 6042 case ARM::ATOMIC_LOAD_NAND_I32: 6043 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 6044 6045 case ARM::ATOMIC_LOAD_SUB_I8: 6046 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 6047 case ARM::ATOMIC_LOAD_SUB_I16: 6048 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 6049 case ARM::ATOMIC_LOAD_SUB_I32: 6050 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 6051 6052 case ARM::ATOMIC_LOAD_MIN_I8: 6053 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::LT); 6054 case ARM::ATOMIC_LOAD_MIN_I16: 6055 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::LT); 6056 case ARM::ATOMIC_LOAD_MIN_I32: 6057 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::LT); 6058 6059 case ARM::ATOMIC_LOAD_MAX_I8: 6060 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::GT); 6061 case ARM::ATOMIC_LOAD_MAX_I16: 6062 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::GT); 6063 case ARM::ATOMIC_LOAD_MAX_I32: 6064 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::GT); 6065 6066 case ARM::ATOMIC_LOAD_UMIN_I8: 6067 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::LO); 6068 case ARM::ATOMIC_LOAD_UMIN_I16: 6069 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::LO); 6070 case ARM::ATOMIC_LOAD_UMIN_I32: 6071 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::LO); 6072 6073 case ARM::ATOMIC_LOAD_UMAX_I8: 6074 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::HI); 6075 case ARM::ATOMIC_LOAD_UMAX_I16: 6076 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::HI); 6077 case ARM::ATOMIC_LOAD_UMAX_I32: 6078 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::HI); 6079 6080 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0); 6081 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0); 6082 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0); 6083 6084 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1); 6085 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2); 6086 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4); 6087 6088 6089 case ARM::ATOMADD6432: 6090 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr, 6091 isThumb2 ? ARM::t2ADCrr : ARM::ADCrr, 6092 /*NeedsCarry*/ true); 6093 case ARM::ATOMSUB6432: 6094 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr, 6095 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr, 6096 /*NeedsCarry*/ true); 6097 case ARM::ATOMOR6432: 6098 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr, 6099 isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 6100 case ARM::ATOMXOR6432: 6101 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2EORrr : ARM::EORrr, 6102 isThumb2 ? ARM::t2EORrr : ARM::EORrr); 6103 case ARM::ATOMAND6432: 6104 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr, 6105 isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 6106 case ARM::ATOMSWAP6432: 6107 return EmitAtomicBinary64(MI, BB, 0, 0, false); 6108 case ARM::ATOMCMPXCHG6432: 6109 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr, 6110 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr, 6111 /*NeedsCarry*/ false, /*IsCmpxchg*/true); 6112 6113 case ARM::tMOVCCr_pseudo: { 6114 // To "insert" a SELECT_CC instruction, we actually have to insert the 6115 // diamond control-flow pattern. The incoming instruction knows the 6116 // destination vreg to set, the condition code register to branch on, the 6117 // true/false values to select between, and a branch opcode to use. 6118 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 6119 MachineFunction::iterator It = BB; 6120 ++It; 6121 6122 // thisMBB: 6123 // ... 6124 // TrueVal = ... 6125 // cmpTY ccX, r1, r2 6126 // bCC copy1MBB 6127 // fallthrough --> copy0MBB 6128 MachineBasicBlock *thisMBB = BB; 6129 MachineFunction *F = BB->getParent(); 6130 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 6131 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 6132 F->insert(It, copy0MBB); 6133 F->insert(It, sinkMBB); 6134 6135 // Transfer the remainder of BB and its successor edges to sinkMBB. 6136 sinkMBB->splice(sinkMBB->begin(), BB, 6137 llvm::next(MachineBasicBlock::iterator(MI)), 6138 BB->end()); 6139 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 6140 6141 BB->addSuccessor(copy0MBB); 6142 BB->addSuccessor(sinkMBB); 6143 6144 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB) 6145 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg()); 6146 6147 // copy0MBB: 6148 // %FalseValue = ... 6149 // # fallthrough to sinkMBB 6150 BB = copy0MBB; 6151 6152 // Update machine-CFG edges 6153 BB->addSuccessor(sinkMBB); 6154 6155 // sinkMBB: 6156 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 6157 // ... 6158 BB = sinkMBB; 6159 BuildMI(*BB, BB->begin(), dl, 6160 TII->get(ARM::PHI), MI->getOperand(0).getReg()) 6161 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 6162 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 6163 6164 MI->eraseFromParent(); // The pseudo instruction is gone now. 6165 return BB; 6166 } 6167 6168 case ARM::BCCi64: 6169 case ARM::BCCZi64: { 6170 // If there is an unconditional branch to the other successor, remove it. 6171 BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 6172 6173 // Compare both parts that make up the double comparison separately for 6174 // equality. 6175 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64; 6176 6177 unsigned LHS1 = MI->getOperand(1).getReg(); 6178 unsigned LHS2 = MI->getOperand(2).getReg(); 6179 if (RHSisZero) { 6180 AddDefaultPred(BuildMI(BB, dl, 6181 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 6182 .addReg(LHS1).addImm(0)); 6183 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 6184 .addReg(LHS2).addImm(0) 6185 .addImm(ARMCC::EQ).addReg(ARM::CPSR); 6186 } else { 6187 unsigned RHS1 = MI->getOperand(3).getReg(); 6188 unsigned RHS2 = MI->getOperand(4).getReg(); 6189 AddDefaultPred(BuildMI(BB, dl, 6190 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 6191 .addReg(LHS1).addReg(RHS1)); 6192 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 6193 .addReg(LHS2).addReg(RHS2) 6194 .addImm(ARMCC::EQ).addReg(ARM::CPSR); 6195 } 6196 6197 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB(); 6198 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB); 6199 if (MI->getOperand(0).getImm() == ARMCC::NE) 6200 std::swap(destMBB, exitMBB); 6201 6202 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 6203 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR); 6204 if (isThumb2) 6205 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB)); 6206 else 6207 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB); 6208 6209 MI->eraseFromParent(); // The pseudo instruction is gone now. 6210 return BB; 6211 } 6212 6213 case ARM::ABS: 6214 case ARM::t2ABS: { 6215 // To insert an ABS instruction, we have to insert the 6216 // diamond control-flow pattern. The incoming instruction knows the 6217 // source vreg to test against 0, the destination vreg to set, 6218 // the condition code register to branch on, the 6219 // true/false values to select between, and a branch opcode to use. 6220 // It transforms 6221 // V1 = ABS V0 6222 // into 6223 // V2 = MOVS V0 6224 // BCC (branch to SinkBB if V0 >= 0) 6225 // RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0) 6226 // SinkBB: V1 = PHI(V2, V3) 6227 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 6228 MachineFunction::iterator BBI = BB; 6229 ++BBI; 6230 MachineFunction *Fn = BB->getParent(); 6231 MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB); 6232 MachineBasicBlock *SinkBB = Fn->CreateMachineBasicBlock(LLVM_BB); 6233 Fn->insert(BBI, RSBBB); 6234 Fn->insert(BBI, SinkBB); 6235 6236 unsigned int ABSSrcReg = MI->getOperand(1).getReg(); 6237 unsigned int ABSDstReg = MI->getOperand(0).getReg(); 6238 bool isThumb2 = Subtarget->isThumb2(); 6239 MachineRegisterInfo &MRI = Fn->getRegInfo(); 6240 // In Thumb mode S must not be specified if source register is the SP or 6241 // PC and if destination register is the SP, so restrict register class 6242 unsigned NewMovDstReg = MRI.createVirtualRegister( 6243 isThumb2 ? ARM::rGPRRegisterClass : ARM::GPRRegisterClass); 6244 unsigned NewRsbDstReg = MRI.createVirtualRegister( 6245 isThumb2 ? ARM::rGPRRegisterClass : ARM::GPRRegisterClass); 6246 6247 // Transfer the remainder of BB and its successor edges to sinkMBB. 6248 SinkBB->splice(SinkBB->begin(), BB, 6249 llvm::next(MachineBasicBlock::iterator(MI)), 6250 BB->end()); 6251 SinkBB->transferSuccessorsAndUpdatePHIs(BB); 6252 6253 BB->addSuccessor(RSBBB); 6254 BB->addSuccessor(SinkBB); 6255 6256 // fall through to SinkMBB 6257 RSBBB->addSuccessor(SinkBB); 6258 6259 // insert a movs at the end of BB 6260 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVr : ARM::MOVr), 6261 NewMovDstReg) 6262 .addReg(ABSSrcReg, RegState::Kill) 6263 .addImm((unsigned)ARMCC::AL).addReg(0) 6264 .addReg(ARM::CPSR, RegState::Define); 6265 6266 // insert a bcc with opposite CC to ARMCC::MI at the end of BB 6267 BuildMI(BB, dl, 6268 TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB) 6269 .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR); 6270 6271 // insert rsbri in RSBBB 6272 // Note: BCC and rsbri will be converted into predicated rsbmi 6273 // by if-conversion pass 6274 BuildMI(*RSBBB, RSBBB->begin(), dl, 6275 TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg) 6276 .addReg(NewMovDstReg, RegState::Kill) 6277 .addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 6278 6279 // insert PHI in SinkBB, 6280 // reuse ABSDstReg to not change uses of ABS instruction 6281 BuildMI(*SinkBB, SinkBB->begin(), dl, 6282 TII->get(ARM::PHI), ABSDstReg) 6283 .addReg(NewRsbDstReg).addMBB(RSBBB) 6284 .addReg(NewMovDstReg).addMBB(BB); 6285 6286 // remove ABS instruction 6287 MI->eraseFromParent(); 6288 6289 // return last added BB 6290 return SinkBB; 6291 } 6292 } 6293} 6294 6295void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, 6296 SDNode *Node) const { 6297 const MCInstrDesc &MCID = MI->getDesc(); 6298 if (!MCID.hasPostISelHook()) { 6299 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) && 6300 "Pseudo flag-setting opcodes must be marked with 'hasPostISelHook'"); 6301 return; 6302 } 6303 6304 // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB, 6305 // RSC. Coming out of isel, they have an implicit CPSR def, but the optional 6306 // operand is still set to noreg. If needed, set the optional operand's 6307 // register to CPSR, and remove the redundant implicit def. 6308 // 6309 // e.g. ADCS (...opt:%noreg, CPSR<imp-def>) -> ADC (... opt:CPSR<def>). 6310 6311 // Rename pseudo opcodes. 6312 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode()); 6313 if (NewOpc) { 6314 const ARMBaseInstrInfo *TII = 6315 static_cast<const ARMBaseInstrInfo*>(getTargetMachine().getInstrInfo()); 6316 MI->setDesc(TII->get(NewOpc)); 6317 } 6318 unsigned ccOutIdx = MCID.getNumOperands() - 1; 6319 6320 // Any ARM instruction that sets the 's' bit should specify an optional 6321 // "cc_out" operand in the last operand position. 6322 if (!MCID.hasOptionalDef() || !MCID.OpInfo[ccOutIdx].isOptionalDef()) { 6323 assert(!NewOpc && "Optional cc_out operand required"); 6324 return; 6325 } 6326 // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it 6327 // since we already have an optional CPSR def. 6328 bool definesCPSR = false; 6329 bool deadCPSR = false; 6330 for (unsigned i = MCID.getNumOperands(), e = MI->getNumOperands(); 6331 i != e; ++i) { 6332 const MachineOperand &MO = MI->getOperand(i); 6333 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) { 6334 definesCPSR = true; 6335 if (MO.isDead()) 6336 deadCPSR = true; 6337 MI->RemoveOperand(i); 6338 break; 6339 } 6340 } 6341 if (!definesCPSR) { 6342 assert(!NewOpc && "Optional cc_out operand required"); 6343 return; 6344 } 6345 assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag"); 6346 if (deadCPSR) { 6347 assert(!MI->getOperand(ccOutIdx).getReg() && 6348 "expect uninitialized optional cc_out operand"); 6349 return; 6350 } 6351 6352 // If this instruction was defined with an optional CPSR def and its dag node 6353 // had a live implicit CPSR def, then activate the optional CPSR def. 6354 MachineOperand &MO = MI->getOperand(ccOutIdx); 6355 MO.setReg(ARM::CPSR); 6356 MO.setIsDef(true); 6357} 6358 6359//===----------------------------------------------------------------------===// 6360// ARM Optimization Hooks 6361//===----------------------------------------------------------------------===// 6362 6363static 6364SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, 6365 TargetLowering::DAGCombinerInfo &DCI) { 6366 SelectionDAG &DAG = DCI.DAG; 6367 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6368 EVT VT = N->getValueType(0); 6369 unsigned Opc = N->getOpcode(); 6370 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 6371 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 6372 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 6373 ISD::CondCode CC = ISD::SETCC_INVALID; 6374 6375 if (isSlctCC) { 6376 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 6377 } else { 6378 SDValue CCOp = Slct.getOperand(0); 6379 if (CCOp.getOpcode() == ISD::SETCC) 6380 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 6381 } 6382 6383 bool DoXform = false; 6384 bool InvCC = false; 6385 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 6386 "Bad input!"); 6387 6388 if (LHS.getOpcode() == ISD::Constant && 6389 cast<ConstantSDNode>(LHS)->isNullValue()) { 6390 DoXform = true; 6391 } else if (CC != ISD::SETCC_INVALID && 6392 RHS.getOpcode() == ISD::Constant && 6393 cast<ConstantSDNode>(RHS)->isNullValue()) { 6394 std::swap(LHS, RHS); 6395 SDValue Op0 = Slct.getOperand(0); 6396 EVT OpVT = isSlctCC ? Op0.getValueType() : 6397 Op0.getOperand(0).getValueType(); 6398 bool isInt = OpVT.isInteger(); 6399 CC = ISD::getSetCCInverse(CC, isInt); 6400 6401 if (!TLI.isCondCodeLegal(CC, OpVT)) 6402 return SDValue(); // Inverse operator isn't legal. 6403 6404 DoXform = true; 6405 InvCC = true; 6406 } 6407 6408 if (DoXform) { 6409 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS); 6410 if (isSlctCC) 6411 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result, 6412 Slct.getOperand(0), Slct.getOperand(1), CC); 6413 SDValue CCOp = Slct.getOperand(0); 6414 if (InvCC) 6415 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(), 6416 CCOp.getOperand(0), CCOp.getOperand(1), CC); 6417 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 6418 CCOp, OtherOp, Result); 6419 } 6420 return SDValue(); 6421} 6422 6423// AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction 6424// (only after legalization). 6425static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1, 6426 TargetLowering::DAGCombinerInfo &DCI, 6427 const ARMSubtarget *Subtarget) { 6428 6429 // Only perform optimization if after legalize, and if NEON is available. We 6430 // also expected both operands to be BUILD_VECTORs. 6431 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON() 6432 || N0.getOpcode() != ISD::BUILD_VECTOR 6433 || N1.getOpcode() != ISD::BUILD_VECTOR) 6434 return SDValue(); 6435 6436 // Check output type since VPADDL operand elements can only be 8, 16, or 32. 6437 EVT VT = N->getValueType(0); 6438 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64) 6439 return SDValue(); 6440 6441 // Check that the vector operands are of the right form. 6442 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR 6443 // operands, where N is the size of the formed vector. 6444 // Each EXTRACT_VECTOR should have the same input vector and odd or even 6445 // index such that we have a pair wise add pattern. 6446 6447 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing. 6448 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 6449 return SDValue(); 6450 SDValue Vec = N0->getOperand(0)->getOperand(0); 6451 SDNode *V = Vec.getNode(); 6452 unsigned nextIndex = 0; 6453 6454 // For each operands to the ADD which are BUILD_VECTORs, 6455 // check to see if each of their operands are an EXTRACT_VECTOR with 6456 // the same vector and appropriate index. 6457 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) { 6458 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT 6459 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) { 6460 6461 SDValue ExtVec0 = N0->getOperand(i); 6462 SDValue ExtVec1 = N1->getOperand(i); 6463 6464 // First operand is the vector, verify its the same. 6465 if (V != ExtVec0->getOperand(0).getNode() || 6466 V != ExtVec1->getOperand(0).getNode()) 6467 return SDValue(); 6468 6469 // Second is the constant, verify its correct. 6470 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1)); 6471 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1)); 6472 6473 // For the constant, we want to see all the even or all the odd. 6474 if (!C0 || !C1 || C0->getZExtValue() != nextIndex 6475 || C1->getZExtValue() != nextIndex+1) 6476 return SDValue(); 6477 6478 // Increment index. 6479 nextIndex+=2; 6480 } else 6481 return SDValue(); 6482 } 6483 6484 // Create VPADDL node. 6485 SelectionDAG &DAG = DCI.DAG; 6486 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6487 6488 // Build operand list. 6489 SmallVector<SDValue, 8> Ops; 6490 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls, 6491 TLI.getPointerTy())); 6492 6493 // Input is the vector. 6494 Ops.push_back(Vec); 6495 6496 // Get widened type and narrowed type. 6497 MVT widenType; 6498 unsigned numElem = VT.getVectorNumElements(); 6499 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) { 6500 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break; 6501 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break; 6502 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break; 6503 default: 6504 assert(0 && "Invalid vector element type for padd optimization."); 6505 } 6506 6507 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), 6508 widenType, &Ops[0], Ops.size()); 6509 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, tmp); 6510} 6511 6512/// PerformADDCombineWithOperands - Try DAG combinations for an ADD with 6513/// operands N0 and N1. This is a helper for PerformADDCombine that is 6514/// called with the default operands, and if that fails, with commuted 6515/// operands. 6516static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, 6517 TargetLowering::DAGCombinerInfo &DCI, 6518 const ARMSubtarget *Subtarget){ 6519 6520 // Attempt to create vpaddl for this add. 6521 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget); 6522 if (Result.getNode()) 6523 return Result; 6524 6525 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 6526 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) { 6527 SDValue Result = combineSelectAndUse(N, N0, N1, DCI); 6528 if (Result.getNode()) return Result; 6529 } 6530 return SDValue(); 6531} 6532 6533/// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD. 6534/// 6535static SDValue PerformADDCombine(SDNode *N, 6536 TargetLowering::DAGCombinerInfo &DCI, 6537 const ARMSubtarget *Subtarget) { 6538 SDValue N0 = N->getOperand(0); 6539 SDValue N1 = N->getOperand(1); 6540 6541 // First try with the default operand order. 6542 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget); 6543 if (Result.getNode()) 6544 return Result; 6545 6546 // If that didn't work, try again with the operands commuted. 6547 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget); 6548} 6549 6550/// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB. 6551/// 6552static SDValue PerformSUBCombine(SDNode *N, 6553 TargetLowering::DAGCombinerInfo &DCI) { 6554 SDValue N0 = N->getOperand(0); 6555 SDValue N1 = N->getOperand(1); 6556 6557 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 6558 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 6559 SDValue Result = combineSelectAndUse(N, N1, N0, DCI); 6560 if (Result.getNode()) return Result; 6561 } 6562 6563 return SDValue(); 6564} 6565 6566/// PerformVMULCombine 6567/// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the 6568/// special multiplier accumulator forwarding. 6569/// vmul d3, d0, d2 6570/// vmla d3, d1, d2 6571/// is faster than 6572/// vadd d3, d0, d1 6573/// vmul d3, d3, d2 6574static SDValue PerformVMULCombine(SDNode *N, 6575 TargetLowering::DAGCombinerInfo &DCI, 6576 const ARMSubtarget *Subtarget) { 6577 if (!Subtarget->hasVMLxForwarding()) 6578 return SDValue(); 6579 6580 SelectionDAG &DAG = DCI.DAG; 6581 SDValue N0 = N->getOperand(0); 6582 SDValue N1 = N->getOperand(1); 6583 unsigned Opcode = N0.getOpcode(); 6584 if (Opcode != ISD::ADD && Opcode != ISD::SUB && 6585 Opcode != ISD::FADD && Opcode != ISD::FSUB) { 6586 Opcode = N1.getOpcode(); 6587 if (Opcode != ISD::ADD && Opcode != ISD::SUB && 6588 Opcode != ISD::FADD && Opcode != ISD::FSUB) 6589 return SDValue(); 6590 std::swap(N0, N1); 6591 } 6592 6593 EVT VT = N->getValueType(0); 6594 DebugLoc DL = N->getDebugLoc(); 6595 SDValue N00 = N0->getOperand(0); 6596 SDValue N01 = N0->getOperand(1); 6597 return DAG.getNode(Opcode, DL, VT, 6598 DAG.getNode(ISD::MUL, DL, VT, N00, N1), 6599 DAG.getNode(ISD::MUL, DL, VT, N01, N1)); 6600} 6601 6602static SDValue PerformMULCombine(SDNode *N, 6603 TargetLowering::DAGCombinerInfo &DCI, 6604 const ARMSubtarget *Subtarget) { 6605 SelectionDAG &DAG = DCI.DAG; 6606 6607 if (Subtarget->isThumb1Only()) 6608 return SDValue(); 6609 6610 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 6611 return SDValue(); 6612 6613 EVT VT = N->getValueType(0); 6614 if (VT.is64BitVector() || VT.is128BitVector()) 6615 return PerformVMULCombine(N, DCI, Subtarget); 6616 if (VT != MVT::i32) 6617 return SDValue(); 6618 6619 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6620 if (!C) 6621 return SDValue(); 6622 6623 uint64_t MulAmt = C->getZExtValue(); 6624 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt); 6625 ShiftAmt = ShiftAmt & (32 - 1); 6626 SDValue V = N->getOperand(0); 6627 DebugLoc DL = N->getDebugLoc(); 6628 6629 SDValue Res; 6630 MulAmt >>= ShiftAmt; 6631 if (isPowerOf2_32(MulAmt - 1)) { 6632 // (mul x, 2^N + 1) => (add (shl x, N), x) 6633 Res = DAG.getNode(ISD::ADD, DL, VT, 6634 V, DAG.getNode(ISD::SHL, DL, VT, 6635 V, DAG.getConstant(Log2_32(MulAmt-1), 6636 MVT::i32))); 6637 } else if (isPowerOf2_32(MulAmt + 1)) { 6638 // (mul x, 2^N - 1) => (sub (shl x, N), x) 6639 Res = DAG.getNode(ISD::SUB, DL, VT, 6640 DAG.getNode(ISD::SHL, DL, VT, 6641 V, DAG.getConstant(Log2_32(MulAmt+1), 6642 MVT::i32)), 6643 V); 6644 } else 6645 return SDValue(); 6646 6647 if (ShiftAmt != 0) 6648 Res = DAG.getNode(ISD::SHL, DL, VT, Res, 6649 DAG.getConstant(ShiftAmt, MVT::i32)); 6650 6651 // Do not add new nodes to DAG combiner worklist. 6652 DCI.CombineTo(N, Res, false); 6653 return SDValue(); 6654} 6655 6656static SDValue PerformANDCombine(SDNode *N, 6657 TargetLowering::DAGCombinerInfo &DCI) { 6658 6659 // Attempt to use immediate-form VBIC 6660 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1)); 6661 DebugLoc dl = N->getDebugLoc(); 6662 EVT VT = N->getValueType(0); 6663 SelectionDAG &DAG = DCI.DAG; 6664 6665 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 6666 return SDValue(); 6667 6668 APInt SplatBits, SplatUndef; 6669 unsigned SplatBitSize; 6670 bool HasAnyUndefs; 6671 if (BVN && 6672 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { 6673 if (SplatBitSize <= 64) { 6674 EVT VbicVT; 6675 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(), 6676 SplatUndef.getZExtValue(), SplatBitSize, 6677 DAG, VbicVT, VT.is128BitVector(), 6678 OtherModImm); 6679 if (Val.getNode()) { 6680 SDValue Input = 6681 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0)); 6682 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val); 6683 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic); 6684 } 6685 } 6686 } 6687 6688 return SDValue(); 6689} 6690 6691/// PerformORCombine - Target-specific dag combine xforms for ISD::OR 6692static SDValue PerformORCombine(SDNode *N, 6693 TargetLowering::DAGCombinerInfo &DCI, 6694 const ARMSubtarget *Subtarget) { 6695 // Attempt to use immediate-form VORR 6696 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1)); 6697 DebugLoc dl = N->getDebugLoc(); 6698 EVT VT = N->getValueType(0); 6699 SelectionDAG &DAG = DCI.DAG; 6700 6701 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 6702 return SDValue(); 6703 6704 APInt SplatBits, SplatUndef; 6705 unsigned SplatBitSize; 6706 bool HasAnyUndefs; 6707 if (BVN && Subtarget->hasNEON() && 6708 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { 6709 if (SplatBitSize <= 64) { 6710 EVT VorrVT; 6711 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(), 6712 SplatUndef.getZExtValue(), SplatBitSize, 6713 DAG, VorrVT, VT.is128BitVector(), 6714 OtherModImm); 6715 if (Val.getNode()) { 6716 SDValue Input = 6717 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0)); 6718 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val); 6719 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr); 6720 } 6721 } 6722 } 6723 6724 SDValue N0 = N->getOperand(0); 6725 if (N0.getOpcode() != ISD::AND) 6726 return SDValue(); 6727 SDValue N1 = N->getOperand(1); 6728 6729 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant. 6730 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() && 6731 DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 6732 APInt SplatUndef; 6733 unsigned SplatBitSize; 6734 bool HasAnyUndefs; 6735 6736 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1)); 6737 APInt SplatBits0; 6738 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize, 6739 HasAnyUndefs) && !HasAnyUndefs) { 6740 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1)); 6741 APInt SplatBits1; 6742 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize, 6743 HasAnyUndefs) && !HasAnyUndefs && 6744 SplatBits0 == ~SplatBits1) { 6745 // Canonicalize the vector type to make instruction selection simpler. 6746 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32; 6747 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT, 6748 N0->getOperand(1), N0->getOperand(0), 6749 N1->getOperand(0)); 6750 return DAG.getNode(ISD::BITCAST, dl, VT, Result); 6751 } 6752 } 6753 } 6754 6755 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when 6756 // reasonable. 6757 6758 // BFI is only available on V6T2+ 6759 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops()) 6760 return SDValue(); 6761 6762 DebugLoc DL = N->getDebugLoc(); 6763 // 1) or (and A, mask), val => ARMbfi A, val, mask 6764 // iff (val & mask) == val 6765 // 6766 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask 6767 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2) 6768 // && mask == ~mask2 6769 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2) 6770 // && ~mask == mask2 6771 // (i.e., copy a bitfield value into another bitfield of the same width) 6772 6773 if (VT != MVT::i32) 6774 return SDValue(); 6775 6776 SDValue N00 = N0.getOperand(0); 6777 6778 // The value and the mask need to be constants so we can verify this is 6779 // actually a bitfield set. If the mask is 0xffff, we can do better 6780 // via a movt instruction, so don't use BFI in that case. 6781 SDValue MaskOp = N0.getOperand(1); 6782 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp); 6783 if (!MaskC) 6784 return SDValue(); 6785 unsigned Mask = MaskC->getZExtValue(); 6786 if (Mask == 0xffff) 6787 return SDValue(); 6788 SDValue Res; 6789 // Case (1): or (and A, mask), val => ARMbfi A, val, mask 6790 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 6791 if (N1C) { 6792 unsigned Val = N1C->getZExtValue(); 6793 if ((Val & ~Mask) != Val) 6794 return SDValue(); 6795 6796 if (ARM::isBitFieldInvertedMask(Mask)) { 6797 Val >>= CountTrailingZeros_32(~Mask); 6798 6799 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, 6800 DAG.getConstant(Val, MVT::i32), 6801 DAG.getConstant(Mask, MVT::i32)); 6802 6803 // Do not add new nodes to DAG combiner worklist. 6804 DCI.CombineTo(N, Res, false); 6805 return SDValue(); 6806 } 6807 } else if (N1.getOpcode() == ISD::AND) { 6808 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask 6809 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 6810 if (!N11C) 6811 return SDValue(); 6812 unsigned Mask2 = N11C->getZExtValue(); 6813 6814 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern 6815 // as is to match. 6816 if (ARM::isBitFieldInvertedMask(Mask) && 6817 (Mask == ~Mask2)) { 6818 // The pack halfword instruction works better for masks that fit it, 6819 // so use that when it's available. 6820 if (Subtarget->hasT2ExtractPack() && 6821 (Mask == 0xffff || Mask == 0xffff0000)) 6822 return SDValue(); 6823 // 2a 6824 unsigned amt = CountTrailingZeros_32(Mask2); 6825 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0), 6826 DAG.getConstant(amt, MVT::i32)); 6827 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res, 6828 DAG.getConstant(Mask, MVT::i32)); 6829 // Do not add new nodes to DAG combiner worklist. 6830 DCI.CombineTo(N, Res, false); 6831 return SDValue(); 6832 } else if (ARM::isBitFieldInvertedMask(~Mask) && 6833 (~Mask == Mask2)) { 6834 // The pack halfword instruction works better for masks that fit it, 6835 // so use that when it's available. 6836 if (Subtarget->hasT2ExtractPack() && 6837 (Mask2 == 0xffff || Mask2 == 0xffff0000)) 6838 return SDValue(); 6839 // 2b 6840 unsigned lsb = CountTrailingZeros_32(Mask); 6841 Res = DAG.getNode(ISD::SRL, DL, VT, N00, 6842 DAG.getConstant(lsb, MVT::i32)); 6843 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res, 6844 DAG.getConstant(Mask2, MVT::i32)); 6845 // Do not add new nodes to DAG combiner worklist. 6846 DCI.CombineTo(N, Res, false); 6847 return SDValue(); 6848 } 6849 } 6850 6851 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) && 6852 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) && 6853 ARM::isBitFieldInvertedMask(~Mask)) { 6854 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask 6855 // where lsb(mask) == #shamt and masked bits of B are known zero. 6856 SDValue ShAmt = N00.getOperand(1); 6857 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 6858 unsigned LSB = CountTrailingZeros_32(Mask); 6859 if (ShAmtC != LSB) 6860 return SDValue(); 6861 6862 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0), 6863 DAG.getConstant(~Mask, MVT::i32)); 6864 6865 // Do not add new nodes to DAG combiner worklist. 6866 DCI.CombineTo(N, Res, false); 6867 } 6868 6869 return SDValue(); 6870} 6871 6872/// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff 6873/// the bits being cleared by the AND are not demanded by the BFI. 6874static SDValue PerformBFICombine(SDNode *N, 6875 TargetLowering::DAGCombinerInfo &DCI) { 6876 SDValue N1 = N->getOperand(1); 6877 if (N1.getOpcode() == ISD::AND) { 6878 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 6879 if (!N11C) 6880 return SDValue(); 6881 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue(); 6882 unsigned LSB = CountTrailingZeros_32(~InvMask); 6883 unsigned Width = (32 - CountLeadingZeros_32(~InvMask)) - LSB; 6884 unsigned Mask = (1 << Width)-1; 6885 unsigned Mask2 = N11C->getZExtValue(); 6886 if ((Mask & (~Mask2)) == 0) 6887 return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0), 6888 N->getOperand(0), N1.getOperand(0), 6889 N->getOperand(2)); 6890 } 6891 return SDValue(); 6892} 6893 6894/// PerformVMOVRRDCombine - Target-specific dag combine xforms for 6895/// ARMISD::VMOVRRD. 6896static SDValue PerformVMOVRRDCombine(SDNode *N, 6897 TargetLowering::DAGCombinerInfo &DCI) { 6898 // vmovrrd(vmovdrr x, y) -> x,y 6899 SDValue InDouble = N->getOperand(0); 6900 if (InDouble.getOpcode() == ARMISD::VMOVDRR) 6901 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1)); 6902 6903 // vmovrrd(load f64) -> (load i32), (load i32) 6904 SDNode *InNode = InDouble.getNode(); 6905 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() && 6906 InNode->getValueType(0) == MVT::f64 && 6907 InNode->getOperand(1).getOpcode() == ISD::FrameIndex && 6908 !cast<LoadSDNode>(InNode)->isVolatile()) { 6909 // TODO: Should this be done for non-FrameIndex operands? 6910 LoadSDNode *LD = cast<LoadSDNode>(InNode); 6911 6912 SelectionDAG &DAG = DCI.DAG; 6913 DebugLoc DL = LD->getDebugLoc(); 6914 SDValue BasePtr = LD->getBasePtr(); 6915 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr, 6916 LD->getPointerInfo(), LD->isVolatile(), 6917 LD->isNonTemporal(), LD->getAlignment()); 6918 6919 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, 6920 DAG.getConstant(4, MVT::i32)); 6921 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr, 6922 LD->getPointerInfo(), LD->isVolatile(), 6923 LD->isNonTemporal(), 6924 std::min(4U, LD->getAlignment() / 2)); 6925 6926 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1)); 6927 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2); 6928 DCI.RemoveFromWorklist(LD); 6929 DAG.DeleteNode(LD); 6930 return Result; 6931 } 6932 6933 return SDValue(); 6934} 6935 6936/// PerformVMOVDRRCombine - Target-specific dag combine xforms for 6937/// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands. 6938static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) { 6939 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X) 6940 SDValue Op0 = N->getOperand(0); 6941 SDValue Op1 = N->getOperand(1); 6942 if (Op0.getOpcode() == ISD::BITCAST) 6943 Op0 = Op0.getOperand(0); 6944 if (Op1.getOpcode() == ISD::BITCAST) 6945 Op1 = Op1.getOperand(0); 6946 if (Op0.getOpcode() == ARMISD::VMOVRRD && 6947 Op0.getNode() == Op1.getNode() && 6948 Op0.getResNo() == 0 && Op1.getResNo() == 1) 6949 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6950 N->getValueType(0), Op0.getOperand(0)); 6951 return SDValue(); 6952} 6953 6954/// PerformSTORECombine - Target-specific dag combine xforms for 6955/// ISD::STORE. 6956static SDValue PerformSTORECombine(SDNode *N, 6957 TargetLowering::DAGCombinerInfo &DCI) { 6958 // Bitcast an i64 store extracted from a vector to f64. 6959 // Otherwise, the i64 value will be legalized to a pair of i32 values. 6960 StoreSDNode *St = cast<StoreSDNode>(N); 6961 SDValue StVal = St->getValue(); 6962 if (!ISD::isNormalStore(St) || St->isVolatile()) 6963 return SDValue(); 6964 6965 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR && 6966 StVal.getNode()->hasOneUse() && !St->isVolatile()) { 6967 SelectionDAG &DAG = DCI.DAG; 6968 DebugLoc DL = St->getDebugLoc(); 6969 SDValue BasePtr = St->getBasePtr(); 6970 SDValue NewST1 = DAG.getStore(St->getChain(), DL, 6971 StVal.getNode()->getOperand(0), BasePtr, 6972 St->getPointerInfo(), St->isVolatile(), 6973 St->isNonTemporal(), St->getAlignment()); 6974 6975 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, 6976 DAG.getConstant(4, MVT::i32)); 6977 return DAG.getStore(NewST1.getValue(0), DL, StVal.getNode()->getOperand(1), 6978 OffsetPtr, St->getPointerInfo(), St->isVolatile(), 6979 St->isNonTemporal(), 6980 std::min(4U, St->getAlignment() / 2)); 6981 } 6982 6983 if (StVal.getValueType() != MVT::i64 || 6984 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 6985 return SDValue(); 6986 6987 SelectionDAG &DAG = DCI.DAG; 6988 DebugLoc dl = StVal.getDebugLoc(); 6989 SDValue IntVec = StVal.getOperand(0); 6990 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, 6991 IntVec.getValueType().getVectorNumElements()); 6992 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec); 6993 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 6994 Vec, StVal.getOperand(1)); 6995 dl = N->getDebugLoc(); 6996 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt); 6997 // Make the DAGCombiner fold the bitcasts. 6998 DCI.AddToWorklist(Vec.getNode()); 6999 DCI.AddToWorklist(ExtElt.getNode()); 7000 DCI.AddToWorklist(V.getNode()); 7001 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(), 7002 St->getPointerInfo(), St->isVolatile(), 7003 St->isNonTemporal(), St->getAlignment(), 7004 St->getTBAAInfo()); 7005} 7006 7007/// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node 7008/// are normal, non-volatile loads. If so, it is profitable to bitcast an 7009/// i64 vector to have f64 elements, since the value can then be loaded 7010/// directly into a VFP register. 7011static bool hasNormalLoadOperand(SDNode *N) { 7012 unsigned NumElts = N->getValueType(0).getVectorNumElements(); 7013 for (unsigned i = 0; i < NumElts; ++i) { 7014 SDNode *Elt = N->getOperand(i).getNode(); 7015 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile()) 7016 return true; 7017 } 7018 return false; 7019} 7020 7021/// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for 7022/// ISD::BUILD_VECTOR. 7023static SDValue PerformBUILD_VECTORCombine(SDNode *N, 7024 TargetLowering::DAGCombinerInfo &DCI){ 7025 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X): 7026 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value 7027 // into a pair of GPRs, which is fine when the value is used as a scalar, 7028 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD. 7029 SelectionDAG &DAG = DCI.DAG; 7030 if (N->getNumOperands() == 2) { 7031 SDValue RV = PerformVMOVDRRCombine(N, DAG); 7032 if (RV.getNode()) 7033 return RV; 7034 } 7035 7036 // Load i64 elements as f64 values so that type legalization does not split 7037 // them up into i32 values. 7038 EVT VT = N->getValueType(0); 7039 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N)) 7040 return SDValue(); 7041 DebugLoc dl = N->getDebugLoc(); 7042 SmallVector<SDValue, 8> Ops; 7043 unsigned NumElts = VT.getVectorNumElements(); 7044 for (unsigned i = 0; i < NumElts; ++i) { 7045 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i)); 7046 Ops.push_back(V); 7047 // Make the DAGCombiner fold the bitcast. 7048 DCI.AddToWorklist(V.getNode()); 7049 } 7050 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts); 7051 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts); 7052 return DAG.getNode(ISD::BITCAST, dl, VT, BV); 7053} 7054 7055/// PerformInsertEltCombine - Target-specific dag combine xforms for 7056/// ISD::INSERT_VECTOR_ELT. 7057static SDValue PerformInsertEltCombine(SDNode *N, 7058 TargetLowering::DAGCombinerInfo &DCI) { 7059 // Bitcast an i64 load inserted into a vector to f64. 7060 // Otherwise, the i64 value will be legalized to a pair of i32 values. 7061 EVT VT = N->getValueType(0); 7062 SDNode *Elt = N->getOperand(1).getNode(); 7063 if (VT.getVectorElementType() != MVT::i64 || 7064 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile()) 7065 return SDValue(); 7066 7067 SelectionDAG &DAG = DCI.DAG; 7068 DebugLoc dl = N->getDebugLoc(); 7069 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, 7070 VT.getVectorNumElements()); 7071 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0)); 7072 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1)); 7073 // Make the DAGCombiner fold the bitcasts. 7074 DCI.AddToWorklist(Vec.getNode()); 7075 DCI.AddToWorklist(V.getNode()); 7076 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT, 7077 Vec, V, N->getOperand(2)); 7078 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt); 7079} 7080 7081/// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for 7082/// ISD::VECTOR_SHUFFLE. 7083static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) { 7084 // The LLVM shufflevector instruction does not require the shuffle mask 7085 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does 7086 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the 7087 // operands do not match the mask length, they are extended by concatenating 7088 // them with undef vectors. That is probably the right thing for other 7089 // targets, but for NEON it is better to concatenate two double-register 7090 // size vector operands into a single quad-register size vector. Do that 7091 // transformation here: 7092 // shuffle(concat(v1, undef), concat(v2, undef)) -> 7093 // shuffle(concat(v1, v2), undef) 7094 SDValue Op0 = N->getOperand(0); 7095 SDValue Op1 = N->getOperand(1); 7096 if (Op0.getOpcode() != ISD::CONCAT_VECTORS || 7097 Op1.getOpcode() != ISD::CONCAT_VECTORS || 7098 Op0.getNumOperands() != 2 || 7099 Op1.getNumOperands() != 2) 7100 return SDValue(); 7101 SDValue Concat0Op1 = Op0.getOperand(1); 7102 SDValue Concat1Op1 = Op1.getOperand(1); 7103 if (Concat0Op1.getOpcode() != ISD::UNDEF || 7104 Concat1Op1.getOpcode() != ISD::UNDEF) 7105 return SDValue(); 7106 // Skip the transformation if any of the types are illegal. 7107 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 7108 EVT VT = N->getValueType(0); 7109 if (!TLI.isTypeLegal(VT) || 7110 !TLI.isTypeLegal(Concat0Op1.getValueType()) || 7111 !TLI.isTypeLegal(Concat1Op1.getValueType())) 7112 return SDValue(); 7113 7114 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, 7115 Op0.getOperand(0), Op1.getOperand(0)); 7116 // Translate the shuffle mask. 7117 SmallVector<int, 16> NewMask; 7118 unsigned NumElts = VT.getVectorNumElements(); 7119 unsigned HalfElts = NumElts/2; 7120 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 7121 for (unsigned n = 0; n < NumElts; ++n) { 7122 int MaskElt = SVN->getMaskElt(n); 7123 int NewElt = -1; 7124 if (MaskElt < (int)HalfElts) 7125 NewElt = MaskElt; 7126 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts)) 7127 NewElt = HalfElts + MaskElt - NumElts; 7128 NewMask.push_back(NewElt); 7129 } 7130 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat, 7131 DAG.getUNDEF(VT), NewMask.data()); 7132} 7133 7134/// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and 7135/// NEON load/store intrinsics to merge base address updates. 7136static SDValue CombineBaseUpdate(SDNode *N, 7137 TargetLowering::DAGCombinerInfo &DCI) { 7138 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 7139 return SDValue(); 7140 7141 SelectionDAG &DAG = DCI.DAG; 7142 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID || 7143 N->getOpcode() == ISD::INTRINSIC_W_CHAIN); 7144 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1); 7145 SDValue Addr = N->getOperand(AddrOpIdx); 7146 7147 // Search for a use of the address operand that is an increment. 7148 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), 7149 UE = Addr.getNode()->use_end(); UI != UE; ++UI) { 7150 SDNode *User = *UI; 7151 if (User->getOpcode() != ISD::ADD || 7152 UI.getUse().getResNo() != Addr.getResNo()) 7153 continue; 7154 7155 // Check that the add is independent of the load/store. Otherwise, folding 7156 // it would create a cycle. 7157 if (User->isPredecessorOf(N) || N->isPredecessorOf(User)) 7158 continue; 7159 7160 // Find the new opcode for the updating load/store. 7161 bool isLoad = true; 7162 bool isLaneOp = false; 7163 unsigned NewOpc = 0; 7164 unsigned NumVecs = 0; 7165 if (isIntrinsic) { 7166 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 7167 switch (IntNo) { 7168 default: assert(0 && "unexpected intrinsic for Neon base update"); 7169 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD; 7170 NumVecs = 1; break; 7171 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD; 7172 NumVecs = 2; break; 7173 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD; 7174 NumVecs = 3; break; 7175 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD; 7176 NumVecs = 4; break; 7177 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD; 7178 NumVecs = 2; isLaneOp = true; break; 7179 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD; 7180 NumVecs = 3; isLaneOp = true; break; 7181 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD; 7182 NumVecs = 4; isLaneOp = true; break; 7183 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD; 7184 NumVecs = 1; isLoad = false; break; 7185 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD; 7186 NumVecs = 2; isLoad = false; break; 7187 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD; 7188 NumVecs = 3; isLoad = false; break; 7189 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD; 7190 NumVecs = 4; isLoad = false; break; 7191 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD; 7192 NumVecs = 2; isLoad = false; isLaneOp = true; break; 7193 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD; 7194 NumVecs = 3; isLoad = false; isLaneOp = true; break; 7195 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD; 7196 NumVecs = 4; isLoad = false; isLaneOp = true; break; 7197 } 7198 } else { 7199 isLaneOp = true; 7200 switch (N->getOpcode()) { 7201 default: assert(0 && "unexpected opcode for Neon base update"); 7202 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break; 7203 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break; 7204 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break; 7205 } 7206 } 7207 7208 // Find the size of memory referenced by the load/store. 7209 EVT VecTy; 7210 if (isLoad) 7211 VecTy = N->getValueType(0); 7212 else 7213 VecTy = N->getOperand(AddrOpIdx+1).getValueType(); 7214 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8; 7215 if (isLaneOp) 7216 NumBytes /= VecTy.getVectorNumElements(); 7217 7218 // If the increment is a constant, it must match the memory ref size. 7219 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0); 7220 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) { 7221 uint64_t IncVal = CInc->getZExtValue(); 7222 if (IncVal != NumBytes) 7223 continue; 7224 } else if (NumBytes >= 3 * 16) { 7225 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two 7226 // separate instructions that make it harder to use a non-constant update. 7227 continue; 7228 } 7229 7230 // Create the new updating load/store node. 7231 EVT Tys[6]; 7232 unsigned NumResultVecs = (isLoad ? NumVecs : 0); 7233 unsigned n; 7234 for (n = 0; n < NumResultVecs; ++n) 7235 Tys[n] = VecTy; 7236 Tys[n++] = MVT::i32; 7237 Tys[n] = MVT::Other; 7238 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs+2); 7239 SmallVector<SDValue, 8> Ops; 7240 Ops.push_back(N->getOperand(0)); // incoming chain 7241 Ops.push_back(N->getOperand(AddrOpIdx)); 7242 Ops.push_back(Inc); 7243 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) { 7244 Ops.push_back(N->getOperand(i)); 7245 } 7246 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N); 7247 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, N->getDebugLoc(), SDTys, 7248 Ops.data(), Ops.size(), 7249 MemInt->getMemoryVT(), 7250 MemInt->getMemOperand()); 7251 7252 // Update the uses. 7253 std::vector<SDValue> NewResults; 7254 for (unsigned i = 0; i < NumResultVecs; ++i) { 7255 NewResults.push_back(SDValue(UpdN.getNode(), i)); 7256 } 7257 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain 7258 DCI.CombineTo(N, NewResults); 7259 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs)); 7260 7261 break; 7262 } 7263 return SDValue(); 7264} 7265 7266/// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a 7267/// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic 7268/// are also VDUPLANEs. If so, combine them to a vldN-dup operation and 7269/// return true. 7270static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { 7271 SelectionDAG &DAG = DCI.DAG; 7272 EVT VT = N->getValueType(0); 7273 // vldN-dup instructions only support 64-bit vectors for N > 1. 7274 if (!VT.is64BitVector()) 7275 return false; 7276 7277 // Check if the VDUPLANE operand is a vldN-dup intrinsic. 7278 SDNode *VLD = N->getOperand(0).getNode(); 7279 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN) 7280 return false; 7281 unsigned NumVecs = 0; 7282 unsigned NewOpc = 0; 7283 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue(); 7284 if (IntNo == Intrinsic::arm_neon_vld2lane) { 7285 NumVecs = 2; 7286 NewOpc = ARMISD::VLD2DUP; 7287 } else if (IntNo == Intrinsic::arm_neon_vld3lane) { 7288 NumVecs = 3; 7289 NewOpc = ARMISD::VLD3DUP; 7290 } else if (IntNo == Intrinsic::arm_neon_vld4lane) { 7291 NumVecs = 4; 7292 NewOpc = ARMISD::VLD4DUP; 7293 } else { 7294 return false; 7295 } 7296 7297 // First check that all the vldN-lane uses are VDUPLANEs and that the lane 7298 // numbers match the load. 7299 unsigned VLDLaneNo = 7300 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue(); 7301 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); 7302 UI != UE; ++UI) { 7303 // Ignore uses of the chain result. 7304 if (UI.getUse().getResNo() == NumVecs) 7305 continue; 7306 SDNode *User = *UI; 7307 if (User->getOpcode() != ARMISD::VDUPLANE || 7308 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue()) 7309 return false; 7310 } 7311 7312 // Create the vldN-dup node. 7313 EVT Tys[5]; 7314 unsigned n; 7315 for (n = 0; n < NumVecs; ++n) 7316 Tys[n] = VT; 7317 Tys[n] = MVT::Other; 7318 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1); 7319 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) }; 7320 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD); 7321 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys, 7322 Ops, 2, VLDMemInt->getMemoryVT(), 7323 VLDMemInt->getMemOperand()); 7324 7325 // Update the uses. 7326 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); 7327 UI != UE; ++UI) { 7328 unsigned ResNo = UI.getUse().getResNo(); 7329 // Ignore uses of the chain result. 7330 if (ResNo == NumVecs) 7331 continue; 7332 SDNode *User = *UI; 7333 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo)); 7334 } 7335 7336 // Now the vldN-lane intrinsic is dead except for its chain result. 7337 // Update uses of the chain. 7338 std::vector<SDValue> VLDDupResults; 7339 for (unsigned n = 0; n < NumVecs; ++n) 7340 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n)); 7341 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs)); 7342 DCI.CombineTo(VLD, VLDDupResults); 7343 7344 return true; 7345} 7346 7347/// PerformVDUPLANECombine - Target-specific dag combine xforms for 7348/// ARMISD::VDUPLANE. 7349static SDValue PerformVDUPLANECombine(SDNode *N, 7350 TargetLowering::DAGCombinerInfo &DCI) { 7351 SDValue Op = N->getOperand(0); 7352 7353 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses 7354 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation. 7355 if (CombineVLDDUP(N, DCI)) 7356 return SDValue(N, 0); 7357 7358 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is 7359 // redundant. Ignore bit_converts for now; element sizes are checked below. 7360 while (Op.getOpcode() == ISD::BITCAST) 7361 Op = Op.getOperand(0); 7362 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM) 7363 return SDValue(); 7364 7365 // Make sure the VMOV element size is not bigger than the VDUPLANE elements. 7366 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits(); 7367 // The canonical VMOV for a zero vector uses a 32-bit element size. 7368 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 7369 unsigned EltBits; 7370 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0) 7371 EltSize = 8; 7372 EVT VT = N->getValueType(0); 7373 if (EltSize > VT.getVectorElementType().getSizeInBits()) 7374 return SDValue(); 7375 7376 return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 7377} 7378 7379// isConstVecPow2 - Return true if each vector element is a power of 2, all 7380// elements are the same constant, C, and Log2(C) ranges from 1 to 32. 7381static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C) 7382{ 7383 integerPart cN; 7384 integerPart c0 = 0; 7385 for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements(); 7386 I != E; I++) { 7387 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I)); 7388 if (!C) 7389 return false; 7390 7391 bool isExact; 7392 APFloat APF = C->getValueAPF(); 7393 if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact) 7394 != APFloat::opOK || !isExact) 7395 return false; 7396 7397 c0 = (I == 0) ? cN : c0; 7398 if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32) 7399 return false; 7400 } 7401 C = c0; 7402 return true; 7403} 7404 7405/// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD) 7406/// can replace combinations of VMUL and VCVT (floating-point to integer) 7407/// when the VMUL has a constant operand that is a power of 2. 7408/// 7409/// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): 7410/// vmul.f32 d16, d17, d16 7411/// vcvt.s32.f32 d16, d16 7412/// becomes: 7413/// vcvt.s32.f32 d16, d16, #3 7414static SDValue PerformVCVTCombine(SDNode *N, 7415 TargetLowering::DAGCombinerInfo &DCI, 7416 const ARMSubtarget *Subtarget) { 7417 SelectionDAG &DAG = DCI.DAG; 7418 SDValue Op = N->getOperand(0); 7419 7420 if (!Subtarget->hasNEON() || !Op.getValueType().isVector() || 7421 Op.getOpcode() != ISD::FMUL) 7422 return SDValue(); 7423 7424 uint64_t C; 7425 SDValue N0 = Op->getOperand(0); 7426 SDValue ConstVec = Op->getOperand(1); 7427 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT; 7428 7429 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR || 7430 !isConstVecPow2(ConstVec, isSigned, C)) 7431 return SDValue(); 7432 7433 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs : 7434 Intrinsic::arm_neon_vcvtfp2fxu; 7435 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), 7436 N->getValueType(0), 7437 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0, 7438 DAG.getConstant(Log2_64(C), MVT::i32)); 7439} 7440 7441/// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD) 7442/// can replace combinations of VCVT (integer to floating-point) and VDIV 7443/// when the VDIV has a constant operand that is a power of 2. 7444/// 7445/// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): 7446/// vcvt.f32.s32 d16, d16 7447/// vdiv.f32 d16, d17, d16 7448/// becomes: 7449/// vcvt.f32.s32 d16, d16, #3 7450static SDValue PerformVDIVCombine(SDNode *N, 7451 TargetLowering::DAGCombinerInfo &DCI, 7452 const ARMSubtarget *Subtarget) { 7453 SelectionDAG &DAG = DCI.DAG; 7454 SDValue Op = N->getOperand(0); 7455 unsigned OpOpcode = Op.getNode()->getOpcode(); 7456 7457 if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() || 7458 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP)) 7459 return SDValue(); 7460 7461 uint64_t C; 7462 SDValue ConstVec = N->getOperand(1); 7463 bool isSigned = OpOpcode == ISD::SINT_TO_FP; 7464 7465 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR || 7466 !isConstVecPow2(ConstVec, isSigned, C)) 7467 return SDValue(); 7468 7469 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp : 7470 Intrinsic::arm_neon_vcvtfxu2fp; 7471 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), 7472 Op.getValueType(), 7473 DAG.getConstant(IntrinsicOpcode, MVT::i32), 7474 Op.getOperand(0), DAG.getConstant(Log2_64(C), MVT::i32)); 7475} 7476 7477/// Getvshiftimm - Check if this is a valid build_vector for the immediate 7478/// operand of a vector shift operation, where all the elements of the 7479/// build_vector must have the same constant integer value. 7480static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) { 7481 // Ignore bit_converts. 7482 while (Op.getOpcode() == ISD::BITCAST) 7483 Op = Op.getOperand(0); 7484 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); 7485 APInt SplatBits, SplatUndef; 7486 unsigned SplatBitSize; 7487 bool HasAnyUndefs; 7488 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, 7489 HasAnyUndefs, ElementBits) || 7490 SplatBitSize > ElementBits) 7491 return false; 7492 Cnt = SplatBits.getSExtValue(); 7493 return true; 7494} 7495 7496/// isVShiftLImm - Check if this is a valid build_vector for the immediate 7497/// operand of a vector shift left operation. That value must be in the range: 7498/// 0 <= Value < ElementBits for a left shift; or 7499/// 0 <= Value <= ElementBits for a long left shift. 7500static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) { 7501 assert(VT.isVector() && "vector shift count is not a vector type"); 7502 unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); 7503 if (! getVShiftImm(Op, ElementBits, Cnt)) 7504 return false; 7505 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits); 7506} 7507 7508/// isVShiftRImm - Check if this is a valid build_vector for the immediate 7509/// operand of a vector shift right operation. For a shift opcode, the value 7510/// is positive, but for an intrinsic the value count must be negative. The 7511/// absolute value must be in the range: 7512/// 1 <= |Value| <= ElementBits for a right shift; or 7513/// 1 <= |Value| <= ElementBits/2 for a narrow right shift. 7514static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic, 7515 int64_t &Cnt) { 7516 assert(VT.isVector() && "vector shift count is not a vector type"); 7517 unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); 7518 if (! getVShiftImm(Op, ElementBits, Cnt)) 7519 return false; 7520 if (isIntrinsic) 7521 Cnt = -Cnt; 7522 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits)); 7523} 7524 7525/// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics. 7526static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { 7527 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); 7528 switch (IntNo) { 7529 default: 7530 // Don't do anything for most intrinsics. 7531 break; 7532 7533 // Vector shifts: check for immediate versions and lower them. 7534 // Note: This is done during DAG combining instead of DAG legalizing because 7535 // the build_vectors for 64-bit vector element shift counts are generally 7536 // not legal, and it is hard to see their values after they get legalized to 7537 // loads from a constant pool. 7538 case Intrinsic::arm_neon_vshifts: 7539 case Intrinsic::arm_neon_vshiftu: 7540 case Intrinsic::arm_neon_vshiftls: 7541 case Intrinsic::arm_neon_vshiftlu: 7542 case Intrinsic::arm_neon_vshiftn: 7543 case Intrinsic::arm_neon_vrshifts: 7544 case Intrinsic::arm_neon_vrshiftu: 7545 case Intrinsic::arm_neon_vrshiftn: 7546 case Intrinsic::arm_neon_vqshifts: 7547 case Intrinsic::arm_neon_vqshiftu: 7548 case Intrinsic::arm_neon_vqshiftsu: 7549 case Intrinsic::arm_neon_vqshiftns: 7550 case Intrinsic::arm_neon_vqshiftnu: 7551 case Intrinsic::arm_neon_vqshiftnsu: 7552 case Intrinsic::arm_neon_vqrshiftns: 7553 case Intrinsic::arm_neon_vqrshiftnu: 7554 case Intrinsic::arm_neon_vqrshiftnsu: { 7555 EVT VT = N->getOperand(1).getValueType(); 7556 int64_t Cnt; 7557 unsigned VShiftOpc = 0; 7558 7559 switch (IntNo) { 7560 case Intrinsic::arm_neon_vshifts: 7561 case Intrinsic::arm_neon_vshiftu: 7562 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) { 7563 VShiftOpc = ARMISD::VSHL; 7564 break; 7565 } 7566 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) { 7567 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ? 7568 ARMISD::VSHRs : ARMISD::VSHRu); 7569 break; 7570 } 7571 return SDValue(); 7572 7573 case Intrinsic::arm_neon_vshiftls: 7574 case Intrinsic::arm_neon_vshiftlu: 7575 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt)) 7576 break; 7577 llvm_unreachable("invalid shift count for vshll intrinsic"); 7578 7579 case Intrinsic::arm_neon_vrshifts: 7580 case Intrinsic::arm_neon_vrshiftu: 7581 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) 7582 break; 7583 return SDValue(); 7584 7585 case Intrinsic::arm_neon_vqshifts: 7586 case Intrinsic::arm_neon_vqshiftu: 7587 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) 7588 break; 7589 return SDValue(); 7590 7591 case Intrinsic::arm_neon_vqshiftsu: 7592 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) 7593 break; 7594 llvm_unreachable("invalid shift count for vqshlu intrinsic"); 7595 7596 case Intrinsic::arm_neon_vshiftn: 7597 case Intrinsic::arm_neon_vrshiftn: 7598 case Intrinsic::arm_neon_vqshiftns: 7599 case Intrinsic::arm_neon_vqshiftnu: 7600 case Intrinsic::arm_neon_vqshiftnsu: 7601 case Intrinsic::arm_neon_vqrshiftns: 7602 case Intrinsic::arm_neon_vqrshiftnu: 7603 case Intrinsic::arm_neon_vqrshiftnsu: 7604 // Narrowing shifts require an immediate right shift. 7605 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt)) 7606 break; 7607 llvm_unreachable("invalid shift count for narrowing vector shift " 7608 "intrinsic"); 7609 7610 default: 7611 llvm_unreachable("unhandled vector shift"); 7612 } 7613 7614 switch (IntNo) { 7615 case Intrinsic::arm_neon_vshifts: 7616 case Intrinsic::arm_neon_vshiftu: 7617 // Opcode already set above. 7618 break; 7619 case Intrinsic::arm_neon_vshiftls: 7620 case Intrinsic::arm_neon_vshiftlu: 7621 if (Cnt == VT.getVectorElementType().getSizeInBits()) 7622 VShiftOpc = ARMISD::VSHLLi; 7623 else 7624 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ? 7625 ARMISD::VSHLLs : ARMISD::VSHLLu); 7626 break; 7627 case Intrinsic::arm_neon_vshiftn: 7628 VShiftOpc = ARMISD::VSHRN; break; 7629 case Intrinsic::arm_neon_vrshifts: 7630 VShiftOpc = ARMISD::VRSHRs; break; 7631 case Intrinsic::arm_neon_vrshiftu: 7632 VShiftOpc = ARMISD::VRSHRu; break; 7633 case Intrinsic::arm_neon_vrshiftn: 7634 VShiftOpc = ARMISD::VRSHRN; break; 7635 case Intrinsic::arm_neon_vqshifts: 7636 VShiftOpc = ARMISD::VQSHLs; break; 7637 case Intrinsic::arm_neon_vqshiftu: 7638 VShiftOpc = ARMISD::VQSHLu; break; 7639 case Intrinsic::arm_neon_vqshiftsu: 7640 VShiftOpc = ARMISD::VQSHLsu; break; 7641 case Intrinsic::arm_neon_vqshiftns: 7642 VShiftOpc = ARMISD::VQSHRNs; break; 7643 case Intrinsic::arm_neon_vqshiftnu: 7644 VShiftOpc = ARMISD::VQSHRNu; break; 7645 case Intrinsic::arm_neon_vqshiftnsu: 7646 VShiftOpc = ARMISD::VQSHRNsu; break; 7647 case Intrinsic::arm_neon_vqrshiftns: 7648 VShiftOpc = ARMISD::VQRSHRNs; break; 7649 case Intrinsic::arm_neon_vqrshiftnu: 7650 VShiftOpc = ARMISD::VQRSHRNu; break; 7651 case Intrinsic::arm_neon_vqrshiftnsu: 7652 VShiftOpc = ARMISD::VQRSHRNsu; break; 7653 } 7654 7655 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), 7656 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32)); 7657 } 7658 7659 case Intrinsic::arm_neon_vshiftins: { 7660 EVT VT = N->getOperand(1).getValueType(); 7661 int64_t Cnt; 7662 unsigned VShiftOpc = 0; 7663 7664 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt)) 7665 VShiftOpc = ARMISD::VSLI; 7666 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt)) 7667 VShiftOpc = ARMISD::VSRI; 7668 else { 7669 llvm_unreachable("invalid shift count for vsli/vsri intrinsic"); 7670 } 7671 7672 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), 7673 N->getOperand(1), N->getOperand(2), 7674 DAG.getConstant(Cnt, MVT::i32)); 7675 } 7676 7677 case Intrinsic::arm_neon_vqrshifts: 7678 case Intrinsic::arm_neon_vqrshiftu: 7679 // No immediate versions of these to check for. 7680 break; 7681 } 7682 7683 return SDValue(); 7684} 7685 7686/// PerformShiftCombine - Checks for immediate versions of vector shifts and 7687/// lowers them. As with the vector shift intrinsics, this is done during DAG 7688/// combining instead of DAG legalizing because the build_vectors for 64-bit 7689/// vector element shift counts are generally not legal, and it is hard to see 7690/// their values after they get legalized to loads from a constant pool. 7691static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG, 7692 const ARMSubtarget *ST) { 7693 EVT VT = N->getValueType(0); 7694 7695 // Nothing to be done for scalar shifts. 7696 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 7697 if (!VT.isVector() || !TLI.isTypeLegal(VT)) 7698 return SDValue(); 7699 7700 assert(ST->hasNEON() && "unexpected vector shift"); 7701 int64_t Cnt; 7702 7703 switch (N->getOpcode()) { 7704 default: llvm_unreachable("unexpected shift opcode"); 7705 7706 case ISD::SHL: 7707 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt)) 7708 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0), 7709 DAG.getConstant(Cnt, MVT::i32)); 7710 break; 7711 7712 case ISD::SRA: 7713 case ISD::SRL: 7714 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) { 7715 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ? 7716 ARMISD::VSHRs : ARMISD::VSHRu); 7717 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0), 7718 DAG.getConstant(Cnt, MVT::i32)); 7719 } 7720 } 7721 return SDValue(); 7722} 7723 7724/// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND, 7725/// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND. 7726static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG, 7727 const ARMSubtarget *ST) { 7728 SDValue N0 = N->getOperand(0); 7729 7730 // Check for sign- and zero-extensions of vector extract operations of 8- 7731 // and 16-bit vector elements. NEON supports these directly. They are 7732 // handled during DAG combining because type legalization will promote them 7733 // to 32-bit types and it is messy to recognize the operations after that. 7734 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { 7735 SDValue Vec = N0.getOperand(0); 7736 SDValue Lane = N0.getOperand(1); 7737 EVT VT = N->getValueType(0); 7738 EVT EltVT = N0.getValueType(); 7739 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 7740 7741 if (VT == MVT::i32 && 7742 (EltVT == MVT::i8 || EltVT == MVT::i16) && 7743 TLI.isTypeLegal(Vec.getValueType()) && 7744 isa<ConstantSDNode>(Lane)) { 7745 7746 unsigned Opc = 0; 7747 switch (N->getOpcode()) { 7748 default: llvm_unreachable("unexpected opcode"); 7749 case ISD::SIGN_EXTEND: 7750 Opc = ARMISD::VGETLANEs; 7751 break; 7752 case ISD::ZERO_EXTEND: 7753 case ISD::ANY_EXTEND: 7754 Opc = ARMISD::VGETLANEu; 7755 break; 7756 } 7757 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane); 7758 } 7759 } 7760 7761 return SDValue(); 7762} 7763 7764/// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC 7765/// to match f32 max/min patterns to use NEON vmax/vmin instructions. 7766static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG, 7767 const ARMSubtarget *ST) { 7768 // If the target supports NEON, try to use vmax/vmin instructions for f32 7769 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set, 7770 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is 7771 // a NaN; only do the transformation when it matches that behavior. 7772 7773 // For now only do this when using NEON for FP operations; if using VFP, it 7774 // is not obvious that the benefit outweighs the cost of switching to the 7775 // NEON pipeline. 7776 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() || 7777 N->getValueType(0) != MVT::f32) 7778 return SDValue(); 7779 7780 SDValue CondLHS = N->getOperand(0); 7781 SDValue CondRHS = N->getOperand(1); 7782 SDValue LHS = N->getOperand(2); 7783 SDValue RHS = N->getOperand(3); 7784 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get(); 7785 7786 unsigned Opcode = 0; 7787 bool IsReversed; 7788 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) { 7789 IsReversed = false; // x CC y ? x : y 7790 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) { 7791 IsReversed = true ; // x CC y ? y : x 7792 } else { 7793 return SDValue(); 7794 } 7795 7796 bool IsUnordered; 7797 switch (CC) { 7798 default: break; 7799 case ISD::SETOLT: 7800 case ISD::SETOLE: 7801 case ISD::SETLT: 7802 case ISD::SETLE: 7803 case ISD::SETULT: 7804 case ISD::SETULE: 7805 // If LHS is NaN, an ordered comparison will be false and the result will 7806 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS 7807 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN. 7808 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE); 7809 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS)) 7810 break; 7811 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin 7812 // will return -0, so vmin can only be used for unsafe math or if one of 7813 // the operands is known to be nonzero. 7814 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) && 7815 !UnsafeFPMath && 7816 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 7817 break; 7818 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN; 7819 break; 7820 7821 case ISD::SETOGT: 7822 case ISD::SETOGE: 7823 case ISD::SETGT: 7824 case ISD::SETGE: 7825 case ISD::SETUGT: 7826 case ISD::SETUGE: 7827 // If LHS is NaN, an ordered comparison will be false and the result will 7828 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS 7829 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN. 7830 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE); 7831 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS)) 7832 break; 7833 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax 7834 // will return +0, so vmax can only be used for unsafe math or if one of 7835 // the operands is known to be nonzero. 7836 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) && 7837 !UnsafeFPMath && 7838 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 7839 break; 7840 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX; 7841 break; 7842 } 7843 7844 if (!Opcode) 7845 return SDValue(); 7846 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS); 7847} 7848 7849/// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV. 7850SDValue 7851ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const { 7852 SDValue Cmp = N->getOperand(4); 7853 if (Cmp.getOpcode() != ARMISD::CMPZ) 7854 // Only looking at EQ and NE cases. 7855 return SDValue(); 7856 7857 EVT VT = N->getValueType(0); 7858 DebugLoc dl = N->getDebugLoc(); 7859 SDValue LHS = Cmp.getOperand(0); 7860 SDValue RHS = Cmp.getOperand(1); 7861 SDValue FalseVal = N->getOperand(0); 7862 SDValue TrueVal = N->getOperand(1); 7863 SDValue ARMcc = N->getOperand(2); 7864 ARMCC::CondCodes CC = 7865 (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue(); 7866 7867 // Simplify 7868 // mov r1, r0 7869 // cmp r1, x 7870 // mov r0, y 7871 // moveq r0, x 7872 // to 7873 // cmp r0, x 7874 // movne r0, y 7875 // 7876 // mov r1, r0 7877 // cmp r1, x 7878 // mov r0, x 7879 // movne r0, y 7880 // to 7881 // cmp r0, x 7882 // movne r0, y 7883 /// FIXME: Turn this into a target neutral optimization? 7884 SDValue Res; 7885 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) { 7886 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc, 7887 N->getOperand(3), Cmp); 7888 } else if (CC == ARMCC::EQ && TrueVal == RHS) { 7889 SDValue ARMcc; 7890 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl); 7891 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc, 7892 N->getOperand(3), NewCmp); 7893 } 7894 7895 if (Res.getNode()) { 7896 APInt KnownZero, KnownOne; 7897 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 7898 DAG.ComputeMaskedBits(SDValue(N,0), Mask, KnownZero, KnownOne); 7899 // Capture demanded bits information that would be otherwise lost. 7900 if (KnownZero == 0xfffffffe) 7901 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, 7902 DAG.getValueType(MVT::i1)); 7903 else if (KnownZero == 0xffffff00) 7904 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, 7905 DAG.getValueType(MVT::i8)); 7906 else if (KnownZero == 0xffff0000) 7907 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, 7908 DAG.getValueType(MVT::i16)); 7909 } 7910 7911 return Res; 7912} 7913 7914SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N, 7915 DAGCombinerInfo &DCI) const { 7916 switch (N->getOpcode()) { 7917 default: break; 7918 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget); 7919 case ISD::SUB: return PerformSUBCombine(N, DCI); 7920 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget); 7921 case ISD::OR: return PerformORCombine(N, DCI, Subtarget); 7922 case ISD::AND: return PerformANDCombine(N, DCI); 7923 case ARMISD::BFI: return PerformBFICombine(N, DCI); 7924 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI); 7925 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG); 7926 case ISD::STORE: return PerformSTORECombine(N, DCI); 7927 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI); 7928 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI); 7929 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG); 7930 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI); 7931 case ISD::FP_TO_SINT: 7932 case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget); 7933 case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget); 7934 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG); 7935 case ISD::SHL: 7936 case ISD::SRA: 7937 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget); 7938 case ISD::SIGN_EXTEND: 7939 case ISD::ZERO_EXTEND: 7940 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget); 7941 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget); 7942 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG); 7943 case ARMISD::VLD2DUP: 7944 case ARMISD::VLD3DUP: 7945 case ARMISD::VLD4DUP: 7946 return CombineBaseUpdate(N, DCI); 7947 case ISD::INTRINSIC_VOID: 7948 case ISD::INTRINSIC_W_CHAIN: 7949 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) { 7950 case Intrinsic::arm_neon_vld1: 7951 case Intrinsic::arm_neon_vld2: 7952 case Intrinsic::arm_neon_vld3: 7953 case Intrinsic::arm_neon_vld4: 7954 case Intrinsic::arm_neon_vld2lane: 7955 case Intrinsic::arm_neon_vld3lane: 7956 case Intrinsic::arm_neon_vld4lane: 7957 case Intrinsic::arm_neon_vst1: 7958 case Intrinsic::arm_neon_vst2: 7959 case Intrinsic::arm_neon_vst3: 7960 case Intrinsic::arm_neon_vst4: 7961 case Intrinsic::arm_neon_vst2lane: 7962 case Intrinsic::arm_neon_vst3lane: 7963 case Intrinsic::arm_neon_vst4lane: 7964 return CombineBaseUpdate(N, DCI); 7965 default: break; 7966 } 7967 break; 7968 } 7969 return SDValue(); 7970} 7971 7972bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc, 7973 EVT VT) const { 7974 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE); 7975} 7976 7977bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { 7978 if (!Subtarget->allowsUnalignedMem()) 7979 return false; 7980 7981 switch (VT.getSimpleVT().SimpleTy) { 7982 default: 7983 return false; 7984 case MVT::i8: 7985 case MVT::i16: 7986 case MVT::i32: 7987 return true; 7988 // FIXME: VLD1 etc with standard alignment is legal. 7989 } 7990} 7991 7992static bool isLegalT1AddressImmediate(int64_t V, EVT VT) { 7993 if (V < 0) 7994 return false; 7995 7996 unsigned Scale = 1; 7997 switch (VT.getSimpleVT().SimpleTy) { 7998 default: return false; 7999 case MVT::i1: 8000 case MVT::i8: 8001 // Scale == 1; 8002 break; 8003 case MVT::i16: 8004 // Scale == 2; 8005 Scale = 2; 8006 break; 8007 case MVT::i32: 8008 // Scale == 4; 8009 Scale = 4; 8010 break; 8011 } 8012 8013 if ((V & (Scale - 1)) != 0) 8014 return false; 8015 V /= Scale; 8016 return V == (V & ((1LL << 5) - 1)); 8017} 8018 8019static bool isLegalT2AddressImmediate(int64_t V, EVT VT, 8020 const ARMSubtarget *Subtarget) { 8021 bool isNeg = false; 8022 if (V < 0) { 8023 isNeg = true; 8024 V = - V; 8025 } 8026 8027 switch (VT.getSimpleVT().SimpleTy) { 8028 default: return false; 8029 case MVT::i1: 8030 case MVT::i8: 8031 case MVT::i16: 8032 case MVT::i32: 8033 // + imm12 or - imm8 8034 if (isNeg) 8035 return V == (V & ((1LL << 8) - 1)); 8036 return V == (V & ((1LL << 12) - 1)); 8037 case MVT::f32: 8038 case MVT::f64: 8039 // Same as ARM mode. FIXME: NEON? 8040 if (!Subtarget->hasVFP2()) 8041 return false; 8042 if ((V & 3) != 0) 8043 return false; 8044 V >>= 2; 8045 return V == (V & ((1LL << 8) - 1)); 8046 } 8047} 8048 8049/// isLegalAddressImmediate - Return true if the integer value can be used 8050/// as the offset of the target addressing mode for load / store of the 8051/// given type. 8052static bool isLegalAddressImmediate(int64_t V, EVT VT, 8053 const ARMSubtarget *Subtarget) { 8054 if (V == 0) 8055 return true; 8056 8057 if (!VT.isSimple()) 8058 return false; 8059 8060 if (Subtarget->isThumb1Only()) 8061 return isLegalT1AddressImmediate(V, VT); 8062 else if (Subtarget->isThumb2()) 8063 return isLegalT2AddressImmediate(V, VT, Subtarget); 8064 8065 // ARM mode. 8066 if (V < 0) 8067 V = - V; 8068 switch (VT.getSimpleVT().SimpleTy) { 8069 default: return false; 8070 case MVT::i1: 8071 case MVT::i8: 8072 case MVT::i32: 8073 // +- imm12 8074 return V == (V & ((1LL << 12) - 1)); 8075 case MVT::i16: 8076 // +- imm8 8077 return V == (V & ((1LL << 8) - 1)); 8078 case MVT::f32: 8079 case MVT::f64: 8080 if (!Subtarget->hasVFP2()) // FIXME: NEON? 8081 return false; 8082 if ((V & 3) != 0) 8083 return false; 8084 V >>= 2; 8085 return V == (V & ((1LL << 8) - 1)); 8086 } 8087} 8088 8089bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM, 8090 EVT VT) const { 8091 int Scale = AM.Scale; 8092 if (Scale < 0) 8093 return false; 8094 8095 switch (VT.getSimpleVT().SimpleTy) { 8096 default: return false; 8097 case MVT::i1: 8098 case MVT::i8: 8099 case MVT::i16: 8100 case MVT::i32: 8101 if (Scale == 1) 8102 return true; 8103 // r + r << imm 8104 Scale = Scale & ~1; 8105 return Scale == 2 || Scale == 4 || Scale == 8; 8106 case MVT::i64: 8107 // r + r 8108 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 8109 return true; 8110 return false; 8111 case MVT::isVoid: 8112 // Note, we allow "void" uses (basically, uses that aren't loads or 8113 // stores), because arm allows folding a scale into many arithmetic 8114 // operations. This should be made more precise and revisited later. 8115 8116 // Allow r << imm, but the imm has to be a multiple of two. 8117 if (Scale & 1) return false; 8118 return isPowerOf2_32(Scale); 8119 } 8120} 8121 8122/// isLegalAddressingMode - Return true if the addressing mode represented 8123/// by AM is legal for this target, for a load/store of the specified type. 8124bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM, 8125 Type *Ty) const { 8126 EVT VT = getValueType(Ty, true); 8127 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget)) 8128 return false; 8129 8130 // Can never fold addr of global into load/store. 8131 if (AM.BaseGV) 8132 return false; 8133 8134 switch (AM.Scale) { 8135 case 0: // no scale reg, must be "r+i" or "r", or "i". 8136 break; 8137 case 1: 8138 if (Subtarget->isThumb1Only()) 8139 return false; 8140 // FALL THROUGH. 8141 default: 8142 // ARM doesn't support any R+R*scale+imm addr modes. 8143 if (AM.BaseOffs) 8144 return false; 8145 8146 if (!VT.isSimple()) 8147 return false; 8148 8149 if (Subtarget->isThumb2()) 8150 return isLegalT2ScaledAddressingMode(AM, VT); 8151 8152 int Scale = AM.Scale; 8153 switch (VT.getSimpleVT().SimpleTy) { 8154 default: return false; 8155 case MVT::i1: 8156 case MVT::i8: 8157 case MVT::i32: 8158 if (Scale < 0) Scale = -Scale; 8159 if (Scale == 1) 8160 return true; 8161 // r + r << imm 8162 return isPowerOf2_32(Scale & ~1); 8163 case MVT::i16: 8164 case MVT::i64: 8165 // r + r 8166 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 8167 return true; 8168 return false; 8169 8170 case MVT::isVoid: 8171 // Note, we allow "void" uses (basically, uses that aren't loads or 8172 // stores), because arm allows folding a scale into many arithmetic 8173 // operations. This should be made more precise and revisited later. 8174 8175 // Allow r << imm, but the imm has to be a multiple of two. 8176 if (Scale & 1) return false; 8177 return isPowerOf2_32(Scale); 8178 } 8179 break; 8180 } 8181 return true; 8182} 8183 8184/// isLegalICmpImmediate - Return true if the specified immediate is legal 8185/// icmp immediate, that is the target has icmp instructions which can compare 8186/// a register against the immediate without having to materialize the 8187/// immediate into a register. 8188bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const { 8189 if (!Subtarget->isThumb()) 8190 return ARM_AM::getSOImmVal(Imm) != -1; 8191 if (Subtarget->isThumb2()) 8192 return ARM_AM::getT2SOImmVal(Imm) != -1; 8193 return Imm >= 0 && Imm <= 255; 8194} 8195 8196/// isLegalAddImmediate - Return true if the specified immediate is legal 8197/// add immediate, that is the target has add instructions which can add 8198/// a register with the immediate without having to materialize the 8199/// immediate into a register. 8200bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const { 8201 return ARM_AM::getSOImmVal(Imm) != -1; 8202} 8203 8204static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT, 8205 bool isSEXTLoad, SDValue &Base, 8206 SDValue &Offset, bool &isInc, 8207 SelectionDAG &DAG) { 8208 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 8209 return false; 8210 8211 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { 8212 // AddressingMode 3 8213 Base = Ptr->getOperand(0); 8214 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 8215 int RHSC = (int)RHS->getZExtValue(); 8216 if (RHSC < 0 && RHSC > -256) { 8217 assert(Ptr->getOpcode() == ISD::ADD); 8218 isInc = false; 8219 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 8220 return true; 8221 } 8222 } 8223 isInc = (Ptr->getOpcode() == ISD::ADD); 8224 Offset = Ptr->getOperand(1); 8225 return true; 8226 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) { 8227 // AddressingMode 2 8228 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 8229 int RHSC = (int)RHS->getZExtValue(); 8230 if (RHSC < 0 && RHSC > -0x1000) { 8231 assert(Ptr->getOpcode() == ISD::ADD); 8232 isInc = false; 8233 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 8234 Base = Ptr->getOperand(0); 8235 return true; 8236 } 8237 } 8238 8239 if (Ptr->getOpcode() == ISD::ADD) { 8240 isInc = true; 8241 ARM_AM::ShiftOpc ShOpcVal= 8242 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode()); 8243 if (ShOpcVal != ARM_AM::no_shift) { 8244 Base = Ptr->getOperand(1); 8245 Offset = Ptr->getOperand(0); 8246 } else { 8247 Base = Ptr->getOperand(0); 8248 Offset = Ptr->getOperand(1); 8249 } 8250 return true; 8251 } 8252 8253 isInc = (Ptr->getOpcode() == ISD::ADD); 8254 Base = Ptr->getOperand(0); 8255 Offset = Ptr->getOperand(1); 8256 return true; 8257 } 8258 8259 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store. 8260 return false; 8261} 8262 8263static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT, 8264 bool isSEXTLoad, SDValue &Base, 8265 SDValue &Offset, bool &isInc, 8266 SelectionDAG &DAG) { 8267 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 8268 return false; 8269 8270 Base = Ptr->getOperand(0); 8271 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 8272 int RHSC = (int)RHS->getZExtValue(); 8273 if (RHSC < 0 && RHSC > -0x100) { // 8 bits. 8274 assert(Ptr->getOpcode() == ISD::ADD); 8275 isInc = false; 8276 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 8277 return true; 8278 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero. 8279 isInc = Ptr->getOpcode() == ISD::ADD; 8280 Offset = DAG.getConstant(RHSC, RHS->getValueType(0)); 8281 return true; 8282 } 8283 } 8284 8285 return false; 8286} 8287 8288/// getPreIndexedAddressParts - returns true by value, base pointer and 8289/// offset pointer and addressing mode by reference if the node's address 8290/// can be legally represented as pre-indexed load / store address. 8291bool 8292ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 8293 SDValue &Offset, 8294 ISD::MemIndexedMode &AM, 8295 SelectionDAG &DAG) const { 8296 if (Subtarget->isThumb1Only()) 8297 return false; 8298 8299 EVT VT; 8300 SDValue Ptr; 8301 bool isSEXTLoad = false; 8302 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 8303 Ptr = LD->getBasePtr(); 8304 VT = LD->getMemoryVT(); 8305 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 8306 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 8307 Ptr = ST->getBasePtr(); 8308 VT = ST->getMemoryVT(); 8309 } else 8310 return false; 8311 8312 bool isInc; 8313 bool isLegal = false; 8314 if (Subtarget->isThumb2()) 8315 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, 8316 Offset, isInc, DAG); 8317 else 8318 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, 8319 Offset, isInc, DAG); 8320 if (!isLegal) 8321 return false; 8322 8323 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC; 8324 return true; 8325} 8326 8327/// getPostIndexedAddressParts - returns true by value, base pointer and 8328/// offset pointer and addressing mode by reference if this node can be 8329/// combined with a load / store to form a post-indexed load / store. 8330bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 8331 SDValue &Base, 8332 SDValue &Offset, 8333 ISD::MemIndexedMode &AM, 8334 SelectionDAG &DAG) const { 8335 if (Subtarget->isThumb1Only()) 8336 return false; 8337 8338 EVT VT; 8339 SDValue Ptr; 8340 bool isSEXTLoad = false; 8341 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 8342 VT = LD->getMemoryVT(); 8343 Ptr = LD->getBasePtr(); 8344 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 8345 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 8346 VT = ST->getMemoryVT(); 8347 Ptr = ST->getBasePtr(); 8348 } else 8349 return false; 8350 8351 bool isInc; 8352 bool isLegal = false; 8353 if (Subtarget->isThumb2()) 8354 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 8355 isInc, DAG); 8356 else 8357 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 8358 isInc, DAG); 8359 if (!isLegal) 8360 return false; 8361 8362 if (Ptr != Base) { 8363 // Swap base ptr and offset to catch more post-index load / store when 8364 // it's legal. In Thumb2 mode, offset must be an immediate. 8365 if (Ptr == Offset && Op->getOpcode() == ISD::ADD && 8366 !Subtarget->isThumb2()) 8367 std::swap(Base, Offset); 8368 8369 // Post-indexed load / store update the base pointer. 8370 if (Ptr != Base) 8371 return false; 8372 } 8373 8374 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; 8375 return true; 8376} 8377 8378void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 8379 const APInt &Mask, 8380 APInt &KnownZero, 8381 APInt &KnownOne, 8382 const SelectionDAG &DAG, 8383 unsigned Depth) const { 8384 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 8385 switch (Op.getOpcode()) { 8386 default: break; 8387 case ARMISD::CMOV: { 8388 // Bits are known zero/one if known on the LHS and RHS. 8389 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 8390 if (KnownZero == 0 && KnownOne == 0) return; 8391 8392 APInt KnownZeroRHS, KnownOneRHS; 8393 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, 8394 KnownZeroRHS, KnownOneRHS, Depth+1); 8395 KnownZero &= KnownZeroRHS; 8396 KnownOne &= KnownOneRHS; 8397 return; 8398 } 8399 } 8400} 8401 8402//===----------------------------------------------------------------------===// 8403// ARM Inline Assembly Support 8404//===----------------------------------------------------------------------===// 8405 8406bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const { 8407 // Looking for "rev" which is V6+. 8408 if (!Subtarget->hasV6Ops()) 8409 return false; 8410 8411 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 8412 std::string AsmStr = IA->getAsmString(); 8413 SmallVector<StringRef, 4> AsmPieces; 8414 SplitString(AsmStr, AsmPieces, ";\n"); 8415 8416 switch (AsmPieces.size()) { 8417 default: return false; 8418 case 1: 8419 AsmStr = AsmPieces[0]; 8420 AsmPieces.clear(); 8421 SplitString(AsmStr, AsmPieces, " \t,"); 8422 8423 // rev $0, $1 8424 if (AsmPieces.size() == 3 && 8425 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" && 8426 IA->getConstraintString().compare(0, 4, "=l,l") == 0) { 8427 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 8428 if (Ty && Ty->getBitWidth() == 32) 8429 return IntrinsicLowering::LowerToByteSwap(CI); 8430 } 8431 break; 8432 } 8433 8434 return false; 8435} 8436 8437/// getConstraintType - Given a constraint letter, return the type of 8438/// constraint it is for this target. 8439ARMTargetLowering::ConstraintType 8440ARMTargetLowering::getConstraintType(const std::string &Constraint) const { 8441 if (Constraint.size() == 1) { 8442 switch (Constraint[0]) { 8443 default: break; 8444 case 'l': return C_RegisterClass; 8445 case 'w': return C_RegisterClass; 8446 case 'h': return C_RegisterClass; 8447 case 'x': return C_RegisterClass; 8448 case 't': return C_RegisterClass; 8449 case 'j': return C_Other; // Constant for movw. 8450 // An address with a single base register. Due to the way we 8451 // currently handle addresses it is the same as an 'r' memory constraint. 8452 case 'Q': return C_Memory; 8453 } 8454 } else if (Constraint.size() == 2) { 8455 switch (Constraint[0]) { 8456 default: break; 8457 // All 'U+' constraints are addresses. 8458 case 'U': return C_Memory; 8459 } 8460 } 8461 return TargetLowering::getConstraintType(Constraint); 8462} 8463 8464/// Examine constraint type and operand type and determine a weight value. 8465/// This object must already have been set up with the operand type 8466/// and the current alternative constraint selected. 8467TargetLowering::ConstraintWeight 8468ARMTargetLowering::getSingleConstraintMatchWeight( 8469 AsmOperandInfo &info, const char *constraint) const { 8470 ConstraintWeight weight = CW_Invalid; 8471 Value *CallOperandVal = info.CallOperandVal; 8472 // If we don't have a value, we can't do a match, 8473 // but allow it at the lowest weight. 8474 if (CallOperandVal == NULL) 8475 return CW_Default; 8476 Type *type = CallOperandVal->getType(); 8477 // Look at the constraint type. 8478 switch (*constraint) { 8479 default: 8480 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 8481 break; 8482 case 'l': 8483 if (type->isIntegerTy()) { 8484 if (Subtarget->isThumb()) 8485 weight = CW_SpecificReg; 8486 else 8487 weight = CW_Register; 8488 } 8489 break; 8490 case 'w': 8491 if (type->isFloatingPointTy()) 8492 weight = CW_Register; 8493 break; 8494 } 8495 return weight; 8496} 8497 8498typedef std::pair<unsigned, const TargetRegisterClass*> RCPair; 8499RCPair 8500ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 8501 EVT VT) const { 8502 if (Constraint.size() == 1) { 8503 // GCC ARM Constraint Letters 8504 switch (Constraint[0]) { 8505 case 'l': // Low regs or general regs. 8506 if (Subtarget->isThumb()) 8507 return RCPair(0U, ARM::tGPRRegisterClass); 8508 else 8509 return RCPair(0U, ARM::GPRRegisterClass); 8510 case 'h': // High regs or no regs. 8511 if (Subtarget->isThumb()) 8512 return RCPair(0U, ARM::hGPRRegisterClass); 8513 break; 8514 case 'r': 8515 return RCPair(0U, ARM::GPRRegisterClass); 8516 case 'w': 8517 if (VT == MVT::f32) 8518 return RCPair(0U, ARM::SPRRegisterClass); 8519 if (VT.getSizeInBits() == 64) 8520 return RCPair(0U, ARM::DPRRegisterClass); 8521 if (VT.getSizeInBits() == 128) 8522 return RCPair(0U, ARM::QPRRegisterClass); 8523 break; 8524 case 'x': 8525 if (VT == MVT::f32) 8526 return RCPair(0U, ARM::SPR_8RegisterClass); 8527 if (VT.getSizeInBits() == 64) 8528 return RCPair(0U, ARM::DPR_8RegisterClass); 8529 if (VT.getSizeInBits() == 128) 8530 return RCPair(0U, ARM::QPR_8RegisterClass); 8531 break; 8532 case 't': 8533 if (VT == MVT::f32) 8534 return RCPair(0U, ARM::SPRRegisterClass); 8535 break; 8536 } 8537 } 8538 if (StringRef("{cc}").equals_lower(Constraint)) 8539 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass); 8540 8541 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 8542} 8543 8544/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 8545/// vector. If it is invalid, don't add anything to Ops. 8546void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 8547 std::string &Constraint, 8548 std::vector<SDValue>&Ops, 8549 SelectionDAG &DAG) const { 8550 SDValue Result(0, 0); 8551 8552 // Currently only support length 1 constraints. 8553 if (Constraint.length() != 1) return; 8554 8555 char ConstraintLetter = Constraint[0]; 8556 switch (ConstraintLetter) { 8557 default: break; 8558 case 'j': 8559 case 'I': case 'J': case 'K': case 'L': 8560 case 'M': case 'N': case 'O': 8561 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 8562 if (!C) 8563 return; 8564 8565 int64_t CVal64 = C->getSExtValue(); 8566 int CVal = (int) CVal64; 8567 // None of these constraints allow values larger than 32 bits. Check 8568 // that the value fits in an int. 8569 if (CVal != CVal64) 8570 return; 8571 8572 switch (ConstraintLetter) { 8573 case 'j': 8574 // Constant suitable for movw, must be between 0 and 8575 // 65535. 8576 if (Subtarget->hasV6T2Ops()) 8577 if (CVal >= 0 && CVal <= 65535) 8578 break; 8579 return; 8580 case 'I': 8581 if (Subtarget->isThumb1Only()) { 8582 // This must be a constant between 0 and 255, for ADD 8583 // immediates. 8584 if (CVal >= 0 && CVal <= 255) 8585 break; 8586 } else if (Subtarget->isThumb2()) { 8587 // A constant that can be used as an immediate value in a 8588 // data-processing instruction. 8589 if (ARM_AM::getT2SOImmVal(CVal) != -1) 8590 break; 8591 } else { 8592 // A constant that can be used as an immediate value in a 8593 // data-processing instruction. 8594 if (ARM_AM::getSOImmVal(CVal) != -1) 8595 break; 8596 } 8597 return; 8598 8599 case 'J': 8600 if (Subtarget->isThumb()) { // FIXME thumb2 8601 // This must be a constant between -255 and -1, for negated ADD 8602 // immediates. This can be used in GCC with an "n" modifier that 8603 // prints the negated value, for use with SUB instructions. It is 8604 // not useful otherwise but is implemented for compatibility. 8605 if (CVal >= -255 && CVal <= -1) 8606 break; 8607 } else { 8608 // This must be a constant between -4095 and 4095. It is not clear 8609 // what this constraint is intended for. Implemented for 8610 // compatibility with GCC. 8611 if (CVal >= -4095 && CVal <= 4095) 8612 break; 8613 } 8614 return; 8615 8616 case 'K': 8617 if (Subtarget->isThumb1Only()) { 8618 // A 32-bit value where only one byte has a nonzero value. Exclude 8619 // zero to match GCC. This constraint is used by GCC internally for 8620 // constants that can be loaded with a move/shift combination. 8621 // It is not useful otherwise but is implemented for compatibility. 8622 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal)) 8623 break; 8624 } else if (Subtarget->isThumb2()) { 8625 // A constant whose bitwise inverse can be used as an immediate 8626 // value in a data-processing instruction. This can be used in GCC 8627 // with a "B" modifier that prints the inverted value, for use with 8628 // BIC and MVN instructions. It is not useful otherwise but is 8629 // implemented for compatibility. 8630 if (ARM_AM::getT2SOImmVal(~CVal) != -1) 8631 break; 8632 } else { 8633 // A constant whose bitwise inverse can be used as an immediate 8634 // value in a data-processing instruction. This can be used in GCC 8635 // with a "B" modifier that prints the inverted value, for use with 8636 // BIC and MVN instructions. It is not useful otherwise but is 8637 // implemented for compatibility. 8638 if (ARM_AM::getSOImmVal(~CVal) != -1) 8639 break; 8640 } 8641 return; 8642 8643 case 'L': 8644 if (Subtarget->isThumb1Only()) { 8645 // This must be a constant between -7 and 7, 8646 // for 3-operand ADD/SUB immediate instructions. 8647 if (CVal >= -7 && CVal < 7) 8648 break; 8649 } else if (Subtarget->isThumb2()) { 8650 // A constant whose negation can be used as an immediate value in a 8651 // data-processing instruction. This can be used in GCC with an "n" 8652 // modifier that prints the negated value, for use with SUB 8653 // instructions. It is not useful otherwise but is implemented for 8654 // compatibility. 8655 if (ARM_AM::getT2SOImmVal(-CVal) != -1) 8656 break; 8657 } else { 8658 // A constant whose negation can be used as an immediate value in a 8659 // data-processing instruction. This can be used in GCC with an "n" 8660 // modifier that prints the negated value, for use with SUB 8661 // instructions. It is not useful otherwise but is implemented for 8662 // compatibility. 8663 if (ARM_AM::getSOImmVal(-CVal) != -1) 8664 break; 8665 } 8666 return; 8667 8668 case 'M': 8669 if (Subtarget->isThumb()) { // FIXME thumb2 8670 // This must be a multiple of 4 between 0 and 1020, for 8671 // ADD sp + immediate. 8672 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0)) 8673 break; 8674 } else { 8675 // A power of two or a constant between 0 and 32. This is used in 8676 // GCC for the shift amount on shifted register operands, but it is 8677 // useful in general for any shift amounts. 8678 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0)) 8679 break; 8680 } 8681 return; 8682 8683 case 'N': 8684 if (Subtarget->isThumb()) { // FIXME thumb2 8685 // This must be a constant between 0 and 31, for shift amounts. 8686 if (CVal >= 0 && CVal <= 31) 8687 break; 8688 } 8689 return; 8690 8691 case 'O': 8692 if (Subtarget->isThumb()) { // FIXME thumb2 8693 // This must be a multiple of 4 between -508 and 508, for 8694 // ADD/SUB sp = sp + immediate. 8695 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0)) 8696 break; 8697 } 8698 return; 8699 } 8700 Result = DAG.getTargetConstant(CVal, Op.getValueType()); 8701 break; 8702 } 8703 8704 if (Result.getNode()) { 8705 Ops.push_back(Result); 8706 return; 8707 } 8708 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 8709} 8710 8711bool 8712ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 8713 // The ARM target isn't yet aware of offsets. 8714 return false; 8715} 8716 8717bool ARM::isBitFieldInvertedMask(unsigned v) { 8718 if (v == 0xffffffff) 8719 return 0; 8720 // there can be 1's on either or both "outsides", all the "inside" 8721 // bits must be 0's 8722 unsigned int lsb = 0, msb = 31; 8723 while (v & (1 << msb)) --msb; 8724 while (v & (1 << lsb)) ++lsb; 8725 for (unsigned int i = lsb; i <= msb; ++i) { 8726 if (v & (1 << i)) 8727 return 0; 8728 } 8729 return 1; 8730} 8731 8732/// isFPImmLegal - Returns true if the target can instruction select the 8733/// specified FP immediate natively. If false, the legalizer will 8734/// materialize the FP immediate as a load from a constant pool. 8735bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 8736 if (!Subtarget->hasVFP3()) 8737 return false; 8738 if (VT == MVT::f32) 8739 return ARM_AM::getFP32Imm(Imm) != -1; 8740 if (VT == MVT::f64) 8741 return ARM_AM::getFP64Imm(Imm) != -1; 8742 return false; 8743} 8744 8745/// getTgtMemIntrinsic - Represent NEON load and store intrinsics as 8746/// MemIntrinsicNodes. The associated MachineMemOperands record the alignment 8747/// specified in the intrinsic calls. 8748bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, 8749 const CallInst &I, 8750 unsigned Intrinsic) const { 8751 switch (Intrinsic) { 8752 case Intrinsic::arm_neon_vld1: 8753 case Intrinsic::arm_neon_vld2: 8754 case Intrinsic::arm_neon_vld3: 8755 case Intrinsic::arm_neon_vld4: 8756 case Intrinsic::arm_neon_vld2lane: 8757 case Intrinsic::arm_neon_vld3lane: 8758 case Intrinsic::arm_neon_vld4lane: { 8759 Info.opc = ISD::INTRINSIC_W_CHAIN; 8760 // Conservatively set memVT to the entire set of vectors loaded. 8761 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8; 8762 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); 8763 Info.ptrVal = I.getArgOperand(0); 8764 Info.offset = 0; 8765 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1); 8766 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue(); 8767 Info.vol = false; // volatile loads with NEON intrinsics not supported 8768 Info.readMem = true; 8769 Info.writeMem = false; 8770 return true; 8771 } 8772 case Intrinsic::arm_neon_vst1: 8773 case Intrinsic::arm_neon_vst2: 8774 case Intrinsic::arm_neon_vst3: 8775 case Intrinsic::arm_neon_vst4: 8776 case Intrinsic::arm_neon_vst2lane: 8777 case Intrinsic::arm_neon_vst3lane: 8778 case Intrinsic::arm_neon_vst4lane: { 8779 Info.opc = ISD::INTRINSIC_VOID; 8780 // Conservatively set memVT to the entire set of vectors stored. 8781 unsigned NumElts = 0; 8782 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) { 8783 Type *ArgTy = I.getArgOperand(ArgI)->getType(); 8784 if (!ArgTy->isVectorTy()) 8785 break; 8786 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8; 8787 } 8788 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); 8789 Info.ptrVal = I.getArgOperand(0); 8790 Info.offset = 0; 8791 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1); 8792 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue(); 8793 Info.vol = false; // volatile stores with NEON intrinsics not supported 8794 Info.readMem = false; 8795 Info.writeMem = true; 8796 return true; 8797 } 8798 case Intrinsic::arm_strexd: { 8799 Info.opc = ISD::INTRINSIC_W_CHAIN; 8800 Info.memVT = MVT::i64; 8801 Info.ptrVal = I.getArgOperand(2); 8802 Info.offset = 0; 8803 Info.align = 8; 8804 Info.vol = true; 8805 Info.readMem = false; 8806 Info.writeMem = true; 8807 return true; 8808 } 8809 case Intrinsic::arm_ldrexd: { 8810 Info.opc = ISD::INTRINSIC_W_CHAIN; 8811 Info.memVT = MVT::i64; 8812 Info.ptrVal = I.getArgOperand(0); 8813 Info.offset = 0; 8814 Info.align = 8; 8815 Info.vol = true; 8816 Info.readMem = true; 8817 Info.writeMem = false; 8818 return true; 8819 } 8820 default: 8821 break; 8822 } 8823 8824 return false; 8825} 8826