ARMISelLowering.cpp revision ae94e594164b193236002516970aeec4c4574768
1//===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "ARM.h" 16#include "ARMAddressingModes.h" 17#include "ARMConstantPoolValue.h" 18#include "ARMISelLowering.h" 19#include "ARMMachineFunctionInfo.h" 20#include "ARMRegisterInfo.h" 21#include "ARMSubtarget.h" 22#include "ARMTargetMachine.h" 23#include "llvm/CallingConv.h" 24#include "llvm/Constants.h" 25#include "llvm/Instruction.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/GlobalValue.h" 28#include "llvm/CodeGen/MachineBasicBlock.h" 29#include "llvm/CodeGen/MachineFrameInfo.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineInstrBuilder.h" 32#include "llvm/CodeGen/MachineRegisterInfo.h" 33#include "llvm/CodeGen/SelectionDAG.h" 34#include "llvm/Target/TargetOptions.h" 35#include "llvm/ADT/VectorExtras.h" 36#include "llvm/Support/MathExtras.h" 37using namespace llvm; 38 39ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) 40 : TargetLowering(TM), ARMPCLabelIndex(0) { 41 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 42 43 if (Subtarget->isTargetDarwin()) { 44 // Uses VFP for Thumb libfuncs if available. 45 if (Subtarget->isThumb() && Subtarget->hasVFP2()) { 46 // Single-precision floating-point arithmetic. 47 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp"); 48 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp"); 49 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp"); 50 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp"); 51 52 // Double-precision floating-point arithmetic. 53 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp"); 54 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp"); 55 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp"); 56 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp"); 57 58 // Single-precision comparisons. 59 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp"); 60 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp"); 61 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp"); 62 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp"); 63 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp"); 64 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp"); 65 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp"); 66 setLibcallName(RTLIB::O_F32, "__unordsf2vfp"); 67 68 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 69 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE); 70 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 71 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 72 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 73 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 74 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 75 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 76 77 // Double-precision comparisons. 78 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp"); 79 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp"); 80 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp"); 81 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp"); 82 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp"); 83 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp"); 84 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp"); 85 setLibcallName(RTLIB::O_F64, "__unorddf2vfp"); 86 87 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 88 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE); 89 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 90 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 91 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 92 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 93 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 94 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 95 96 // Floating-point to integer conversions. 97 // i64 conversions are done via library routines even when generating VFP 98 // instructions, so use the same ones. 99 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp"); 100 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp"); 101 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp"); 102 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp"); 103 104 // Conversions between floating types. 105 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp"); 106 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp"); 107 108 // Integer to floating-point conversions. 109 // i64 conversions are done via library routines even when generating VFP 110 // instructions, so use the same ones. 111 // FIXME: There appears to be some naming inconsistency in ARM libgcc: e.g. 112 // __floatunsidf vs. __floatunssidfvfp. 113 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp"); 114 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp"); 115 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp"); 116 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp"); 117 } 118 } 119 120 addRegisterClass(MVT::i32, ARM::GPRRegisterClass); 121 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) { 122 addRegisterClass(MVT::f32, ARM::SPRRegisterClass); 123 addRegisterClass(MVT::f64, ARM::DPRRegisterClass); 124 125 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 126 } 127 computeRegisterProperties(); 128 129 // ARM does not have f32 extending load. 130 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 131 132 // ARM does not have i1 sign extending load. 133 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 134 135 // ARM supports all 4 flavors of integer indexed load / store. 136 for (unsigned im = (unsigned)ISD::PRE_INC; 137 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { 138 setIndexedLoadAction(im, MVT::i1, Legal); 139 setIndexedLoadAction(im, MVT::i8, Legal); 140 setIndexedLoadAction(im, MVT::i16, Legal); 141 setIndexedLoadAction(im, MVT::i32, Legal); 142 setIndexedStoreAction(im, MVT::i1, Legal); 143 setIndexedStoreAction(im, MVT::i8, Legal); 144 setIndexedStoreAction(im, MVT::i16, Legal); 145 setIndexedStoreAction(im, MVT::i32, Legal); 146 } 147 148 // i64 operation support. 149 if (Subtarget->isThumb()) { 150 setOperationAction(ISD::MUL, MVT::i64, Expand); 151 setOperationAction(ISD::MULHU, MVT::i32, Expand); 152 setOperationAction(ISD::MULHS, MVT::i32, Expand); 153 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 154 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 155 } else { 156 setOperationAction(ISD::MUL, MVT::i64, Expand); 157 setOperationAction(ISD::MULHU, MVT::i32, Expand); 158 if (!Subtarget->hasV6Ops()) 159 setOperationAction(ISD::MULHS, MVT::i32, Expand); 160 } 161 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 162 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 163 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 164 setOperationAction(ISD::SRL, MVT::i64, Custom); 165 setOperationAction(ISD::SRA, MVT::i64, Custom); 166 167 // ARM does not have ROTL. 168 setOperationAction(ISD::ROTL, MVT::i32, Expand); 169 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 170 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 171 if (!Subtarget->hasV5TOps() || Subtarget->isThumb()) 172 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 173 174 // Only ARMv6 has BSWAP. 175 if (!Subtarget->hasV6Ops()) 176 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 177 178 // These are expanded into libcalls. 179 setOperationAction(ISD::SDIV, MVT::i32, Expand); 180 setOperationAction(ISD::UDIV, MVT::i32, Expand); 181 setOperationAction(ISD::SREM, MVT::i32, Expand); 182 setOperationAction(ISD::UREM, MVT::i32, Expand); 183 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 184 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 185 186 // Support label based line numbers. 187 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); 188 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 189 190 setOperationAction(ISD::RET, MVT::Other, Custom); 191 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 192 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 193 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom); 194 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 195 196 // Use the default implementation. 197 setOperationAction(ISD::VASTART , MVT::Other, Custom); 198 setOperationAction(ISD::VAARG , MVT::Other, Expand); 199 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 200 setOperationAction(ISD::VAEND , MVT::Other, Expand); 201 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 202 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 203 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand); 204 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand); 205 206 if (!Subtarget->hasV6Ops()) { 207 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 208 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 209 } 210 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 211 212 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) 213 // Turn f64->i64 into FMRRD, i64 -> f64 to FMDRR iff target supports vfp2. 214 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom); 215 216 // We want to custom lower some of our intrinsics. 217 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 218 219 setOperationAction(ISD::SETCC , MVT::i32, Expand); 220 setOperationAction(ISD::SETCC , MVT::f32, Expand); 221 setOperationAction(ISD::SETCC , MVT::f64, Expand); 222 setOperationAction(ISD::SELECT , MVT::i32, Expand); 223 setOperationAction(ISD::SELECT , MVT::f32, Expand); 224 setOperationAction(ISD::SELECT , MVT::f64, Expand); 225 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 226 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 227 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 228 229 setOperationAction(ISD::BRCOND , MVT::Other, Expand); 230 setOperationAction(ISD::BR_CC , MVT::i32, Custom); 231 setOperationAction(ISD::BR_CC , MVT::f32, Custom); 232 setOperationAction(ISD::BR_CC , MVT::f64, Custom); 233 setOperationAction(ISD::BR_JT , MVT::Other, Custom); 234 235 // We don't support sin/cos/fmod/copysign/pow 236 setOperationAction(ISD::FSIN , MVT::f64, Expand); 237 setOperationAction(ISD::FSIN , MVT::f32, Expand); 238 setOperationAction(ISD::FCOS , MVT::f32, Expand); 239 setOperationAction(ISD::FCOS , MVT::f64, Expand); 240 setOperationAction(ISD::FREM , MVT::f64, Expand); 241 setOperationAction(ISD::FREM , MVT::f32, Expand); 242 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) { 243 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 244 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 245 } 246 setOperationAction(ISD::FPOW , MVT::f64, Expand); 247 setOperationAction(ISD::FPOW , MVT::f32, Expand); 248 249 // int <-> fp are custom expanded into bit_convert + ARMISD ops. 250 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) { 251 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 252 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 253 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 254 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 255 } 256 257 // We have target-specific dag combine patterns for the following nodes: 258 // ARMISD::FMRRD - No need to call setTargetDAGCombine 259 260 setStackPointerRegisterToSaveRestore(ARM::SP); 261 setSchedulingPreference(SchedulingForRegPressure); 262 setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10); 263 setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2); 264 265 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type 266} 267 268 269const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { 270 switch (Opcode) { 271 default: return 0; 272 case ARMISD::Wrapper: return "ARMISD::Wrapper"; 273 case ARMISD::WrapperJT: return "ARMISD::WrapperJT"; 274 case ARMISD::CALL: return "ARMISD::CALL"; 275 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED"; 276 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK"; 277 case ARMISD::tCALL: return "ARMISD::tCALL"; 278 case ARMISD::BRCOND: return "ARMISD::BRCOND"; 279 case ARMISD::BR_JT: return "ARMISD::BR_JT"; 280 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; 281 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD"; 282 case ARMISD::CMP: return "ARMISD::CMP"; 283 case ARMISD::CMPNZ: return "ARMISD::CMPNZ"; 284 case ARMISD::CMPFP: return "ARMISD::CMPFP"; 285 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0"; 286 case ARMISD::FMSTAT: return "ARMISD::FMSTAT"; 287 case ARMISD::CMOV: return "ARMISD::CMOV"; 288 case ARMISD::CNEG: return "ARMISD::CNEG"; 289 290 case ARMISD::FTOSI: return "ARMISD::FTOSI"; 291 case ARMISD::FTOUI: return "ARMISD::FTOUI"; 292 case ARMISD::SITOF: return "ARMISD::SITOF"; 293 case ARMISD::UITOF: return "ARMISD::UITOF"; 294 295 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG"; 296 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG"; 297 case ARMISD::RRX: return "ARMISD::RRX"; 298 299 case ARMISD::FMRRD: return "ARMISD::FMRRD"; 300 case ARMISD::FMDRR: return "ARMISD::FMDRR"; 301 302 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER"; 303 } 304} 305 306//===----------------------------------------------------------------------===// 307// Lowering Code 308//===----------------------------------------------------------------------===// 309 310 311/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC 312static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { 313 switch (CC) { 314 default: assert(0 && "Unknown condition code!"); 315 case ISD::SETNE: return ARMCC::NE; 316 case ISD::SETEQ: return ARMCC::EQ; 317 case ISD::SETGT: return ARMCC::GT; 318 case ISD::SETGE: return ARMCC::GE; 319 case ISD::SETLT: return ARMCC::LT; 320 case ISD::SETLE: return ARMCC::LE; 321 case ISD::SETUGT: return ARMCC::HI; 322 case ISD::SETUGE: return ARMCC::HS; 323 case ISD::SETULT: return ARMCC::LO; 324 case ISD::SETULE: return ARMCC::LS; 325 } 326} 327 328/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It 329/// returns true if the operands should be inverted to form the proper 330/// comparison. 331static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, 332 ARMCC::CondCodes &CondCode2) { 333 bool Invert = false; 334 CondCode2 = ARMCC::AL; 335 switch (CC) { 336 default: assert(0 && "Unknown FP condition!"); 337 case ISD::SETEQ: 338 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; 339 case ISD::SETGT: 340 case ISD::SETOGT: CondCode = ARMCC::GT; break; 341 case ISD::SETGE: 342 case ISD::SETOGE: CondCode = ARMCC::GE; break; 343 case ISD::SETOLT: CondCode = ARMCC::MI; break; 344 case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break; 345 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break; 346 case ISD::SETO: CondCode = ARMCC::VC; break; 347 case ISD::SETUO: CondCode = ARMCC::VS; break; 348 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break; 349 case ISD::SETUGT: CondCode = ARMCC::HI; break; 350 case ISD::SETUGE: CondCode = ARMCC::PL; break; 351 case ISD::SETLT: 352 case ISD::SETULT: CondCode = ARMCC::LT; break; 353 case ISD::SETLE: 354 case ISD::SETULE: CondCode = ARMCC::LE; break; 355 case ISD::SETNE: 356 case ISD::SETUNE: CondCode = ARMCC::NE; break; 357 } 358 return Invert; 359} 360 361static void 362HowToPassArgument(MVT ObjectVT, unsigned NumGPRs, 363 unsigned StackOffset, unsigned &NeededGPRs, 364 unsigned &NeededStackSize, unsigned &GPRPad, 365 unsigned &StackPad, ISD::ArgFlagsTy Flags) { 366 NeededStackSize = 0; 367 NeededGPRs = 0; 368 StackPad = 0; 369 GPRPad = 0; 370 unsigned align = Flags.getOrigAlign(); 371 GPRPad = NumGPRs % ((align + 3)/4); 372 StackPad = StackOffset % align; 373 unsigned firstGPR = NumGPRs + GPRPad; 374 switch (ObjectVT.getSimpleVT()) { 375 default: assert(0 && "Unhandled argument type!"); 376 case MVT::i32: 377 case MVT::f32: 378 if (firstGPR < 4) 379 NeededGPRs = 1; 380 else 381 NeededStackSize = 4; 382 break; 383 case MVT::i64: 384 case MVT::f64: 385 if (firstGPR < 3) 386 NeededGPRs = 2; 387 else if (firstGPR == 3) { 388 NeededGPRs = 1; 389 NeededStackSize = 4; 390 } else 391 NeededStackSize = 8; 392 } 393} 394 395/// LowerCALL - Lowering a ISD::CALL node into a callseq_start <- 396/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter 397/// nodes. 398SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { 399 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode()); 400 MVT RetVT = TheCall->getRetValType(0); 401 SDValue Chain = TheCall->getChain(); 402 unsigned CallConv = TheCall->getCallingConv(); 403 assert((CallConv == CallingConv::C || 404 CallConv == CallingConv::Fast) && "unknown calling convention"); 405 SDValue Callee = TheCall->getCallee(); 406 unsigned NumOps = TheCall->getNumArgs(); 407 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 408 unsigned NumGPRs = 0; // GPRs used for parameter passing. 409 410 // Count how many bytes are to be pushed on the stack. 411 unsigned NumBytes = 0; 412 413 // Add up all the space actually used. 414 for (unsigned i = 0; i < NumOps; ++i) { 415 unsigned ObjSize; 416 unsigned ObjGPRs; 417 unsigned StackPad; 418 unsigned GPRPad; 419 MVT ObjectVT = TheCall->getArg(i).getValueType(); 420 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i); 421 HowToPassArgument(ObjectVT, NumGPRs, NumBytes, ObjGPRs, ObjSize, 422 GPRPad, StackPad, Flags); 423 NumBytes += ObjSize + StackPad; 424 NumGPRs += ObjGPRs + GPRPad; 425 } 426 427 // Adjust the stack pointer for the new arguments... 428 // These operations are automatically eliminated by the prolog/epilog pass 429 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 430 431 SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32); 432 433 static const unsigned GPRArgRegs[] = { 434 ARM::R0, ARM::R1, ARM::R2, ARM::R3 435 }; 436 437 NumGPRs = 0; 438 std::vector<std::pair<unsigned, SDValue> > RegsToPass; 439 std::vector<SDValue> MemOpChains; 440 for (unsigned i = 0; i != NumOps; ++i) { 441 SDValue Arg = TheCall->getArg(i); 442 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i); 443 MVT ArgVT = Arg.getValueType(); 444 445 unsigned ObjSize; 446 unsigned ObjGPRs; 447 unsigned GPRPad; 448 unsigned StackPad; 449 HowToPassArgument(ArgVT, NumGPRs, ArgOffset, ObjGPRs, 450 ObjSize, GPRPad, StackPad, Flags); 451 NumGPRs += GPRPad; 452 ArgOffset += StackPad; 453 if (ObjGPRs > 0) { 454 switch (ArgVT.getSimpleVT()) { 455 default: assert(0 && "Unexpected ValueType for argument!"); 456 case MVT::i32: 457 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Arg)); 458 break; 459 case MVT::f32: 460 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], 461 DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg))); 462 break; 463 case MVT::i64: { 464 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg, 465 DAG.getConstant(0, getPointerTy())); 466 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg, 467 DAG.getConstant(1, getPointerTy())); 468 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo)); 469 if (ObjGPRs == 2) 470 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi)); 471 else { 472 SDValue PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType()); 473 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 474 MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0)); 475 } 476 break; 477 } 478 case MVT::f64: { 479 SDValue Cvt = DAG.getNode(ARMISD::FMRRD, 480 DAG.getVTList(MVT::i32, MVT::i32), 481 &Arg, 1); 482 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Cvt)); 483 if (ObjGPRs == 2) 484 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], 485 Cvt.getValue(1))); 486 else { 487 SDValue PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType()); 488 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 489 MemOpChains.push_back(DAG.getStore(Chain, Cvt.getValue(1), PtrOff, 490 NULL, 0)); 491 } 492 break; 493 } 494 } 495 } else { 496 assert(ObjSize != 0); 497 SDValue PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 498 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 499 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 500 } 501 502 NumGPRs += ObjGPRs; 503 ArgOffset += ObjSize; 504 } 505 506 if (!MemOpChains.empty()) 507 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 508 &MemOpChains[0], MemOpChains.size()); 509 510 // Build a sequence of copy-to-reg nodes chained together with token chain 511 // and flag operands which copy the outgoing args into the appropriate regs. 512 SDValue InFlag; 513 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 514 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 515 InFlag); 516 InFlag = Chain.getValue(1); 517 } 518 519 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 520 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 521 // node so that legalize doesn't hack it. 522 bool isDirect = false; 523 bool isARMFunc = false; 524 bool isLocalARMFunc = false; 525 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 526 GlobalValue *GV = G->getGlobal(); 527 isDirect = true; 528 bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() || 529 GV->hasLinkOnceLinkage()); 530 bool isStub = (isExt && Subtarget->isTargetDarwin()) && 531 getTargetMachine().getRelocationModel() != Reloc::Static; 532 isARMFunc = !Subtarget->isThumb() || isStub; 533 // ARM call to a local ARM function is predicable. 534 isLocalARMFunc = !Subtarget->isThumb() && !isExt; 535 // tBX takes a register source operand. 536 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) { 537 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex, 538 ARMCP::CPStub, 4); 539 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2); 540 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 541 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0); 542 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 543 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel); 544 } else 545 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy()); 546 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 547 isDirect = true; 548 bool isStub = Subtarget->isTargetDarwin() && 549 getTargetMachine().getRelocationModel() != Reloc::Static; 550 isARMFunc = !Subtarget->isThumb() || isStub; 551 // tBX takes a register source operand. 552 const char *Sym = S->getSymbol(); 553 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) { 554 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex, 555 ARMCP::CPStub, 4); 556 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2); 557 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 558 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0); 559 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 560 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel); 561 } else 562 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy()); 563 } 564 565 // FIXME: handle tail calls differently. 566 unsigned CallOpc; 567 if (Subtarget->isThumb()) { 568 if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc)) 569 CallOpc = ARMISD::CALL_NOLINK; 570 else 571 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL; 572 } else { 573 CallOpc = (isDirect || Subtarget->hasV5TOps()) 574 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL) 575 : ARMISD::CALL_NOLINK; 576 } 577 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) { 578 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK 579 Chain = DAG.getCopyToReg(Chain, ARM::LR, 580 DAG.getNode(ISD::UNDEF, MVT::i32), InFlag); 581 InFlag = Chain.getValue(1); 582 } 583 584 std::vector<SDValue> Ops; 585 Ops.push_back(Chain); 586 Ops.push_back(Callee); 587 588 // Add argument registers to the end of the list so that they are known live 589 // into the call. 590 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 591 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 592 RegsToPass[i].second.getValueType())); 593 594 if (InFlag.getNode()) 595 Ops.push_back(InFlag); 596 // Returns a chain and a flag for retval copy to use. 597 Chain = DAG.getNode(CallOpc, DAG.getVTList(MVT::Other, MVT::Flag), 598 &Ops[0], Ops.size()); 599 InFlag = Chain.getValue(1); 600 601 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 602 DAG.getIntPtrConstant(0, true), InFlag); 603 if (RetVT != MVT::Other) 604 InFlag = Chain.getValue(1); 605 606 std::vector<SDValue> ResultVals; 607 608 // If the call has results, copy the values out of the ret val registers. 609 switch (RetVT.getSimpleVT()) { 610 default: assert(0 && "Unexpected ret value!"); 611 case MVT::Other: 612 break; 613 case MVT::i32: 614 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1); 615 ResultVals.push_back(Chain.getValue(0)); 616 if (TheCall->getNumRetVals() > 1 && 617 TheCall->getRetValType(1) == MVT::i32) { 618 // Returns a i64 value. 619 Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32, 620 Chain.getValue(2)).getValue(1); 621 ResultVals.push_back(Chain.getValue(0)); 622 } 623 break; 624 case MVT::f32: 625 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1); 626 ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f32, 627 Chain.getValue(0))); 628 break; 629 case MVT::f64: { 630 SDValue Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag); 631 SDValue Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2)); 632 ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi)); 633 break; 634 } 635 } 636 637 if (ResultVals.empty()) 638 return Chain; 639 640 ResultVals.push_back(Chain); 641 SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size()); 642 return Res.getValue(Op.getResNo()); 643} 644 645static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) { 646 SDValue Copy; 647 SDValue Chain = Op.getOperand(0); 648 switch(Op.getNumOperands()) { 649 default: 650 assert(0 && "Do not know how to return this many arguments!"); 651 abort(); 652 case 1: { 653 SDValue LR = DAG.getRegister(ARM::LR, MVT::i32); 654 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain); 655 } 656 case 3: 657 Op = Op.getOperand(1); 658 if (Op.getValueType() == MVT::f32) { 659 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 660 } else if (Op.getValueType() == MVT::f64) { 661 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is 662 // available. 663 Op = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), &Op,1); 664 SDValue Sign = DAG.getConstant(0, MVT::i32); 665 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op, Sign, 666 Op.getValue(1), Sign); 667 } 668 Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDValue()); 669 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) 670 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0); 671 break; 672 case 5: 673 Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDValue()); 674 Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1)); 675 // If we haven't noted the R0+R1 are live out, do so now. 676 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 677 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0); 678 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R1); 679 } 680 break; 681 case 9: // i128 -> 4 regs 682 Copy = DAG.getCopyToReg(Chain, ARM::R3, Op.getOperand(7), SDValue()); 683 Copy = DAG.getCopyToReg(Copy , ARM::R2, Op.getOperand(5), Copy.getValue(1)); 684 Copy = DAG.getCopyToReg(Copy , ARM::R1, Op.getOperand(3), Copy.getValue(1)); 685 Copy = DAG.getCopyToReg(Copy , ARM::R0, Op.getOperand(1), Copy.getValue(1)); 686 // If we haven't noted the R0+R1 are live out, do so now. 687 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 688 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0); 689 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R1); 690 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R2); 691 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R3); 692 } 693 break; 694 695 } 696 697 //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag 698 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 699} 700 701// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 702// their target countpart wrapped in the ARMISD::Wrapper node. Suppose N is 703// one of the above mentioned nodes. It has to be wrapped because otherwise 704// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 705// be used to form addressing mode. These wrapped nodes will be selected 706// into MOVi. 707static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) { 708 MVT PtrVT = Op.getValueType(); 709 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 710 SDValue Res; 711 if (CP->isMachineConstantPoolEntry()) 712 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, 713 CP->getAlignment()); 714 else 715 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, 716 CP->getAlignment()); 717 return DAG.getNode(ARMISD::Wrapper, MVT::i32, Res); 718} 719 720// Lower ISD::GlobalTLSAddress using the "general dynamic" model 721SDValue 722ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 723 SelectionDAG &DAG) { 724 MVT PtrVT = getPointerTy(); 725 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 726 ARMConstantPoolValue *CPV = 727 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue, 728 PCAdj, "tlsgd", true); 729 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 2); 730 Argument = DAG.getNode(ARMISD::Wrapper, MVT::i32, Argument); 731 Argument = DAG.getLoad(PtrVT, DAG.getEntryNode(), Argument, NULL, 0); 732 SDValue Chain = Argument.getValue(1); 733 734 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 735 Argument = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Argument, PICLabel); 736 737 // call __tls_get_addr. 738 ArgListTy Args; 739 ArgListEntry Entry; 740 Entry.Node = Argument; 741 Entry.Ty = (const Type *) Type::Int32Ty; 742 Args.push_back(Entry); 743 std::pair<SDValue, SDValue> CallResult = 744 LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false, false, 745 CallingConv::C, false, 746 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG); 747 return CallResult.first; 748} 749 750// Lower ISD::GlobalTLSAddress using the "initial exec" or 751// "local exec" model. 752SDValue 753ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, 754 SelectionDAG &DAG) { 755 GlobalValue *GV = GA->getGlobal(); 756 SDValue Offset; 757 SDValue Chain = DAG.getEntryNode(); 758 MVT PtrVT = getPointerTy(); 759 // Get the Thread Pointer 760 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, PtrVT); 761 762 if (GV->isDeclaration()){ 763 // initial exec model 764 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 765 ARMConstantPoolValue *CPV = 766 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue, 767 PCAdj, "gottpoff", true); 768 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2); 769 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset); 770 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); 771 Chain = Offset.getValue(1); 772 773 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 774 Offset = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Offset, PICLabel); 775 776 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); 777 } else { 778 // local exec model 779 ARMConstantPoolValue *CPV = 780 new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff"); 781 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2); 782 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset); 783 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); 784 } 785 786 // The address of the thread local variable is the add of the thread 787 // pointer with the offset of the variable. 788 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset); 789} 790 791SDValue 792ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { 793 // TODO: implement the "local dynamic" model 794 assert(Subtarget->isTargetELF() && 795 "TLS not implemented for non-ELF targets"); 796 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 797 // If the relocation model is PIC, use the "General Dynamic" TLS Model, 798 // otherwise use the "Local Exec" TLS Model 799 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) 800 return LowerToTLSGeneralDynamicModel(GA, DAG); 801 else 802 return LowerToTLSExecModels(GA, DAG); 803} 804 805SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, 806 SelectionDAG &DAG) { 807 MVT PtrVT = getPointerTy(); 808 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 809 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 810 if (RelocM == Reloc::PIC_) { 811 bool UseGOTOFF = GV->hasInternalLinkage() || GV->hasHiddenVisibility(); 812 ARMConstantPoolValue *CPV = 813 new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT"); 814 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); 815 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 816 SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 817 SDValue Chain = Result.getValue(1); 818 SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT); 819 Result = DAG.getNode(ISD::ADD, PtrVT, Result, GOT); 820 if (!UseGOTOFF) 821 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0); 822 return Result; 823 } else { 824 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2); 825 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 826 return DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 827 } 828} 829 830/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol 831/// even in non-static mode. 832static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) { 833 // If symbol visibility is hidden, the extra load is not needed if 834 // the symbol is definitely defined in the current translation unit. 835 bool isDecl = GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode(); 836 if (GV->hasHiddenVisibility() && (!isDecl && !GV->hasCommonLinkage())) 837 return false; 838 return RelocM != Reloc::Static && (isDecl || GV->mayBeOverridden()); 839} 840 841SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op, 842 SelectionDAG &DAG) { 843 MVT PtrVT = getPointerTy(); 844 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 845 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 846 bool IsIndirect = GVIsIndirectSymbol(GV, RelocM); 847 SDValue CPAddr; 848 if (RelocM == Reloc::Static) 849 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2); 850 else { 851 unsigned PCAdj = (RelocM != Reloc::PIC_) 852 ? 0 : (Subtarget->isThumb() ? 4 : 8); 853 ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr 854 : ARMCP::CPValue; 855 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex, 856 Kind, PCAdj); 857 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); 858 } 859 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 860 861 SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 862 SDValue Chain = Result.getValue(1); 863 864 if (RelocM == Reloc::PIC_) { 865 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 866 Result = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel); 867 } 868 if (IsIndirect) 869 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0); 870 871 return Result; 872} 873 874SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, 875 SelectionDAG &DAG){ 876 assert(Subtarget->isTargetELF() && 877 "GLOBAL OFFSET TABLE not implemented for non-ELF targets"); 878 MVT PtrVT = getPointerTy(); 879 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 880 ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_", 881 ARMPCLabelIndex, 882 ARMCP::CPValue, PCAdj); 883 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); 884 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 885 SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 886 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 887 return DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel); 888} 889 890static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { 891 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 892 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 893 switch (IntNo) { 894 default: return SDValue(); // Don't custom lower most intrinsics. 895 case Intrinsic::arm_thread_pointer: 896 return DAG.getNode(ARMISD::THREAD_POINTER, PtrVT); 897 } 898} 899 900static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 901 unsigned VarArgsFrameIndex) { 902 // vastart just stores the address of the VarArgsFrameIndex slot into the 903 // memory location argument. 904 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 905 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 906 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 907 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); 908} 909 910static SDValue LowerFORMAL_ARGUMENT(SDValue Op, SelectionDAG &DAG, 911 unsigned ArgNo, unsigned &NumGPRs, 912 unsigned &ArgOffset) { 913 MachineFunction &MF = DAG.getMachineFunction(); 914 MVT ObjectVT = Op.getValue(ArgNo).getValueType(); 915 SDValue Root = Op.getOperand(0); 916 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 917 918 static const unsigned GPRArgRegs[] = { 919 ARM::R0, ARM::R1, ARM::R2, ARM::R3 920 }; 921 922 unsigned ObjSize; 923 unsigned ObjGPRs; 924 unsigned GPRPad; 925 unsigned StackPad; 926 ISD::ArgFlagsTy Flags = 927 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo + 3))->getArgFlags(); 928 HowToPassArgument(ObjectVT, NumGPRs, ArgOffset, ObjGPRs, 929 ObjSize, GPRPad, StackPad, Flags); 930 NumGPRs += GPRPad; 931 ArgOffset += StackPad; 932 933 SDValue ArgValue; 934 if (ObjGPRs == 1) { 935 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); 936 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); 937 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); 938 if (ObjectVT == MVT::f32) 939 ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue); 940 } else if (ObjGPRs == 2) { 941 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); 942 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); 943 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); 944 945 VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); 946 RegInfo.addLiveIn(GPRArgRegs[NumGPRs+1], VReg); 947 SDValue ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32); 948 949 assert(ObjectVT != MVT::i64 && "i64 should already be lowered"); 950 ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2); 951 } 952 NumGPRs += ObjGPRs; 953 954 if (ObjSize) { 955 MachineFrameInfo *MFI = MF.getFrameInfo(); 956 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 957 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 958 if (ObjGPRs == 0) 959 ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); 960 else { 961 SDValue ArgValue2 = DAG.getLoad(MVT::i32, Root, FIN, NULL, 0); 962 assert(ObjectVT != MVT::i64 && "i64 should already be lowered"); 963 ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2); 964 } 965 966 ArgOffset += ObjSize; // Move on to the next argument. 967 } 968 969 return ArgValue; 970} 971 972SDValue 973ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) { 974 std::vector<SDValue> ArgValues; 975 SDValue Root = Op.getOperand(0); 976 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 977 unsigned NumGPRs = 0; // GPRs used for parameter passing. 978 979 unsigned NumArgs = Op.getNode()->getNumValues()-1; 980 for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo) 981 ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, ArgNo, 982 NumGPRs, ArgOffset)); 983 984 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0; 985 if (isVarArg) { 986 static const unsigned GPRArgRegs[] = { 987 ARM::R0, ARM::R1, ARM::R2, ARM::R3 988 }; 989 990 MachineFunction &MF = DAG.getMachineFunction(); 991 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 992 MachineFrameInfo *MFI = MF.getFrameInfo(); 993 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 994 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 995 unsigned VARegSize = (4 - NumGPRs) * 4; 996 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1); 997 if (VARegSaveSize) { 998 // If this function is vararg, store any remaining integer argument regs 999 // to their spots on the stack so that they may be loaded by deferencing 1000 // the result of va_next. 1001 AFI->setVarArgsRegSaveSize(VARegSaveSize); 1002 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset + 1003 VARegSaveSize - VARegSize); 1004 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 1005 1006 SmallVector<SDValue, 4> MemOps; 1007 for (; NumGPRs < 4; ++NumGPRs) { 1008 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); 1009 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); 1010 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i32); 1011 SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1012 MemOps.push_back(Store); 1013 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 1014 DAG.getConstant(4, getPointerTy())); 1015 } 1016 if (!MemOps.empty()) 1017 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 1018 &MemOps[0], MemOps.size()); 1019 } else 1020 // This will point to the next argument passed via stack. 1021 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset); 1022 } 1023 1024 ArgValues.push_back(Root); 1025 1026 // Return the new list of results. 1027 return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(), 1028 &ArgValues[0], ArgValues.size()); 1029} 1030 1031/// isFloatingPointZero - Return true if this is +0.0. 1032static bool isFloatingPointZero(SDValue Op) { 1033 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 1034 return CFP->getValueAPF().isPosZero(); 1035 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 1036 // Maybe this has already been legalized into the constant pool? 1037 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) { 1038 SDValue WrapperOp = Op.getOperand(1).getOperand(0); 1039 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp)) 1040 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 1041 return CFP->getValueAPF().isPosZero(); 1042 } 1043 } 1044 return false; 1045} 1046 1047static bool isLegalCmpImmediate(unsigned C, bool isThumb) { 1048 return ( isThumb && (C & ~255U) == 0) || 1049 (!isThumb && ARM_AM::getSOImmVal(C) != -1); 1050} 1051 1052/// Returns appropriate ARM CMP (cmp) and corresponding condition code for 1053/// the given operands. 1054static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 1055 SDValue &ARMCC, SelectionDAG &DAG, bool isThumb) { 1056 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) { 1057 unsigned C = RHSC->getZExtValue(); 1058 if (!isLegalCmpImmediate(C, isThumb)) { 1059 // Constant does not fit, try adjusting it by one? 1060 switch (CC) { 1061 default: break; 1062 case ISD::SETLT: 1063 case ISD::SETGE: 1064 if (isLegalCmpImmediate(C-1, isThumb)) { 1065 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 1066 RHS = DAG.getConstant(C-1, MVT::i32); 1067 } 1068 break; 1069 case ISD::SETULT: 1070 case ISD::SETUGE: 1071 if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) { 1072 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 1073 RHS = DAG.getConstant(C-1, MVT::i32); 1074 } 1075 break; 1076 case ISD::SETLE: 1077 case ISD::SETGT: 1078 if (isLegalCmpImmediate(C+1, isThumb)) { 1079 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; 1080 RHS = DAG.getConstant(C+1, MVT::i32); 1081 } 1082 break; 1083 case ISD::SETULE: 1084 case ISD::SETUGT: 1085 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb)) { 1086 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 1087 RHS = DAG.getConstant(C+1, MVT::i32); 1088 } 1089 break; 1090 } 1091 } 1092 } 1093 1094 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 1095 ARMISD::NodeType CompareType; 1096 switch (CondCode) { 1097 default: 1098 CompareType = ARMISD::CMP; 1099 break; 1100 case ARMCC::EQ: 1101 case ARMCC::NE: 1102 case ARMCC::MI: 1103 case ARMCC::PL: 1104 // Uses only N and Z Flags 1105 CompareType = ARMISD::CMPNZ; 1106 break; 1107 } 1108 ARMCC = DAG.getConstant(CondCode, MVT::i32); 1109 return DAG.getNode(CompareType, MVT::Flag, LHS, RHS); 1110} 1111 1112/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands. 1113static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG) { 1114 SDValue Cmp; 1115 if (!isFloatingPointZero(RHS)) 1116 Cmp = DAG.getNode(ARMISD::CMPFP, MVT::Flag, LHS, RHS); 1117 else 1118 Cmp = DAG.getNode(ARMISD::CMPFPw0, MVT::Flag, LHS); 1119 return DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp); 1120} 1121 1122static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, 1123 const ARMSubtarget *ST) { 1124 MVT VT = Op.getValueType(); 1125 SDValue LHS = Op.getOperand(0); 1126 SDValue RHS = Op.getOperand(1); 1127 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 1128 SDValue TrueVal = Op.getOperand(2); 1129 SDValue FalseVal = Op.getOperand(3); 1130 1131 if (LHS.getValueType() == MVT::i32) { 1132 SDValue ARMCC; 1133 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1134 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb()); 1135 return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, CCR, Cmp); 1136 } 1137 1138 ARMCC::CondCodes CondCode, CondCode2; 1139 if (FPCCToARMCC(CC, CondCode, CondCode2)) 1140 std::swap(TrueVal, FalseVal); 1141 1142 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32); 1143 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1144 SDValue Cmp = getVFPCmp(LHS, RHS, DAG); 1145 SDValue Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, 1146 ARMCC, CCR, Cmp); 1147 if (CondCode2 != ARMCC::AL) { 1148 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32); 1149 // FIXME: Needs another CMP because flag can have but one use. 1150 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG); 1151 Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, CCR, Cmp2); 1152 } 1153 return Result; 1154} 1155 1156static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, 1157 const ARMSubtarget *ST) { 1158 SDValue Chain = Op.getOperand(0); 1159 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 1160 SDValue LHS = Op.getOperand(2); 1161 SDValue RHS = Op.getOperand(3); 1162 SDValue Dest = Op.getOperand(4); 1163 1164 if (LHS.getValueType() == MVT::i32) { 1165 SDValue ARMCC; 1166 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1167 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb()); 1168 return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, CCR,Cmp); 1169 } 1170 1171 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); 1172 ARMCC::CondCodes CondCode, CondCode2; 1173 if (FPCCToARMCC(CC, CondCode, CondCode2)) 1174 // Swap the LHS/RHS of the comparison if needed. 1175 std::swap(LHS, RHS); 1176 1177 SDValue Cmp = getVFPCmp(LHS, RHS, DAG); 1178 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32); 1179 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1180 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag); 1181 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp }; 1182 SDValue Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5); 1183 if (CondCode2 != ARMCC::AL) { 1184 ARMCC = DAG.getConstant(CondCode2, MVT::i32); 1185 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) }; 1186 Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5); 1187 } 1188 return Res; 1189} 1190 1191SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) { 1192 SDValue Chain = Op.getOperand(0); 1193 SDValue Table = Op.getOperand(1); 1194 SDValue Index = Op.getOperand(2); 1195 1196 MVT PTy = getPointerTy(); 1197 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); 1198 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>(); 1199 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); 1200 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); 1201 Table = DAG.getNode(ARMISD::WrapperJT, MVT::i32, JTI, UId); 1202 Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy)); 1203 SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1204 bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1205 Addr = DAG.getLoad(isPIC ? (MVT)MVT::i32 : PTy, 1206 Chain, Addr, NULL, 0); 1207 Chain = Addr.getValue(1); 1208 if (isPIC) 1209 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Table); 1210 return DAG.getNode(ARMISD::BR_JT, MVT::Other, Chain, Addr, JTI, UId); 1211} 1212 1213static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) { 1214 unsigned Opc = 1215 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI; 1216 Op = DAG.getNode(Opc, MVT::f32, Op.getOperand(0)); 1217 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 1218} 1219 1220static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 1221 MVT VT = Op.getValueType(); 1222 unsigned Opc = 1223 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF; 1224 1225 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 1226 return DAG.getNode(Opc, VT, Op); 1227} 1228 1229static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) { 1230 // Implement fcopysign with a fabs and a conditional fneg. 1231 SDValue Tmp0 = Op.getOperand(0); 1232 SDValue Tmp1 = Op.getOperand(1); 1233 MVT VT = Op.getValueType(); 1234 MVT SrcVT = Tmp1.getValueType(); 1235 SDValue AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0); 1236 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG); 1237 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32); 1238 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1239 return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp); 1240} 1241 1242SDValue 1243ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, 1244 SDValue Chain, 1245 SDValue Dst, SDValue Src, 1246 SDValue Size, unsigned Align, 1247 bool AlwaysInline, 1248 const Value *DstSV, uint64_t DstSVOff, 1249 const Value *SrcSV, uint64_t SrcSVOff){ 1250 // Do repeated 4-byte loads and stores. To be improved. 1251 // This requires 4-byte alignment. 1252 if ((Align & 3) != 0) 1253 return SDValue(); 1254 // This requires the copy size to be a constant, preferrably 1255 // within a subtarget-specific limit. 1256 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 1257 if (!ConstantSize) 1258 return SDValue(); 1259 uint64_t SizeVal = ConstantSize->getZExtValue(); 1260 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold()) 1261 return SDValue(); 1262 1263 unsigned BytesLeft = SizeVal & 3; 1264 unsigned NumMemOps = SizeVal >> 2; 1265 unsigned EmittedNumMemOps = 0; 1266 MVT VT = MVT::i32; 1267 unsigned VTSize = 4; 1268 unsigned i = 0; 1269 const unsigned MAX_LOADS_IN_LDM = 6; 1270 SDValue TFOps[MAX_LOADS_IN_LDM]; 1271 SDValue Loads[MAX_LOADS_IN_LDM]; 1272 uint64_t SrcOff = 0, DstOff = 0; 1273 1274 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the 1275 // same number of stores. The loads and stores will get combined into 1276 // ldm/stm later on. 1277 while (EmittedNumMemOps < NumMemOps) { 1278 for (i = 0; 1279 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) { 1280 Loads[i] = DAG.getLoad(VT, Chain, 1281 DAG.getNode(ISD::ADD, MVT::i32, Src, 1282 DAG.getConstant(SrcOff, MVT::i32)), 1283 SrcSV, SrcSVOff + SrcOff); 1284 TFOps[i] = Loads[i].getValue(1); 1285 SrcOff += VTSize; 1286 } 1287 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i); 1288 1289 for (i = 0; 1290 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) { 1291 TFOps[i] = DAG.getStore(Chain, Loads[i], 1292 DAG.getNode(ISD::ADD, MVT::i32, Dst, 1293 DAG.getConstant(DstOff, MVT::i32)), 1294 DstSV, DstSVOff + DstOff); 1295 DstOff += VTSize; 1296 } 1297 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i); 1298 1299 EmittedNumMemOps += i; 1300 } 1301 1302 if (BytesLeft == 0) 1303 return Chain; 1304 1305 // Issue loads / stores for the trailing (1 - 3) bytes. 1306 unsigned BytesLeftSave = BytesLeft; 1307 i = 0; 1308 while (BytesLeft) { 1309 if (BytesLeft >= 2) { 1310 VT = MVT::i16; 1311 VTSize = 2; 1312 } else { 1313 VT = MVT::i8; 1314 VTSize = 1; 1315 } 1316 1317 Loads[i] = DAG.getLoad(VT, Chain, 1318 DAG.getNode(ISD::ADD, MVT::i32, Src, 1319 DAG.getConstant(SrcOff, MVT::i32)), 1320 SrcSV, SrcSVOff + SrcOff); 1321 TFOps[i] = Loads[i].getValue(1); 1322 ++i; 1323 SrcOff += VTSize; 1324 BytesLeft -= VTSize; 1325 } 1326 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i); 1327 1328 i = 0; 1329 BytesLeft = BytesLeftSave; 1330 while (BytesLeft) { 1331 if (BytesLeft >= 2) { 1332 VT = MVT::i16; 1333 VTSize = 2; 1334 } else { 1335 VT = MVT::i8; 1336 VTSize = 1; 1337 } 1338 1339 TFOps[i] = DAG.getStore(Chain, Loads[i], 1340 DAG.getNode(ISD::ADD, MVT::i32, Dst, 1341 DAG.getConstant(DstOff, MVT::i32)), 1342 DstSV, DstSVOff + DstOff); 1343 ++i; 1344 DstOff += VTSize; 1345 BytesLeft -= VTSize; 1346 } 1347 return DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i); 1348} 1349 1350static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) { 1351 SDValue Op = N->getOperand(0); 1352 if (N->getValueType(0) == MVT::f64) { 1353 // Turn i64->f64 into FMDRR. 1354 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 1355 DAG.getConstant(0, MVT::i32)); 1356 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 1357 DAG.getConstant(1, MVT::i32)); 1358 return DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi); 1359 } 1360 1361 // Turn f64->i64 into FMRRD. 1362 SDValue Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), 1363 &Op, 1); 1364 1365 // Merge the pieces into a single i64 value. 1366 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1)); 1367} 1368 1369static SDValue ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) { 1370 assert(N->getValueType(0) == MVT::i64 && 1371 (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && 1372 "Unknown shift to lower!"); 1373 1374 // We only lower SRA, SRL of 1 here, all others use generic lowering. 1375 if (!isa<ConstantSDNode>(N->getOperand(1)) || 1376 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1) 1377 return SDValue(); 1378 1379 // If we are in thumb mode, we don't have RRX. 1380 if (ST->isThumb()) return SDValue(); 1381 1382 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr. 1383 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0), 1384 DAG.getConstant(0, MVT::i32)); 1385 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0), 1386 DAG.getConstant(1, MVT::i32)); 1387 1388 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and 1389 // captures the result into a carry flag. 1390 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG; 1391 Hi = DAG.getNode(Opc, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1); 1392 1393 // The low part is an ARMISD::RRX operand, which shifts the carry in. 1394 Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1)); 1395 1396 // Merge the pieces into a single i64 value. 1397 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 1398} 1399 1400 1401SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 1402 switch (Op.getOpcode()) { 1403 default: assert(0 && "Don't know how to custom lower this!"); abort(); 1404 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 1405 case ISD::GlobalAddress: 1406 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) : 1407 LowerGlobalAddressELF(Op, DAG); 1408 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 1409 case ISD::CALL: return LowerCALL(Op, DAG); 1410 case ISD::RET: return LowerRET(Op, DAG); 1411 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget); 1412 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget); 1413 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 1414 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex); 1415 case ISD::SINT_TO_FP: 1416 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); 1417 case ISD::FP_TO_SINT: 1418 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG); 1419 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 1420 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG); 1421 case ISD::RETURNADDR: break; 1422 case ISD::FRAMEADDR: break; 1423 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG); 1424 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 1425 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG); 1426 case ISD::SRL: 1427 case ISD::SRA: return ExpandSRx(Op.getNode(), DAG,Subtarget); 1428 } 1429 return SDValue(); 1430} 1431 1432 1433/// ReplaceNodeResults - Replace the results of node with an illegal result 1434/// type with new values built out of custom code. 1435/// 1436void ARMTargetLowering::ReplaceNodeResults(SDNode *N, 1437 SmallVectorImpl<SDValue>&Results, 1438 SelectionDAG &DAG) { 1439 switch (N->getOpcode()) { 1440 default: 1441 assert(0 && "Don't know how to custom expand this!"); 1442 return; 1443 case ISD::BIT_CONVERT: 1444 Results.push_back(ExpandBIT_CONVERT(N, DAG)); 1445 return; 1446 case ISD::SRL: 1447 case ISD::SRA: { 1448 SDValue Res = ExpandSRx(N, DAG, Subtarget); 1449 if (Res.getNode()) 1450 Results.push_back(Res); 1451 return; 1452 } 1453 } 1454} 1455 1456 1457//===----------------------------------------------------------------------===// 1458// ARM Scheduler Hooks 1459//===----------------------------------------------------------------------===// 1460 1461MachineBasicBlock * 1462ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1463 MachineBasicBlock *BB) { 1464 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1465 switch (MI->getOpcode()) { 1466 default: assert(false && "Unexpected instr type to insert"); 1467 case ARM::tMOVCCr: { 1468 // To "insert" a SELECT_CC instruction, we actually have to insert the 1469 // diamond control-flow pattern. The incoming instruction knows the 1470 // destination vreg to set, the condition code register to branch on, the 1471 // true/false values to select between, and a branch opcode to use. 1472 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1473 MachineFunction::iterator It = BB; 1474 ++It; 1475 1476 // thisMBB: 1477 // ... 1478 // TrueVal = ... 1479 // cmpTY ccX, r1, r2 1480 // bCC copy1MBB 1481 // fallthrough --> copy0MBB 1482 MachineBasicBlock *thisMBB = BB; 1483 MachineFunction *F = BB->getParent(); 1484 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1485 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 1486 BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB) 1487 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg()); 1488 F->insert(It, copy0MBB); 1489 F->insert(It, sinkMBB); 1490 // Update machine-CFG edges by first adding all successors of the current 1491 // block to the new block which will contain the Phi node for the select. 1492 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 1493 e = BB->succ_end(); i != e; ++i) 1494 sinkMBB->addSuccessor(*i); 1495 // Next, remove all successors of the current block, and add the true 1496 // and fallthrough blocks as its successors. 1497 while(!BB->succ_empty()) 1498 BB->removeSuccessor(BB->succ_begin()); 1499 BB->addSuccessor(copy0MBB); 1500 BB->addSuccessor(sinkMBB); 1501 1502 // copy0MBB: 1503 // %FalseValue = ... 1504 // # fallthrough to sinkMBB 1505 BB = copy0MBB; 1506 1507 // Update machine-CFG edges 1508 BB->addSuccessor(sinkMBB); 1509 1510 // sinkMBB: 1511 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1512 // ... 1513 BB = sinkMBB; 1514 BuildMI(BB, TII->get(ARM::PHI), MI->getOperand(0).getReg()) 1515 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 1516 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 1517 1518 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 1519 return BB; 1520 } 1521 } 1522} 1523 1524//===----------------------------------------------------------------------===// 1525// ARM Optimization Hooks 1526//===----------------------------------------------------------------------===// 1527 1528/// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD. 1529static SDValue PerformFMRRDCombine(SDNode *N, 1530 TargetLowering::DAGCombinerInfo &DCI) { 1531 // fmrrd(fmdrr x, y) -> x,y 1532 SDValue InDouble = N->getOperand(0); 1533 if (InDouble.getOpcode() == ARMISD::FMDRR) 1534 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1)); 1535 return SDValue(); 1536} 1537 1538SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N, 1539 DAGCombinerInfo &DCI) const { 1540 switch (N->getOpcode()) { 1541 default: break; 1542 case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI); 1543 } 1544 1545 return SDValue(); 1546} 1547 1548 1549/// isLegalAddressImmediate - Return true if the integer value can be used 1550/// as the offset of the target addressing mode for load / store of the 1551/// given type. 1552static bool isLegalAddressImmediate(int64_t V, MVT VT, 1553 const ARMSubtarget *Subtarget) { 1554 if (V == 0) 1555 return true; 1556 1557 if (Subtarget->isThumb()) { 1558 if (V < 0) 1559 return false; 1560 1561 unsigned Scale = 1; 1562 switch (VT.getSimpleVT()) { 1563 default: return false; 1564 case MVT::i1: 1565 case MVT::i8: 1566 // Scale == 1; 1567 break; 1568 case MVT::i16: 1569 // Scale == 2; 1570 Scale = 2; 1571 break; 1572 case MVT::i32: 1573 // Scale == 4; 1574 Scale = 4; 1575 break; 1576 } 1577 1578 if ((V & (Scale - 1)) != 0) 1579 return false; 1580 V /= Scale; 1581 return V == (V & ((1LL << 5) - 1)); 1582 } 1583 1584 if (V < 0) 1585 V = - V; 1586 switch (VT.getSimpleVT()) { 1587 default: return false; 1588 case MVT::i1: 1589 case MVT::i8: 1590 case MVT::i32: 1591 // +- imm12 1592 return V == (V & ((1LL << 12) - 1)); 1593 case MVT::i16: 1594 // +- imm8 1595 return V == (V & ((1LL << 8) - 1)); 1596 case MVT::f32: 1597 case MVT::f64: 1598 if (!Subtarget->hasVFP2()) 1599 return false; 1600 if ((V & 3) != 0) 1601 return false; 1602 V >>= 2; 1603 return V == (V & ((1LL << 8) - 1)); 1604 } 1605} 1606 1607/// isLegalAddressingMode - Return true if the addressing mode represented 1608/// by AM is legal for this target, for a load/store of the specified type. 1609bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM, 1610 const Type *Ty) const { 1611 if (!isLegalAddressImmediate(AM.BaseOffs, getValueType(Ty, true), Subtarget)) 1612 return false; 1613 1614 // Can never fold addr of global into load/store. 1615 if (AM.BaseGV) 1616 return false; 1617 1618 switch (AM.Scale) { 1619 case 0: // no scale reg, must be "r+i" or "r", or "i". 1620 break; 1621 case 1: 1622 if (Subtarget->isThumb()) 1623 return false; 1624 // FALL THROUGH. 1625 default: 1626 // ARM doesn't support any R+R*scale+imm addr modes. 1627 if (AM.BaseOffs) 1628 return false; 1629 1630 int Scale = AM.Scale; 1631 switch (getValueType(Ty).getSimpleVT()) { 1632 default: return false; 1633 case MVT::i1: 1634 case MVT::i8: 1635 case MVT::i32: 1636 case MVT::i64: 1637 // This assumes i64 is legalized to a pair of i32. If not (i.e. 1638 // ldrd / strd are used, then its address mode is same as i16. 1639 // r + r 1640 if (Scale < 0) Scale = -Scale; 1641 if (Scale == 1) 1642 return true; 1643 // r + r << imm 1644 return isPowerOf2_32(Scale & ~1); 1645 case MVT::i16: 1646 // r + r 1647 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 1648 return true; 1649 return false; 1650 1651 case MVT::isVoid: 1652 // Note, we allow "void" uses (basically, uses that aren't loads or 1653 // stores), because arm allows folding a scale into many arithmetic 1654 // operations. This should be made more precise and revisited later. 1655 1656 // Allow r << imm, but the imm has to be a multiple of two. 1657 if (AM.Scale & 1) return false; 1658 return isPowerOf2_32(AM.Scale); 1659 } 1660 break; 1661 } 1662 return true; 1663} 1664 1665 1666static bool getIndexedAddressParts(SDNode *Ptr, MVT VT, 1667 bool isSEXTLoad, SDValue &Base, 1668 SDValue &Offset, bool &isInc, 1669 SelectionDAG &DAG) { 1670 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 1671 return false; 1672 1673 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { 1674 // AddressingMode 3 1675 Base = Ptr->getOperand(0); 1676 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 1677 int RHSC = (int)RHS->getZExtValue(); 1678 if (RHSC < 0 && RHSC > -256) { 1679 isInc = false; 1680 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 1681 return true; 1682 } 1683 } 1684 isInc = (Ptr->getOpcode() == ISD::ADD); 1685 Offset = Ptr->getOperand(1); 1686 return true; 1687 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) { 1688 // AddressingMode 2 1689 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 1690 int RHSC = (int)RHS->getZExtValue(); 1691 if (RHSC < 0 && RHSC > -0x1000) { 1692 isInc = false; 1693 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 1694 Base = Ptr->getOperand(0); 1695 return true; 1696 } 1697 } 1698 1699 if (Ptr->getOpcode() == ISD::ADD) { 1700 isInc = true; 1701 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0)); 1702 if (ShOpcVal != ARM_AM::no_shift) { 1703 Base = Ptr->getOperand(1); 1704 Offset = Ptr->getOperand(0); 1705 } else { 1706 Base = Ptr->getOperand(0); 1707 Offset = Ptr->getOperand(1); 1708 } 1709 return true; 1710 } 1711 1712 isInc = (Ptr->getOpcode() == ISD::ADD); 1713 Base = Ptr->getOperand(0); 1714 Offset = Ptr->getOperand(1); 1715 return true; 1716 } 1717 1718 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store. 1719 return false; 1720} 1721 1722/// getPreIndexedAddressParts - returns true by value, base pointer and 1723/// offset pointer and addressing mode by reference if the node's address 1724/// can be legally represented as pre-indexed load / store address. 1725bool 1726ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 1727 SDValue &Offset, 1728 ISD::MemIndexedMode &AM, 1729 SelectionDAG &DAG) { 1730 if (Subtarget->isThumb()) 1731 return false; 1732 1733 MVT VT; 1734 SDValue Ptr; 1735 bool isSEXTLoad = false; 1736 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1737 Ptr = LD->getBasePtr(); 1738 VT = LD->getMemoryVT(); 1739 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 1740 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1741 Ptr = ST->getBasePtr(); 1742 VT = ST->getMemoryVT(); 1743 } else 1744 return false; 1745 1746 bool isInc; 1747 bool isLegal = getIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, Offset, 1748 isInc, DAG); 1749 if (isLegal) { 1750 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC; 1751 return true; 1752 } 1753 return false; 1754} 1755 1756/// getPostIndexedAddressParts - returns true by value, base pointer and 1757/// offset pointer and addressing mode by reference if this node can be 1758/// combined with a load / store to form a post-indexed load / store. 1759bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 1760 SDValue &Base, 1761 SDValue &Offset, 1762 ISD::MemIndexedMode &AM, 1763 SelectionDAG &DAG) { 1764 if (Subtarget->isThumb()) 1765 return false; 1766 1767 MVT VT; 1768 SDValue Ptr; 1769 bool isSEXTLoad = false; 1770 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1771 VT = LD->getMemoryVT(); 1772 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 1773 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1774 VT = ST->getMemoryVT(); 1775 } else 1776 return false; 1777 1778 bool isInc; 1779 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 1780 isInc, DAG); 1781 if (isLegal) { 1782 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; 1783 return true; 1784 } 1785 return false; 1786} 1787 1788void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1789 const APInt &Mask, 1790 APInt &KnownZero, 1791 APInt &KnownOne, 1792 const SelectionDAG &DAG, 1793 unsigned Depth) const { 1794 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1795 switch (Op.getOpcode()) { 1796 default: break; 1797 case ARMISD::CMOV: { 1798 // Bits are known zero/one if known on the LHS and RHS. 1799 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 1800 if (KnownZero == 0 && KnownOne == 0) return; 1801 1802 APInt KnownZeroRHS, KnownOneRHS; 1803 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, 1804 KnownZeroRHS, KnownOneRHS, Depth+1); 1805 KnownZero &= KnownZeroRHS; 1806 KnownOne &= KnownOneRHS; 1807 return; 1808 } 1809 } 1810} 1811 1812//===----------------------------------------------------------------------===// 1813// ARM Inline Assembly Support 1814//===----------------------------------------------------------------------===// 1815 1816/// getConstraintType - Given a constraint letter, return the type of 1817/// constraint it is for this target. 1818ARMTargetLowering::ConstraintType 1819ARMTargetLowering::getConstraintType(const std::string &Constraint) const { 1820 if (Constraint.size() == 1) { 1821 switch (Constraint[0]) { 1822 default: break; 1823 case 'l': return C_RegisterClass; 1824 case 'w': return C_RegisterClass; 1825 } 1826 } 1827 return TargetLowering::getConstraintType(Constraint); 1828} 1829 1830std::pair<unsigned, const TargetRegisterClass*> 1831ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 1832 MVT VT) const { 1833 if (Constraint.size() == 1) { 1834 // GCC RS6000 Constraint Letters 1835 switch (Constraint[0]) { 1836 case 'l': 1837 // FIXME: in thumb mode, 'l' is only low-regs. 1838 // FALL THROUGH. 1839 case 'r': 1840 return std::make_pair(0U, ARM::GPRRegisterClass); 1841 case 'w': 1842 if (VT == MVT::f32) 1843 return std::make_pair(0U, ARM::SPRRegisterClass); 1844 if (VT == MVT::f64) 1845 return std::make_pair(0U, ARM::DPRRegisterClass); 1846 break; 1847 } 1848 } 1849 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 1850} 1851 1852std::vector<unsigned> ARMTargetLowering:: 1853getRegClassForInlineAsmConstraint(const std::string &Constraint, 1854 MVT VT) const { 1855 if (Constraint.size() != 1) 1856 return std::vector<unsigned>(); 1857 1858 switch (Constraint[0]) { // GCC ARM Constraint Letters 1859 default: break; 1860 case 'l': 1861 case 'r': 1862 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1863 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1864 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1865 ARM::R12, ARM::LR, 0); 1866 case 'w': 1867 if (VT == MVT::f32) 1868 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1869 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1870 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1871 ARM::S12,ARM::S13,ARM::S14,ARM::S15, 1872 ARM::S16,ARM::S17,ARM::S18,ARM::S19, 1873 ARM::S20,ARM::S21,ARM::S22,ARM::S23, 1874 ARM::S24,ARM::S25,ARM::S26,ARM::S27, 1875 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0); 1876 if (VT == MVT::f64) 1877 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1878 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1879 ARM::D8, ARM::D9, ARM::D10,ARM::D11, 1880 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0); 1881 break; 1882 } 1883 1884 return std::vector<unsigned>(); 1885} 1886