ARMISelLowering.cpp revision b5fb4282cd2968be81a853c0f3199d167e402bdf 
1//===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "ARM.h"
16#include "ARMAddressingModes.h"
17#include "ARMConstantPoolValue.h"
18#include "ARMISelLowering.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMPerfectShuffle.h"
21#include "ARMRegisterInfo.h"
22#include "ARMSubtarget.h"
23#include "ARMTargetMachine.h"
24#include "ARMTargetObjectFile.h"
25#include "llvm/CallingConv.h"
26#include "llvm/Constants.h"
27#include "llvm/Function.h"
28#include "llvm/Instruction.h"
29#include "llvm/Intrinsics.h"
30#include "llvm/GlobalValue.h"
31#include "llvm/CodeGen/CallingConvLower.h"
32#include "llvm/CodeGen/MachineBasicBlock.h"
33#include "llvm/CodeGen/MachineFrameInfo.h"
34#include "llvm/CodeGen/MachineFunction.h"
35#include "llvm/CodeGen/MachineInstrBuilder.h"
36#include "llvm/CodeGen/MachineRegisterInfo.h"
37#include "llvm/CodeGen/PseudoSourceValue.h"
38#include "llvm/CodeGen/SelectionDAG.h"
39#include "llvm/Target/TargetOptions.h"
40#include "llvm/ADT/VectorExtras.h"
41#include "llvm/Support/ErrorHandling.h"
42#include "llvm/Support/MathExtras.h"
43using namespace llvm;
44
45static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
46                                   CCValAssign::LocInfo &LocInfo,
47                                   ISD::ArgFlagsTy &ArgFlags,
48                                   CCState &State);
49static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
50                                    CCValAssign::LocInfo &LocInfo,
51                                    ISD::ArgFlagsTy &ArgFlags,
52                                    CCState &State);
53static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
54                                      CCValAssign::LocInfo &LocInfo,
55                                      ISD::ArgFlagsTy &ArgFlags,
56                                      CCState &State);
57static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
58                                       CCValAssign::LocInfo &LocInfo,
59                                       ISD::ArgFlagsTy &ArgFlags,
60                                       CCState &State);
61
62void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
63                                       EVT PromotedBitwiseVT) {
64  if (VT != PromotedLdStVT) {
65    setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
66    AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
67                       PromotedLdStVT.getSimpleVT());
68
69    setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
70    AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
71                       PromotedLdStVT.getSimpleVT());
72  }
73
74  EVT ElemTy = VT.getVectorElementType();
75  if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
76    setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
77  if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
78    setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
79  setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
80  setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
81  setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Custom);
82  setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
83  if (VT.isInteger()) {
84    setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
85    setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
86    setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
87  }
88
89  // Promote all bit-wise operations.
90  if (VT.isInteger() && VT != PromotedBitwiseVT) {
91    setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
92    AddPromotedToType (ISD::AND, VT.getSimpleVT(),
93                       PromotedBitwiseVT.getSimpleVT());
94    setOperationAction(ISD::OR,  VT.getSimpleVT(), Promote);
95    AddPromotedToType (ISD::OR,  VT.getSimpleVT(),
96                       PromotedBitwiseVT.getSimpleVT());
97    setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
98    AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
99                       PromotedBitwiseVT.getSimpleVT());
100  }
101}
102
103void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
104  addRegisterClass(VT, ARM::DPRRegisterClass);
105  addTypeForNEON(VT, MVT::f64, MVT::v2i32);
106}
107
108void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
109  addRegisterClass(VT, ARM::QPRRegisterClass);
110  addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
111}
112
113static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
114  if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
115    return new TargetLoweringObjectFileMachO();
116  return new ARMElfTargetObjectFile();
117}
118
119ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
120    : TargetLowering(TM, createTLOF(TM)), ARMPCLabelIndex(0) {
121  Subtarget = &TM.getSubtarget<ARMSubtarget>();
122
123  if (Subtarget->isTargetDarwin()) {
124    // Uses VFP for Thumb libfuncs if available.
125    if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
126      // Single-precision floating-point arithmetic.
127      setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
128      setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
129      setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
130      setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
131
132      // Double-precision floating-point arithmetic.
133      setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
134      setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
135      setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
136      setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
137
138      // Single-precision comparisons.
139      setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
140      setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
141      setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
142      setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
143      setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
144      setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
145      setLibcallName(RTLIB::UO_F32,  "__unordsf2vfp");
146      setLibcallName(RTLIB::O_F32,   "__unordsf2vfp");
147
148      setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
149      setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
150      setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
151      setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
152      setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
153      setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
154      setCmpLibcallCC(RTLIB::UO_F32,  ISD::SETNE);
155      setCmpLibcallCC(RTLIB::O_F32,   ISD::SETEQ);
156
157      // Double-precision comparisons.
158      setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
159      setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
160      setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
161      setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
162      setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
163      setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
164      setLibcallName(RTLIB::UO_F64,  "__unorddf2vfp");
165      setLibcallName(RTLIB::O_F64,   "__unorddf2vfp");
166
167      setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
168      setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
169      setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
170      setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
171      setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
172      setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
173      setCmpLibcallCC(RTLIB::UO_F64,  ISD::SETNE);
174      setCmpLibcallCC(RTLIB::O_F64,   ISD::SETEQ);
175
176      // Floating-point to integer conversions.
177      // i64 conversions are done via library routines even when generating VFP
178      // instructions, so use the same ones.
179      setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
180      setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
181      setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
182      setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
183
184      // Conversions between floating types.
185      setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
186      setLibcallName(RTLIB::FPEXT_F32_F64,   "__extendsfdf2vfp");
187
188      // Integer to floating-point conversions.
189      // i64 conversions are done via library routines even when generating VFP
190      // instructions, so use the same ones.
191      // FIXME: There appears to be some naming inconsistency in ARM libgcc:
192      // e.g., __floatunsidf vs. __floatunssidfvfp.
193      setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
194      setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
195      setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
196      setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
197    }
198  }
199
200  // These libcalls are not available in 32-bit.
201  setLibcallName(RTLIB::SHL_I128, 0);
202  setLibcallName(RTLIB::SRL_I128, 0);
203  setLibcallName(RTLIB::SRA_I128, 0);
204
205  // Libcalls should use the AAPCS base standard ABI, even if hard float
206  // is in effect, as per the ARM RTABI specification, section 4.1.2.
207  if (Subtarget->isAAPCS_ABI()) {
208    for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
209      setLibcallCallingConv(static_cast<RTLIB::Libcall>(i),
210                            CallingConv::ARM_AAPCS);
211    }
212  }
213
214  if (Subtarget->isThumb1Only())
215    addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
216  else
217    addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
218  if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
219    addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
220    addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
221
222    setTruncStoreAction(MVT::f64, MVT::f32, Expand);
223  }
224
225  if (Subtarget->hasNEON()) {
226    addDRTypeForNEON(MVT::v2f32);
227    addDRTypeForNEON(MVT::v8i8);
228    addDRTypeForNEON(MVT::v4i16);
229    addDRTypeForNEON(MVT::v2i32);
230    addDRTypeForNEON(MVT::v1i64);
231
232    addQRTypeForNEON(MVT::v4f32);
233    addQRTypeForNEON(MVT::v2f64);
234    addQRTypeForNEON(MVT::v16i8);
235    addQRTypeForNEON(MVT::v8i16);
236    addQRTypeForNEON(MVT::v4i32);
237    addQRTypeForNEON(MVT::v2i64);
238
239    setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
240    setTargetDAGCombine(ISD::SHL);
241    setTargetDAGCombine(ISD::SRL);
242    setTargetDAGCombine(ISD::SRA);
243    setTargetDAGCombine(ISD::SIGN_EXTEND);
244    setTargetDAGCombine(ISD::ZERO_EXTEND);
245    setTargetDAGCombine(ISD::ANY_EXTEND);
246  }
247
248  computeRegisterProperties();
249
250  // ARM does not have f32 extending load.
251  setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
252
253  // ARM does not have i1 sign extending load.
254  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
255
256  // ARM supports all 4 flavors of integer indexed load / store.
257  if (!Subtarget->isThumb1Only()) {
258    for (unsigned im = (unsigned)ISD::PRE_INC;
259         im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
260      setIndexedLoadAction(im,  MVT::i1,  Legal);
261      setIndexedLoadAction(im,  MVT::i8,  Legal);
262      setIndexedLoadAction(im,  MVT::i16, Legal);
263      setIndexedLoadAction(im,  MVT::i32, Legal);
264      setIndexedStoreAction(im, MVT::i1,  Legal);
265      setIndexedStoreAction(im, MVT::i8,  Legal);
266      setIndexedStoreAction(im, MVT::i16, Legal);
267      setIndexedStoreAction(im, MVT::i32, Legal);
268    }
269  }
270
271  // i64 operation support.
272  if (Subtarget->isThumb1Only()) {
273    setOperationAction(ISD::MUL,     MVT::i64, Expand);
274    setOperationAction(ISD::MULHU,   MVT::i32, Expand);
275    setOperationAction(ISD::MULHS,   MVT::i32, Expand);
276    setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
277    setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
278  } else {
279    setOperationAction(ISD::MUL,     MVT::i64, Expand);
280    setOperationAction(ISD::MULHU,   MVT::i32, Expand);
281    if (!Subtarget->hasV6Ops())
282      setOperationAction(ISD::MULHS, MVT::i32, Expand);
283  }
284  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
285  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
286  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
287  setOperationAction(ISD::SRL,       MVT::i64, Custom);
288  setOperationAction(ISD::SRA,       MVT::i64, Custom);
289
290  // ARM does not have ROTL.
291  setOperationAction(ISD::ROTL,  MVT::i32, Expand);
292  setOperationAction(ISD::CTTZ,  MVT::i32, Expand);
293  setOperationAction(ISD::CTPOP, MVT::i32, Expand);
294  if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
295    setOperationAction(ISD::CTLZ, MVT::i32, Expand);
296
297  // Only ARMv6 has BSWAP.
298  if (!Subtarget->hasV6Ops())
299    setOperationAction(ISD::BSWAP, MVT::i32, Expand);
300
301  // These are expanded into libcalls.
302  setOperationAction(ISD::SDIV,  MVT::i32, Expand);
303  setOperationAction(ISD::UDIV,  MVT::i32, Expand);
304  setOperationAction(ISD::SREM,  MVT::i32, Expand);
305  setOperationAction(ISD::UREM,  MVT::i32, Expand);
306  setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
307  setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
308
309  // Support label based line numbers.
310  setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
311  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
312
313  setOperationAction(ISD::GlobalAddress, MVT::i32,   Custom);
314  setOperationAction(ISD::ConstantPool,  MVT::i32,   Custom);
315  setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
316  setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
317
318  // Use the default implementation.
319  setOperationAction(ISD::VASTART,            MVT::Other, Custom);
320  setOperationAction(ISD::VAARG,              MVT::Other, Expand);
321  setOperationAction(ISD::VACOPY,             MVT::Other, Expand);
322  setOperationAction(ISD::VAEND,              MVT::Other, Expand);
323  setOperationAction(ISD::STACKSAVE,          MVT::Other, Expand);
324  setOperationAction(ISD::STACKRESTORE,       MVT::Other, Expand);
325  setOperationAction(ISD::EHSELECTION,        MVT::i32,   Expand);
326  // FIXME: Shouldn't need this, since no register is used, but the legalizer
327  // doesn't yet know how to not do that for SjLj.
328  setExceptionSelectorRegister(ARM::R0);
329  if (Subtarget->isThumb())
330    setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
331  else
332    setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
333  setOperationAction(ISD::MEMBARRIER,         MVT::Other, Expand);
334
335  if (!Subtarget->hasV6Ops() && !Subtarget->isThumb2()) {
336    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
337    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8,  Expand);
338  }
339  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
340
341  if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only())
342    // Turn f64->i64 into FMRRD, i64 -> f64 to FMDRR iff target supports vfp2.
343    setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
344
345  // We want to custom lower some of our intrinsics.
346  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
347  setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
348  setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
349
350  setOperationAction(ISD::SETCC,     MVT::i32, Expand);
351  setOperationAction(ISD::SETCC,     MVT::f32, Expand);
352  setOperationAction(ISD::SETCC,     MVT::f64, Expand);
353  setOperationAction(ISD::SELECT,    MVT::i32, Expand);
354  setOperationAction(ISD::SELECT,    MVT::f32, Expand);
355  setOperationAction(ISD::SELECT,    MVT::f64, Expand);
356  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
357  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
358  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
359
360  setOperationAction(ISD::BRCOND,    MVT::Other, Expand);
361  setOperationAction(ISD::BR_CC,     MVT::i32,   Custom);
362  setOperationAction(ISD::BR_CC,     MVT::f32,   Custom);
363  setOperationAction(ISD::BR_CC,     MVT::f64,   Custom);
364  setOperationAction(ISD::BR_JT,     MVT::Other, Custom);
365
366  // We don't support sin/cos/fmod/copysign/pow
367  setOperationAction(ISD::FSIN,      MVT::f64, Expand);
368  setOperationAction(ISD::FSIN,      MVT::f32, Expand);
369  setOperationAction(ISD::FCOS,      MVT::f32, Expand);
370  setOperationAction(ISD::FCOS,      MVT::f64, Expand);
371  setOperationAction(ISD::FREM,      MVT::f64, Expand);
372  setOperationAction(ISD::FREM,      MVT::f32, Expand);
373  if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
374    setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
375    setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
376  }
377  setOperationAction(ISD::FPOW,      MVT::f64, Expand);
378  setOperationAction(ISD::FPOW,      MVT::f32, Expand);
379
380  // int <-> fp are custom expanded into bit_convert + ARMISD ops.
381  if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
382    setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
383    setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
384    setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
385    setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
386  }
387
388  // We have target-specific dag combine patterns for the following nodes:
389  // ARMISD::FMRRD  - No need to call setTargetDAGCombine
390  setTargetDAGCombine(ISD::ADD);
391  setTargetDAGCombine(ISD::SUB);
392
393  setStackPointerRegisterToSaveRestore(ARM::SP);
394  setSchedulingPreference(SchedulingForRegPressure);
395
396  // FIXME: If-converter should use instruction latency to determine
397  // profitability rather than relying on fixed limits.
398  if (Subtarget->getCPUString() == "generic") {
399    // Generic (and overly aggressive) if-conversion limits.
400    setIfCvtBlockSizeLimit(10);
401    setIfCvtDupBlockSizeLimit(2);
402  } else if (Subtarget->hasV6Ops()) {
403    setIfCvtBlockSizeLimit(2);
404    setIfCvtDupBlockSizeLimit(1);
405  } else {
406    setIfCvtBlockSizeLimit(3);
407    setIfCvtDupBlockSizeLimit(2);
408  }
409
410  maxStoresPerMemcpy = 1;   //// temporary - rewrite interface to use type
411  // Do not enable CodePlacementOpt for now: it currently runs after the
412  // ARMConstantIslandPass and messes up branch relaxation and placement
413  // of constant islands.
414  // benefitFromCodePlacementOpt = true;
415}
416
417const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
418  switch (Opcode) {
419  default: return 0;
420  case ARMISD::Wrapper:       return "ARMISD::Wrapper";
421  case ARMISD::WrapperJT:     return "ARMISD::WrapperJT";
422  case ARMISD::CALL:          return "ARMISD::CALL";
423  case ARMISD::CALL_PRED:     return "ARMISD::CALL_PRED";
424  case ARMISD::CALL_NOLINK:   return "ARMISD::CALL_NOLINK";
425  case ARMISD::tCALL:         return "ARMISD::tCALL";
426  case ARMISD::BRCOND:        return "ARMISD::BRCOND";
427  case ARMISD::BR_JT:         return "ARMISD::BR_JT";
428  case ARMISD::BR2_JT:        return "ARMISD::BR2_JT";
429  case ARMISD::RET_FLAG:      return "ARMISD::RET_FLAG";
430  case ARMISD::PIC_ADD:       return "ARMISD::PIC_ADD";
431  case ARMISD::CMP:           return "ARMISD::CMP";
432  case ARMISD::CMPZ:          return "ARMISD::CMPZ";
433  case ARMISD::CMPFP:         return "ARMISD::CMPFP";
434  case ARMISD::CMPFPw0:       return "ARMISD::CMPFPw0";
435  case ARMISD::FMSTAT:        return "ARMISD::FMSTAT";
436  case ARMISD::CMOV:          return "ARMISD::CMOV";
437  case ARMISD::CNEG:          return "ARMISD::CNEG";
438
439  case ARMISD::FTOSI:         return "ARMISD::FTOSI";
440  case ARMISD::FTOUI:         return "ARMISD::FTOUI";
441  case ARMISD::SITOF:         return "ARMISD::SITOF";
442  case ARMISD::UITOF:         return "ARMISD::UITOF";
443
444  case ARMISD::SRL_FLAG:      return "ARMISD::SRL_FLAG";
445  case ARMISD::SRA_FLAG:      return "ARMISD::SRA_FLAG";
446  case ARMISD::RRX:           return "ARMISD::RRX";
447
448  case ARMISD::FMRRD:         return "ARMISD::FMRRD";
449  case ARMISD::FMDRR:         return "ARMISD::FMDRR";
450
451  case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
452
453  case ARMISD::DYN_ALLOC:     return "ARMISD::DYN_ALLOC";
454
455  case ARMISD::VCEQ:          return "ARMISD::VCEQ";
456  case ARMISD::VCGE:          return "ARMISD::VCGE";
457  case ARMISD::VCGEU:         return "ARMISD::VCGEU";
458  case ARMISD::VCGT:          return "ARMISD::VCGT";
459  case ARMISD::VCGTU:         return "ARMISD::VCGTU";
460  case ARMISD::VTST:          return "ARMISD::VTST";
461
462  case ARMISD::VSHL:          return "ARMISD::VSHL";
463  case ARMISD::VSHRs:         return "ARMISD::VSHRs";
464  case ARMISD::VSHRu:         return "ARMISD::VSHRu";
465  case ARMISD::VSHLLs:        return "ARMISD::VSHLLs";
466  case ARMISD::VSHLLu:        return "ARMISD::VSHLLu";
467  case ARMISD::VSHLLi:        return "ARMISD::VSHLLi";
468  case ARMISD::VSHRN:         return "ARMISD::VSHRN";
469  case ARMISD::VRSHRs:        return "ARMISD::VRSHRs";
470  case ARMISD::VRSHRu:        return "ARMISD::VRSHRu";
471  case ARMISD::VRSHRN:        return "ARMISD::VRSHRN";
472  case ARMISD::VQSHLs:        return "ARMISD::VQSHLs";
473  case ARMISD::VQSHLu:        return "ARMISD::VQSHLu";
474  case ARMISD::VQSHLsu:       return "ARMISD::VQSHLsu";
475  case ARMISD::VQSHRNs:       return "ARMISD::VQSHRNs";
476  case ARMISD::VQSHRNu:       return "ARMISD::VQSHRNu";
477  case ARMISD::VQSHRNsu:      return "ARMISD::VQSHRNsu";
478  case ARMISD::VQRSHRNs:      return "ARMISD::VQRSHRNs";
479  case ARMISD::VQRSHRNu:      return "ARMISD::VQRSHRNu";
480  case ARMISD::VQRSHRNsu:     return "ARMISD::VQRSHRNsu";
481  case ARMISD::VGETLANEu:     return "ARMISD::VGETLANEu";
482  case ARMISD::VGETLANEs:     return "ARMISD::VGETLANEs";
483  case ARMISD::VDUP:          return "ARMISD::VDUP";
484  case ARMISD::VDUPLANE:      return "ARMISD::VDUPLANE";
485  case ARMISD::VEXT:          return "ARMISD::VEXT";
486  case ARMISD::VREV64:        return "ARMISD::VREV64";
487  case ARMISD::VREV32:        return "ARMISD::VREV32";
488  case ARMISD::VREV16:        return "ARMISD::VREV16";
489  case ARMISD::VZIP:          return "ARMISD::VZIP";
490  case ARMISD::VUZP:          return "ARMISD::VUZP";
491  case ARMISD::VTRN:          return "ARMISD::VTRN";
492  }
493}
494
495/// getFunctionAlignment - Return the Log2 alignment of this function.
496unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
497  return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
498}
499
500//===----------------------------------------------------------------------===//
501// Lowering Code
502//===----------------------------------------------------------------------===//
503
504/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
505static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
506  switch (CC) {
507  default: llvm_unreachable("Unknown condition code!");
508  case ISD::SETNE:  return ARMCC::NE;
509  case ISD::SETEQ:  return ARMCC::EQ;
510  case ISD::SETGT:  return ARMCC::GT;
511  case ISD::SETGE:  return ARMCC::GE;
512  case ISD::SETLT:  return ARMCC::LT;
513  case ISD::SETLE:  return ARMCC::LE;
514  case ISD::SETUGT: return ARMCC::HI;
515  case ISD::SETUGE: return ARMCC::HS;
516  case ISD::SETULT: return ARMCC::LO;
517  case ISD::SETULE: return ARMCC::LS;
518  }
519}
520
521/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It
522/// returns true if the operands should be inverted to form the proper
523/// comparison.
524static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
525                        ARMCC::CondCodes &CondCode2) {
526  bool Invert = false;
527  CondCode2 = ARMCC::AL;
528  switch (CC) {
529  default: llvm_unreachable("Unknown FP condition!");
530  case ISD::SETEQ:
531  case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
532  case ISD::SETGT:
533  case ISD::SETOGT: CondCode = ARMCC::GT; break;
534  case ISD::SETGE:
535  case ISD::SETOGE: CondCode = ARMCC::GE; break;
536  case ISD::SETOLT: CondCode = ARMCC::MI; break;
537  case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break;
538  case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
539  case ISD::SETO:   CondCode = ARMCC::VC; break;
540  case ISD::SETUO:  CondCode = ARMCC::VS; break;
541  case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
542  case ISD::SETUGT: CondCode = ARMCC::HI; break;
543  case ISD::SETUGE: CondCode = ARMCC::PL; break;
544  case ISD::SETLT:
545  case ISD::SETULT: CondCode = ARMCC::LT; break;
546  case ISD::SETLE:
547  case ISD::SETULE: CondCode = ARMCC::LE; break;
548  case ISD::SETNE:
549  case ISD::SETUNE: CondCode = ARMCC::NE; break;
550  }
551  return Invert;
552}
553
554//===----------------------------------------------------------------------===//
555//                      Calling Convention Implementation
556//===----------------------------------------------------------------------===//
557
558#include "ARMGenCallingConv.inc"
559
560// APCS f64 is in register pairs, possibly split to stack
561static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
562                          CCValAssign::LocInfo &LocInfo,
563                          CCState &State, bool CanFail) {
564  static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
565
566  // Try to get the first register.
567  if (unsigned Reg = State.AllocateReg(RegList, 4))
568    State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
569  else {
570    // For the 2nd half of a v2f64, do not fail.
571    if (CanFail)
572      return false;
573
574    // Put the whole thing on the stack.
575    State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
576                                           State.AllocateStack(8, 4),
577                                           LocVT, LocInfo));
578    return true;
579  }
580
581  // Try to get the second register.
582  if (unsigned Reg = State.AllocateReg(RegList, 4))
583    State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
584  else
585    State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
586                                           State.AllocateStack(4, 4),
587                                           LocVT, LocInfo));
588  return true;
589}
590
591static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
592                                   CCValAssign::LocInfo &LocInfo,
593                                   ISD::ArgFlagsTy &ArgFlags,
594                                   CCState &State) {
595  if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
596    return false;
597  if (LocVT == MVT::v2f64 &&
598      !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
599    return false;
600  return true;  // we handled it
601}
602
603// AAPCS f64 is in aligned register pairs
604static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
605                           CCValAssign::LocInfo &LocInfo,
606                           CCState &State, bool CanFail) {
607  static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
608  static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
609
610  unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
611  if (Reg == 0) {
612    // For the 2nd half of a v2f64, do not just fail.
613    if (CanFail)
614      return false;
615
616    // Put the whole thing on the stack.
617    State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
618                                           State.AllocateStack(8, 8),
619                                           LocVT, LocInfo));
620    return true;
621  }
622
623  unsigned i;
624  for (i = 0; i < 2; ++i)
625    if (HiRegList[i] == Reg)
626      break;
627
628  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
629  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
630                                         LocVT, LocInfo));
631  return true;
632}
633
634static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
635                                    CCValAssign::LocInfo &LocInfo,
636                                    ISD::ArgFlagsTy &ArgFlags,
637                                    CCState &State) {
638  if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
639    return false;
640  if (LocVT == MVT::v2f64 &&
641      !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
642    return false;
643  return true;  // we handled it
644}
645
646static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
647                         CCValAssign::LocInfo &LocInfo, CCState &State) {
648  static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
649  static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
650
651  unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
652  if (Reg == 0)
653    return false; // we didn't handle it
654
655  unsigned i;
656  for (i = 0; i < 2; ++i)
657    if (HiRegList[i] == Reg)
658      break;
659
660  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
661  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
662                                         LocVT, LocInfo));
663  return true;
664}
665
666static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
667                                      CCValAssign::LocInfo &LocInfo,
668                                      ISD::ArgFlagsTy &ArgFlags,
669                                      CCState &State) {
670  if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
671    return false;
672  if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
673    return false;
674  return true;  // we handled it
675}
676
677static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
678                                       CCValAssign::LocInfo &LocInfo,
679                                       ISD::ArgFlagsTy &ArgFlags,
680                                       CCState &State) {
681  return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
682                                   State);
683}
684
685/// CCAssignFnForNode - Selects the correct CCAssignFn for a the
686/// given CallingConvention value.
687CCAssignFn *ARMTargetLowering::CCAssignFnForNode(unsigned CC,
688                                                 bool Return,
689                                                 bool isVarArg) const {
690  switch (CC) {
691  default:
692    llvm_unreachable("Unsupported calling convention");
693  case CallingConv::C:
694  case CallingConv::Fast:
695    // Use target triple & subtarget features to do actual dispatch.
696    if (Subtarget->isAAPCS_ABI()) {
697      if (Subtarget->hasVFP2() &&
698          FloatABIType == FloatABI::Hard && !isVarArg)
699        return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
700      else
701        return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
702    } else
703        return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
704  case CallingConv::ARM_AAPCS_VFP:
705    return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
706  case CallingConv::ARM_AAPCS:
707    return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
708  case CallingConv::ARM_APCS:
709    return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
710  }
711}
712
713/// LowerCallResult - Lower the result values of a call into the
714/// appropriate copies out of appropriate physical registers.
715SDValue
716ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
717                                   unsigned CallConv, bool isVarArg,
718                                   const SmallVectorImpl<ISD::InputArg> &Ins,
719                                   DebugLoc dl, SelectionDAG &DAG,
720                                   SmallVectorImpl<SDValue> &InVals) {
721
722  // Assign locations to each value returned by this call.
723  SmallVector<CCValAssign, 16> RVLocs;
724  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
725                 RVLocs, *DAG.getContext());
726  CCInfo.AnalyzeCallResult(Ins,
727                           CCAssignFnForNode(CallConv, /* Return*/ true,
728                                             isVarArg));
729
730  // Copy all of the result registers out of their specified physreg.
731  for (unsigned i = 0; i != RVLocs.size(); ++i) {
732    CCValAssign VA = RVLocs[i];
733
734    SDValue Val;
735    if (VA.needsCustom()) {
736      // Handle f64 or half of a v2f64.
737      SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
738                                      InFlag);
739      Chain = Lo.getValue(1);
740      InFlag = Lo.getValue(2);
741      VA = RVLocs[++i]; // skip ahead to next loc
742      SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
743                                      InFlag);
744      Chain = Hi.getValue(1);
745      InFlag = Hi.getValue(2);
746      Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
747
748      if (VA.getLocVT() == MVT::v2f64) {
749        SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
750        Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
751                          DAG.getConstant(0, MVT::i32));
752
753        VA = RVLocs[++i]; // skip ahead to next loc
754        Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
755        Chain = Lo.getValue(1);
756        InFlag = Lo.getValue(2);
757        VA = RVLocs[++i]; // skip ahead to next loc
758        Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
759        Chain = Hi.getValue(1);
760        InFlag = Hi.getValue(2);
761        Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
762        Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
763                          DAG.getConstant(1, MVT::i32));
764      }
765    } else {
766      Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
767                               InFlag);
768      Chain = Val.getValue(1);
769      InFlag = Val.getValue(2);
770    }
771
772    switch (VA.getLocInfo()) {
773    default: llvm_unreachable("Unknown loc info!");
774    case CCValAssign::Full: break;
775    case CCValAssign::BCvt:
776      Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
777      break;
778    }
779
780    InVals.push_back(Val);
781  }
782
783  return Chain;
784}
785
786/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
787/// by "Src" to address "Dst" of size "Size".  Alignment information is
788/// specified by the specific parameter attribute.  The copy will be passed as
789/// a byval function parameter.
790/// Sometimes what we are copying is the end of a larger object, the part that
791/// does not fit in registers.
792static SDValue
793CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
794                          ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
795                          DebugLoc dl) {
796  SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
797  return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
798                       /*AlwaysInline=*/false, NULL, 0, NULL, 0);
799}
800
801/// LowerMemOpCallTo - Store the argument to the stack.
802SDValue
803ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
804                                    SDValue StackPtr, SDValue Arg,
805                                    DebugLoc dl, SelectionDAG &DAG,
806                                    const CCValAssign &VA,
807                                    ISD::ArgFlagsTy Flags) {
808  unsigned LocMemOffset = VA.getLocMemOffset();
809  SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
810  PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
811  if (Flags.isByVal()) {
812    return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
813  }
814  return DAG.getStore(Chain, dl, Arg, PtrOff,
815                      PseudoSourceValue::getStack(), LocMemOffset);
816}
817
818void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
819                                         SDValue Chain, SDValue &Arg,
820                                         RegsToPassVector &RegsToPass,
821                                         CCValAssign &VA, CCValAssign &NextVA,
822                                         SDValue &StackPtr,
823                                         SmallVector<SDValue, 8> &MemOpChains,
824                                         ISD::ArgFlagsTy Flags) {
825
826  SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
827                              DAG.getVTList(MVT::i32, MVT::i32), Arg);
828  RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
829
830  if (NextVA.isRegLoc())
831    RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
832  else {
833    assert(NextVA.isMemLoc());
834    if (StackPtr.getNode() == 0)
835      StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
836
837    MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
838                                           dl, DAG, NextVA,
839                                           Flags));
840  }
841}
842
843/// LowerCall - Lowering a call into a callseq_start <-
844/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
845/// nodes.
846SDValue
847ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
848                             unsigned CallConv, bool isVarArg,
849                             bool isTailCall,
850                             const SmallVectorImpl<ISD::OutputArg> &Outs,
851                             const SmallVectorImpl<ISD::InputArg> &Ins,
852                             DebugLoc dl, SelectionDAG &DAG,
853                             SmallVectorImpl<SDValue> &InVals) {
854
855  // Analyze operands of the call, assigning locations to each operand.
856  SmallVector<CCValAssign, 16> ArgLocs;
857  CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
858                 *DAG.getContext());
859  CCInfo.AnalyzeCallOperands(Outs,
860                             CCAssignFnForNode(CallConv, /* Return*/ false,
861                                               isVarArg));
862
863  // Get a count of how many bytes are to be pushed on the stack.
864  unsigned NumBytes = CCInfo.getNextStackOffset();
865
866  // Adjust the stack pointer for the new arguments...
867  // These operations are automatically eliminated by the prolog/epilog pass
868  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
869
870  SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
871
872  RegsToPassVector RegsToPass;
873  SmallVector<SDValue, 8> MemOpChains;
874
875  // Walk the register/memloc assignments, inserting copies/loads.  In the case
876  // of tail call optimization, arguments are handled later.
877  for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
878       i != e;
879       ++i, ++realArgIdx) {
880    CCValAssign &VA = ArgLocs[i];
881    SDValue Arg = Outs[realArgIdx].Val;
882    ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
883
884    // Promote the value if needed.
885    switch (VA.getLocInfo()) {
886    default: llvm_unreachable("Unknown loc info!");
887    case CCValAssign::Full: break;
888    case CCValAssign::SExt:
889      Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
890      break;
891    case CCValAssign::ZExt:
892      Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
893      break;
894    case CCValAssign::AExt:
895      Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
896      break;
897    case CCValAssign::BCvt:
898      Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
899      break;
900    }
901
902    // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
903    if (VA.needsCustom()) {
904      if (VA.getLocVT() == MVT::v2f64) {
905        SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
906                                  DAG.getConstant(0, MVT::i32));
907        SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
908                                  DAG.getConstant(1, MVT::i32));
909
910        PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
911                         VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
912
913        VA = ArgLocs[++i]; // skip ahead to next loc
914        if (VA.isRegLoc()) {
915          PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
916                           VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
917        } else {
918          assert(VA.isMemLoc());
919          if (StackPtr.getNode() == 0)
920            StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
921
922          MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
923                                                 dl, DAG, VA, Flags));
924        }
925      } else {
926        PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
927                         StackPtr, MemOpChains, Flags);
928      }
929    } else if (VA.isRegLoc()) {
930      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
931    } else {
932      assert(VA.isMemLoc());
933      if (StackPtr.getNode() == 0)
934        StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
935
936      MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
937                                             dl, DAG, VA, Flags));
938    }
939  }
940
941  if (!MemOpChains.empty())
942    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
943                        &MemOpChains[0], MemOpChains.size());
944
945  // Build a sequence of copy-to-reg nodes chained together with token chain
946  // and flag operands which copy the outgoing args into the appropriate regs.
947  SDValue InFlag;
948  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
949    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
950                             RegsToPass[i].second, InFlag);
951    InFlag = Chain.getValue(1);
952  }
953
954  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
955  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
956  // node so that legalize doesn't hack it.
957  bool isDirect = false;
958  bool isARMFunc = false;
959  bool isLocalARMFunc = false;
960  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
961    GlobalValue *GV = G->getGlobal();
962    isDirect = true;
963    bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
964    bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
965                   getTargetMachine().getRelocationModel() != Reloc::Static;
966    isARMFunc = !Subtarget->isThumb() || isStub;
967    // ARM call to a local ARM function is predicable.
968    isLocalARMFunc = !Subtarget->isThumb() && !isExt;
969    // tBX takes a register source operand.
970    if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
971      ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
972                                                           ARMCP::CPStub, 4);
973      SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
974      CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
975      Callee = DAG.getLoad(getPointerTy(), dl,
976                           DAG.getEntryNode(), CPAddr, NULL, 0);
977      SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
978      Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
979                           getPointerTy(), Callee, PICLabel);
980   } else
981      Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
982  } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
983    isDirect = true;
984    bool isStub = Subtarget->isTargetDarwin() &&
985                  getTargetMachine().getRelocationModel() != Reloc::Static;
986    isARMFunc = !Subtarget->isThumb() || isStub;
987    // tBX takes a register source operand.
988    const char *Sym = S->getSymbol();
989    if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
990      ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
991                                                          Sym, ARMPCLabelIndex,
992                                                           ARMCP::CPStub, 4);
993      SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
994      CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
995      Callee = DAG.getLoad(getPointerTy(), dl,
996                           DAG.getEntryNode(), CPAddr, NULL, 0);
997      SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
998      Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
999                           getPointerTy(), Callee, PICLabel);
1000    } else
1001      Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
1002  }
1003
1004  // FIXME: handle tail calls differently.
1005  unsigned CallOpc;
1006  if (Subtarget->isThumb()) {
1007    if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1008      CallOpc = ARMISD::CALL_NOLINK;
1009    else
1010      CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1011  } else {
1012    CallOpc = (isDirect || Subtarget->hasV5TOps())
1013      ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1014      : ARMISD::CALL_NOLINK;
1015  }
1016  if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb1Only()) {
1017    // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
1018    Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag);
1019    InFlag = Chain.getValue(1);
1020  }
1021
1022  std::vector<SDValue> Ops;
1023  Ops.push_back(Chain);
1024  Ops.push_back(Callee);
1025
1026  // Add argument registers to the end of the list so that they are known live
1027  // into the call.
1028  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1029    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1030                                  RegsToPass[i].second.getValueType()));
1031
1032  if (InFlag.getNode())
1033    Ops.push_back(InFlag);
1034  // Returns a chain and a flag for retval copy to use.
1035  Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
1036                      &Ops[0], Ops.size());
1037  InFlag = Chain.getValue(1);
1038
1039  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1040                             DAG.getIntPtrConstant(0, true), InFlag);
1041  if (!Ins.empty())
1042    InFlag = Chain.getValue(1);
1043
1044  // Handle result values, copying them out of physregs into vregs that we
1045  // return.
1046  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1047                         dl, DAG, InVals);
1048}
1049
1050SDValue
1051ARMTargetLowering::LowerReturn(SDValue Chain,
1052                               unsigned CallConv, bool isVarArg,
1053                               const SmallVectorImpl<ISD::OutputArg> &Outs,
1054                               DebugLoc dl, SelectionDAG &DAG) {
1055
1056  // CCValAssign - represent the assignment of the return value to a location.
1057  SmallVector<CCValAssign, 16> RVLocs;
1058
1059  // CCState - Info about the registers and stack slots.
1060  CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1061                 *DAG.getContext());
1062
1063  // Analyze outgoing return values.
1064  CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1065                                               isVarArg));
1066
1067  // If this is the first return lowered for this function, add
1068  // the regs to the liveout set for the function.
1069  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1070    for (unsigned i = 0; i != RVLocs.size(); ++i)
1071      if (RVLocs[i].isRegLoc())
1072        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1073  }
1074
1075  SDValue Flag;
1076
1077  // Copy the result values into the output registers.
1078  for (unsigned i = 0, realRVLocIdx = 0;
1079       i != RVLocs.size();
1080       ++i, ++realRVLocIdx) {
1081    CCValAssign &VA = RVLocs[i];
1082    assert(VA.isRegLoc() && "Can only return in registers!");
1083
1084    SDValue Arg = Outs[realRVLocIdx].Val;
1085
1086    switch (VA.getLocInfo()) {
1087    default: llvm_unreachable("Unknown loc info!");
1088    case CCValAssign::Full: break;
1089    case CCValAssign::BCvt:
1090      Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1091      break;
1092    }
1093
1094    if (VA.needsCustom()) {
1095      if (VA.getLocVT() == MVT::v2f64) {
1096        // Extract the first half and return it in two registers.
1097        SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1098                                   DAG.getConstant(0, MVT::i32));
1099        SDValue HalfGPRs = DAG.getNode(ARMISD::FMRRD, dl,
1100                                       DAG.getVTList(MVT::i32, MVT::i32), Half);
1101
1102        Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1103        Flag = Chain.getValue(1);
1104        VA = RVLocs[++i]; // skip ahead to next loc
1105        Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1106                                 HalfGPRs.getValue(1), Flag);
1107        Flag = Chain.getValue(1);
1108        VA = RVLocs[++i]; // skip ahead to next loc
1109
1110        // Extract the 2nd half and fall through to handle it as an f64 value.
1111        Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1112                          DAG.getConstant(1, MVT::i32));
1113      }
1114      // Legalize ret f64 -> ret 2 x i32.  We always have fmrrd if f64 is
1115      // available.
1116      SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
1117                                  DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1118      Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1119      Flag = Chain.getValue(1);
1120      VA = RVLocs[++i]; // skip ahead to next loc
1121      Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1122                               Flag);
1123    } else
1124      Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1125
1126    // Guarantee that all emitted copies are
1127    // stuck together, avoiding something bad.
1128    Flag = Chain.getValue(1);
1129  }
1130
1131  SDValue result;
1132  if (Flag.getNode())
1133    result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1134  else // Return Void
1135    result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1136
1137  return result;
1138}
1139
1140// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1141// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1142// one of the above mentioned nodes. It has to be wrapped because otherwise
1143// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1144// be used to form addressing mode. These wrapped nodes will be selected
1145// into MOVi.
1146static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1147  EVT PtrVT = Op.getValueType();
1148  // FIXME there is no actual debug info here
1149  DebugLoc dl = Op.getDebugLoc();
1150  ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1151  SDValue Res;
1152  if (CP->isMachineConstantPoolEntry())
1153    Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1154                                    CP->getAlignment());
1155  else
1156    Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1157                                    CP->getAlignment());
1158  return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1159}
1160
1161// Lower ISD::GlobalTLSAddress using the "general dynamic" model
1162SDValue
1163ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1164                                                 SelectionDAG &DAG) {
1165  DebugLoc dl = GA->getDebugLoc();
1166  EVT PtrVT = getPointerTy();
1167  unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1168  ARMConstantPoolValue *CPV =
1169    new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
1170                             PCAdj, "tlsgd", true);
1171  SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1172  Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1173  Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, NULL, 0);
1174  SDValue Chain = Argument.getValue(1);
1175
1176  SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1177  Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1178
1179  // call __tls_get_addr.
1180  ArgListTy Args;
1181  ArgListEntry Entry;
1182  Entry.Node = Argument;
1183  Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1184  Args.push_back(Entry);
1185  // FIXME: is there useful debug info available here?
1186  std::pair<SDValue, SDValue> CallResult =
1187    LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1188                false, false, false, false,
1189                0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1190                DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1191  return CallResult.first;
1192}
1193
1194// Lower ISD::GlobalTLSAddress using the "initial exec" or
1195// "local exec" model.
1196SDValue
1197ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1198                                        SelectionDAG &DAG) {
1199  GlobalValue *GV = GA->getGlobal();
1200  DebugLoc dl = GA->getDebugLoc();
1201  SDValue Offset;
1202  SDValue Chain = DAG.getEntryNode();
1203  EVT PtrVT = getPointerTy();
1204  // Get the Thread Pointer
1205  SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1206
1207  if (GV->isDeclaration()) {
1208    // initial exec model
1209    unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1210    ARMConstantPoolValue *CPV =
1211      new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
1212                               PCAdj, "gottpoff", true);
1213    Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1214    Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1215    Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1216    Chain = Offset.getValue(1);
1217
1218    SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1219    Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1220
1221    Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1222  } else {
1223    // local exec model
1224    ARMConstantPoolValue *CPV =
1225      new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff");
1226    Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1227    Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1228    Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1229  }
1230
1231  // The address of the thread local variable is the add of the thread
1232  // pointer with the offset of the variable.
1233  return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1234}
1235
1236SDValue
1237ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
1238  // TODO: implement the "local dynamic" model
1239  assert(Subtarget->isTargetELF() &&
1240         "TLS not implemented for non-ELF targets");
1241  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1242  // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1243  // otherwise use the "Local Exec" TLS Model
1244  if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1245    return LowerToTLSGeneralDynamicModel(GA, DAG);
1246  else
1247    return LowerToTLSExecModels(GA, DAG);
1248}
1249
1250SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1251                                                 SelectionDAG &DAG) {
1252  EVT PtrVT = getPointerTy();
1253  DebugLoc dl = Op.getDebugLoc();
1254  GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1255  Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1256  if (RelocM == Reloc::PIC_) {
1257    bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1258    ARMConstantPoolValue *CPV =
1259      new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
1260    SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1261    CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1262    SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1263                                 CPAddr, NULL, 0);
1264    SDValue Chain = Result.getValue(1);
1265    SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1266    Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1267    if (!UseGOTOFF)
1268      Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
1269    return Result;
1270  } else {
1271    SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1272    CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1273    return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1274  }
1275}
1276
1277/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol
1278/// even in non-static mode.
1279static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) {
1280  // If symbol visibility is hidden, the extra load is not needed if
1281  // the symbol is definitely defined in the current translation unit.
1282  bool isDecl = GV->isDeclaration() || GV->hasAvailableExternallyLinkage();
1283  if (GV->hasHiddenVisibility() && (!isDecl && !GV->hasCommonLinkage()))
1284    return false;
1285  return RelocM != Reloc::Static && (isDecl || GV->isWeakForLinker());
1286}
1287
1288SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1289                                                    SelectionDAG &DAG) {
1290  EVT PtrVT = getPointerTy();
1291  DebugLoc dl = Op.getDebugLoc();
1292  GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1293  Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1294  bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
1295  SDValue CPAddr;
1296  if (RelocM == Reloc::Static)
1297    CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1298  else {
1299    unsigned PCAdj = (RelocM != Reloc::PIC_)
1300      ? 0 : (Subtarget->isThumb() ? 4 : 8);
1301    ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr
1302      : ARMCP::CPValue;
1303    ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
1304                                                         Kind, PCAdj);
1305    CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1306  }
1307  CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1308
1309  SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1310  SDValue Chain = Result.getValue(1);
1311
1312  if (RelocM == Reloc::PIC_) {
1313    SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1314    Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1315  }
1316  if (IsIndirect)
1317    Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
1318
1319  return Result;
1320}
1321
1322SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1323                                                    SelectionDAG &DAG){
1324  assert(Subtarget->isTargetELF() &&
1325         "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1326  EVT PtrVT = getPointerTy();
1327  DebugLoc dl = Op.getDebugLoc();
1328  unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1329  ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1330                                                       "_GLOBAL_OFFSET_TABLE_",
1331                                                       ARMPCLabelIndex,
1332                                                       ARMCP::CPValue, PCAdj);
1333  SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1334  CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1335  SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1336  SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1337  return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1338}
1339
1340static SDValue LowerNeonVLDIntrinsic(SDValue Op, SelectionDAG &DAG,
1341                                     unsigned NumVecs) {
1342  SDNode *Node = Op.getNode();
1343  EVT VT = Node->getValueType(0);
1344
1345  // No expansion needed for 64-bit vectors.
1346  if (VT.is64BitVector())
1347    return SDValue();
1348
1349  // FIXME: We need to expand VLD3 and VLD4 of 128-bit vectors into separate
1350  // operations to load the even and odd registers.
1351  return SDValue();
1352}
1353
1354static SDValue LowerNeonVSTIntrinsic(SDValue Op, SelectionDAG &DAG,
1355                                     unsigned NumVecs) {
1356  SDNode *Node = Op.getNode();
1357  EVT VT = Node->getOperand(3).getValueType();
1358
1359  // No expansion needed for 64-bit vectors.
1360  if (VT.is64BitVector())
1361    return SDValue();
1362
1363  // FIXME: We need to expand VST3 and VST4 of 128-bit vectors into separate
1364  // operations to store the even and odd registers.
1365  return SDValue();
1366}
1367
1368SDValue
1369ARMTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
1370  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1371  switch (IntNo) {
1372  case Intrinsic::arm_neon_vld3:
1373    return LowerNeonVLDIntrinsic(Op, DAG, 3);
1374  case Intrinsic::arm_neon_vld4:
1375    return LowerNeonVLDIntrinsic(Op, DAG, 4);
1376  case Intrinsic::arm_neon_vst3:
1377    return LowerNeonVSTIntrinsic(Op, DAG, 3);
1378  case Intrinsic::arm_neon_vst4:
1379    return LowerNeonVSTIntrinsic(Op, DAG, 4);
1380  default: return SDValue();    // Don't custom lower most intrinsics.
1381  }
1382}
1383
1384SDValue
1385ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
1386  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1387  DebugLoc dl = Op.getDebugLoc();
1388  switch (IntNo) {
1389  default: return SDValue();    // Don't custom lower most intrinsics.
1390  case Intrinsic::arm_thread_pointer: {
1391    EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1392    return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1393  }
1394  case Intrinsic::eh_sjlj_lsda: {
1395    // blah. horrible, horrible hack with the forced magic name.
1396    // really need to clean this up. It belongs in the target-independent
1397    // layer somehow that doesn't require the coupling with the asm
1398    // printer.
1399    MachineFunction &MF = DAG.getMachineFunction();
1400    EVT PtrVT = getPointerTy();
1401    DebugLoc dl = Op.getDebugLoc();
1402    Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1403    SDValue CPAddr;
1404    unsigned PCAdj = (RelocM != Reloc::PIC_)
1405      ? 0 : (Subtarget->isThumb() ? 4 : 8);
1406    ARMCP::ARMCPKind Kind = ARMCP::CPValue;
1407    // Save off the LSDA name for the AsmPrinter to use when it's time
1408    // to emit the table
1409    std::string LSDAName = "L_lsda_";
1410    LSDAName += MF.getFunction()->getName();
1411    ARMConstantPoolValue *CPV =
1412      new ARMConstantPoolValue(*DAG.getContext(), LSDAName.c_str(),
1413                               ARMPCLabelIndex, Kind, PCAdj);
1414    CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1415    CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1416    SDValue Result =
1417      DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1418    SDValue Chain = Result.getValue(1);
1419
1420    if (RelocM == Reloc::PIC_) {
1421      SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1422      Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1423    }
1424    return Result;
1425  }
1426  case Intrinsic::eh_sjlj_setjmp:
1427    return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(1));
1428  }
1429}
1430
1431static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
1432                            unsigned VarArgsFrameIndex) {
1433  // vastart just stores the address of the VarArgsFrameIndex slot into the
1434  // memory location argument.
1435  DebugLoc dl = Op.getDebugLoc();
1436  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1437  SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1438  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1439  return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
1440}
1441
1442SDValue
1443ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
1444  SDNode *Node = Op.getNode();
1445  DebugLoc dl = Node->getDebugLoc();
1446  EVT VT = Node->getValueType(0);
1447  SDValue Chain = Op.getOperand(0);
1448  SDValue Size  = Op.getOperand(1);
1449  SDValue Align = Op.getOperand(2);
1450
1451  // Chain the dynamic stack allocation so that it doesn't modify the stack
1452  // pointer when other instructions are using the stack.
1453  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1454
1455  unsigned AlignVal = cast<ConstantSDNode>(Align)->getZExtValue();
1456  unsigned StackAlign = getTargetMachine().getFrameInfo()->getStackAlignment();
1457  if (AlignVal > StackAlign)
1458    // Do this now since selection pass cannot introduce new target
1459    // independent node.
1460    Align = DAG.getConstant(-(uint64_t)AlignVal, VT);
1461
1462  // In Thumb1 mode, there isn't a "sub r, sp, r" instruction, we will end up
1463  // using a "add r, sp, r" instead. Negate the size now so we don't have to
1464  // do even more horrible hack later.
1465  MachineFunction &MF = DAG.getMachineFunction();
1466  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1467  if (AFI->isThumb1OnlyFunction()) {
1468    bool Negate = true;
1469    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Size);
1470    if (C) {
1471      uint32_t Val = C->getZExtValue();
1472      if (Val <= 508 && ((Val & 3) == 0))
1473        Negate = false;
1474    }
1475    if (Negate)
1476      Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size);
1477  }
1478
1479  SDVTList VTList = DAG.getVTList(VT, MVT::Other);
1480  SDValue Ops1[] = { Chain, Size, Align };
1481  SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3);
1482  Chain = Res.getValue(1);
1483  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1484                             DAG.getIntPtrConstant(0, true), SDValue());
1485  SDValue Ops2[] = { Res, Chain };
1486  return DAG.getMergeValues(Ops2, 2, dl);
1487}
1488
1489SDValue
1490ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
1491                                        SDValue &Root, SelectionDAG &DAG,
1492                                        DebugLoc dl) {
1493  MachineFunction &MF = DAG.getMachineFunction();
1494  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1495
1496  TargetRegisterClass *RC;
1497  if (AFI->isThumb1OnlyFunction())
1498    RC = ARM::tGPRRegisterClass;
1499  else
1500    RC = ARM::GPRRegisterClass;
1501
1502  // Transform the arguments stored in physical registers into virtual ones.
1503  unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1504  SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1505
1506  SDValue ArgValue2;
1507  if (NextVA.isMemLoc()) {
1508    unsigned ArgSize = NextVA.getLocVT().getSizeInBits()/8;
1509    MachineFrameInfo *MFI = MF.getFrameInfo();
1510    int FI = MFI->CreateFixedObject(ArgSize, NextVA.getLocMemOffset());
1511
1512    // Create load node to retrieve arguments from the stack.
1513    SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1514    ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0);
1515  } else {
1516    Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
1517    ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1518  }
1519
1520  return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, ArgValue, ArgValue2);
1521}
1522
1523SDValue
1524ARMTargetLowering::LowerFormalArguments(SDValue Chain,
1525                                        unsigned CallConv, bool isVarArg,
1526                                        const SmallVectorImpl<ISD::InputArg>
1527                                          &Ins,
1528                                        DebugLoc dl, SelectionDAG &DAG,
1529                                        SmallVectorImpl<SDValue> &InVals) {
1530
1531  MachineFunction &MF = DAG.getMachineFunction();
1532  MachineFrameInfo *MFI = MF.getFrameInfo();
1533
1534  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1535
1536  // Assign locations to all of the incoming arguments.
1537  SmallVector<CCValAssign, 16> ArgLocs;
1538  CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1539                 *DAG.getContext());
1540  CCInfo.AnalyzeFormalArguments(Ins,
1541                                CCAssignFnForNode(CallConv, /* Return*/ false,
1542                                                  isVarArg));
1543
1544  SmallVector<SDValue, 16> ArgValues;
1545
1546  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1547    CCValAssign &VA = ArgLocs[i];
1548
1549    // Arguments stored in registers.
1550    if (VA.isRegLoc()) {
1551      EVT RegVT = VA.getLocVT();
1552
1553      SDValue ArgValue;
1554      if (VA.needsCustom()) {
1555        // f64 and vector types are split up into multiple registers or
1556        // combinations of registers and stack slots.
1557        RegVT = MVT::i32;
1558
1559        if (VA.getLocVT() == MVT::v2f64) {
1560          SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
1561                                                   Chain, DAG, dl);
1562          VA = ArgLocs[++i]; // skip ahead to next loc
1563          SDValue ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
1564                                                   Chain, DAG, dl);
1565          ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1566          ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1567                                 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
1568          ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1569                                 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
1570        } else
1571          ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
1572
1573      } else {
1574        TargetRegisterClass *RC;
1575
1576        if (RegVT == MVT::f32)
1577          RC = ARM::SPRRegisterClass;
1578        else if (RegVT == MVT::f64)
1579          RC = ARM::DPRRegisterClass;
1580        else if (RegVT == MVT::v2f64)
1581          RC = ARM::QPRRegisterClass;
1582        else if (RegVT == MVT::i32)
1583          RC = (AFI->isThumb1OnlyFunction() ?
1584                ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
1585        else
1586          llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
1587
1588        // Transform the arguments in physical registers into virtual ones.
1589        unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1590        ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1591      }
1592
1593      // If this is an 8 or 16-bit value, it is really passed promoted
1594      // to 32 bits.  Insert an assert[sz]ext to capture this, then
1595      // truncate to the right size.
1596      switch (VA.getLocInfo()) {
1597      default: llvm_unreachable("Unknown loc info!");
1598      case CCValAssign::Full: break;
1599      case CCValAssign::BCvt:
1600        ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1601        break;
1602      case CCValAssign::SExt:
1603        ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1604                               DAG.getValueType(VA.getValVT()));
1605        ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1606        break;
1607      case CCValAssign::ZExt:
1608        ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1609                               DAG.getValueType(VA.getValVT()));
1610        ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1611        break;
1612      }
1613
1614      InVals.push_back(ArgValue);
1615
1616    } else { // VA.isRegLoc()
1617
1618      // sanity check
1619      assert(VA.isMemLoc());
1620      assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
1621
1622      unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1623      int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset());
1624
1625      // Create load nodes to retrieve arguments from the stack.
1626      SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1627      InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0));
1628    }
1629  }
1630
1631  // varargs
1632  if (isVarArg) {
1633    static const unsigned GPRArgRegs[] = {
1634      ARM::R0, ARM::R1, ARM::R2, ARM::R3
1635    };
1636
1637    unsigned NumGPRs = CCInfo.getFirstUnallocated
1638      (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
1639
1640    unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1641    unsigned VARegSize = (4 - NumGPRs) * 4;
1642    unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
1643    unsigned ArgOffset = 0;
1644    if (VARegSaveSize) {
1645      // If this function is vararg, store any remaining integer argument regs
1646      // to their spots on the stack so that they may be loaded by deferencing
1647      // the result of va_next.
1648      AFI->setVarArgsRegSaveSize(VARegSaveSize);
1649      ArgOffset = CCInfo.getNextStackOffset();
1650      VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
1651                                                 VARegSaveSize - VARegSize);
1652      SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
1653
1654      SmallVector<SDValue, 4> MemOps;
1655      for (; NumGPRs < 4; ++NumGPRs) {
1656        TargetRegisterClass *RC;
1657        if (AFI->isThumb1OnlyFunction())
1658          RC = ARM::tGPRRegisterClass;
1659        else
1660          RC = ARM::GPRRegisterClass;
1661
1662        unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
1663        SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1664        SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1665        MemOps.push_back(Store);
1666        FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1667                          DAG.getConstant(4, getPointerTy()));
1668      }
1669      if (!MemOps.empty())
1670        Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1671                            &MemOps[0], MemOps.size());
1672    } else
1673      // This will point to the next argument passed via stack.
1674      VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
1675  }
1676
1677  return Chain;
1678}
1679
1680/// isFloatingPointZero - Return true if this is +0.0.
1681static bool isFloatingPointZero(SDValue Op) {
1682  if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1683    return CFP->getValueAPF().isPosZero();
1684  else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1685    // Maybe this has already been legalized into the constant pool?
1686    if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
1687      SDValue WrapperOp = Op.getOperand(1).getOperand(0);
1688      if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1689        if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1690          return CFP->getValueAPF().isPosZero();
1691    }
1692  }
1693  return false;
1694}
1695
1696static bool isLegalCmpImmediate(unsigned C, bool isThumb1Only) {
1697  return ( isThumb1Only && (C & ~255U) == 0) ||
1698         (!isThumb1Only && ARM_AM::getSOImmVal(C) != -1);
1699}
1700
1701/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1702/// the given operands.
1703static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1704                         SDValue &ARMCC, SelectionDAG &DAG, bool isThumb1Only,
1705                         DebugLoc dl) {
1706  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1707    unsigned C = RHSC->getZExtValue();
1708    if (!isLegalCmpImmediate(C, isThumb1Only)) {
1709      // Constant does not fit, try adjusting it by one?
1710      switch (CC) {
1711      default: break;
1712      case ISD::SETLT:
1713      case ISD::SETGE:
1714        if (isLegalCmpImmediate(C-1, isThumb1Only)) {
1715          CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1716          RHS = DAG.getConstant(C-1, MVT::i32);
1717        }
1718        break;
1719      case ISD::SETULT:
1720      case ISD::SETUGE:
1721        if (C > 0 && isLegalCmpImmediate(C-1, isThumb1Only)) {
1722          CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1723          RHS = DAG.getConstant(C-1, MVT::i32);
1724        }
1725        break;
1726      case ISD::SETLE:
1727      case ISD::SETGT:
1728        if (isLegalCmpImmediate(C+1, isThumb1Only)) {
1729          CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1730          RHS = DAG.getConstant(C+1, MVT::i32);
1731        }
1732        break;
1733      case ISD::SETULE:
1734      case ISD::SETUGT:
1735        if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb1Only)) {
1736          CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1737          RHS = DAG.getConstant(C+1, MVT::i32);
1738        }
1739        break;
1740      }
1741    }
1742  }
1743
1744  ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
1745  ARMISD::NodeType CompareType;
1746  switch (CondCode) {
1747  default:
1748    CompareType = ARMISD::CMP;
1749    break;
1750  case ARMCC::EQ:
1751  case ARMCC::NE:
1752    // Uses only Z Flag
1753    CompareType = ARMISD::CMPZ;
1754    break;
1755  }
1756  ARMCC = DAG.getConstant(CondCode, MVT::i32);
1757  return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
1758}
1759
1760/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1761static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
1762                         DebugLoc dl) {
1763  SDValue Cmp;
1764  if (!isFloatingPointZero(RHS))
1765    Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
1766  else
1767    Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
1768  return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
1769}
1770
1771static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
1772                              const ARMSubtarget *ST) {
1773  EVT VT = Op.getValueType();
1774  SDValue LHS = Op.getOperand(0);
1775  SDValue RHS = Op.getOperand(1);
1776  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1777  SDValue TrueVal = Op.getOperand(2);
1778  SDValue FalseVal = Op.getOperand(3);
1779  DebugLoc dl = Op.getDebugLoc();
1780
1781  if (LHS.getValueType() == MVT::i32) {
1782    SDValue ARMCC;
1783    SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1784    SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb1Only(), dl);
1785    return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
1786  }
1787
1788  ARMCC::CondCodes CondCode, CondCode2;
1789  if (FPCCToARMCC(CC, CondCode, CondCode2))
1790    std::swap(TrueVal, FalseVal);
1791
1792  SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1793  SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1794  SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1795  SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
1796                                 ARMCC, CCR, Cmp);
1797  if (CondCode2 != ARMCC::AL) {
1798    SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
1799    // FIXME: Needs another CMP because flag can have but one use.
1800    SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
1801    Result = DAG.getNode(ARMISD::CMOV, dl, VT,
1802                         Result, TrueVal, ARMCC2, CCR, Cmp2);
1803  }
1804  return Result;
1805}
1806
1807static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
1808                          const ARMSubtarget *ST) {
1809  SDValue  Chain = Op.getOperand(0);
1810  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1811  SDValue    LHS = Op.getOperand(2);
1812  SDValue    RHS = Op.getOperand(3);
1813  SDValue   Dest = Op.getOperand(4);
1814  DebugLoc dl = Op.getDebugLoc();
1815
1816  if (LHS.getValueType() == MVT::i32) {
1817    SDValue ARMCC;
1818    SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1819    SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb1Only(), dl);
1820    return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
1821                       Chain, Dest, ARMCC, CCR,Cmp);
1822  }
1823
1824  assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1825  ARMCC::CondCodes CondCode, CondCode2;
1826  if (FPCCToARMCC(CC, CondCode, CondCode2))
1827    // Swap the LHS/RHS of the comparison if needed.
1828    std::swap(LHS, RHS);
1829
1830  SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1831  SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1832  SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1833  SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1834  SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
1835  SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1836  if (CondCode2 != ARMCC::AL) {
1837    ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1838    SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
1839    Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1840  }
1841  return Res;
1842}
1843
1844SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) {
1845  SDValue Chain = Op.getOperand(0);
1846  SDValue Table = Op.getOperand(1);
1847  SDValue Index = Op.getOperand(2);
1848  DebugLoc dl = Op.getDebugLoc();
1849
1850  EVT PTy = getPointerTy();
1851  JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1852  ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1853  SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
1854  SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1855  Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
1856  Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
1857  SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
1858  if (Subtarget->isThumb2()) {
1859    // Thumb2 uses a two-level jump. That is, it jumps into the jump table
1860    // which does another jump to the destination. This also makes it easier
1861    // to translate it to TBB / TBH later.
1862    // FIXME: This might not work if the function is extremely large.
1863    return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
1864                       Addr, Op.getOperand(2), JTI, UId);
1865  }
1866  if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1867    Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr, NULL, 0);
1868    Chain = Addr.getValue(1);
1869    Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
1870    return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1871  } else {
1872    Addr = DAG.getLoad(PTy, dl, Chain, Addr, NULL, 0);
1873    Chain = Addr.getValue(1);
1874    return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1875  }
1876}
1877
1878static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1879  DebugLoc dl = Op.getDebugLoc();
1880  unsigned Opc =
1881    Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1882  Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
1883  return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
1884}
1885
1886static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1887  EVT VT = Op.getValueType();
1888  DebugLoc dl = Op.getDebugLoc();
1889  unsigned Opc =
1890    Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1891
1892  Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
1893  return DAG.getNode(Opc, dl, VT, Op);
1894}
1895
1896static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
1897  // Implement fcopysign with a fabs and a conditional fneg.
1898  SDValue Tmp0 = Op.getOperand(0);
1899  SDValue Tmp1 = Op.getOperand(1);
1900  DebugLoc dl = Op.getDebugLoc();
1901  EVT VT = Op.getValueType();
1902  EVT SrcVT = Tmp1.getValueType();
1903  SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
1904  SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
1905  SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1906  SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1907  return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
1908}
1909
1910SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
1911  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1912  MFI->setFrameAddressIsTaken(true);
1913  EVT VT = Op.getValueType();
1914  DebugLoc dl = Op.getDebugLoc();  // FIXME probably not meaningful
1915  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1916  unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
1917    ? ARM::R7 : ARM::R11;
1918  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
1919  while (Depth--)
1920    FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
1921  return FrameAddr;
1922}
1923
1924SDValue
1925ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1926                                           SDValue Chain,
1927                                           SDValue Dst, SDValue Src,
1928                                           SDValue Size, unsigned Align,
1929                                           bool AlwaysInline,
1930                                         const Value *DstSV, uint64_t DstSVOff,
1931                                         const Value *SrcSV, uint64_t SrcSVOff){
1932  // Do repeated 4-byte loads and stores. To be improved.
1933  // This requires 4-byte alignment.
1934  if ((Align & 3) != 0)
1935    return SDValue();
1936  // This requires the copy size to be a constant, preferrably
1937  // within a subtarget-specific limit.
1938  ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
1939  if (!ConstantSize)
1940    return SDValue();
1941  uint64_t SizeVal = ConstantSize->getZExtValue();
1942  if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
1943    return SDValue();
1944
1945  unsigned BytesLeft = SizeVal & 3;
1946  unsigned NumMemOps = SizeVal >> 2;
1947  unsigned EmittedNumMemOps = 0;
1948  EVT VT = MVT::i32;
1949  unsigned VTSize = 4;
1950  unsigned i = 0;
1951  const unsigned MAX_LOADS_IN_LDM = 6;
1952  SDValue TFOps[MAX_LOADS_IN_LDM];
1953  SDValue Loads[MAX_LOADS_IN_LDM];
1954  uint64_t SrcOff = 0, DstOff = 0;
1955
1956  // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
1957  // same number of stores.  The loads and stores will get combined into
1958  // ldm/stm later on.
1959  while (EmittedNumMemOps < NumMemOps) {
1960    for (i = 0;
1961         i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1962      Loads[i] = DAG.getLoad(VT, dl, Chain,
1963                             DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
1964                                         DAG.getConstant(SrcOff, MVT::i32)),
1965                             SrcSV, SrcSVOff + SrcOff);
1966      TFOps[i] = Loads[i].getValue(1);
1967      SrcOff += VTSize;
1968    }
1969    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1970
1971    for (i = 0;
1972         i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1973      TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
1974                           DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
1975                                       DAG.getConstant(DstOff, MVT::i32)),
1976                           DstSV, DstSVOff + DstOff);
1977      DstOff += VTSize;
1978    }
1979    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1980
1981    EmittedNumMemOps += i;
1982  }
1983
1984  if (BytesLeft == 0)
1985    return Chain;
1986
1987  // Issue loads / stores for the trailing (1 - 3) bytes.
1988  unsigned BytesLeftSave = BytesLeft;
1989  i = 0;
1990  while (BytesLeft) {
1991    if (BytesLeft >= 2) {
1992      VT = MVT::i16;
1993      VTSize = 2;
1994    } else {
1995      VT = MVT::i8;
1996      VTSize = 1;
1997    }
1998
1999    Loads[i] = DAG.getLoad(VT, dl, Chain,
2000                           DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
2001                                       DAG.getConstant(SrcOff, MVT::i32)),
2002                           SrcSV, SrcSVOff + SrcOff);
2003    TFOps[i] = Loads[i].getValue(1);
2004    ++i;
2005    SrcOff += VTSize;
2006    BytesLeft -= VTSize;
2007  }
2008  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
2009
2010  i = 0;
2011  BytesLeft = BytesLeftSave;
2012  while (BytesLeft) {
2013    if (BytesLeft >= 2) {
2014      VT = MVT::i16;
2015      VTSize = 2;
2016    } else {
2017      VT = MVT::i8;
2018      VTSize = 1;
2019    }
2020
2021    TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
2022                            DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
2023                                        DAG.getConstant(DstOff, MVT::i32)),
2024                            DstSV, DstSVOff + DstOff);
2025    ++i;
2026    DstOff += VTSize;
2027    BytesLeft -= VTSize;
2028  }
2029  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
2030}
2031
2032static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
2033  SDValue Op = N->getOperand(0);
2034  DebugLoc dl = N->getDebugLoc();
2035  if (N->getValueType(0) == MVT::f64) {
2036    // Turn i64->f64 into FMDRR.
2037    SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2038                             DAG.getConstant(0, MVT::i32));
2039    SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2040                             DAG.getConstant(1, MVT::i32));
2041    return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
2042  }
2043
2044  // Turn f64->i64 into FMRRD.
2045  SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl,
2046                            DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2047
2048  // Merge the pieces into a single i64 value.
2049  return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2050}
2051
2052/// getZeroVector - Returns a vector of specified type with all zero elements.
2053///
2054static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2055  assert(VT.isVector() && "Expected a vector type");
2056
2057  // Zero vectors are used to represent vector negation and in those cases
2058  // will be implemented with the NEON VNEG instruction.  However, VNEG does
2059  // not support i64 elements, so sometimes the zero vectors will need to be
2060  // explicitly constructed.  For those cases, and potentially other uses in
2061  // the future, always build zero vectors as <4 x i32> or <2 x i32> bitcasted
2062  // to their dest type.  This ensures they get CSE'd.
2063  SDValue Vec;
2064  SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2065  if (VT.getSizeInBits() == 64)
2066    Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2067  else
2068    Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2069
2070  return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2071}
2072
2073/// getOnesVector - Returns a vector of specified type with all bits set.
2074///
2075static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2076  assert(VT.isVector() && "Expected a vector type");
2077
2078  // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2079  // type.  This ensures they get CSE'd.
2080  SDValue Vec;
2081  SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
2082  if (VT.getSizeInBits() == 64)
2083    Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2084  else
2085    Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2086
2087  return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2088}
2089
2090static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2091                          const ARMSubtarget *ST) {
2092  EVT VT = N->getValueType(0);
2093  DebugLoc dl = N->getDebugLoc();
2094
2095  // Lower vector shifts on NEON to use VSHL.
2096  if (VT.isVector()) {
2097    assert(ST->hasNEON() && "unexpected vector shift");
2098
2099    // Left shifts translate directly to the vshiftu intrinsic.
2100    if (N->getOpcode() == ISD::SHL)
2101      return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2102                         DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2103                         N->getOperand(0), N->getOperand(1));
2104
2105    assert((N->getOpcode() == ISD::SRA ||
2106            N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2107
2108    // NEON uses the same intrinsics for both left and right shifts.  For
2109    // right shifts, the shift amounts are negative, so negate the vector of
2110    // shift amounts.
2111    EVT ShiftVT = N->getOperand(1).getValueType();
2112    SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2113                                       getZeroVector(ShiftVT, DAG, dl),
2114                                       N->getOperand(1));
2115    Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2116                               Intrinsic::arm_neon_vshifts :
2117                               Intrinsic::arm_neon_vshiftu);
2118    return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2119                       DAG.getConstant(vshiftInt, MVT::i32),
2120                       N->getOperand(0), NegatedCount);
2121  }
2122
2123  // We can get here for a node like i32 = ISD::SHL i32, i64
2124  if (VT != MVT::i64)
2125    return SDValue();
2126
2127  assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2128         "Unknown shift to lower!");
2129
2130  // We only lower SRA, SRL of 1 here, all others use generic lowering.
2131  if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2132      cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2133    return SDValue();
2134
2135  // If we are in thumb mode, we don't have RRX.
2136  if (ST->isThumb1Only()) return SDValue();
2137
2138  // Okay, we have a 64-bit SRA or SRL of 1.  Lower this to an RRX expr.
2139  SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2140                             DAG.getConstant(0, MVT::i32));
2141  SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2142                             DAG.getConstant(1, MVT::i32));
2143
2144  // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2145  // captures the result into a carry flag.
2146  unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2147  Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2148
2149  // The low part is an ARMISD::RRX operand, which shifts the carry in.
2150  Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2151
2152  // Merge the pieces into a single i64 value.
2153 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2154}
2155
2156static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2157  SDValue TmpOp0, TmpOp1;
2158  bool Invert = false;
2159  bool Swap = false;
2160  unsigned Opc = 0;
2161
2162  SDValue Op0 = Op.getOperand(0);
2163  SDValue Op1 = Op.getOperand(1);
2164  SDValue CC = Op.getOperand(2);
2165  EVT VT = Op.getValueType();
2166  ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2167  DebugLoc dl = Op.getDebugLoc();
2168
2169  if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2170    switch (SetCCOpcode) {
2171    default: llvm_unreachable("Illegal FP comparison"); break;
2172    case ISD::SETUNE:
2173    case ISD::SETNE:  Invert = true; // Fallthrough
2174    case ISD::SETOEQ:
2175    case ISD::SETEQ:  Opc = ARMISD::VCEQ; break;
2176    case ISD::SETOLT:
2177    case ISD::SETLT: Swap = true; // Fallthrough
2178    case ISD::SETOGT:
2179    case ISD::SETGT:  Opc = ARMISD::VCGT; break;
2180    case ISD::SETOLE:
2181    case ISD::SETLE:  Swap = true; // Fallthrough
2182    case ISD::SETOGE:
2183    case ISD::SETGE: Opc = ARMISD::VCGE; break;
2184    case ISD::SETUGE: Swap = true; // Fallthrough
2185    case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
2186    case ISD::SETUGT: Swap = true; // Fallthrough
2187    case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
2188    case ISD::SETUEQ: Invert = true; // Fallthrough
2189    case ISD::SETONE:
2190      // Expand this to (OLT | OGT).
2191      TmpOp0 = Op0;
2192      TmpOp1 = Op1;
2193      Opc = ISD::OR;
2194      Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2195      Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
2196      break;
2197    case ISD::SETUO: Invert = true; // Fallthrough
2198    case ISD::SETO:
2199      // Expand this to (OLT | OGE).
2200      TmpOp0 = Op0;
2201      TmpOp1 = Op1;
2202      Opc = ISD::OR;
2203      Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2204      Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
2205      break;
2206    }
2207  } else {
2208    // Integer comparisons.
2209    switch (SetCCOpcode) {
2210    default: llvm_unreachable("Illegal integer comparison"); break;
2211    case ISD::SETNE:  Invert = true;
2212    case ISD::SETEQ:  Opc = ARMISD::VCEQ; break;
2213    case ISD::SETLT:  Swap = true;
2214    case ISD::SETGT:  Opc = ARMISD::VCGT; break;
2215    case ISD::SETLE:  Swap = true;
2216    case ISD::SETGE:  Opc = ARMISD::VCGE; break;
2217    case ISD::SETULT: Swap = true;
2218    case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
2219    case ISD::SETULE: Swap = true;
2220    case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
2221    }
2222
2223    // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
2224    if (Opc == ARMISD::VCEQ) {
2225
2226      SDValue AndOp;
2227      if (ISD::isBuildVectorAllZeros(Op1.getNode()))
2228        AndOp = Op0;
2229      else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
2230        AndOp = Op1;
2231
2232      // Ignore bitconvert.
2233      if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
2234        AndOp = AndOp.getOperand(0);
2235
2236      if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
2237        Opc = ARMISD::VTST;
2238        Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
2239        Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
2240        Invert = !Invert;
2241      }
2242    }
2243  }
2244
2245  if (Swap)
2246    std::swap(Op0, Op1);
2247
2248  SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
2249
2250  if (Invert)
2251    Result = DAG.getNOT(dl, Result, VT);
2252
2253  return Result;
2254}
2255
2256/// isVMOVSplat - Check if the specified splat value corresponds to an immediate
2257/// VMOV instruction, and if so, return the constant being splatted.
2258static SDValue isVMOVSplat(uint64_t SplatBits, uint64_t SplatUndef,
2259                           unsigned SplatBitSize, SelectionDAG &DAG) {
2260  switch (SplatBitSize) {
2261  case 8:
2262    // Any 1-byte value is OK.
2263    assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
2264    return DAG.getTargetConstant(SplatBits, MVT::i8);
2265
2266  case 16:
2267    // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
2268    if ((SplatBits & ~0xff) == 0 ||
2269        (SplatBits & ~0xff00) == 0)
2270      return DAG.getTargetConstant(SplatBits, MVT::i16);
2271    break;
2272
2273  case 32:
2274    // NEON's 32-bit VMOV supports splat values where:
2275    // * only one byte is nonzero, or
2276    // * the least significant byte is 0xff and the second byte is nonzero, or
2277    // * the least significant 2 bytes are 0xff and the third is nonzero.
2278    if ((SplatBits & ~0xff) == 0 ||
2279        (SplatBits & ~0xff00) == 0 ||
2280        (SplatBits & ~0xff0000) == 0 ||
2281        (SplatBits & ~0xff000000) == 0)
2282      return DAG.getTargetConstant(SplatBits, MVT::i32);
2283
2284    if ((SplatBits & ~0xffff) == 0 &&
2285        ((SplatBits | SplatUndef) & 0xff) == 0xff)
2286      return DAG.getTargetConstant(SplatBits | 0xff, MVT::i32);
2287
2288    if ((SplatBits & ~0xffffff) == 0 &&
2289        ((SplatBits | SplatUndef) & 0xffff) == 0xffff)
2290      return DAG.getTargetConstant(SplatBits | 0xffff, MVT::i32);
2291
2292    // Note: there are a few 32-bit splat values (specifically: 00ffff00,
2293    // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
2294    // VMOV.I32.  A (very) minor optimization would be to replicate the value
2295    // and fall through here to test for a valid 64-bit splat.  But, then the
2296    // caller would also need to check and handle the change in size.
2297    break;
2298
2299  case 64: {
2300    // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
2301    uint64_t BitMask = 0xff;
2302    uint64_t Val = 0;
2303    for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
2304      if (((SplatBits | SplatUndef) & BitMask) == BitMask)
2305        Val |= BitMask;
2306      else if ((SplatBits & BitMask) != 0)
2307        return SDValue();
2308      BitMask <<= 8;
2309    }
2310    return DAG.getTargetConstant(Val, MVT::i64);
2311  }
2312
2313  default:
2314    llvm_unreachable("unexpected size for isVMOVSplat");
2315    break;
2316  }
2317
2318  return SDValue();
2319}
2320
2321/// getVMOVImm - If this is a build_vector of constants which can be
2322/// formed by using a VMOV instruction of the specified element size,
2323/// return the constant being splatted.  The ByteSize field indicates the
2324/// number of bytes of each element [1248].
2325SDValue ARM::getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2326  BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
2327  APInt SplatBits, SplatUndef;
2328  unsigned SplatBitSize;
2329  bool HasAnyUndefs;
2330  if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
2331                                      HasAnyUndefs, ByteSize * 8))
2332    return SDValue();
2333
2334  if (SplatBitSize > ByteSize * 8)
2335    return SDValue();
2336
2337  return isVMOVSplat(SplatBits.getZExtValue(), SplatUndef.getZExtValue(),
2338                     SplatBitSize, DAG);
2339}
2340
2341static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
2342                       bool &ReverseVEXT, unsigned &Imm) {
2343  unsigned NumElts = VT.getVectorNumElements();
2344  ReverseVEXT = false;
2345  Imm = M[0];
2346
2347  // If this is a VEXT shuffle, the immediate value is the index of the first
2348  // element.  The other shuffle indices must be the successive elements after
2349  // the first one.
2350  unsigned ExpectedElt = Imm;
2351  for (unsigned i = 1; i < NumElts; ++i) {
2352    // Increment the expected index.  If it wraps around, it may still be
2353    // a VEXT but the source vectors must be swapped.
2354    ExpectedElt += 1;
2355    if (ExpectedElt == NumElts * 2) {
2356      ExpectedElt = 0;
2357      ReverseVEXT = true;
2358    }
2359
2360    if (ExpectedElt != static_cast<unsigned>(M[i]))
2361      return false;
2362  }
2363
2364  // Adjust the index value if the source operands will be swapped.
2365  if (ReverseVEXT)
2366    Imm -= NumElts;
2367
2368  return true;
2369}
2370
2371/// isVREVMask - Check if a vector shuffle corresponds to a VREV
2372/// instruction with the specified blocksize.  (The order of the elements
2373/// within each block of the vector is reversed.)
2374static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
2375                       unsigned BlockSize) {
2376  assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
2377         "Only possible block sizes for VREV are: 16, 32, 64");
2378
2379  unsigned NumElts = VT.getVectorNumElements();
2380  unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2381  unsigned BlockElts = M[0] + 1;
2382
2383  if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
2384    return false;
2385
2386  for (unsigned i = 0; i < NumElts; ++i) {
2387    if ((unsigned) M[i] !=
2388        (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
2389      return false;
2390  }
2391
2392  return true;
2393}
2394
2395static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
2396                       unsigned &WhichResult) {
2397  unsigned NumElts = VT.getVectorNumElements();
2398  WhichResult = (M[0] == 0 ? 0 : 1);
2399  for (unsigned i = 0; i < NumElts; i += 2) {
2400    if ((unsigned) M[i] != i + WhichResult ||
2401        (unsigned) M[i+1] != i + NumElts + WhichResult)
2402      return false;
2403  }
2404  return true;
2405}
2406
2407static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
2408                       unsigned &WhichResult) {
2409  unsigned NumElts = VT.getVectorNumElements();
2410  WhichResult = (M[0] == 0 ? 0 : 1);
2411  for (unsigned i = 0; i != NumElts; ++i) {
2412    if ((unsigned) M[i] != 2 * i + WhichResult)
2413      return false;
2414  }
2415
2416  // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
2417  if (VT.is64BitVector() && VT.getVectorElementType().getSizeInBits() == 32)
2418    return false;
2419
2420  return true;
2421}
2422
2423static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
2424                       unsigned &WhichResult) {
2425  unsigned NumElts = VT.getVectorNumElements();
2426  WhichResult = (M[0] == 0 ? 0 : 1);
2427  unsigned Idx = WhichResult * NumElts / 2;
2428  for (unsigned i = 0; i != NumElts; i += 2) {
2429    if ((unsigned) M[i] != Idx ||
2430        (unsigned) M[i+1] != Idx + NumElts)
2431      return false;
2432    Idx += 1;
2433  }
2434
2435  // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
2436  if (VT.is64BitVector() && VT.getVectorElementType().getSizeInBits() == 32)
2437    return false;
2438
2439  return true;
2440}
2441
2442static SDValue BuildSplat(SDValue Val, EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2443  // Canonicalize all-zeros and all-ones vectors.
2444  ConstantSDNode *ConstVal = cast<ConstantSDNode>(Val.getNode());
2445  if (ConstVal->isNullValue())
2446    return getZeroVector(VT, DAG, dl);
2447  if (ConstVal->isAllOnesValue())
2448    return getOnesVector(VT, DAG, dl);
2449
2450  EVT CanonicalVT;
2451  if (VT.is64BitVector()) {
2452    switch (Val.getValueType().getSizeInBits()) {
2453    case 8:  CanonicalVT = MVT::v8i8; break;
2454    case 16: CanonicalVT = MVT::v4i16; break;
2455    case 32: CanonicalVT = MVT::v2i32; break;
2456    case 64: CanonicalVT = MVT::v1i64; break;
2457    default: llvm_unreachable("unexpected splat element type"); break;
2458    }
2459  } else {
2460    assert(VT.is128BitVector() && "unknown splat vector size");
2461    switch (Val.getValueType().getSizeInBits()) {
2462    case 8:  CanonicalVT = MVT::v16i8; break;
2463    case 16: CanonicalVT = MVT::v8i16; break;
2464    case 32: CanonicalVT = MVT::v4i32; break;
2465    case 64: CanonicalVT = MVT::v2i64; break;
2466    default: llvm_unreachable("unexpected splat element type"); break;
2467    }
2468  }
2469
2470  // Build a canonical splat for this value.
2471  SmallVector<SDValue, 8> Ops;
2472  Ops.assign(CanonicalVT.getVectorNumElements(), Val);
2473  SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, &Ops[0],
2474                            Ops.size());
2475  return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Res);
2476}
2477
2478// If this is a case we can't handle, return null and let the default
2479// expansion code take care of it.
2480static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
2481  BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
2482  DebugLoc dl = Op.getDebugLoc();
2483  EVT VT = Op.getValueType();
2484
2485  APInt SplatBits, SplatUndef;
2486  unsigned SplatBitSize;
2487  bool HasAnyUndefs;
2488  if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
2489    SDValue Val = isVMOVSplat(SplatBits.getZExtValue(),
2490                              SplatUndef.getZExtValue(), SplatBitSize, DAG);
2491    if (Val.getNode())
2492      return BuildSplat(Val, VT, DAG, dl);
2493  }
2494
2495  // If there are only 2 elements in a 128-bit vector, insert them into an
2496  // undef vector.  This handles the common case for 128-bit vector argument
2497  // passing, where the insertions should be translated to subreg accesses
2498  // with no real instructions.
2499  if (VT.is128BitVector() && Op.getNumOperands() == 2) {
2500    SDValue Val = DAG.getUNDEF(VT);
2501    SDValue Op0 = Op.getOperand(0);
2502    SDValue Op1 = Op.getOperand(1);
2503    if (Op0.getOpcode() != ISD::UNDEF)
2504      Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op0,
2505                        DAG.getIntPtrConstant(0));
2506    if (Op1.getOpcode() != ISD::UNDEF)
2507      Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op1,
2508                        DAG.getIntPtrConstant(1));
2509    return Val;
2510  }
2511
2512  return SDValue();
2513}
2514
2515/// isShuffleMaskLegal - Targets can use this to indicate that they only
2516/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
2517/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
2518/// are assumed to be legal.
2519bool
2520ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
2521                                      EVT VT) const {
2522  if (VT.getVectorNumElements() == 4 &&
2523      (VT.is128BitVector() || VT.is64BitVector())) {
2524    unsigned PFIndexes[4];
2525    for (unsigned i = 0; i != 4; ++i) {
2526      if (M[i] < 0)
2527        PFIndexes[i] = 8;
2528      else
2529        PFIndexes[i] = M[i];
2530    }
2531
2532    // Compute the index in the perfect shuffle table.
2533    unsigned PFTableIndex =
2534      PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2535    unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2536    unsigned Cost = (PFEntry >> 30);
2537
2538    if (Cost <= 4)
2539      return true;
2540  }
2541
2542  bool ReverseVEXT;
2543  unsigned Imm, WhichResult;
2544
2545  return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
2546          isVREVMask(M, VT, 64) ||
2547          isVREVMask(M, VT, 32) ||
2548          isVREVMask(M, VT, 16) ||
2549          isVEXTMask(M, VT, ReverseVEXT, Imm) ||
2550          isVTRNMask(M, VT, WhichResult) ||
2551          isVUZPMask(M, VT, WhichResult) ||
2552          isVZIPMask(M, VT, WhichResult));
2553}
2554
2555/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
2556/// the specified operations to build the shuffle.
2557static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
2558                                      SDValue RHS, SelectionDAG &DAG,
2559                                      DebugLoc dl) {
2560  unsigned OpNum = (PFEntry >> 26) & 0x0F;
2561  unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
2562  unsigned RHSID = (PFEntry >>  0) & ((1 << 13)-1);
2563
2564  enum {
2565    OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
2566    OP_VREV,
2567    OP_VDUP0,
2568    OP_VDUP1,
2569    OP_VDUP2,
2570    OP_VDUP3,
2571    OP_VEXT1,
2572    OP_VEXT2,
2573    OP_VEXT3,
2574    OP_VUZPL, // VUZP, left result
2575    OP_VUZPR, // VUZP, right result
2576    OP_VZIPL, // VZIP, left result
2577    OP_VZIPR, // VZIP, right result
2578    OP_VTRNL, // VTRN, left result
2579    OP_VTRNR  // VTRN, right result
2580  };
2581
2582  if (OpNum == OP_COPY) {
2583    if (LHSID == (1*9+2)*9+3) return LHS;
2584    assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
2585    return RHS;
2586  }
2587
2588  SDValue OpLHS, OpRHS;
2589  OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
2590  OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
2591  EVT VT = OpLHS.getValueType();
2592
2593  switch (OpNum) {
2594  default: llvm_unreachable("Unknown shuffle opcode!");
2595  case OP_VREV:
2596    return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
2597  case OP_VDUP0:
2598  case OP_VDUP1:
2599  case OP_VDUP2:
2600  case OP_VDUP3:
2601    return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
2602                       OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
2603  case OP_VEXT1:
2604  case OP_VEXT2:
2605  case OP_VEXT3:
2606    return DAG.getNode(ARMISD::VEXT, dl, VT,
2607                       OpLHS, OpRHS,
2608                       DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
2609  case OP_VUZPL:
2610  case OP_VUZPR:
2611    return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
2612                       OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
2613  case OP_VZIPL:
2614  case OP_VZIPR:
2615    return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
2616                       OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
2617  case OP_VTRNL:
2618  case OP_VTRNR:
2619    return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
2620                       OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
2621  }
2622}
2623
2624static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
2625  SDValue V1 = Op.getOperand(0);
2626  SDValue V2 = Op.getOperand(1);
2627  DebugLoc dl = Op.getDebugLoc();
2628  EVT VT = Op.getValueType();
2629  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
2630  SmallVector<int, 8> ShuffleMask;
2631
2632  // Convert shuffles that are directly supported on NEON to target-specific
2633  // DAG nodes, instead of keeping them as shuffles and matching them again
2634  // during code selection.  This is more efficient and avoids the possibility
2635  // of inconsistencies between legalization and selection.
2636  // FIXME: floating-point vectors should be canonicalized to integer vectors
2637  // of the same time so that they get CSEd properly.
2638  SVN->getMask(ShuffleMask);
2639
2640  if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
2641    int Lane = SVN->getSplatIndex();
2642    if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
2643      return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
2644    }
2645    return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
2646                       DAG.getConstant(Lane, MVT::i32));
2647  }
2648
2649  bool ReverseVEXT;
2650  unsigned Imm;
2651  if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
2652    if (ReverseVEXT)
2653      std::swap(V1, V2);
2654    return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
2655                       DAG.getConstant(Imm, MVT::i32));
2656  }
2657
2658  if (isVREVMask(ShuffleMask, VT, 64))
2659    return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
2660  if (isVREVMask(ShuffleMask, VT, 32))
2661    return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
2662  if (isVREVMask(ShuffleMask, VT, 16))
2663    return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
2664
2665  // Check for Neon shuffles that modify both input vectors in place.
2666  // If both results are used, i.e., if there are two shuffles with the same
2667  // source operands and with masks corresponding to both results of one of
2668  // these operations, DAG memoization will ensure that a single node is
2669  // used for both shuffles.
2670  unsigned WhichResult;
2671  if (isVTRNMask(ShuffleMask, VT, WhichResult))
2672    return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
2673                       V1, V2).getValue(WhichResult);
2674  if (isVUZPMask(ShuffleMask, VT, WhichResult))
2675    return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
2676                       V1, V2).getValue(WhichResult);
2677  if (isVZIPMask(ShuffleMask, VT, WhichResult))
2678    return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
2679                       V1, V2).getValue(WhichResult);
2680
2681  // If the shuffle is not directly supported and it has 4 elements, use
2682  // the PerfectShuffle-generated table to synthesize it from other shuffles.
2683  if (VT.getVectorNumElements() == 4 &&
2684      (VT.is128BitVector() || VT.is64BitVector())) {
2685    unsigned PFIndexes[4];
2686    for (unsigned i = 0; i != 4; ++i) {
2687      if (ShuffleMask[i] < 0)
2688        PFIndexes[i] = 8;
2689      else
2690        PFIndexes[i] = ShuffleMask[i];
2691    }
2692
2693    // Compute the index in the perfect shuffle table.
2694    unsigned PFTableIndex =
2695      PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2696
2697    unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2698    unsigned Cost = (PFEntry >> 30);
2699
2700    if (Cost <= 4)
2701      return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
2702  }
2703
2704  return SDValue();
2705}
2706
2707static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
2708  EVT VT = Op.getValueType();
2709  DebugLoc dl = Op.getDebugLoc();
2710  assert((VT == MVT::i8 || VT == MVT::i16) &&
2711         "unexpected type for custom-lowering vector extract");
2712  SDValue Vec = Op.getOperand(0);
2713  SDValue Lane = Op.getOperand(1);
2714  Op = DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
2715  Op = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Op, DAG.getValueType(VT));
2716  return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
2717}
2718
2719static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
2720  // The only time a CONCAT_VECTORS operation can have legal types is when
2721  // two 64-bit vectors are concatenated to a 128-bit vector.
2722  assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
2723         "unexpected CONCAT_VECTORS");
2724  DebugLoc dl = Op.getDebugLoc();
2725  SDValue Val = DAG.getUNDEF(MVT::v2f64);
2726  SDValue Op0 = Op.getOperand(0);
2727  SDValue Op1 = Op.getOperand(1);
2728  if (Op0.getOpcode() != ISD::UNDEF)
2729    Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
2730                      DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
2731                      DAG.getIntPtrConstant(0));
2732  if (Op1.getOpcode() != ISD::UNDEF)
2733    Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
2734                      DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
2735                      DAG.getIntPtrConstant(1));
2736  return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
2737}
2738
2739SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
2740  switch (Op.getOpcode()) {
2741  default: llvm_unreachable("Don't know how to custom lower this!");
2742  case ISD::ConstantPool:  return LowerConstantPool(Op, DAG);
2743  case ISD::GlobalAddress:
2744    return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
2745      LowerGlobalAddressELF(Op, DAG);
2746  case ISD::GlobalTLSAddress:   return LowerGlobalTLSAddress(Op, DAG);
2747  case ISD::SELECT_CC:     return LowerSELECT_CC(Op, DAG, Subtarget);
2748  case ISD::BR_CC:         return LowerBR_CC(Op, DAG, Subtarget);
2749  case ISD::BR_JT:         return LowerBR_JT(Op, DAG);
2750  case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
2751  case ISD::VASTART:       return LowerVASTART(Op, DAG, VarArgsFrameIndex);
2752  case ISD::SINT_TO_FP:
2753  case ISD::UINT_TO_FP:    return LowerINT_TO_FP(Op, DAG);
2754  case ISD::FP_TO_SINT:
2755  case ISD::FP_TO_UINT:    return LowerFP_TO_INT(Op, DAG);
2756  case ISD::FCOPYSIGN:     return LowerFCOPYSIGN(Op, DAG);
2757  case ISD::RETURNADDR:    break;
2758  case ISD::FRAMEADDR:     return LowerFRAMEADDR(Op, DAG);
2759  case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
2760  case ISD::INTRINSIC_VOID:
2761  case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
2762  case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2763  case ISD::BIT_CONVERT:   return ExpandBIT_CONVERT(Op.getNode(), DAG);
2764  case ISD::SHL:
2765  case ISD::SRL:
2766  case ISD::SRA:           return LowerShift(Op.getNode(), DAG, Subtarget);
2767  case ISD::VSETCC:        return LowerVSETCC(Op, DAG);
2768  case ISD::BUILD_VECTOR:  return LowerBUILD_VECTOR(Op, DAG);
2769  case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2770  case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2771  case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
2772  }
2773  return SDValue();
2774}
2775
2776/// ReplaceNodeResults - Replace the results of node with an illegal result
2777/// type with new values built out of custom code.
2778void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
2779                                           SmallVectorImpl<SDValue>&Results,
2780                                           SelectionDAG &DAG) {
2781  switch (N->getOpcode()) {
2782  default:
2783    llvm_unreachable("Don't know how to custom expand this!");
2784    return;
2785  case ISD::BIT_CONVERT:
2786    Results.push_back(ExpandBIT_CONVERT(N, DAG));
2787    return;
2788  case ISD::SRL:
2789  case ISD::SRA: {
2790    SDValue Res = LowerShift(N, DAG, Subtarget);
2791    if (Res.getNode())
2792      Results.push_back(Res);
2793    return;
2794  }
2795  }
2796}
2797
2798//===----------------------------------------------------------------------===//
2799//                           ARM Scheduler Hooks
2800//===----------------------------------------------------------------------===//
2801
2802MachineBasicBlock *
2803ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
2804                                               MachineBasicBlock *BB) const {
2805  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2806  DebugLoc dl = MI->getDebugLoc();
2807  switch (MI->getOpcode()) {
2808  default:
2809    llvm_unreachable("Unexpected instr type to insert");
2810  case ARM::tMOVCCr_pseudo: {
2811    // To "insert" a SELECT_CC instruction, we actually have to insert the
2812    // diamond control-flow pattern.  The incoming instruction knows the
2813    // destination vreg to set, the condition code register to branch on, the
2814    // true/false values to select between, and a branch opcode to use.
2815    const BasicBlock *LLVM_BB = BB->getBasicBlock();
2816    MachineFunction::iterator It = BB;
2817    ++It;
2818
2819    //  thisMBB:
2820    //  ...
2821    //   TrueVal = ...
2822    //   cmpTY ccX, r1, r2
2823    //   bCC copy1MBB
2824    //   fallthrough --> copy0MBB
2825    MachineBasicBlock *thisMBB  = BB;
2826    MachineFunction *F = BB->getParent();
2827    MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
2828    MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
2829    BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
2830      .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
2831    F->insert(It, copy0MBB);
2832    F->insert(It, sinkMBB);
2833    // Update machine-CFG edges by first adding all successors of the current
2834    // block to the new block which will contain the Phi node for the select.
2835    for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
2836        e = BB->succ_end(); i != e; ++i)
2837      sinkMBB->addSuccessor(*i);
2838    // Next, remove all successors of the current block, and add the true
2839    // and fallthrough blocks as its successors.
2840    while(!BB->succ_empty())
2841      BB->removeSuccessor(BB->succ_begin());
2842    BB->addSuccessor(copy0MBB);
2843    BB->addSuccessor(sinkMBB);
2844
2845    //  copy0MBB:
2846    //   %FalseValue = ...
2847    //   # fallthrough to sinkMBB
2848    BB = copy0MBB;
2849
2850    // Update machine-CFG edges
2851    BB->addSuccessor(sinkMBB);
2852
2853    //  sinkMBB:
2854    //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2855    //  ...
2856    BB = sinkMBB;
2857    BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg())
2858      .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
2859      .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
2860
2861    F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
2862    return BB;
2863  }
2864
2865  case ARM::tANDsp:
2866  case ARM::tADDspr_:
2867  case ARM::tSUBspi_:
2868  case ARM::t2SUBrSPi_:
2869  case ARM::t2SUBrSPi12_:
2870  case ARM::t2SUBrSPs_: {
2871    MachineFunction *MF = BB->getParent();
2872    unsigned DstReg = MI->getOperand(0).getReg();
2873    unsigned SrcReg = MI->getOperand(1).getReg();
2874    bool DstIsDead = MI->getOperand(0).isDead();
2875    bool SrcIsKill = MI->getOperand(1).isKill();
2876
2877    if (SrcReg != ARM::SP) {
2878      // Copy the source to SP from virtual register.
2879      const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg);
2880      unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
2881        ? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr;
2882      BuildMI(BB, dl, TII->get(CopyOpc), ARM::SP)
2883        .addReg(SrcReg, getKillRegState(SrcIsKill));
2884    }
2885
2886    unsigned OpOpc = 0;
2887    bool NeedPred = false, NeedCC = false, NeedOp3 = false;
2888    switch (MI->getOpcode()) {
2889    default:
2890      llvm_unreachable("Unexpected pseudo instruction!");
2891    case ARM::tANDsp:
2892      OpOpc = ARM::tAND;
2893      NeedPred = true;
2894      break;
2895    case ARM::tADDspr_:
2896      OpOpc = ARM::tADDspr;
2897      break;
2898    case ARM::tSUBspi_:
2899      OpOpc = ARM::tSUBspi;
2900      break;
2901    case ARM::t2SUBrSPi_:
2902      OpOpc = ARM::t2SUBrSPi;
2903      NeedPred = true; NeedCC = true;
2904      break;
2905    case ARM::t2SUBrSPi12_:
2906      OpOpc = ARM::t2SUBrSPi12;
2907      NeedPred = true;
2908      break;
2909    case ARM::t2SUBrSPs_:
2910      OpOpc = ARM::t2SUBrSPs;
2911      NeedPred = true; NeedCC = true; NeedOp3 = true;
2912      break;
2913    }
2914    MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(OpOpc), ARM::SP);
2915    if (OpOpc == ARM::tAND)
2916      AddDefaultT1CC(MIB);
2917    MIB.addReg(ARM::SP);
2918    MIB.addOperand(MI->getOperand(2));
2919    if (NeedOp3)
2920      MIB.addOperand(MI->getOperand(3));
2921    if (NeedPred)
2922      AddDefaultPred(MIB);
2923    if (NeedCC)
2924      AddDefaultCC(MIB);
2925
2926    // Copy the result from SP to virtual register.
2927    const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg);
2928    unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
2929      ? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr;
2930    BuildMI(BB, dl, TII->get(CopyOpc))
2931      .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
2932      .addReg(ARM::SP);
2933    MF->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
2934    return BB;
2935  }
2936  }
2937}
2938
2939//===----------------------------------------------------------------------===//
2940//                           ARM Optimization Hooks
2941//===----------------------------------------------------------------------===//
2942
2943static
2944SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
2945                            TargetLowering::DAGCombinerInfo &DCI) {
2946  SelectionDAG &DAG = DCI.DAG;
2947  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2948  EVT VT = N->getValueType(0);
2949  unsigned Opc = N->getOpcode();
2950  bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
2951  SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
2952  SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
2953  ISD::CondCode CC = ISD::SETCC_INVALID;
2954
2955  if (isSlctCC) {
2956    CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
2957  } else {
2958    SDValue CCOp = Slct.getOperand(0);
2959    if (CCOp.getOpcode() == ISD::SETCC)
2960      CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
2961  }
2962
2963  bool DoXform = false;
2964  bool InvCC = false;
2965  assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
2966          "Bad input!");
2967
2968  if (LHS.getOpcode() == ISD::Constant &&
2969      cast<ConstantSDNode>(LHS)->isNullValue()) {
2970    DoXform = true;
2971  } else if (CC != ISD::SETCC_INVALID &&
2972             RHS.getOpcode() == ISD::Constant &&
2973             cast<ConstantSDNode>(RHS)->isNullValue()) {
2974    std::swap(LHS, RHS);
2975    SDValue Op0 = Slct.getOperand(0);
2976    EVT OpVT = isSlctCC ? Op0.getValueType() :
2977                          Op0.getOperand(0).getValueType();
2978    bool isInt = OpVT.isInteger();
2979    CC = ISD::getSetCCInverse(CC, isInt);
2980
2981    if (!TLI.isCondCodeLegal(CC, OpVT))
2982      return SDValue();         // Inverse operator isn't legal.
2983
2984    DoXform = true;
2985    InvCC = true;
2986  }
2987
2988  if (DoXform) {
2989    SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
2990    if (isSlctCC)
2991      return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
2992                             Slct.getOperand(0), Slct.getOperand(1), CC);
2993    SDValue CCOp = Slct.getOperand(0);
2994    if (InvCC)
2995      CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
2996                          CCOp.getOperand(0), CCOp.getOperand(1), CC);
2997    return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
2998                       CCOp, OtherOp, Result);
2999  }
3000  return SDValue();
3001}
3002
3003/// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
3004static SDValue PerformADDCombine(SDNode *N,
3005                                 TargetLowering::DAGCombinerInfo &DCI) {
3006  // added by evan in r37685 with no testcase.
3007  SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
3008
3009  // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
3010  if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
3011    SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
3012    if (Result.getNode()) return Result;
3013  }
3014  if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
3015    SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
3016    if (Result.getNode()) return Result;
3017  }
3018
3019  return SDValue();
3020}
3021
3022/// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
3023static SDValue PerformSUBCombine(SDNode *N,
3024                                 TargetLowering::DAGCombinerInfo &DCI) {
3025  // added by evan in r37685 with no testcase.
3026  SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
3027
3028  // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
3029  if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
3030    SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
3031    if (Result.getNode()) return Result;
3032  }
3033
3034  return SDValue();
3035}
3036
3037
3038/// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD.
3039static SDValue PerformFMRRDCombine(SDNode *N,
3040                                   TargetLowering::DAGCombinerInfo &DCI) {
3041  // fmrrd(fmdrr x, y) -> x,y
3042  SDValue InDouble = N->getOperand(0);
3043  if (InDouble.getOpcode() == ARMISD::FMDRR)
3044    return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
3045  return SDValue();
3046}
3047
3048/// getVShiftImm - Check if this is a valid build_vector for the immediate
3049/// operand of a vector shift operation, where all the elements of the
3050/// build_vector must have the same constant integer value.
3051static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
3052  // Ignore bit_converts.
3053  while (Op.getOpcode() == ISD::BIT_CONVERT)
3054    Op = Op.getOperand(0);
3055  BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
3056  APInt SplatBits, SplatUndef;
3057  unsigned SplatBitSize;
3058  bool HasAnyUndefs;
3059  if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
3060                                      HasAnyUndefs, ElementBits) ||
3061      SplatBitSize > ElementBits)
3062    return false;
3063  Cnt = SplatBits.getSExtValue();
3064  return true;
3065}
3066
3067/// isVShiftLImm - Check if this is a valid build_vector for the immediate
3068/// operand of a vector shift left operation.  That value must be in the range:
3069///   0 <= Value < ElementBits for a left shift; or
3070///   0 <= Value <= ElementBits for a long left shift.
3071static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
3072  assert(VT.isVector() && "vector shift count is not a vector type");
3073  unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
3074  if (! getVShiftImm(Op, ElementBits, Cnt))
3075    return false;
3076  return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
3077}
3078
3079/// isVShiftRImm - Check if this is a valid build_vector for the immediate
3080/// operand of a vector shift right operation.  For a shift opcode, the value
3081/// is positive, but for an intrinsic the value count must be negative. The
3082/// absolute value must be in the range:
3083///   1 <= |Value| <= ElementBits for a right shift; or
3084///   1 <= |Value| <= ElementBits/2 for a narrow right shift.
3085static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
3086                         int64_t &Cnt) {
3087  assert(VT.isVector() && "vector shift count is not a vector type");
3088  unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
3089  if (! getVShiftImm(Op, ElementBits, Cnt))
3090    return false;
3091  if (isIntrinsic)
3092    Cnt = -Cnt;
3093  return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
3094}
3095
3096/// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
3097static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
3098  unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3099  switch (IntNo) {
3100  default:
3101    // Don't do anything for most intrinsics.
3102    break;
3103
3104  // Vector shifts: check for immediate versions and lower them.
3105  // Note: This is done during DAG combining instead of DAG legalizing because
3106  // the build_vectors for 64-bit vector element shift counts are generally
3107  // not legal, and it is hard to see their values after they get legalized to
3108  // loads from a constant pool.
3109  case Intrinsic::arm_neon_vshifts:
3110  case Intrinsic::arm_neon_vshiftu:
3111  case Intrinsic::arm_neon_vshiftls:
3112  case Intrinsic::arm_neon_vshiftlu:
3113  case Intrinsic::arm_neon_vshiftn:
3114  case Intrinsic::arm_neon_vrshifts:
3115  case Intrinsic::arm_neon_vrshiftu:
3116  case Intrinsic::arm_neon_vrshiftn:
3117  case Intrinsic::arm_neon_vqshifts:
3118  case Intrinsic::arm_neon_vqshiftu:
3119  case Intrinsic::arm_neon_vqshiftsu:
3120  case Intrinsic::arm_neon_vqshiftns:
3121  case Intrinsic::arm_neon_vqshiftnu:
3122  case Intrinsic::arm_neon_vqshiftnsu:
3123  case Intrinsic::arm_neon_vqrshiftns:
3124  case Intrinsic::arm_neon_vqrshiftnu:
3125  case Intrinsic::arm_neon_vqrshiftnsu: {
3126    EVT VT = N->getOperand(1).getValueType();
3127    int64_t Cnt;
3128    unsigned VShiftOpc = 0;
3129
3130    switch (IntNo) {
3131    case Intrinsic::arm_neon_vshifts:
3132    case Intrinsic::arm_neon_vshiftu:
3133      if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
3134        VShiftOpc = ARMISD::VSHL;
3135        break;
3136      }
3137      if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
3138        VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
3139                     ARMISD::VSHRs : ARMISD::VSHRu);
3140        break;
3141      }
3142      return SDValue();
3143
3144    case Intrinsic::arm_neon_vshiftls:
3145    case Intrinsic::arm_neon_vshiftlu:
3146      if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
3147        break;
3148      llvm_unreachable("invalid shift count for vshll intrinsic");
3149
3150    case Intrinsic::arm_neon_vrshifts:
3151    case Intrinsic::arm_neon_vrshiftu:
3152      if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
3153        break;
3154      return SDValue();
3155
3156    case Intrinsic::arm_neon_vqshifts:
3157    case Intrinsic::arm_neon_vqshiftu:
3158      if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
3159        break;
3160      return SDValue();
3161
3162    case Intrinsic::arm_neon_vqshiftsu:
3163      if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
3164        break;
3165      llvm_unreachable("invalid shift count for vqshlu intrinsic");
3166
3167    case Intrinsic::arm_neon_vshiftn:
3168    case Intrinsic::arm_neon_vrshiftn:
3169    case Intrinsic::arm_neon_vqshiftns:
3170    case Intrinsic::arm_neon_vqshiftnu:
3171    case Intrinsic::arm_neon_vqshiftnsu:
3172    case Intrinsic::arm_neon_vqrshiftns:
3173    case Intrinsic::arm_neon_vqrshiftnu:
3174    case Intrinsic::arm_neon_vqrshiftnsu:
3175      // Narrowing shifts require an immediate right shift.
3176      if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
3177        break;
3178      llvm_unreachable("invalid shift count for narrowing vector shift intrinsic");
3179
3180    default:
3181      llvm_unreachable("unhandled vector shift");
3182    }
3183
3184    switch (IntNo) {
3185    case Intrinsic::arm_neon_vshifts:
3186    case Intrinsic::arm_neon_vshiftu:
3187      // Opcode already set above.
3188      break;
3189    case Intrinsic::arm_neon_vshiftls:
3190    case Intrinsic::arm_neon_vshiftlu:
3191      if (Cnt == VT.getVectorElementType().getSizeInBits())
3192        VShiftOpc = ARMISD::VSHLLi;
3193      else
3194        VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
3195                     ARMISD::VSHLLs : ARMISD::VSHLLu);
3196      break;
3197    case Intrinsic::arm_neon_vshiftn:
3198      VShiftOpc = ARMISD::VSHRN; break;
3199    case Intrinsic::arm_neon_vrshifts:
3200      VShiftOpc = ARMISD::VRSHRs; break;
3201    case Intrinsic::arm_neon_vrshiftu:
3202      VShiftOpc = ARMISD::VRSHRu; break;
3203    case Intrinsic::arm_neon_vrshiftn:
3204      VShiftOpc = ARMISD::VRSHRN; break;
3205    case Intrinsic::arm_neon_vqshifts:
3206      VShiftOpc = ARMISD::VQSHLs; break;
3207    case Intrinsic::arm_neon_vqshiftu:
3208      VShiftOpc = ARMISD::VQSHLu; break;
3209    case Intrinsic::arm_neon_vqshiftsu:
3210      VShiftOpc = ARMISD::VQSHLsu; break;
3211    case Intrinsic::arm_neon_vqshiftns:
3212      VShiftOpc = ARMISD::VQSHRNs; break;
3213    case Intrinsic::arm_neon_vqshiftnu:
3214      VShiftOpc = ARMISD::VQSHRNu; break;
3215    case Intrinsic::arm_neon_vqshiftnsu:
3216      VShiftOpc = ARMISD::VQSHRNsu; break;
3217    case Intrinsic::arm_neon_vqrshiftns:
3218      VShiftOpc = ARMISD::VQRSHRNs; break;
3219    case Intrinsic::arm_neon_vqrshiftnu:
3220      VShiftOpc = ARMISD::VQRSHRNu; break;
3221    case Intrinsic::arm_neon_vqrshiftnsu:
3222      VShiftOpc = ARMISD::VQRSHRNsu; break;
3223    }
3224
3225    return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
3226                       N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
3227  }
3228
3229  case Intrinsic::arm_neon_vshiftins: {
3230    EVT VT = N->getOperand(1).getValueType();
3231    int64_t Cnt;
3232    unsigned VShiftOpc = 0;
3233
3234    if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
3235      VShiftOpc = ARMISD::VSLI;
3236    else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
3237      VShiftOpc = ARMISD::VSRI;
3238    else {
3239      llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
3240    }
3241
3242    return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
3243                       N->getOperand(1), N->getOperand(2),
3244                       DAG.getConstant(Cnt, MVT::i32));
3245  }
3246
3247  case Intrinsic::arm_neon_vqrshifts:
3248  case Intrinsic::arm_neon_vqrshiftu:
3249    // No immediate versions of these to check for.
3250    break;
3251  }
3252
3253  return SDValue();
3254}
3255
3256/// PerformShiftCombine - Checks for immediate versions of vector shifts and
3257/// lowers them.  As with the vector shift intrinsics, this is done during DAG
3258/// combining instead of DAG legalizing because the build_vectors for 64-bit
3259/// vector element shift counts are generally not legal, and it is hard to see
3260/// their values after they get legalized to loads from a constant pool.
3261static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
3262                                   const ARMSubtarget *ST) {
3263  EVT VT = N->getValueType(0);
3264
3265  // Nothing to be done for scalar shifts.
3266  if (! VT.isVector())
3267    return SDValue();
3268
3269  assert(ST->hasNEON() && "unexpected vector shift");
3270  int64_t Cnt;
3271
3272  switch (N->getOpcode()) {
3273  default: llvm_unreachable("unexpected shift opcode");
3274
3275  case ISD::SHL:
3276    if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
3277      return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
3278                         DAG.getConstant(Cnt, MVT::i32));
3279    break;
3280
3281  case ISD::SRA:
3282  case ISD::SRL:
3283    if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
3284      unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
3285                            ARMISD::VSHRs : ARMISD::VSHRu);
3286      return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
3287                         DAG.getConstant(Cnt, MVT::i32));
3288    }
3289  }
3290  return SDValue();
3291}
3292
3293/// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
3294/// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
3295static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
3296                                    const ARMSubtarget *ST) {
3297  SDValue N0 = N->getOperand(0);
3298
3299  // Check for sign- and zero-extensions of vector extract operations of 8-
3300  // and 16-bit vector elements.  NEON supports these directly.  They are
3301  // handled during DAG combining because type legalization will promote them
3302  // to 32-bit types and it is messy to recognize the operations after that.
3303  if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
3304    SDValue Vec = N0.getOperand(0);
3305    SDValue Lane = N0.getOperand(1);
3306    EVT VT = N->getValueType(0);
3307    EVT EltVT = N0.getValueType();
3308    const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3309
3310    if (VT == MVT::i32 &&
3311        (EltVT == MVT::i8 || EltVT == MVT::i16) &&
3312        TLI.isTypeLegal(Vec.getValueType())) {
3313
3314      unsigned Opc = 0;
3315      switch (N->getOpcode()) {
3316      default: llvm_unreachable("unexpected opcode");
3317      case ISD::SIGN_EXTEND:
3318        Opc = ARMISD::VGETLANEs;
3319        break;
3320      case ISD::ZERO_EXTEND:
3321      case ISD::ANY_EXTEND:
3322        Opc = ARMISD::VGETLANEu;
3323        break;
3324      }
3325      return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
3326    }
3327  }
3328
3329  return SDValue();
3330}
3331
3332SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
3333                                             DAGCombinerInfo &DCI) const {
3334  switch (N->getOpcode()) {
3335  default: break;
3336  case ISD::ADD:      return PerformADDCombine(N, DCI);
3337  case ISD::SUB:      return PerformSUBCombine(N, DCI);
3338  case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI);
3339  case ISD::INTRINSIC_WO_CHAIN:
3340    return PerformIntrinsicCombine(N, DCI.DAG);
3341  case ISD::SHL:
3342  case ISD::SRA:
3343  case ISD::SRL:
3344    return PerformShiftCombine(N, DCI.DAG, Subtarget);
3345  case ISD::SIGN_EXTEND:
3346  case ISD::ZERO_EXTEND:
3347  case ISD::ANY_EXTEND:
3348    return PerformExtendCombine(N, DCI.DAG, Subtarget);
3349  }
3350  return SDValue();
3351}
3352
3353bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
3354  if (!Subtarget->hasV6Ops())
3355    // Pre-v6 does not support unaligned mem access.
3356    return false;
3357  else if (!Subtarget->hasV6Ops()) {
3358    // v6 may or may not support unaligned mem access.
3359    if (!Subtarget->isTargetDarwin())
3360      return false;
3361  }
3362
3363  switch (VT.getSimpleVT().SimpleTy) {
3364  default:
3365    return false;
3366  case MVT::i8:
3367  case MVT::i16:
3368  case MVT::i32:
3369    return true;
3370  // FIXME: VLD1 etc with standard alignment is legal.
3371  }
3372}
3373
3374static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
3375  if (V < 0)
3376    return false;
3377
3378  unsigned Scale = 1;
3379  switch (VT.getSimpleVT().SimpleTy) {
3380  default: return false;
3381  case MVT::i1:
3382  case MVT::i8:
3383    // Scale == 1;
3384    break;
3385  case MVT::i16:
3386    // Scale == 2;
3387    Scale = 2;
3388    break;
3389  case MVT::i32:
3390    // Scale == 4;
3391    Scale = 4;
3392    break;
3393  }
3394
3395  if ((V & (Scale - 1)) != 0)
3396    return false;
3397  V /= Scale;
3398  return V == (V & ((1LL << 5) - 1));
3399}
3400
3401static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
3402                                      const ARMSubtarget *Subtarget) {
3403  bool isNeg = false;
3404  if (V < 0) {
3405    isNeg = true;
3406    V = - V;
3407  }
3408
3409  switch (VT.getSimpleVT().SimpleTy) {
3410  default: return false;
3411  case MVT::i1:
3412  case MVT::i8:
3413  case MVT::i16:
3414  case MVT::i32:
3415    // + imm12 or - imm8
3416    if (isNeg)
3417      return V == (V & ((1LL << 8) - 1));
3418    return V == (V & ((1LL << 12) - 1));
3419  case MVT::f32:
3420  case MVT::f64:
3421    // Same as ARM mode. FIXME: NEON?
3422    if (!Subtarget->hasVFP2())
3423      return false;
3424    if ((V & 3) != 0)
3425      return false;
3426    V >>= 2;
3427    return V == (V & ((1LL << 8) - 1));
3428  }
3429}
3430
3431/// isLegalAddressImmediate - Return true if the integer value can be used
3432/// as the offset of the target addressing mode for load / store of the
3433/// given type.
3434static bool isLegalAddressImmediate(int64_t V, EVT VT,
3435                                    const ARMSubtarget *Subtarget) {
3436  if (V == 0)
3437    return true;
3438
3439  if (!VT.isSimple())
3440    return false;
3441
3442  if (Subtarget->isThumb1Only())
3443    return isLegalT1AddressImmediate(V, VT);
3444  else if (Subtarget->isThumb2())
3445    return isLegalT2AddressImmediate(V, VT, Subtarget);
3446
3447  // ARM mode.
3448  if (V < 0)
3449    V = - V;
3450  switch (VT.getSimpleVT().SimpleTy) {
3451  default: return false;
3452  case MVT::i1:
3453  case MVT::i8:
3454  case MVT::i32:
3455    // +- imm12
3456    return V == (V & ((1LL << 12) - 1));
3457  case MVT::i16:
3458    // +- imm8
3459    return V == (V & ((1LL << 8) - 1));
3460  case MVT::f32:
3461  case MVT::f64:
3462    if (!Subtarget->hasVFP2()) // FIXME: NEON?
3463      return false;
3464    if ((V & 3) != 0)
3465      return false;
3466    V >>= 2;
3467    return V == (V & ((1LL << 8) - 1));
3468  }
3469}
3470
3471bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
3472                                                      EVT VT) const {
3473  int Scale = AM.Scale;
3474  if (Scale < 0)
3475    return false;
3476
3477  switch (VT.getSimpleVT().SimpleTy) {
3478  default: return false;
3479  case MVT::i1:
3480  case MVT::i8:
3481  case MVT::i16:
3482  case MVT::i32:
3483    if (Scale == 1)
3484      return true;
3485    // r + r << imm
3486    Scale = Scale & ~1;
3487    return Scale == 2 || Scale == 4 || Scale == 8;
3488  case MVT::i64:
3489    // r + r
3490    if (((unsigned)AM.HasBaseReg + Scale) <= 2)
3491      return true;
3492    return false;
3493  case MVT::isVoid:
3494    // Note, we allow "void" uses (basically, uses that aren't loads or
3495    // stores), because arm allows folding a scale into many arithmetic
3496    // operations.  This should be made more precise and revisited later.
3497
3498    // Allow r << imm, but the imm has to be a multiple of two.
3499    if (Scale & 1) return false;
3500    return isPowerOf2_32(Scale);
3501  }
3502}
3503
3504/// isLegalAddressingMode - Return true if the addressing mode represented
3505/// by AM is legal for this target, for a load/store of the specified type.
3506bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3507                                              const Type *Ty) const {
3508  EVT VT = getValueType(Ty, true);
3509  if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
3510    return false;
3511
3512  // Can never fold addr of global into load/store.
3513  if (AM.BaseGV)
3514    return false;
3515
3516  switch (AM.Scale) {
3517  case 0:  // no scale reg, must be "r+i" or "r", or "i".
3518    break;
3519  case 1:
3520    if (Subtarget->isThumb1Only())
3521      return false;
3522    // FALL THROUGH.
3523  default:
3524    // ARM doesn't support any R+R*scale+imm addr modes.
3525    if (AM.BaseOffs)
3526      return false;
3527
3528    if (!VT.isSimple())
3529      return false;
3530
3531    if (Subtarget->isThumb2())
3532      return isLegalT2ScaledAddressingMode(AM, VT);
3533
3534    int Scale = AM.Scale;
3535    switch (VT.getSimpleVT().SimpleTy) {
3536    default: return false;
3537    case MVT::i1:
3538    case MVT::i8:
3539    case MVT::i32:
3540      if (Scale < 0) Scale = -Scale;
3541      if (Scale == 1)
3542        return true;
3543      // r + r << imm
3544      return isPowerOf2_32(Scale & ~1);
3545    case MVT::i16:
3546    case MVT::i64:
3547      // r + r
3548      if (((unsigned)AM.HasBaseReg + Scale) <= 2)
3549        return true;
3550      return false;
3551
3552    case MVT::isVoid:
3553      // Note, we allow "void" uses (basically, uses that aren't loads or
3554      // stores), because arm allows folding a scale into many arithmetic
3555      // operations.  This should be made more precise and revisited later.
3556
3557      // Allow r << imm, but the imm has to be a multiple of two.
3558      if (Scale & 1) return false;
3559      return isPowerOf2_32(Scale);
3560    }
3561    break;
3562  }
3563  return true;
3564}
3565
3566static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
3567                                      bool isSEXTLoad, SDValue &Base,
3568                                      SDValue &Offset, bool &isInc,
3569                                      SelectionDAG &DAG) {
3570  if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
3571    return false;
3572
3573  if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
3574    // AddressingMode 3
3575    Base = Ptr->getOperand(0);
3576    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3577      int RHSC = (int)RHS->getZExtValue();
3578      if (RHSC < 0 && RHSC > -256) {
3579        assert(Ptr->getOpcode() == ISD::ADD);
3580        isInc = false;
3581        Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3582        return true;
3583      }
3584    }
3585    isInc = (Ptr->getOpcode() == ISD::ADD);
3586    Offset = Ptr->getOperand(1);
3587    return true;
3588  } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
3589    // AddressingMode 2
3590    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3591      int RHSC = (int)RHS->getZExtValue();
3592      if (RHSC < 0 && RHSC > -0x1000) {
3593        assert(Ptr->getOpcode() == ISD::ADD);
3594        isInc = false;
3595        Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3596        Base = Ptr->getOperand(0);
3597        return true;
3598      }
3599    }
3600
3601    if (Ptr->getOpcode() == ISD::ADD) {
3602      isInc = true;
3603      ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
3604      if (ShOpcVal != ARM_AM::no_shift) {
3605        Base = Ptr->getOperand(1);
3606        Offset = Ptr->getOperand(0);
3607      } else {
3608        Base = Ptr->getOperand(0);
3609        Offset = Ptr->getOperand(1);
3610      }
3611      return true;
3612    }
3613
3614    isInc = (Ptr->getOpcode() == ISD::ADD);
3615    Base = Ptr->getOperand(0);
3616    Offset = Ptr->getOperand(1);
3617    return true;
3618  }
3619
3620  // FIXME: Use FLDM / FSTM to emulate indexed FP load / store.
3621  return false;
3622}
3623
3624static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
3625                                     bool isSEXTLoad, SDValue &Base,
3626                                     SDValue &Offset, bool &isInc,
3627                                     SelectionDAG &DAG) {
3628  if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
3629    return false;
3630
3631  Base = Ptr->getOperand(0);
3632  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3633    int RHSC = (int)RHS->getZExtValue();
3634    if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
3635      assert(Ptr->getOpcode() == ISD::ADD);
3636      isInc = false;
3637      Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3638      return true;
3639    } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
3640      isInc = Ptr->getOpcode() == ISD::ADD;
3641      Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
3642      return true;
3643    }
3644  }
3645
3646  return false;
3647}
3648
3649/// getPreIndexedAddressParts - returns true by value, base pointer and
3650/// offset pointer and addressing mode by reference if the node's address
3651/// can be legally represented as pre-indexed load / store address.
3652bool
3653ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
3654                                             SDValue &Offset,
3655                                             ISD::MemIndexedMode &AM,
3656                                             SelectionDAG &DAG) const {
3657  if (Subtarget->isThumb1Only())
3658    return false;
3659
3660  EVT VT;
3661  SDValue Ptr;
3662  bool isSEXTLoad = false;
3663  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3664    Ptr = LD->getBasePtr();
3665    VT  = LD->getMemoryVT();
3666    isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
3667  } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3668    Ptr = ST->getBasePtr();
3669    VT  = ST->getMemoryVT();
3670  } else
3671    return false;
3672
3673  bool isInc;
3674  bool isLegal = false;
3675  if (Subtarget->isThumb2())
3676    isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
3677                                       Offset, isInc, DAG);
3678  else
3679    isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
3680                                        Offset, isInc, DAG);
3681  if (!isLegal)
3682    return false;
3683
3684  AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
3685  return true;
3686}
3687
3688/// getPostIndexedAddressParts - returns true by value, base pointer and
3689/// offset pointer and addressing mode by reference if this node can be
3690/// combined with a load / store to form a post-indexed load / store.
3691bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
3692                                                   SDValue &Base,
3693                                                   SDValue &Offset,
3694                                                   ISD::MemIndexedMode &AM,
3695                                                   SelectionDAG &DAG) const {
3696  if (Subtarget->isThumb1Only())
3697    return false;
3698
3699  EVT VT;
3700  SDValue Ptr;
3701  bool isSEXTLoad = false;
3702  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3703    VT  = LD->getMemoryVT();
3704    isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
3705  } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3706    VT  = ST->getMemoryVT();
3707  } else
3708    return false;
3709
3710  bool isInc;
3711  bool isLegal = false;
3712  if (Subtarget->isThumb2())
3713    isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
3714                                        isInc, DAG);
3715  else
3716    isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
3717                                        isInc, DAG);
3718  if (!isLegal)
3719    return false;
3720
3721  AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
3722  return true;
3723}
3724
3725void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
3726                                                       const APInt &Mask,
3727                                                       APInt &KnownZero,
3728                                                       APInt &KnownOne,
3729                                                       const SelectionDAG &DAG,
3730                                                       unsigned Depth) const {
3731  KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
3732  switch (Op.getOpcode()) {
3733  default: break;
3734  case ARMISD::CMOV: {
3735    // Bits are known zero/one if known on the LHS and RHS.
3736    DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
3737    if (KnownZero == 0 && KnownOne == 0) return;
3738
3739    APInt KnownZeroRHS, KnownOneRHS;
3740    DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
3741                          KnownZeroRHS, KnownOneRHS, Depth+1);
3742    KnownZero &= KnownZeroRHS;
3743    KnownOne  &= KnownOneRHS;
3744    return;
3745  }
3746  }
3747}
3748
3749//===----------------------------------------------------------------------===//
3750//                           ARM Inline Assembly Support
3751//===----------------------------------------------------------------------===//
3752
3753/// getConstraintType - Given a constraint letter, return the type of
3754/// constraint it is for this target.
3755ARMTargetLowering::ConstraintType
3756ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
3757  if (Constraint.size() == 1) {
3758    switch (Constraint[0]) {
3759    default:  break;
3760    case 'l': return C_RegisterClass;
3761    case 'w': return C_RegisterClass;
3762    }
3763  }
3764  return TargetLowering::getConstraintType(Constraint);
3765}
3766
3767std::pair<unsigned, const TargetRegisterClass*>
3768ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3769                                                EVT VT) const {
3770  if (Constraint.size() == 1) {
3771    // GCC RS6000 Constraint Letters
3772    switch (Constraint[0]) {
3773    case 'l':
3774      if (Subtarget->isThumb1Only())
3775        return std::make_pair(0U, ARM::tGPRRegisterClass);
3776      else
3777        return std::make_pair(0U, ARM::GPRRegisterClass);
3778    case 'r':
3779      return std::make_pair(0U, ARM::GPRRegisterClass);
3780    case 'w':
3781      if (VT == MVT::f32)
3782        return std::make_pair(0U, ARM::SPRRegisterClass);
3783      if (VT == MVT::f64)
3784        return std::make_pair(0U, ARM::DPRRegisterClass);
3785      break;
3786    }
3787  }
3788  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3789}
3790
3791std::vector<unsigned> ARMTargetLowering::
3792getRegClassForInlineAsmConstraint(const std::string &Constraint,
3793                                  EVT VT) const {
3794  if (Constraint.size() != 1)
3795    return std::vector<unsigned>();
3796
3797  switch (Constraint[0]) {      // GCC ARM Constraint Letters
3798  default: break;
3799  case 'l':
3800    return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
3801                                 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
3802                                 0);
3803  case 'r':
3804    return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
3805                                 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
3806                                 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
3807                                 ARM::R12, ARM::LR, 0);
3808  case 'w':
3809    if (VT == MVT::f32)
3810      return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
3811                                   ARM::S4, ARM::S5, ARM::S6, ARM::S7,
3812                                   ARM::S8, ARM::S9, ARM::S10, ARM::S11,
3813                                   ARM::S12,ARM::S13,ARM::S14,ARM::S15,
3814                                   ARM::S16,ARM::S17,ARM::S18,ARM::S19,
3815                                   ARM::S20,ARM::S21,ARM::S22,ARM::S23,
3816                                   ARM::S24,ARM::S25,ARM::S26,ARM::S27,
3817                                   ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
3818    if (VT == MVT::f64)
3819      return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
3820                                   ARM::D4, ARM::D5, ARM::D6, ARM::D7,
3821                                   ARM::D8, ARM::D9, ARM::D10,ARM::D11,
3822                                   ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
3823      break;
3824  }
3825
3826  return std::vector<unsigned>();
3827}
3828
3829/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3830/// vector.  If it is invalid, don't add anything to Ops.
3831void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3832                                                     char Constraint,
3833                                                     bool hasMemory,
3834                                                     std::vector<SDValue>&Ops,
3835                                                     SelectionDAG &DAG) const {
3836  SDValue Result(0, 0);
3837
3838  switch (Constraint) {
3839  default: break;
3840  case 'I': case 'J': case 'K': case 'L':
3841  case 'M': case 'N': case 'O':
3842    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3843    if (!C)
3844      return;
3845
3846    int64_t CVal64 = C->getSExtValue();
3847    int CVal = (int) CVal64;
3848    // None of these constraints allow values larger than 32 bits.  Check
3849    // that the value fits in an int.
3850    if (CVal != CVal64)
3851      return;
3852
3853    switch (Constraint) {
3854      case 'I':
3855        if (Subtarget->isThumb1Only()) {
3856          // This must be a constant between 0 and 255, for ADD
3857          // immediates.
3858          if (CVal >= 0 && CVal <= 255)
3859            break;
3860        } else if (Subtarget->isThumb2()) {
3861          // A constant that can be used as an immediate value in a
3862          // data-processing instruction.
3863          if (ARM_AM::getT2SOImmVal(CVal) != -1)
3864            break;
3865        } else {
3866          // A constant that can be used as an immediate value in a
3867          // data-processing instruction.
3868          if (ARM_AM::getSOImmVal(CVal) != -1)
3869            break;
3870        }
3871        return;
3872
3873      case 'J':
3874        if (Subtarget->isThumb()) {  // FIXME thumb2
3875          // This must be a constant between -255 and -1, for negated ADD
3876          // immediates. This can be used in GCC with an "n" modifier that
3877          // prints the negated value, for use with SUB instructions. It is
3878          // not useful otherwise but is implemented for compatibility.
3879          if (CVal >= -255 && CVal <= -1)
3880            break;
3881        } else {
3882          // This must be a constant between -4095 and 4095. It is not clear
3883          // what this constraint is intended for. Implemented for
3884          // compatibility with GCC.
3885          if (CVal >= -4095 && CVal <= 4095)
3886            break;
3887        }
3888        return;
3889
3890      case 'K':
3891        if (Subtarget->isThumb1Only()) {
3892          // A 32-bit value where only one byte has a nonzero value. Exclude
3893          // zero to match GCC. This constraint is used by GCC internally for
3894          // constants that can be loaded with a move/shift combination.
3895          // It is not useful otherwise but is implemented for compatibility.
3896          if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
3897            break;
3898        } else if (Subtarget->isThumb2()) {
3899          // A constant whose bitwise inverse can be used as an immediate
3900          // value in a data-processing instruction. This can be used in GCC
3901          // with a "B" modifier that prints the inverted value, for use with
3902          // BIC and MVN instructions. It is not useful otherwise but is
3903          // implemented for compatibility.
3904          if (ARM_AM::getT2SOImmVal(~CVal) != -1)
3905            break;
3906        } else {
3907          // A constant whose bitwise inverse can be used as an immediate
3908          // value in a data-processing instruction. This can be used in GCC
3909          // with a "B" modifier that prints the inverted value, for use with
3910          // BIC and MVN instructions. It is not useful otherwise but is
3911          // implemented for compatibility.
3912          if (ARM_AM::getSOImmVal(~CVal) != -1)
3913            break;
3914        }
3915        return;
3916
3917      case 'L':
3918        if (Subtarget->isThumb1Only()) {
3919          // This must be a constant between -7 and 7,
3920          // for 3-operand ADD/SUB immediate instructions.
3921          if (CVal >= -7 && CVal < 7)
3922            break;
3923        } else if (Subtarget->isThumb2()) {
3924          // A constant whose negation can be used as an immediate value in a
3925          // data-processing instruction. This can be used in GCC with an "n"
3926          // modifier that prints the negated value, for use with SUB
3927          // instructions. It is not useful otherwise but is implemented for
3928          // compatibility.
3929          if (ARM_AM::getT2SOImmVal(-CVal) != -1)
3930            break;
3931        } else {
3932          // A constant whose negation can be used as an immediate value in a
3933          // data-processing instruction. This can be used in GCC with an "n"
3934          // modifier that prints the negated value, for use with SUB
3935          // instructions. It is not useful otherwise but is implemented for
3936          // compatibility.
3937          if (ARM_AM::getSOImmVal(-CVal) != -1)
3938            break;
3939        }
3940        return;
3941
3942      case 'M':
3943        if (Subtarget->isThumb()) { // FIXME thumb2
3944          // This must be a multiple of 4 between 0 and 1020, for
3945          // ADD sp + immediate.
3946          if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
3947            break;
3948        } else {
3949          // A power of two or a constant between 0 and 32.  This is used in
3950          // GCC for the shift amount on shifted register operands, but it is
3951          // useful in general for any shift amounts.
3952          if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
3953            break;
3954        }
3955        return;
3956
3957      case 'N':
3958        if (Subtarget->isThumb()) {  // FIXME thumb2
3959          // This must be a constant between 0 and 31, for shift amounts.
3960          if (CVal >= 0 && CVal <= 31)
3961            break;
3962        }
3963        return;
3964
3965      case 'O':
3966        if (Subtarget->isThumb()) {  // FIXME thumb2
3967          // This must be a multiple of 4 between -508 and 508, for
3968          // ADD/SUB sp = sp + immediate.
3969          if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
3970            break;
3971        }
3972        return;
3973    }
3974    Result = DAG.getTargetConstant(CVal, Op.getValueType());
3975    break;
3976  }
3977
3978  if (Result.getNode()) {
3979    Ops.push_back(Result);
3980    return;
3981  }
3982  return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
3983                                                      Ops, DAG);
3984}
3985