ARMISelLowering.cpp revision c892aeb26601cc5109490d30c7e170cb07f84428
1//===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "arm-isel" 16#include "ARM.h" 17#include "ARMCallingConv.h" 18#include "ARMConstantPoolValue.h" 19#include "ARMISelLowering.h" 20#include "ARMMachineFunctionInfo.h" 21#include "ARMPerfectShuffle.h" 22#include "ARMRegisterInfo.h" 23#include "ARMSubtarget.h" 24#include "ARMTargetMachine.h" 25#include "ARMTargetObjectFile.h" 26#include "MCTargetDesc/ARMAddressingModes.h" 27#include "llvm/CallingConv.h" 28#include "llvm/Constants.h" 29#include "llvm/Function.h" 30#include "llvm/GlobalValue.h" 31#include "llvm/Instruction.h" 32#include "llvm/Instructions.h" 33#include "llvm/Intrinsics.h" 34#include "llvm/Type.h" 35#include "llvm/CodeGen/CallingConvLower.h" 36#include "llvm/CodeGen/IntrinsicLowering.h" 37#include "llvm/CodeGen/MachineBasicBlock.h" 38#include "llvm/CodeGen/MachineFrameInfo.h" 39#include "llvm/CodeGen/MachineFunction.h" 40#include "llvm/CodeGen/MachineInstrBuilder.h" 41#include "llvm/CodeGen/MachineModuleInfo.h" 42#include "llvm/CodeGen/MachineRegisterInfo.h" 43#include "llvm/CodeGen/SelectionDAG.h" 44#include "llvm/MC/MCSectionMachO.h" 45#include "llvm/Target/TargetOptions.h" 46#include "llvm/ADT/StringExtras.h" 47#include "llvm/ADT/Statistic.h" 48#include "llvm/Support/CommandLine.h" 49#include "llvm/Support/ErrorHandling.h" 50#include "llvm/Support/MathExtras.h" 51#include "llvm/Support/raw_ostream.h" 52#include <sstream> 53using namespace llvm; 54 55STATISTIC(NumTailCalls, "Number of tail calls"); 56STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt"); 57 58// This option should go away when tail calls fully work. 59static cl::opt<bool> 60EnableARMTailCalls("arm-tail-calls", cl::Hidden, 61 cl::desc("Generate tail calls (TEMPORARY OPTION)."), 62 cl::init(false)); 63 64cl::opt<bool> 65EnableARMLongCalls("arm-long-calls", cl::Hidden, 66 cl::desc("Generate calls via indirect call instructions"), 67 cl::init(false)); 68 69static cl::opt<bool> 70ARMInterworking("arm-interworking", cl::Hidden, 71 cl::desc("Enable / disable ARM interworking (for debugging only)"), 72 cl::init(true)); 73 74namespace { 75 class ARMCCState : public CCState { 76 public: 77 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF, 78 const TargetMachine &TM, SmallVector<CCValAssign, 16> &locs, 79 LLVMContext &C, ParmContext PC) 80 : CCState(CC, isVarArg, MF, TM, locs, C) { 81 assert(((PC == Call) || (PC == Prologue)) && 82 "ARMCCState users must specify whether their context is call" 83 "or prologue generation."); 84 CallOrPrologue = PC; 85 } 86 }; 87} 88 89// The APCS parameter registers. 90static const unsigned GPRArgRegs[] = { 91 ARM::R0, ARM::R1, ARM::R2, ARM::R3 92}; 93 94void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT, 95 EVT PromotedBitwiseVT) { 96 if (VT != PromotedLdStVT) { 97 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote); 98 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(), 99 PromotedLdStVT.getSimpleVT()); 100 101 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote); 102 AddPromotedToType (ISD::STORE, VT.getSimpleVT(), 103 PromotedLdStVT.getSimpleVT()); 104 } 105 106 EVT ElemTy = VT.getVectorElementType(); 107 if (ElemTy != MVT::i64 && ElemTy != MVT::f64) 108 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom); 109 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom); 110 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom); 111 if (ElemTy == MVT::i32) { 112 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Custom); 113 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Custom); 114 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom); 115 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom); 116 } else { 117 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand); 118 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand); 119 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand); 120 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand); 121 } 122 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom); 123 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom); 124 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal); 125 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Legal); 126 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand); 127 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand); 128 setOperationAction(ISD::SIGN_EXTEND_INREG, VT.getSimpleVT(), Expand); 129 if (VT.isInteger()) { 130 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom); 131 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom); 132 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom); 133 } 134 135 // Promote all bit-wise operations. 136 if (VT.isInteger() && VT != PromotedBitwiseVT) { 137 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote); 138 AddPromotedToType (ISD::AND, VT.getSimpleVT(), 139 PromotedBitwiseVT.getSimpleVT()); 140 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote); 141 AddPromotedToType (ISD::OR, VT.getSimpleVT(), 142 PromotedBitwiseVT.getSimpleVT()); 143 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote); 144 AddPromotedToType (ISD::XOR, VT.getSimpleVT(), 145 PromotedBitwiseVT.getSimpleVT()); 146 } 147 148 // Neon does not support vector divide/remainder operations. 149 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand); 150 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand); 151 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand); 152 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand); 153 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand); 154 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand); 155} 156 157void ARMTargetLowering::addDRTypeForNEON(EVT VT) { 158 addRegisterClass(VT, ARM::DPRRegisterClass); 159 addTypeForNEON(VT, MVT::f64, MVT::v2i32); 160} 161 162void ARMTargetLowering::addQRTypeForNEON(EVT VT) { 163 addRegisterClass(VT, ARM::QPRRegisterClass); 164 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32); 165} 166 167static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) { 168 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin()) 169 return new TargetLoweringObjectFileMachO(); 170 171 return new ARMElfTargetObjectFile(); 172} 173 174ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) 175 : TargetLowering(TM, createTLOF(TM)) { 176 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 177 RegInfo = TM.getRegisterInfo(); 178 Itins = TM.getInstrItineraryData(); 179 180 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 181 182 if (Subtarget->isTargetDarwin()) { 183 // Uses VFP for Thumb libfuncs if available. 184 if (Subtarget->isThumb() && Subtarget->hasVFP2()) { 185 // Single-precision floating-point arithmetic. 186 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp"); 187 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp"); 188 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp"); 189 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp"); 190 191 // Double-precision floating-point arithmetic. 192 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp"); 193 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp"); 194 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp"); 195 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp"); 196 197 // Single-precision comparisons. 198 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp"); 199 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp"); 200 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp"); 201 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp"); 202 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp"); 203 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp"); 204 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp"); 205 setLibcallName(RTLIB::O_F32, "__unordsf2vfp"); 206 207 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 208 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE); 209 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 210 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 211 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 212 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 213 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 214 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 215 216 // Double-precision comparisons. 217 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp"); 218 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp"); 219 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp"); 220 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp"); 221 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp"); 222 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp"); 223 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp"); 224 setLibcallName(RTLIB::O_F64, "__unorddf2vfp"); 225 226 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 227 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE); 228 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 229 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 230 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 231 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 232 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 233 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 234 235 // Floating-point to integer conversions. 236 // i64 conversions are done via library routines even when generating VFP 237 // instructions, so use the same ones. 238 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp"); 239 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp"); 240 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp"); 241 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp"); 242 243 // Conversions between floating types. 244 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp"); 245 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp"); 246 247 // Integer to floating-point conversions. 248 // i64 conversions are done via library routines even when generating VFP 249 // instructions, so use the same ones. 250 // FIXME: There appears to be some naming inconsistency in ARM libgcc: 251 // e.g., __floatunsidf vs. __floatunssidfvfp. 252 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp"); 253 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp"); 254 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp"); 255 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp"); 256 } 257 } 258 259 // These libcalls are not available in 32-bit. 260 setLibcallName(RTLIB::SHL_I128, 0); 261 setLibcallName(RTLIB::SRL_I128, 0); 262 setLibcallName(RTLIB::SRA_I128, 0); 263 264 if (Subtarget->isAAPCS_ABI() && !Subtarget->isTargetDarwin()) { 265 // Double-precision floating-point arithmetic helper functions 266 // RTABI chapter 4.1.2, Table 2 267 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd"); 268 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv"); 269 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul"); 270 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub"); 271 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS); 272 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS); 273 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS); 274 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS); 275 276 // Double-precision floating-point comparison helper functions 277 // RTABI chapter 4.1.2, Table 3 278 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq"); 279 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 280 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq"); 281 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ); 282 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt"); 283 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 284 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple"); 285 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 286 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge"); 287 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 288 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt"); 289 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 290 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun"); 291 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 292 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun"); 293 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 294 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS); 295 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS); 296 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS); 297 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS); 298 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS); 299 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS); 300 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS); 301 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS); 302 303 // Single-precision floating-point arithmetic helper functions 304 // RTABI chapter 4.1.2, Table 4 305 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd"); 306 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv"); 307 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul"); 308 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub"); 309 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS); 310 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS); 311 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS); 312 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS); 313 314 // Single-precision floating-point comparison helper functions 315 // RTABI chapter 4.1.2, Table 5 316 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq"); 317 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 318 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq"); 319 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ); 320 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt"); 321 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 322 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple"); 323 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 324 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge"); 325 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 326 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt"); 327 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 328 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun"); 329 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 330 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun"); 331 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 332 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS); 333 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS); 334 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS); 335 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS); 336 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS); 337 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS); 338 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS); 339 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS); 340 341 // Floating-point to integer conversions. 342 // RTABI chapter 4.1.2, Table 6 343 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz"); 344 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz"); 345 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz"); 346 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz"); 347 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz"); 348 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz"); 349 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz"); 350 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz"); 351 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS); 352 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS); 353 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS); 354 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS); 355 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS); 356 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS); 357 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS); 358 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS); 359 360 // Conversions between floating types. 361 // RTABI chapter 4.1.2, Table 7 362 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f"); 363 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d"); 364 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS); 365 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS); 366 367 // Integer to floating-point conversions. 368 // RTABI chapter 4.1.2, Table 8 369 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d"); 370 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d"); 371 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d"); 372 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d"); 373 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f"); 374 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f"); 375 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f"); 376 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f"); 377 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS); 378 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS); 379 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS); 380 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS); 381 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS); 382 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS); 383 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS); 384 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS); 385 386 // Long long helper functions 387 // RTABI chapter 4.2, Table 9 388 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul"); 389 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl"); 390 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr"); 391 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr"); 392 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS); 393 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS); 394 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS); 395 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS); 396 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS); 397 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS); 398 399 // Integer division functions 400 // RTABI chapter 4.3.1 401 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv"); 402 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv"); 403 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv"); 404 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod"); 405 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv"); 406 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv"); 407 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv"); 408 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod"); 409 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS); 410 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS); 411 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS); 412 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS); 413 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS); 414 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS); 415 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS); 416 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS); 417 418 // Memory operations 419 // RTABI chapter 4.3.4 420 setLibcallName(RTLIB::MEMCPY, "__aeabi_memcpy"); 421 setLibcallName(RTLIB::MEMMOVE, "__aeabi_memmove"); 422 setLibcallName(RTLIB::MEMSET, "__aeabi_memset"); 423 setLibcallCallingConv(RTLIB::MEMCPY, CallingConv::ARM_AAPCS); 424 setLibcallCallingConv(RTLIB::MEMMOVE, CallingConv::ARM_AAPCS); 425 setLibcallCallingConv(RTLIB::MEMSET, CallingConv::ARM_AAPCS); 426 } 427 428 // Use divmod compiler-rt calls for iOS 5.0 and later. 429 if (Subtarget->getTargetTriple().getOS() == Triple::IOS && 430 !Subtarget->getTargetTriple().isOSVersionLT(5, 0)) { 431 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4"); 432 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4"); 433 } 434 435 if (Subtarget->isThumb1Only()) 436 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass); 437 else 438 addRegisterClass(MVT::i32, ARM::GPRRegisterClass); 439 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() && 440 !Subtarget->isThumb1Only()) { 441 addRegisterClass(MVT::f32, ARM::SPRRegisterClass); 442 if (!Subtarget->isFPOnlySP()) 443 addRegisterClass(MVT::f64, ARM::DPRRegisterClass); 444 445 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 446 } 447 448 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 449 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 450 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 451 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 452 setTruncStoreAction((MVT::SimpleValueType)VT, 453 (MVT::SimpleValueType)InnerVT, Expand); 454 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 455 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 456 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 457 } 458 459 if (Subtarget->hasNEON()) { 460 addDRTypeForNEON(MVT::v2f32); 461 addDRTypeForNEON(MVT::v8i8); 462 addDRTypeForNEON(MVT::v4i16); 463 addDRTypeForNEON(MVT::v2i32); 464 addDRTypeForNEON(MVT::v1i64); 465 466 addQRTypeForNEON(MVT::v4f32); 467 addQRTypeForNEON(MVT::v2f64); 468 addQRTypeForNEON(MVT::v16i8); 469 addQRTypeForNEON(MVT::v8i16); 470 addQRTypeForNEON(MVT::v4i32); 471 addQRTypeForNEON(MVT::v2i64); 472 473 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but 474 // neither Neon nor VFP support any arithmetic operations on it. 475 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively 476 // supported for v4f32. 477 setOperationAction(ISD::FADD, MVT::v2f64, Expand); 478 setOperationAction(ISD::FSUB, MVT::v2f64, Expand); 479 setOperationAction(ISD::FMUL, MVT::v2f64, Expand); 480 // FIXME: Code duplication: FDIV and FREM are expanded always, see 481 // ARMTargetLowering::addTypeForNEON method for details. 482 setOperationAction(ISD::FDIV, MVT::v2f64, Expand); 483 setOperationAction(ISD::FREM, MVT::v2f64, Expand); 484 // FIXME: Create unittest. 485 // In another words, find a way when "copysign" appears in DAG with vector 486 // operands. 487 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand); 488 // FIXME: Code duplication: SETCC has custom operation action, see 489 // ARMTargetLowering::addTypeForNEON method for details. 490 setOperationAction(ISD::SETCC, MVT::v2f64, Expand); 491 // FIXME: Create unittest for FNEG and for FABS. 492 setOperationAction(ISD::FNEG, MVT::v2f64, Expand); 493 setOperationAction(ISD::FABS, MVT::v2f64, Expand); 494 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand); 495 setOperationAction(ISD::FSIN, MVT::v2f64, Expand); 496 setOperationAction(ISD::FCOS, MVT::v2f64, Expand); 497 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand); 498 setOperationAction(ISD::FPOW, MVT::v2f64, Expand); 499 setOperationAction(ISD::FLOG, MVT::v2f64, Expand); 500 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand); 501 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand); 502 setOperationAction(ISD::FEXP, MVT::v2f64, Expand); 503 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand); 504 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR. 505 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand); 506 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand); 507 setOperationAction(ISD::FRINT, MVT::v2f64, Expand); 508 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand); 509 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand); 510 511 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand); 512 setOperationAction(ISD::FSIN, MVT::v4f32, Expand); 513 setOperationAction(ISD::FCOS, MVT::v4f32, Expand); 514 setOperationAction(ISD::FPOWI, MVT::v4f32, Expand); 515 setOperationAction(ISD::FPOW, MVT::v4f32, Expand); 516 setOperationAction(ISD::FLOG, MVT::v4f32, Expand); 517 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand); 518 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand); 519 setOperationAction(ISD::FEXP, MVT::v4f32, Expand); 520 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand); 521 522 // Neon does not support some operations on v1i64 and v2i64 types. 523 setOperationAction(ISD::MUL, MVT::v1i64, Expand); 524 // Custom handling for some quad-vector types to detect VMULL. 525 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 526 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 527 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 528 // Custom handling for some vector types to avoid expensive expansions 529 setOperationAction(ISD::SDIV, MVT::v4i16, Custom); 530 setOperationAction(ISD::SDIV, MVT::v8i8, Custom); 531 setOperationAction(ISD::UDIV, MVT::v4i16, Custom); 532 setOperationAction(ISD::UDIV, MVT::v8i8, Custom); 533 setOperationAction(ISD::SETCC, MVT::v1i64, Expand); 534 setOperationAction(ISD::SETCC, MVT::v2i64, Expand); 535 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with 536 // a destination type that is wider than the source, and nor does 537 // it have a FP_TO_[SU]INT instruction with a narrower destination than 538 // source. 539 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom); 540 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom); 541 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom); 542 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom); 543 544 setTargetDAGCombine(ISD::INTRINSIC_VOID); 545 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN); 546 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); 547 setTargetDAGCombine(ISD::SHL); 548 setTargetDAGCombine(ISD::SRL); 549 setTargetDAGCombine(ISD::SRA); 550 setTargetDAGCombine(ISD::SIGN_EXTEND); 551 setTargetDAGCombine(ISD::ZERO_EXTEND); 552 setTargetDAGCombine(ISD::ANY_EXTEND); 553 setTargetDAGCombine(ISD::SELECT_CC); 554 setTargetDAGCombine(ISD::BUILD_VECTOR); 555 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 556 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); 557 setTargetDAGCombine(ISD::STORE); 558 setTargetDAGCombine(ISD::FP_TO_SINT); 559 setTargetDAGCombine(ISD::FP_TO_UINT); 560 setTargetDAGCombine(ISD::FDIV); 561 562 // It is legal to extload from v4i8 to v4i16 or v4i32. 563 MVT Tys[6] = {MVT::v8i8, MVT::v4i8, MVT::v2i8, 564 MVT::v4i16, MVT::v2i16, 565 MVT::v2i32}; 566 for (unsigned i = 0; i < 6; ++i) { 567 setLoadExtAction(ISD::EXTLOAD, Tys[i], Legal); 568 setLoadExtAction(ISD::ZEXTLOAD, Tys[i], Legal); 569 setLoadExtAction(ISD::SEXTLOAD, Tys[i], Legal); 570 } 571 } 572 573 computeRegisterProperties(); 574 575 // ARM does not have f32 extending load. 576 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 577 578 // ARM does not have i1 sign extending load. 579 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 580 581 // ARM supports all 4 flavors of integer indexed load / store. 582 if (!Subtarget->isThumb1Only()) { 583 for (unsigned im = (unsigned)ISD::PRE_INC; 584 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { 585 setIndexedLoadAction(im, MVT::i1, Legal); 586 setIndexedLoadAction(im, MVT::i8, Legal); 587 setIndexedLoadAction(im, MVT::i16, Legal); 588 setIndexedLoadAction(im, MVT::i32, Legal); 589 setIndexedStoreAction(im, MVT::i1, Legal); 590 setIndexedStoreAction(im, MVT::i8, Legal); 591 setIndexedStoreAction(im, MVT::i16, Legal); 592 setIndexedStoreAction(im, MVT::i32, Legal); 593 } 594 } 595 596 // i64 operation support. 597 setOperationAction(ISD::MUL, MVT::i64, Expand); 598 setOperationAction(ISD::MULHU, MVT::i32, Expand); 599 if (Subtarget->isThumb1Only()) { 600 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 601 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 602 } 603 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops() 604 || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP())) 605 setOperationAction(ISD::MULHS, MVT::i32, Expand); 606 607 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 608 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 609 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 610 setOperationAction(ISD::SRL, MVT::i64, Custom); 611 setOperationAction(ISD::SRA, MVT::i64, Custom); 612 613 if (!Subtarget->isThumb1Only()) { 614 // FIXME: We should do this for Thumb1 as well. 615 setOperationAction(ISD::ADDC, MVT::i32, Custom); 616 setOperationAction(ISD::ADDE, MVT::i32, Custom); 617 setOperationAction(ISD::SUBC, MVT::i32, Custom); 618 setOperationAction(ISD::SUBE, MVT::i32, Custom); 619 } 620 621 // ARM does not have ROTL. 622 setOperationAction(ISD::ROTL, MVT::i32, Expand); 623 setOperationAction(ISD::CTTZ, MVT::i32, Custom); 624 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 625 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) 626 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 627 628 // These just redirect to CTTZ and CTLZ on ARM. 629 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i32 , Expand); 630 setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i32 , Expand); 631 632 // Only ARMv6 has BSWAP. 633 if (!Subtarget->hasV6Ops()) 634 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 635 636 // These are expanded into libcalls. 637 if (!Subtarget->hasDivide() || !Subtarget->isThumb2()) { 638 // v7M has a hardware divider 639 setOperationAction(ISD::SDIV, MVT::i32, Expand); 640 setOperationAction(ISD::UDIV, MVT::i32, Expand); 641 } 642 setOperationAction(ISD::SREM, MVT::i32, Expand); 643 setOperationAction(ISD::UREM, MVT::i32, Expand); 644 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 645 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 646 647 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 648 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 649 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom); 650 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 651 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 652 653 setOperationAction(ISD::TRAP, MVT::Other, Legal); 654 655 // Use the default implementation. 656 setOperationAction(ISD::VASTART, MVT::Other, Custom); 657 setOperationAction(ISD::VAARG, MVT::Other, Expand); 658 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 659 setOperationAction(ISD::VAEND, MVT::Other, Expand); 660 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 661 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 662 663 if (!Subtarget->isTargetDarwin()) { 664 // Non-Darwin platforms may return values in these registers via the 665 // personality function. 666 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 667 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 668 setExceptionPointerRegister(ARM::R0); 669 setExceptionSelectorRegister(ARM::R1); 670 } 671 672 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 673 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use 674 // the default expansion. 675 // FIXME: This should be checking for v6k, not just v6. 676 if (Subtarget->hasDataBarrier() || 677 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) { 678 // membarrier needs custom lowering; the rest are legal and handled 679 // normally. 680 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); 681 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 682 // Custom lowering for 64-bit ops 683 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 684 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 685 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 686 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 687 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 688 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 689 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom); 690 // Automatically insert fences (dmb ist) around ATOMIC_SWAP etc. 691 setInsertFencesForAtomic(true); 692 } else { 693 // Set them all for expansion, which will force libcalls. 694 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 695 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); 696 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand); 697 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand); 698 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand); 699 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand); 700 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand); 701 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand); 702 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand); 703 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand); 704 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand); 705 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand); 706 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand); 707 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand); 708 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the 709 // Unordered/Monotonic case. 710 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom); 711 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom); 712 // Since the libcalls include locking, fold in the fences 713 setShouldFoldAtomicFences(true); 714 } 715 716 setOperationAction(ISD::PREFETCH, MVT::Other, Custom); 717 718 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes. 719 if (!Subtarget->hasV6Ops()) { 720 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 721 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 722 } 723 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 724 725 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() && 726 !Subtarget->isThumb1Only()) { 727 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR 728 // iff target supports vfp2. 729 setOperationAction(ISD::BITCAST, MVT::i64, Custom); 730 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); 731 } 732 733 // We want to custom lower some of our intrinsics. 734 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 735 if (Subtarget->isTargetDarwin()) { 736 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom); 737 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom); 738 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume"); 739 } 740 741 setOperationAction(ISD::SETCC, MVT::i32, Expand); 742 setOperationAction(ISD::SETCC, MVT::f32, Expand); 743 setOperationAction(ISD::SETCC, MVT::f64, Expand); 744 setOperationAction(ISD::SELECT, MVT::i32, Custom); 745 setOperationAction(ISD::SELECT, MVT::f32, Custom); 746 setOperationAction(ISD::SELECT, MVT::f64, Custom); 747 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 748 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 749 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 750 751 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 752 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 753 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 754 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 755 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 756 757 // We don't support sin/cos/fmod/copysign/pow 758 setOperationAction(ISD::FSIN, MVT::f64, Expand); 759 setOperationAction(ISD::FSIN, MVT::f32, Expand); 760 setOperationAction(ISD::FCOS, MVT::f32, Expand); 761 setOperationAction(ISD::FCOS, MVT::f64, Expand); 762 setOperationAction(ISD::FREM, MVT::f64, Expand); 763 setOperationAction(ISD::FREM, MVT::f32, Expand); 764 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() && 765 !Subtarget->isThumb1Only()) { 766 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 767 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 768 } 769 setOperationAction(ISD::FPOW, MVT::f64, Expand); 770 setOperationAction(ISD::FPOW, MVT::f32, Expand); 771 772 setOperationAction(ISD::FMA, MVT::f64, Expand); 773 setOperationAction(ISD::FMA, MVT::f32, Expand); 774 775 // Various VFP goodness 776 if (!TM.Options.UseSoftFloat && !Subtarget->isThumb1Only()) { 777 // int <-> fp are custom expanded into bit_convert + ARMISD ops. 778 if (Subtarget->hasVFP2()) { 779 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 780 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 781 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 782 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 783 } 784 // Special handling for half-precision FP. 785 if (!Subtarget->hasFP16()) { 786 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand); 787 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand); 788 } 789 } 790 791 // We have target-specific dag combine patterns for the following nodes: 792 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine 793 setTargetDAGCombine(ISD::ADD); 794 setTargetDAGCombine(ISD::SUB); 795 setTargetDAGCombine(ISD::MUL); 796 797 if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON()) { 798 setTargetDAGCombine(ISD::AND); 799 setTargetDAGCombine(ISD::OR); 800 setTargetDAGCombine(ISD::XOR); 801 } 802 803 setStackPointerRegisterToSaveRestore(ARM::SP); 804 805 if (TM.Options.UseSoftFloat || Subtarget->isThumb1Only() || 806 !Subtarget->hasVFP2()) 807 setSchedulingPreference(Sched::RegPressure); 808 else 809 setSchedulingPreference(Sched::Hybrid); 810 811 //// temporary - rewrite interface to use type 812 maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 1; 813 maxStoresPerMemset = 16; 814 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 815 816 // On ARM arguments smaller than 4 bytes are extended, so all arguments 817 // are at least 4 bytes aligned. 818 setMinStackArgumentAlignment(4); 819 820 benefitFromCodePlacementOpt = true; 821 822 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2); 823} 824 825// FIXME: It might make sense to define the representative register class as the 826// nearest super-register that has a non-null superset. For example, DPR_VFP2 is 827// a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently, 828// SPR's representative would be DPR_VFP2. This should work well if register 829// pressure tracking were modified such that a register use would increment the 830// pressure of the register class's representative and all of it's super 831// classes' representatives transitively. We have not implemented this because 832// of the difficulty prior to coalescing of modeling operand register classes 833// due to the common occurrence of cross class copies and subregister insertions 834// and extractions. 835std::pair<const TargetRegisterClass*, uint8_t> 836ARMTargetLowering::findRepresentativeClass(EVT VT) const{ 837 const TargetRegisterClass *RRC = 0; 838 uint8_t Cost = 1; 839 switch (VT.getSimpleVT().SimpleTy) { 840 default: 841 return TargetLowering::findRepresentativeClass(VT); 842 // Use DPR as representative register class for all floating point 843 // and vector types. Since there are 32 SPR registers and 32 DPR registers so 844 // the cost is 1 for both f32 and f64. 845 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16: 846 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32: 847 RRC = ARM::DPRRegisterClass; 848 // When NEON is used for SP, only half of the register file is available 849 // because operations that define both SP and DP results will be constrained 850 // to the VFP2 class (D0-D15). We currently model this constraint prior to 851 // coalescing by double-counting the SP regs. See the FIXME above. 852 if (Subtarget->useNEONForSinglePrecisionFP()) 853 Cost = 2; 854 break; 855 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 856 case MVT::v4f32: case MVT::v2f64: 857 RRC = ARM::DPRRegisterClass; 858 Cost = 2; 859 break; 860 case MVT::v4i64: 861 RRC = ARM::DPRRegisterClass; 862 Cost = 4; 863 break; 864 case MVT::v8i64: 865 RRC = ARM::DPRRegisterClass; 866 Cost = 8; 867 break; 868 } 869 return std::make_pair(RRC, Cost); 870} 871 872const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { 873 switch (Opcode) { 874 default: return 0; 875 case ARMISD::Wrapper: return "ARMISD::Wrapper"; 876 case ARMISD::WrapperDYN: return "ARMISD::WrapperDYN"; 877 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC"; 878 case ARMISD::WrapperJT: return "ARMISD::WrapperJT"; 879 case ARMISD::CALL: return "ARMISD::CALL"; 880 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED"; 881 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK"; 882 case ARMISD::tCALL: return "ARMISD::tCALL"; 883 case ARMISD::BRCOND: return "ARMISD::BRCOND"; 884 case ARMISD::BR_JT: return "ARMISD::BR_JT"; 885 case ARMISD::BR2_JT: return "ARMISD::BR2_JT"; 886 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; 887 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD"; 888 case ARMISD::CMP: return "ARMISD::CMP"; 889 case ARMISD::CMPZ: return "ARMISD::CMPZ"; 890 case ARMISD::CMPFP: return "ARMISD::CMPFP"; 891 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0"; 892 case ARMISD::BCC_i64: return "ARMISD::BCC_i64"; 893 case ARMISD::FMSTAT: return "ARMISD::FMSTAT"; 894 895 case ARMISD::CMOV: return "ARMISD::CMOV"; 896 case ARMISD::CAND: return "ARMISD::CAND"; 897 case ARMISD::COR: return "ARMISD::COR"; 898 case ARMISD::CXOR: return "ARMISD::CXOR"; 899 900 case ARMISD::RBIT: return "ARMISD::RBIT"; 901 902 case ARMISD::FTOSI: return "ARMISD::FTOSI"; 903 case ARMISD::FTOUI: return "ARMISD::FTOUI"; 904 case ARMISD::SITOF: return "ARMISD::SITOF"; 905 case ARMISD::UITOF: return "ARMISD::UITOF"; 906 907 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG"; 908 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG"; 909 case ARMISD::RRX: return "ARMISD::RRX"; 910 911 case ARMISD::ADDC: return "ARMISD::ADDC"; 912 case ARMISD::ADDE: return "ARMISD::ADDE"; 913 case ARMISD::SUBC: return "ARMISD::SUBC"; 914 case ARMISD::SUBE: return "ARMISD::SUBE"; 915 916 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD"; 917 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR"; 918 919 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP"; 920 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP"; 921 922 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN"; 923 924 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER"; 925 926 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC"; 927 928 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER"; 929 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR"; 930 931 case ARMISD::PRELOAD: return "ARMISD::PRELOAD"; 932 933 case ARMISD::VCEQ: return "ARMISD::VCEQ"; 934 case ARMISD::VCEQZ: return "ARMISD::VCEQZ"; 935 case ARMISD::VCGE: return "ARMISD::VCGE"; 936 case ARMISD::VCGEZ: return "ARMISD::VCGEZ"; 937 case ARMISD::VCLEZ: return "ARMISD::VCLEZ"; 938 case ARMISD::VCGEU: return "ARMISD::VCGEU"; 939 case ARMISD::VCGT: return "ARMISD::VCGT"; 940 case ARMISD::VCGTZ: return "ARMISD::VCGTZ"; 941 case ARMISD::VCLTZ: return "ARMISD::VCLTZ"; 942 case ARMISD::VCGTU: return "ARMISD::VCGTU"; 943 case ARMISD::VTST: return "ARMISD::VTST"; 944 945 case ARMISD::VSHL: return "ARMISD::VSHL"; 946 case ARMISD::VSHRs: return "ARMISD::VSHRs"; 947 case ARMISD::VSHRu: return "ARMISD::VSHRu"; 948 case ARMISD::VSHLLs: return "ARMISD::VSHLLs"; 949 case ARMISD::VSHLLu: return "ARMISD::VSHLLu"; 950 case ARMISD::VSHLLi: return "ARMISD::VSHLLi"; 951 case ARMISD::VSHRN: return "ARMISD::VSHRN"; 952 case ARMISD::VRSHRs: return "ARMISD::VRSHRs"; 953 case ARMISD::VRSHRu: return "ARMISD::VRSHRu"; 954 case ARMISD::VRSHRN: return "ARMISD::VRSHRN"; 955 case ARMISD::VQSHLs: return "ARMISD::VQSHLs"; 956 case ARMISD::VQSHLu: return "ARMISD::VQSHLu"; 957 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu"; 958 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs"; 959 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu"; 960 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu"; 961 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs"; 962 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu"; 963 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu"; 964 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu"; 965 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs"; 966 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM"; 967 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM"; 968 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM"; 969 case ARMISD::VDUP: return "ARMISD::VDUP"; 970 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE"; 971 case ARMISD::VEXT: return "ARMISD::VEXT"; 972 case ARMISD::VREV64: return "ARMISD::VREV64"; 973 case ARMISD::VREV32: return "ARMISD::VREV32"; 974 case ARMISD::VREV16: return "ARMISD::VREV16"; 975 case ARMISD::VZIP: return "ARMISD::VZIP"; 976 case ARMISD::VUZP: return "ARMISD::VUZP"; 977 case ARMISD::VTRN: return "ARMISD::VTRN"; 978 case ARMISD::VTBL1: return "ARMISD::VTBL1"; 979 case ARMISD::VTBL2: return "ARMISD::VTBL2"; 980 case ARMISD::VMULLs: return "ARMISD::VMULLs"; 981 case ARMISD::VMULLu: return "ARMISD::VMULLu"; 982 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR"; 983 case ARMISD::FMAX: return "ARMISD::FMAX"; 984 case ARMISD::FMIN: return "ARMISD::FMIN"; 985 case ARMISD::BFI: return "ARMISD::BFI"; 986 case ARMISD::VORRIMM: return "ARMISD::VORRIMM"; 987 case ARMISD::VBICIMM: return "ARMISD::VBICIMM"; 988 case ARMISD::VBSL: return "ARMISD::VBSL"; 989 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP"; 990 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP"; 991 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP"; 992 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD"; 993 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD"; 994 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD"; 995 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD"; 996 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD"; 997 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD"; 998 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD"; 999 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD"; 1000 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD"; 1001 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD"; 1002 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD"; 1003 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD"; 1004 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD"; 1005 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD"; 1006 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD"; 1007 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD"; 1008 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD"; 1009 } 1010} 1011 1012EVT ARMTargetLowering::getSetCCResultType(EVT VT) const { 1013 if (!VT.isVector()) return getPointerTy(); 1014 return VT.changeVectorElementTypeToInteger(); 1015} 1016 1017/// getRegClassFor - Return the register class that should be used for the 1018/// specified value type. 1019const TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const { 1020 // Map v4i64 to QQ registers but do not make the type legal. Similarly map 1021 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to 1022 // load / store 4 to 8 consecutive D registers. 1023 if (Subtarget->hasNEON()) { 1024 if (VT == MVT::v4i64) 1025 return ARM::QQPRRegisterClass; 1026 else if (VT == MVT::v8i64) 1027 return ARM::QQQQPRRegisterClass; 1028 } 1029 return TargetLowering::getRegClassFor(VT); 1030} 1031 1032// Create a fast isel object. 1033FastISel * 1034ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 1035 return ARM::createFastISel(funcInfo); 1036} 1037 1038/// getMaximalGlobalOffset - Returns the maximal possible offset which can 1039/// be used for loads / stores from the global. 1040unsigned ARMTargetLowering::getMaximalGlobalOffset() const { 1041 return (Subtarget->isThumb1Only() ? 127 : 4095); 1042} 1043 1044Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const { 1045 unsigned NumVals = N->getNumValues(); 1046 if (!NumVals) 1047 return Sched::RegPressure; 1048 1049 for (unsigned i = 0; i != NumVals; ++i) { 1050 EVT VT = N->getValueType(i); 1051 if (VT == MVT::Glue || VT == MVT::Other) 1052 continue; 1053 if (VT.isFloatingPoint() || VT.isVector()) 1054 return Sched::ILP; 1055 } 1056 1057 if (!N->isMachineOpcode()) 1058 return Sched::RegPressure; 1059 1060 // Load are scheduled for latency even if there instruction itinerary 1061 // is not available. 1062 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1063 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); 1064 1065 if (MCID.getNumDefs() == 0) 1066 return Sched::RegPressure; 1067 if (!Itins->isEmpty() && 1068 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2) 1069 return Sched::ILP; 1070 1071 return Sched::RegPressure; 1072} 1073 1074//===----------------------------------------------------------------------===// 1075// Lowering Code 1076//===----------------------------------------------------------------------===// 1077 1078/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC 1079static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { 1080 switch (CC) { 1081 default: llvm_unreachable("Unknown condition code!"); 1082 case ISD::SETNE: return ARMCC::NE; 1083 case ISD::SETEQ: return ARMCC::EQ; 1084 case ISD::SETGT: return ARMCC::GT; 1085 case ISD::SETGE: return ARMCC::GE; 1086 case ISD::SETLT: return ARMCC::LT; 1087 case ISD::SETLE: return ARMCC::LE; 1088 case ISD::SETUGT: return ARMCC::HI; 1089 case ISD::SETUGE: return ARMCC::HS; 1090 case ISD::SETULT: return ARMCC::LO; 1091 case ISD::SETULE: return ARMCC::LS; 1092 } 1093} 1094 1095/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. 1096static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, 1097 ARMCC::CondCodes &CondCode2) { 1098 CondCode2 = ARMCC::AL; 1099 switch (CC) { 1100 default: llvm_unreachable("Unknown FP condition!"); 1101 case ISD::SETEQ: 1102 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; 1103 case ISD::SETGT: 1104 case ISD::SETOGT: CondCode = ARMCC::GT; break; 1105 case ISD::SETGE: 1106 case ISD::SETOGE: CondCode = ARMCC::GE; break; 1107 case ISD::SETOLT: CondCode = ARMCC::MI; break; 1108 case ISD::SETOLE: CondCode = ARMCC::LS; break; 1109 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break; 1110 case ISD::SETO: CondCode = ARMCC::VC; break; 1111 case ISD::SETUO: CondCode = ARMCC::VS; break; 1112 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break; 1113 case ISD::SETUGT: CondCode = ARMCC::HI; break; 1114 case ISD::SETUGE: CondCode = ARMCC::PL; break; 1115 case ISD::SETLT: 1116 case ISD::SETULT: CondCode = ARMCC::LT; break; 1117 case ISD::SETLE: 1118 case ISD::SETULE: CondCode = ARMCC::LE; break; 1119 case ISD::SETNE: 1120 case ISD::SETUNE: CondCode = ARMCC::NE; break; 1121 } 1122} 1123 1124//===----------------------------------------------------------------------===// 1125// Calling Convention Implementation 1126//===----------------------------------------------------------------------===// 1127 1128#include "ARMGenCallingConv.inc" 1129 1130/// CCAssignFnForNode - Selects the correct CCAssignFn for a the 1131/// given CallingConvention value. 1132CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC, 1133 bool Return, 1134 bool isVarArg) const { 1135 switch (CC) { 1136 default: 1137 llvm_unreachable("Unsupported calling convention"); 1138 case CallingConv::Fast: 1139 if (Subtarget->hasVFP2() && !isVarArg) { 1140 if (!Subtarget->isAAPCS_ABI()) 1141 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS); 1142 // For AAPCS ABI targets, just use VFP variant of the calling convention. 1143 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP); 1144 } 1145 // Fallthrough 1146 case CallingConv::C: { 1147 // Use target triple & subtarget features to do actual dispatch. 1148 if (!Subtarget->isAAPCS_ABI()) 1149 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS); 1150 else if (Subtarget->hasVFP2() && 1151 getTargetMachine().Options.FloatABIType == FloatABI::Hard && 1152 !isVarArg) 1153 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP); 1154 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS); 1155 } 1156 case CallingConv::ARM_AAPCS_VFP: 1157 if (!isVarArg) 1158 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP); 1159 // Fallthrough 1160 case CallingConv::ARM_AAPCS: 1161 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS); 1162 case CallingConv::ARM_APCS: 1163 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS); 1164 } 1165} 1166 1167/// LowerCallResult - Lower the result values of a call into the 1168/// appropriate copies out of appropriate physical registers. 1169SDValue 1170ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1171 CallingConv::ID CallConv, bool isVarArg, 1172 const SmallVectorImpl<ISD::InputArg> &Ins, 1173 DebugLoc dl, SelectionDAG &DAG, 1174 SmallVectorImpl<SDValue> &InVals) const { 1175 1176 // Assign locations to each value returned by this call. 1177 SmallVector<CCValAssign, 16> RVLocs; 1178 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1179 getTargetMachine(), RVLocs, *DAG.getContext(), Call); 1180 CCInfo.AnalyzeCallResult(Ins, 1181 CCAssignFnForNode(CallConv, /* Return*/ true, 1182 isVarArg)); 1183 1184 // Copy all of the result registers out of their specified physreg. 1185 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1186 CCValAssign VA = RVLocs[i]; 1187 1188 SDValue Val; 1189 if (VA.needsCustom()) { 1190 // Handle f64 or half of a v2f64. 1191 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 1192 InFlag); 1193 Chain = Lo.getValue(1); 1194 InFlag = Lo.getValue(2); 1195 VA = RVLocs[++i]; // skip ahead to next loc 1196 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 1197 InFlag); 1198 Chain = Hi.getValue(1); 1199 InFlag = Hi.getValue(2); 1200 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); 1201 1202 if (VA.getLocVT() == MVT::v2f64) { 1203 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); 1204 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 1205 DAG.getConstant(0, MVT::i32)); 1206 1207 VA = RVLocs[++i]; // skip ahead to next loc 1208 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); 1209 Chain = Lo.getValue(1); 1210 InFlag = Lo.getValue(2); 1211 VA = RVLocs[++i]; // skip ahead to next loc 1212 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); 1213 Chain = Hi.getValue(1); 1214 InFlag = Hi.getValue(2); 1215 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); 1216 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 1217 DAG.getConstant(1, MVT::i32)); 1218 } 1219 } else { 1220 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), 1221 InFlag); 1222 Chain = Val.getValue(1); 1223 InFlag = Val.getValue(2); 1224 } 1225 1226 switch (VA.getLocInfo()) { 1227 default: llvm_unreachable("Unknown loc info!"); 1228 case CCValAssign::Full: break; 1229 case CCValAssign::BCvt: 1230 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val); 1231 break; 1232 } 1233 1234 InVals.push_back(Val); 1235 } 1236 1237 return Chain; 1238} 1239 1240/// LowerMemOpCallTo - Store the argument to the stack. 1241SDValue 1242ARMTargetLowering::LowerMemOpCallTo(SDValue Chain, 1243 SDValue StackPtr, SDValue Arg, 1244 DebugLoc dl, SelectionDAG &DAG, 1245 const CCValAssign &VA, 1246 ISD::ArgFlagsTy Flags) const { 1247 unsigned LocMemOffset = VA.getLocMemOffset(); 1248 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1249 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1250 return DAG.getStore(Chain, dl, Arg, PtrOff, 1251 MachinePointerInfo::getStack(LocMemOffset), 1252 false, false, 0); 1253} 1254 1255void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, 1256 SDValue Chain, SDValue &Arg, 1257 RegsToPassVector &RegsToPass, 1258 CCValAssign &VA, CCValAssign &NextVA, 1259 SDValue &StackPtr, 1260 SmallVector<SDValue, 8> &MemOpChains, 1261 ISD::ArgFlagsTy Flags) const { 1262 1263 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, 1264 DAG.getVTList(MVT::i32, MVT::i32), Arg); 1265 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd)); 1266 1267 if (NextVA.isRegLoc()) 1268 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1))); 1269 else { 1270 assert(NextVA.isMemLoc()); 1271 if (StackPtr.getNode() == 0) 1272 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); 1273 1274 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1), 1275 dl, DAG, NextVA, 1276 Flags)); 1277 } 1278} 1279 1280/// LowerCall - Lowering a call into a callseq_start <- 1281/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter 1282/// nodes. 1283SDValue 1284ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 1285 CallingConv::ID CallConv, bool isVarArg, 1286 bool &isTailCall, 1287 const SmallVectorImpl<ISD::OutputArg> &Outs, 1288 const SmallVectorImpl<SDValue> &OutVals, 1289 const SmallVectorImpl<ISD::InputArg> &Ins, 1290 DebugLoc dl, SelectionDAG &DAG, 1291 SmallVectorImpl<SDValue> &InVals) const { 1292 MachineFunction &MF = DAG.getMachineFunction(); 1293 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet(); 1294 bool IsSibCall = false; 1295 // Disable tail calls if they're not supported. 1296 if (!EnableARMTailCalls && !Subtarget->supportsTailCall()) 1297 isTailCall = false; 1298 if (isTailCall) { 1299 // Check if it's really possible to do a tail call. 1300 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 1301 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 1302 Outs, OutVals, Ins, DAG); 1303 // We don't support GuaranteedTailCallOpt for ARM, only automatically 1304 // detected sibcalls. 1305 if (isTailCall) { 1306 ++NumTailCalls; 1307 IsSibCall = true; 1308 } 1309 } 1310 1311 // Analyze operands of the call, assigning locations to each operand. 1312 SmallVector<CCValAssign, 16> ArgLocs; 1313 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1314 getTargetMachine(), ArgLocs, *DAG.getContext(), Call); 1315 CCInfo.AnalyzeCallOperands(Outs, 1316 CCAssignFnForNode(CallConv, /* Return*/ false, 1317 isVarArg)); 1318 1319 // Get a count of how many bytes are to be pushed on the stack. 1320 unsigned NumBytes = CCInfo.getNextStackOffset(); 1321 1322 // For tail calls, memory operands are available in our caller's stack. 1323 if (IsSibCall) 1324 NumBytes = 0; 1325 1326 // Adjust the stack pointer for the new arguments... 1327 // These operations are automatically eliminated by the prolog/epilog pass 1328 if (!IsSibCall) 1329 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 1330 1331 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); 1332 1333 RegsToPassVector RegsToPass; 1334 SmallVector<SDValue, 8> MemOpChains; 1335 1336 // Walk the register/memloc assignments, inserting copies/loads. In the case 1337 // of tail call optimization, arguments are handled later. 1338 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); 1339 i != e; 1340 ++i, ++realArgIdx) { 1341 CCValAssign &VA = ArgLocs[i]; 1342 SDValue Arg = OutVals[realArgIdx]; 1343 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 1344 bool isByVal = Flags.isByVal(); 1345 1346 // Promote the value if needed. 1347 switch (VA.getLocInfo()) { 1348 default: llvm_unreachable("Unknown loc info!"); 1349 case CCValAssign::Full: break; 1350 case CCValAssign::SExt: 1351 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 1352 break; 1353 case CCValAssign::ZExt: 1354 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 1355 break; 1356 case CCValAssign::AExt: 1357 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 1358 break; 1359 case CCValAssign::BCvt: 1360 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 1361 break; 1362 } 1363 1364 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces 1365 if (VA.needsCustom()) { 1366 if (VA.getLocVT() == MVT::v2f64) { 1367 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1368 DAG.getConstant(0, MVT::i32)); 1369 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1370 DAG.getConstant(1, MVT::i32)); 1371 1372 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass, 1373 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); 1374 1375 VA = ArgLocs[++i]; // skip ahead to next loc 1376 if (VA.isRegLoc()) { 1377 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass, 1378 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); 1379 } else { 1380 assert(VA.isMemLoc()); 1381 1382 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1, 1383 dl, DAG, VA, Flags)); 1384 } 1385 } else { 1386 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i], 1387 StackPtr, MemOpChains, Flags); 1388 } 1389 } else if (VA.isRegLoc()) { 1390 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1391 } else if (isByVal) { 1392 assert(VA.isMemLoc()); 1393 unsigned offset = 0; 1394 1395 // True if this byval aggregate will be split between registers 1396 // and memory. 1397 if (CCInfo.isFirstByValRegValid()) { 1398 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1399 unsigned int i, j; 1400 for (i = 0, j = CCInfo.getFirstByValReg(); j < ARM::R4; i++, j++) { 1401 SDValue Const = DAG.getConstant(4*i, MVT::i32); 1402 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 1403 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, 1404 MachinePointerInfo(), 1405 false, false, false, 0); 1406 MemOpChains.push_back(Load.getValue(1)); 1407 RegsToPass.push_back(std::make_pair(j, Load)); 1408 } 1409 offset = ARM::R4 - CCInfo.getFirstByValReg(); 1410 CCInfo.clearFirstByValReg(); 1411 } 1412 1413 unsigned LocMemOffset = VA.getLocMemOffset(); 1414 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset); 1415 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, 1416 StkPtrOff); 1417 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset); 1418 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset); 1419 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, 1420 MVT::i32); 1421 MemOpChains.push_back(DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, 1422 Flags.getByValAlign(), 1423 /*isVolatile=*/false, 1424 /*AlwaysInline=*/false, 1425 MachinePointerInfo(0), 1426 MachinePointerInfo(0))); 1427 1428 } else if (!IsSibCall) { 1429 assert(VA.isMemLoc()); 1430 1431 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 1432 dl, DAG, VA, Flags)); 1433 } 1434 } 1435 1436 if (!MemOpChains.empty()) 1437 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1438 &MemOpChains[0], MemOpChains.size()); 1439 1440 // Build a sequence of copy-to-reg nodes chained together with token chain 1441 // and flag operands which copy the outgoing args into the appropriate regs. 1442 SDValue InFlag; 1443 // Tail call byval lowering might overwrite argument registers so in case of 1444 // tail call optimization the copies to registers are lowered later. 1445 if (!isTailCall) 1446 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1447 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1448 RegsToPass[i].second, InFlag); 1449 InFlag = Chain.getValue(1); 1450 } 1451 1452 // For tail calls lower the arguments to the 'real' stack slot. 1453 if (isTailCall) { 1454 // Force all the incoming stack arguments to be loaded from the stack 1455 // before any new outgoing arguments are stored to the stack, because the 1456 // outgoing stack slots may alias the incoming argument stack slots, and 1457 // the alias isn't otherwise explicit. This is slightly more conservative 1458 // than necessary, because it means that each store effectively depends 1459 // on every argument instead of just those arguments it would clobber. 1460 1461 // Do not flag preceding copytoreg stuff together with the following stuff. 1462 InFlag = SDValue(); 1463 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1464 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1465 RegsToPass[i].second, InFlag); 1466 InFlag = Chain.getValue(1); 1467 } 1468 InFlag =SDValue(); 1469 } 1470 1471 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 1472 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 1473 // node so that legalize doesn't hack it. 1474 bool isDirect = false; 1475 bool isARMFunc = false; 1476 bool isLocalARMFunc = false; 1477 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1478 1479 if (EnableARMLongCalls) { 1480 assert (getTargetMachine().getRelocationModel() == Reloc::Static 1481 && "long-calls with non-static relocation model!"); 1482 // Handle a global address or an external symbol. If it's not one of 1483 // those, the target's already in a register, so we don't need to do 1484 // anything extra. 1485 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1486 const GlobalValue *GV = G->getGlobal(); 1487 // Create a constant pool entry for the callee address 1488 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1489 ARMConstantPoolValue *CPV = 1490 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0); 1491 1492 // Get the address of the callee into a register 1493 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1494 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1495 Callee = DAG.getLoad(getPointerTy(), dl, 1496 DAG.getEntryNode(), CPAddr, 1497 MachinePointerInfo::getConstantPool(), 1498 false, false, false, 0); 1499 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) { 1500 const char *Sym = S->getSymbol(); 1501 1502 // Create a constant pool entry for the callee address 1503 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1504 ARMConstantPoolValue *CPV = 1505 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym, 1506 ARMPCLabelIndex, 0); 1507 // Get the address of the callee into a register 1508 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1509 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1510 Callee = DAG.getLoad(getPointerTy(), dl, 1511 DAG.getEntryNode(), CPAddr, 1512 MachinePointerInfo::getConstantPool(), 1513 false, false, false, 0); 1514 } 1515 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1516 const GlobalValue *GV = G->getGlobal(); 1517 isDirect = true; 1518 bool isExt = GV->isDeclaration() || GV->isWeakForLinker(); 1519 bool isStub = (isExt && Subtarget->isTargetDarwin()) && 1520 getTargetMachine().getRelocationModel() != Reloc::Static; 1521 isARMFunc = !Subtarget->isThumb() || isStub; 1522 // ARM call to a local ARM function is predicable. 1523 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking); 1524 // tBX takes a register source operand. 1525 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { 1526 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1527 ARMConstantPoolValue *CPV = 1528 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 4); 1529 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1530 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1531 Callee = DAG.getLoad(getPointerTy(), dl, 1532 DAG.getEntryNode(), CPAddr, 1533 MachinePointerInfo::getConstantPool(), 1534 false, false, false, 0); 1535 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1536 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, 1537 getPointerTy(), Callee, PICLabel); 1538 } else { 1539 // On ELF targets for PIC code, direct calls should go through the PLT 1540 unsigned OpFlags = 0; 1541 if (Subtarget->isTargetELF() && 1542 getTargetMachine().getRelocationModel() == Reloc::PIC_) 1543 OpFlags = ARMII::MO_PLT; 1544 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 1545 } 1546 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 1547 isDirect = true; 1548 bool isStub = Subtarget->isTargetDarwin() && 1549 getTargetMachine().getRelocationModel() != Reloc::Static; 1550 isARMFunc = !Subtarget->isThumb() || isStub; 1551 // tBX takes a register source operand. 1552 const char *Sym = S->getSymbol(); 1553 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { 1554 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1555 ARMConstantPoolValue *CPV = 1556 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym, 1557 ARMPCLabelIndex, 4); 1558 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1559 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1560 Callee = DAG.getLoad(getPointerTy(), dl, 1561 DAG.getEntryNode(), CPAddr, 1562 MachinePointerInfo::getConstantPool(), 1563 false, false, false, 0); 1564 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1565 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, 1566 getPointerTy(), Callee, PICLabel); 1567 } else { 1568 unsigned OpFlags = 0; 1569 // On ELF targets for PIC code, direct calls should go through the PLT 1570 if (Subtarget->isTargetELF() && 1571 getTargetMachine().getRelocationModel() == Reloc::PIC_) 1572 OpFlags = ARMII::MO_PLT; 1573 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags); 1574 } 1575 } 1576 1577 // FIXME: handle tail calls differently. 1578 unsigned CallOpc; 1579 if (Subtarget->isThumb()) { 1580 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps()) 1581 CallOpc = ARMISD::CALL_NOLINK; 1582 else 1583 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL; 1584 } else { 1585 CallOpc = (isDirect || Subtarget->hasV5TOps()) 1586 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL) 1587 : ARMISD::CALL_NOLINK; 1588 } 1589 1590 std::vector<SDValue> Ops; 1591 Ops.push_back(Chain); 1592 Ops.push_back(Callee); 1593 1594 // Add argument registers to the end of the list so that they are known live 1595 // into the call. 1596 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1597 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1598 RegsToPass[i].second.getValueType())); 1599 1600 if (InFlag.getNode()) 1601 Ops.push_back(InFlag); 1602 1603 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 1604 if (isTailCall) 1605 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size()); 1606 1607 // Returns a chain and a flag for retval copy to use. 1608 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); 1609 InFlag = Chain.getValue(1); 1610 1611 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 1612 DAG.getIntPtrConstant(0, true), InFlag); 1613 if (!Ins.empty()) 1614 InFlag = Chain.getValue(1); 1615 1616 // Handle result values, copying them out of physregs into vregs that we 1617 // return. 1618 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, 1619 dl, DAG, InVals); 1620} 1621 1622/// HandleByVal - Every parameter *after* a byval parameter is passed 1623/// on the stack. Remember the next parameter register to allocate, 1624/// and then confiscate the rest of the parameter registers to insure 1625/// this. 1626void 1627llvm::ARMTargetLowering::HandleByVal(CCState *State, unsigned &size) const { 1628 unsigned reg = State->AllocateReg(GPRArgRegs, 4); 1629 assert((State->getCallOrPrologue() == Prologue || 1630 State->getCallOrPrologue() == Call) && 1631 "unhandled ParmContext"); 1632 if ((!State->isFirstByValRegValid()) && 1633 (ARM::R0 <= reg) && (reg <= ARM::R3)) { 1634 State->setFirstByValReg(reg); 1635 // At a call site, a byval parameter that is split between 1636 // registers and memory needs its size truncated here. In a 1637 // function prologue, such byval parameters are reassembled in 1638 // memory, and are not truncated. 1639 if (State->getCallOrPrologue() == Call) { 1640 unsigned excess = 4 * (ARM::R4 - reg); 1641 assert(size >= excess && "expected larger existing stack allocation"); 1642 size -= excess; 1643 } 1644 } 1645 // Confiscate any remaining parameter registers to preclude their 1646 // assignment to subsequent parameters. 1647 while (State->AllocateReg(GPRArgRegs, 4)) 1648 ; 1649} 1650 1651/// MatchingStackOffset - Return true if the given stack call argument is 1652/// already available in the same position (relatively) of the caller's 1653/// incoming argument stack. 1654static 1655bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 1656 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 1657 const ARMInstrInfo *TII) { 1658 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 1659 int FI = INT_MAX; 1660 if (Arg.getOpcode() == ISD::CopyFromReg) { 1661 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 1662 if (!TargetRegisterInfo::isVirtualRegister(VR)) 1663 return false; 1664 MachineInstr *Def = MRI->getVRegDef(VR); 1665 if (!Def) 1666 return false; 1667 if (!Flags.isByVal()) { 1668 if (!TII->isLoadFromStackSlot(Def, FI)) 1669 return false; 1670 } else { 1671 return false; 1672 } 1673 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 1674 if (Flags.isByVal()) 1675 // ByVal argument is passed in as a pointer but it's now being 1676 // dereferenced. e.g. 1677 // define @foo(%struct.X* %A) { 1678 // tail call @bar(%struct.X* byval %A) 1679 // } 1680 return false; 1681 SDValue Ptr = Ld->getBasePtr(); 1682 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 1683 if (!FINode) 1684 return false; 1685 FI = FINode->getIndex(); 1686 } else 1687 return false; 1688 1689 assert(FI != INT_MAX); 1690 if (!MFI->isFixedObjectIndex(FI)) 1691 return false; 1692 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 1693} 1694 1695/// IsEligibleForTailCallOptimization - Check whether the call is eligible 1696/// for tail call optimization. Targets which want to do tail call 1697/// optimization should implement this function. 1698bool 1699ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 1700 CallingConv::ID CalleeCC, 1701 bool isVarArg, 1702 bool isCalleeStructRet, 1703 bool isCallerStructRet, 1704 const SmallVectorImpl<ISD::OutputArg> &Outs, 1705 const SmallVectorImpl<SDValue> &OutVals, 1706 const SmallVectorImpl<ISD::InputArg> &Ins, 1707 SelectionDAG& DAG) const { 1708 const Function *CallerF = DAG.getMachineFunction().getFunction(); 1709 CallingConv::ID CallerCC = CallerF->getCallingConv(); 1710 bool CCMatch = CallerCC == CalleeCC; 1711 1712 // Look for obvious safe cases to perform tail call optimization that do not 1713 // require ABI changes. This is what gcc calls sibcall. 1714 1715 // Do not sibcall optimize vararg calls unless the call site is not passing 1716 // any arguments. 1717 if (isVarArg && !Outs.empty()) 1718 return false; 1719 1720 // Also avoid sibcall optimization if either caller or callee uses struct 1721 // return semantics. 1722 if (isCalleeStructRet || isCallerStructRet) 1723 return false; 1724 1725 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo:: 1726 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as 1727 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation 1728 // support in the assembler and linker to be used. This would need to be 1729 // fixed to fully support tail calls in Thumb1. 1730 // 1731 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take 1732 // LR. This means if we need to reload LR, it takes an extra instructions, 1733 // which outweighs the value of the tail call; but here we don't know yet 1734 // whether LR is going to be used. Probably the right approach is to 1735 // generate the tail call here and turn it back into CALL/RET in 1736 // emitEpilogue if LR is used. 1737 1738 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls, 1739 // but we need to make sure there are enough registers; the only valid 1740 // registers are the 4 used for parameters. We don't currently do this 1741 // case. 1742 if (Subtarget->isThumb1Only()) 1743 return false; 1744 1745 // If the calling conventions do not match, then we'd better make sure the 1746 // results are returned in the same way as what the caller expects. 1747 if (!CCMatch) { 1748 SmallVector<CCValAssign, 16> RVLocs1; 1749 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 1750 getTargetMachine(), RVLocs1, *DAG.getContext(), Call); 1751 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg)); 1752 1753 SmallVector<CCValAssign, 16> RVLocs2; 1754 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 1755 getTargetMachine(), RVLocs2, *DAG.getContext(), Call); 1756 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg)); 1757 1758 if (RVLocs1.size() != RVLocs2.size()) 1759 return false; 1760 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 1761 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 1762 return false; 1763 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 1764 return false; 1765 if (RVLocs1[i].isRegLoc()) { 1766 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 1767 return false; 1768 } else { 1769 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 1770 return false; 1771 } 1772 } 1773 } 1774 1775 // If the callee takes no arguments then go on to check the results of the 1776 // call. 1777 if (!Outs.empty()) { 1778 // Check if stack adjustment is needed. For now, do not do this if any 1779 // argument is passed on the stack. 1780 SmallVector<CCValAssign, 16> ArgLocs; 1781 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 1782 getTargetMachine(), ArgLocs, *DAG.getContext(), Call); 1783 CCInfo.AnalyzeCallOperands(Outs, 1784 CCAssignFnForNode(CalleeCC, false, isVarArg)); 1785 if (CCInfo.getNextStackOffset()) { 1786 MachineFunction &MF = DAG.getMachineFunction(); 1787 1788 // Check if the arguments are already laid out in the right way as 1789 // the caller's fixed stack objects. 1790 MachineFrameInfo *MFI = MF.getFrameInfo(); 1791 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 1792 const ARMInstrInfo *TII = 1793 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo(); 1794 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); 1795 i != e; 1796 ++i, ++realArgIdx) { 1797 CCValAssign &VA = ArgLocs[i]; 1798 EVT RegVT = VA.getLocVT(); 1799 SDValue Arg = OutVals[realArgIdx]; 1800 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 1801 if (VA.getLocInfo() == CCValAssign::Indirect) 1802 return false; 1803 if (VA.needsCustom()) { 1804 // f64 and vector types are split into multiple registers or 1805 // register/stack-slot combinations. The types will not match 1806 // the registers; give up on memory f64 refs until we figure 1807 // out what to do about this. 1808 if (!VA.isRegLoc()) 1809 return false; 1810 if (!ArgLocs[++i].isRegLoc()) 1811 return false; 1812 if (RegVT == MVT::v2f64) { 1813 if (!ArgLocs[++i].isRegLoc()) 1814 return false; 1815 if (!ArgLocs[++i].isRegLoc()) 1816 return false; 1817 } 1818 } else if (!VA.isRegLoc()) { 1819 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 1820 MFI, MRI, TII)) 1821 return false; 1822 } 1823 } 1824 } 1825 } 1826 1827 return true; 1828} 1829 1830SDValue 1831ARMTargetLowering::LowerReturn(SDValue Chain, 1832 CallingConv::ID CallConv, bool isVarArg, 1833 const SmallVectorImpl<ISD::OutputArg> &Outs, 1834 const SmallVectorImpl<SDValue> &OutVals, 1835 DebugLoc dl, SelectionDAG &DAG) const { 1836 1837 // CCValAssign - represent the assignment of the return value to a location. 1838 SmallVector<CCValAssign, 16> RVLocs; 1839 1840 // CCState - Info about the registers and stack slots. 1841 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1842 getTargetMachine(), RVLocs, *DAG.getContext(), Call); 1843 1844 // Analyze outgoing return values. 1845 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true, 1846 isVarArg)); 1847 1848 // If this is the first return lowered for this function, add 1849 // the regs to the liveout set for the function. 1850 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 1851 for (unsigned i = 0; i != RVLocs.size(); ++i) 1852 if (RVLocs[i].isRegLoc()) 1853 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 1854 } 1855 1856 SDValue Flag; 1857 1858 // Copy the result values into the output registers. 1859 for (unsigned i = 0, realRVLocIdx = 0; 1860 i != RVLocs.size(); 1861 ++i, ++realRVLocIdx) { 1862 CCValAssign &VA = RVLocs[i]; 1863 assert(VA.isRegLoc() && "Can only return in registers!"); 1864 1865 SDValue Arg = OutVals[realRVLocIdx]; 1866 1867 switch (VA.getLocInfo()) { 1868 default: llvm_unreachable("Unknown loc info!"); 1869 case CCValAssign::Full: break; 1870 case CCValAssign::BCvt: 1871 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 1872 break; 1873 } 1874 1875 if (VA.needsCustom()) { 1876 if (VA.getLocVT() == MVT::v2f64) { 1877 // Extract the first half and return it in two registers. 1878 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1879 DAG.getConstant(0, MVT::i32)); 1880 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl, 1881 DAG.getVTList(MVT::i32, MVT::i32), Half); 1882 1883 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag); 1884 Flag = Chain.getValue(1); 1885 VA = RVLocs[++i]; // skip ahead to next loc 1886 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 1887 HalfGPRs.getValue(1), Flag); 1888 Flag = Chain.getValue(1); 1889 VA = RVLocs[++i]; // skip ahead to next loc 1890 1891 // Extract the 2nd half and fall through to handle it as an f64 value. 1892 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1893 DAG.getConstant(1, MVT::i32)); 1894 } 1895 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is 1896 // available. 1897 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, 1898 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1); 1899 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag); 1900 Flag = Chain.getValue(1); 1901 VA = RVLocs[++i]; // skip ahead to next loc 1902 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1), 1903 Flag); 1904 } else 1905 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); 1906 1907 // Guarantee that all emitted copies are 1908 // stuck together, avoiding something bad. 1909 Flag = Chain.getValue(1); 1910 } 1911 1912 SDValue result; 1913 if (Flag.getNode()) 1914 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 1915 else // Return Void 1916 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain); 1917 1918 return result; 1919} 1920 1921bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N) const { 1922 if (N->getNumValues() != 1) 1923 return false; 1924 if (!N->hasNUsesOfValue(1, 0)) 1925 return false; 1926 1927 unsigned NumCopies = 0; 1928 SDNode* Copies[2] = { 0, 0 }; 1929 SDNode *Use = *N->use_begin(); 1930 if (Use->getOpcode() == ISD::CopyToReg) { 1931 Copies[NumCopies++] = Use; 1932 } else if (Use->getOpcode() == ARMISD::VMOVRRD) { 1933 // f64 returned in a pair of GPRs. 1934 for (SDNode::use_iterator UI = Use->use_begin(), UE = Use->use_end(); 1935 UI != UE; ++UI) { 1936 if (UI->getOpcode() != ISD::CopyToReg) 1937 return false; 1938 Copies[UI.getUse().getResNo()] = *UI; 1939 ++NumCopies; 1940 } 1941 } else if (Use->getOpcode() == ISD::BITCAST) { 1942 // f32 returned in a single GPR. 1943 if (!Use->hasNUsesOfValue(1, 0)) 1944 return false; 1945 Use = *Use->use_begin(); 1946 if (Use->getOpcode() != ISD::CopyToReg || !Use->hasNUsesOfValue(1, 0)) 1947 return false; 1948 Copies[NumCopies++] = Use; 1949 } else { 1950 return false; 1951 } 1952 1953 if (NumCopies != 1 && NumCopies != 2) 1954 return false; 1955 1956 bool HasRet = false; 1957 for (unsigned i = 0; i < NumCopies; ++i) { 1958 SDNode *Copy = Copies[i]; 1959 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1960 UI != UE; ++UI) { 1961 if (UI->getOpcode() == ISD::CopyToReg) { 1962 SDNode *Use = *UI; 1963 if (Use == Copies[0] || ((NumCopies == 2) && (Use == Copies[1]))) 1964 continue; 1965 return false; 1966 } 1967 if (UI->getOpcode() != ARMISD::RET_FLAG) 1968 return false; 1969 HasRet = true; 1970 } 1971 } 1972 1973 return HasRet; 1974} 1975 1976bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1977 if (!EnableARMTailCalls) 1978 return false; 1979 1980 if (!CI->isTailCall()) 1981 return false; 1982 1983 return !Subtarget->isThumb1Only(); 1984} 1985 1986// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 1987// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is 1988// one of the above mentioned nodes. It has to be wrapped because otherwise 1989// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 1990// be used to form addressing mode. These wrapped nodes will be selected 1991// into MOVi. 1992static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) { 1993 EVT PtrVT = Op.getValueType(); 1994 // FIXME there is no actual debug info here 1995 DebugLoc dl = Op.getDebugLoc(); 1996 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1997 SDValue Res; 1998 if (CP->isMachineConstantPoolEntry()) 1999 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, 2000 CP->getAlignment()); 2001 else 2002 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, 2003 CP->getAlignment()); 2004 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res); 2005} 2006 2007unsigned ARMTargetLowering::getJumpTableEncoding() const { 2008 return MachineJumpTableInfo::EK_Inline; 2009} 2010 2011SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op, 2012 SelectionDAG &DAG) const { 2013 MachineFunction &MF = DAG.getMachineFunction(); 2014 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2015 unsigned ARMPCLabelIndex = 0; 2016 DebugLoc DL = Op.getDebugLoc(); 2017 EVT PtrVT = getPointerTy(); 2018 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 2019 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 2020 SDValue CPAddr; 2021 if (RelocM == Reloc::Static) { 2022 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4); 2023 } else { 2024 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 2025 ARMPCLabelIndex = AFI->createPICLabelUId(); 2026 ARMConstantPoolValue *CPV = 2027 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex, 2028 ARMCP::CPBlockAddress, PCAdj); 2029 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2030 } 2031 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr); 2032 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr, 2033 MachinePointerInfo::getConstantPool(), 2034 false, false, false, 0); 2035 if (RelocM == Reloc::Static) 2036 return Result; 2037 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2038 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel); 2039} 2040 2041// Lower ISD::GlobalTLSAddress using the "general dynamic" model 2042SDValue 2043ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 2044 SelectionDAG &DAG) const { 2045 DebugLoc dl = GA->getDebugLoc(); 2046 EVT PtrVT = getPointerTy(); 2047 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 2048 MachineFunction &MF = DAG.getMachineFunction(); 2049 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2050 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 2051 ARMConstantPoolValue *CPV = 2052 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex, 2053 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true); 2054 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2055 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument); 2056 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, 2057 MachinePointerInfo::getConstantPool(), 2058 false, false, false, 0); 2059 SDValue Chain = Argument.getValue(1); 2060 2061 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2062 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel); 2063 2064 // call __tls_get_addr. 2065 ArgListTy Args; 2066 ArgListEntry Entry; 2067 Entry.Node = Argument; 2068 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext()); 2069 Args.push_back(Entry); 2070 // FIXME: is there useful debug info available here? 2071 std::pair<SDValue, SDValue> CallResult = 2072 LowerCallTo(Chain, (Type *) Type::getInt32Ty(*DAG.getContext()), 2073 false, false, false, false, 2074 0, CallingConv::C, false, /*isReturnValueUsed=*/true, 2075 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl); 2076 return CallResult.first; 2077} 2078 2079// Lower ISD::GlobalTLSAddress using the "initial exec" or 2080// "local exec" model. 2081SDValue 2082ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, 2083 SelectionDAG &DAG) const { 2084 const GlobalValue *GV = GA->getGlobal(); 2085 DebugLoc dl = GA->getDebugLoc(); 2086 SDValue Offset; 2087 SDValue Chain = DAG.getEntryNode(); 2088 EVT PtrVT = getPointerTy(); 2089 // Get the Thread Pointer 2090 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); 2091 2092 if (GV->isDeclaration()) { 2093 MachineFunction &MF = DAG.getMachineFunction(); 2094 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2095 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 2096 // Initial exec model. 2097 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 2098 ARMConstantPoolValue *CPV = 2099 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex, 2100 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF, 2101 true); 2102 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2103 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); 2104 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 2105 MachinePointerInfo::getConstantPool(), 2106 false, false, false, 0); 2107 Chain = Offset.getValue(1); 2108 2109 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2110 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel); 2111 2112 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 2113 MachinePointerInfo::getConstantPool(), 2114 false, false, false, 0); 2115 } else { 2116 // local exec model 2117 ARMConstantPoolValue *CPV = 2118 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF); 2119 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2120 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); 2121 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 2122 MachinePointerInfo::getConstantPool(), 2123 false, false, false, 0); 2124 } 2125 2126 // The address of the thread local variable is the add of the thread 2127 // pointer with the offset of the variable. 2128 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 2129} 2130 2131SDValue 2132ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 2133 // TODO: implement the "local dynamic" model 2134 assert(Subtarget->isTargetELF() && 2135 "TLS not implemented for non-ELF targets"); 2136 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 2137 // If the relocation model is PIC, use the "General Dynamic" TLS Model, 2138 // otherwise use the "Local Exec" TLS Model 2139 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) 2140 return LowerToTLSGeneralDynamicModel(GA, DAG); 2141 else 2142 return LowerToTLSExecModels(GA, DAG); 2143} 2144 2145SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, 2146 SelectionDAG &DAG) const { 2147 EVT PtrVT = getPointerTy(); 2148 DebugLoc dl = Op.getDebugLoc(); 2149 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 2150 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 2151 if (RelocM == Reloc::PIC_) { 2152 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility(); 2153 ARMConstantPoolValue *CPV = 2154 ARMConstantPoolConstant::Create(GV, 2155 UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT); 2156 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2157 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2158 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 2159 CPAddr, 2160 MachinePointerInfo::getConstantPool(), 2161 false, false, false, 0); 2162 SDValue Chain = Result.getValue(1); 2163 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT); 2164 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT); 2165 if (!UseGOTOFF) 2166 Result = DAG.getLoad(PtrVT, dl, Chain, Result, 2167 MachinePointerInfo::getGOT(), 2168 false, false, false, 0); 2169 return Result; 2170 } 2171 2172 // If we have T2 ops, we can materialize the address directly via movt/movw 2173 // pair. This is always cheaper. 2174 if (Subtarget->useMovt()) { 2175 ++NumMovwMovt; 2176 // FIXME: Once remat is capable of dealing with instructions with register 2177 // operands, expand this into two nodes. 2178 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT, 2179 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); 2180 } else { 2181 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); 2182 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2183 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2184 MachinePointerInfo::getConstantPool(), 2185 false, false, false, 0); 2186 } 2187} 2188 2189SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op, 2190 SelectionDAG &DAG) const { 2191 EVT PtrVT = getPointerTy(); 2192 DebugLoc dl = Op.getDebugLoc(); 2193 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 2194 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 2195 MachineFunction &MF = DAG.getMachineFunction(); 2196 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2197 2198 // FIXME: Enable this for static codegen when tool issues are fixed. Also 2199 // update ARMFastISel::ARMMaterializeGV. 2200 if (Subtarget->useMovt() && RelocM != Reloc::Static) { 2201 ++NumMovwMovt; 2202 // FIXME: Once remat is capable of dealing with instructions with register 2203 // operands, expand this into two nodes. 2204 if (RelocM == Reloc::Static) 2205 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT, 2206 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); 2207 2208 unsigned Wrapper = (RelocM == Reloc::PIC_) 2209 ? ARMISD::WrapperPIC : ARMISD::WrapperDYN; 2210 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, 2211 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); 2212 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) 2213 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result, 2214 MachinePointerInfo::getGOT(), 2215 false, false, false, 0); 2216 return Result; 2217 } 2218 2219 unsigned ARMPCLabelIndex = 0; 2220 SDValue CPAddr; 2221 if (RelocM == Reloc::Static) { 2222 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); 2223 } else { 2224 ARMPCLabelIndex = AFI->createPICLabelUId(); 2225 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8); 2226 ARMConstantPoolValue *CPV = 2227 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 2228 PCAdj); 2229 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2230 } 2231 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2232 2233 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2234 MachinePointerInfo::getConstantPool(), 2235 false, false, false, 0); 2236 SDValue Chain = Result.getValue(1); 2237 2238 if (RelocM == Reloc::PIC_) { 2239 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2240 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 2241 } 2242 2243 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) 2244 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(), 2245 false, false, false, 0); 2246 2247 return Result; 2248} 2249 2250SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, 2251 SelectionDAG &DAG) const { 2252 assert(Subtarget->isTargetELF() && 2253 "GLOBAL OFFSET TABLE not implemented for non-ELF targets"); 2254 MachineFunction &MF = DAG.getMachineFunction(); 2255 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2256 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 2257 EVT PtrVT = getPointerTy(); 2258 DebugLoc dl = Op.getDebugLoc(); 2259 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 2260 ARMConstantPoolValue *CPV = 2261 ARMConstantPoolSymbol::Create(*DAG.getContext(), "_GLOBAL_OFFSET_TABLE_", 2262 ARMPCLabelIndex, PCAdj); 2263 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2264 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2265 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2266 MachinePointerInfo::getConstantPool(), 2267 false, false, false, 0); 2268 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2269 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 2270} 2271 2272SDValue 2273ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const { 2274 DebugLoc dl = Op.getDebugLoc(); 2275 SDValue Val = DAG.getConstant(0, MVT::i32); 2276 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, 2277 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0), 2278 Op.getOperand(1), Val); 2279} 2280 2281SDValue 2282ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const { 2283 DebugLoc dl = Op.getDebugLoc(); 2284 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0), 2285 Op.getOperand(1), DAG.getConstant(0, MVT::i32)); 2286} 2287 2288SDValue 2289ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 2290 const ARMSubtarget *Subtarget) const { 2291 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 2292 DebugLoc dl = Op.getDebugLoc(); 2293 switch (IntNo) { 2294 default: return SDValue(); // Don't custom lower most intrinsics. 2295 case Intrinsic::arm_thread_pointer: { 2296 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2297 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); 2298 } 2299 case Intrinsic::eh_sjlj_lsda: { 2300 MachineFunction &MF = DAG.getMachineFunction(); 2301 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2302 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 2303 EVT PtrVT = getPointerTy(); 2304 DebugLoc dl = Op.getDebugLoc(); 2305 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 2306 SDValue CPAddr; 2307 unsigned PCAdj = (RelocM != Reloc::PIC_) 2308 ? 0 : (Subtarget->isThumb() ? 4 : 8); 2309 ARMConstantPoolValue *CPV = 2310 ARMConstantPoolConstant::Create(MF.getFunction(), ARMPCLabelIndex, 2311 ARMCP::CPLSDA, PCAdj); 2312 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2313 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2314 SDValue Result = 2315 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2316 MachinePointerInfo::getConstantPool(), 2317 false, false, false, 0); 2318 2319 if (RelocM == Reloc::PIC_) { 2320 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2321 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 2322 } 2323 return Result; 2324 } 2325 case Intrinsic::arm_neon_vmulls: 2326 case Intrinsic::arm_neon_vmullu: { 2327 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls) 2328 ? ARMISD::VMULLs : ARMISD::VMULLu; 2329 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(), 2330 Op.getOperand(1), Op.getOperand(2)); 2331 } 2332 } 2333} 2334 2335static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG, 2336 const ARMSubtarget *Subtarget) { 2337 DebugLoc dl = Op.getDebugLoc(); 2338 if (!Subtarget->hasDataBarrier()) { 2339 // Some ARMv6 cpus can support data barriers with an mcr instruction. 2340 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get 2341 // here. 2342 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() && 2343 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!"); 2344 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0), 2345 DAG.getConstant(0, MVT::i32)); 2346 } 2347 2348 SDValue Op5 = Op.getOperand(5); 2349 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0; 2350 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 2351 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 2352 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0); 2353 2354 ARM_MB::MemBOpt DMBOpt; 2355 if (isDeviceBarrier) 2356 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY; 2357 else 2358 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH; 2359 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0), 2360 DAG.getConstant(DMBOpt, MVT::i32)); 2361} 2362 2363 2364static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, 2365 const ARMSubtarget *Subtarget) { 2366 // FIXME: handle "fence singlethread" more efficiently. 2367 DebugLoc dl = Op.getDebugLoc(); 2368 if (!Subtarget->hasDataBarrier()) { 2369 // Some ARMv6 cpus can support data barriers with an mcr instruction. 2370 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get 2371 // here. 2372 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() && 2373 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!"); 2374 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0), 2375 DAG.getConstant(0, MVT::i32)); 2376 } 2377 2378 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0), 2379 DAG.getConstant(ARM_MB::ISH, MVT::i32)); 2380} 2381 2382static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG, 2383 const ARMSubtarget *Subtarget) { 2384 // ARM pre v5TE and Thumb1 does not have preload instructions. 2385 if (!(Subtarget->isThumb2() || 2386 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps()))) 2387 // Just preserve the chain. 2388 return Op.getOperand(0); 2389 2390 DebugLoc dl = Op.getDebugLoc(); 2391 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1; 2392 if (!isRead && 2393 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension())) 2394 // ARMv7 with MP extension has PLDW. 2395 return Op.getOperand(0); 2396 2397 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 2398 if (Subtarget->isThumb()) { 2399 // Invert the bits. 2400 isRead = ~isRead & 1; 2401 isData = ~isData & 1; 2402 } 2403 2404 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0), 2405 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32), 2406 DAG.getConstant(isData, MVT::i32)); 2407} 2408 2409static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) { 2410 MachineFunction &MF = DAG.getMachineFunction(); 2411 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>(); 2412 2413 // vastart just stores the address of the VarArgsFrameIndex slot into the 2414 // memory location argument. 2415 DebugLoc dl = Op.getDebugLoc(); 2416 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2417 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2418 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 2419 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), 2420 MachinePointerInfo(SV), false, false, 0); 2421} 2422 2423SDValue 2424ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 2425 SDValue &Root, SelectionDAG &DAG, 2426 DebugLoc dl) const { 2427 MachineFunction &MF = DAG.getMachineFunction(); 2428 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2429 2430 const TargetRegisterClass *RC; 2431 if (AFI->isThumb1OnlyFunction()) 2432 RC = ARM::tGPRRegisterClass; 2433 else 2434 RC = ARM::GPRRegisterClass; 2435 2436 // Transform the arguments stored in physical registers into virtual ones. 2437 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 2438 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); 2439 2440 SDValue ArgValue2; 2441 if (NextVA.isMemLoc()) { 2442 MachineFrameInfo *MFI = MF.getFrameInfo(); 2443 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true); 2444 2445 // Create load node to retrieve arguments from the stack. 2446 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2447 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, 2448 MachinePointerInfo::getFixedStack(FI), 2449 false, false, false, 0); 2450 } else { 2451 Reg = MF.addLiveIn(NextVA.getLocReg(), RC); 2452 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); 2453 } 2454 2455 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2); 2456} 2457 2458void 2459ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF, 2460 unsigned &VARegSize, unsigned &VARegSaveSize) 2461 const { 2462 unsigned NumGPRs; 2463 if (CCInfo.isFirstByValRegValid()) 2464 NumGPRs = ARM::R4 - CCInfo.getFirstByValReg(); 2465 else { 2466 unsigned int firstUnalloced; 2467 firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs, 2468 sizeof(GPRArgRegs) / 2469 sizeof(GPRArgRegs[0])); 2470 NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0; 2471 } 2472 2473 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment(); 2474 VARegSize = NumGPRs * 4; 2475 VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1); 2476} 2477 2478// The remaining GPRs hold either the beginning of variable-argument 2479// data, or the beginning of an aggregate passed by value (usuall 2480// byval). Either way, we allocate stack slots adjacent to the data 2481// provided by our caller, and store the unallocated registers there. 2482// If this is a variadic function, the va_list pointer will begin with 2483// these values; otherwise, this reassembles a (byval) structure that 2484// was split between registers and memory. 2485void 2486ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, 2487 DebugLoc dl, SDValue &Chain, 2488 unsigned ArgOffset) const { 2489 MachineFunction &MF = DAG.getMachineFunction(); 2490 MachineFrameInfo *MFI = MF.getFrameInfo(); 2491 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2492 unsigned firstRegToSaveIndex; 2493 if (CCInfo.isFirstByValRegValid()) 2494 firstRegToSaveIndex = CCInfo.getFirstByValReg() - ARM::R0; 2495 else { 2496 firstRegToSaveIndex = CCInfo.getFirstUnallocated 2497 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0])); 2498 } 2499 2500 unsigned VARegSize, VARegSaveSize; 2501 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize); 2502 if (VARegSaveSize) { 2503 // If this function is vararg, store any remaining integer argument regs 2504 // to their spots on the stack so that they may be loaded by deferencing 2505 // the result of va_next. 2506 AFI->setVarArgsRegSaveSize(VARegSaveSize); 2507 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(VARegSaveSize, 2508 ArgOffset + VARegSaveSize 2509 - VARegSize, 2510 false)); 2511 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), 2512 getPointerTy()); 2513 2514 SmallVector<SDValue, 4> MemOps; 2515 for (; firstRegToSaveIndex < 4; ++firstRegToSaveIndex) { 2516 const TargetRegisterClass *RC; 2517 if (AFI->isThumb1OnlyFunction()) 2518 RC = ARM::tGPRRegisterClass; 2519 else 2520 RC = ARM::GPRRegisterClass; 2521 2522 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC); 2523 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 2524 SDValue Store = 2525 DAG.getStore(Val.getValue(1), dl, Val, FIN, 2526 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()), 2527 false, false, 0); 2528 MemOps.push_back(Store); 2529 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN, 2530 DAG.getConstant(4, getPointerTy())); 2531 } 2532 if (!MemOps.empty()) 2533 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2534 &MemOps[0], MemOps.size()); 2535 } else 2536 // This will point to the next argument passed via stack. 2537 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true)); 2538} 2539 2540SDValue 2541ARMTargetLowering::LowerFormalArguments(SDValue Chain, 2542 CallingConv::ID CallConv, bool isVarArg, 2543 const SmallVectorImpl<ISD::InputArg> 2544 &Ins, 2545 DebugLoc dl, SelectionDAG &DAG, 2546 SmallVectorImpl<SDValue> &InVals) 2547 const { 2548 MachineFunction &MF = DAG.getMachineFunction(); 2549 MachineFrameInfo *MFI = MF.getFrameInfo(); 2550 2551 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2552 2553 // Assign locations to all of the incoming arguments. 2554 SmallVector<CCValAssign, 16> ArgLocs; 2555 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2556 getTargetMachine(), ArgLocs, *DAG.getContext(), Prologue); 2557 CCInfo.AnalyzeFormalArguments(Ins, 2558 CCAssignFnForNode(CallConv, /* Return*/ false, 2559 isVarArg)); 2560 2561 SmallVector<SDValue, 16> ArgValues; 2562 int lastInsIndex = -1; 2563 2564 SDValue ArgValue; 2565 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2566 CCValAssign &VA = ArgLocs[i]; 2567 2568 // Arguments stored in registers. 2569 if (VA.isRegLoc()) { 2570 EVT RegVT = VA.getLocVT(); 2571 2572 if (VA.needsCustom()) { 2573 // f64 and vector types are split up into multiple registers or 2574 // combinations of registers and stack slots. 2575 if (VA.getLocVT() == MVT::v2f64) { 2576 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i], 2577 Chain, DAG, dl); 2578 VA = ArgLocs[++i]; // skip ahead to next loc 2579 SDValue ArgValue2; 2580 if (VA.isMemLoc()) { 2581 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true); 2582 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2583 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN, 2584 MachinePointerInfo::getFixedStack(FI), 2585 false, false, false, 0); 2586 } else { 2587 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], 2588 Chain, DAG, dl); 2589 } 2590 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); 2591 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, 2592 ArgValue, ArgValue1, DAG.getIntPtrConstant(0)); 2593 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, 2594 ArgValue, ArgValue2, DAG.getIntPtrConstant(1)); 2595 } else 2596 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl); 2597 2598 } else { 2599 const TargetRegisterClass *RC; 2600 2601 if (RegVT == MVT::f32) 2602 RC = ARM::SPRRegisterClass; 2603 else if (RegVT == MVT::f64) 2604 RC = ARM::DPRRegisterClass; 2605 else if (RegVT == MVT::v2f64) 2606 RC = ARM::QPRRegisterClass; 2607 else if (RegVT == MVT::i32) 2608 RC = (AFI->isThumb1OnlyFunction() ? 2609 ARM::tGPRRegisterClass : ARM::GPRRegisterClass); 2610 else 2611 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering"); 2612 2613 // Transform the arguments in physical registers into virtual ones. 2614 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 2615 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 2616 } 2617 2618 // If this is an 8 or 16-bit value, it is really passed promoted 2619 // to 32 bits. Insert an assert[sz]ext to capture this, then 2620 // truncate to the right size. 2621 switch (VA.getLocInfo()) { 2622 default: llvm_unreachable("Unknown loc info!"); 2623 case CCValAssign::Full: break; 2624 case CCValAssign::BCvt: 2625 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 2626 break; 2627 case CCValAssign::SExt: 2628 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 2629 DAG.getValueType(VA.getValVT())); 2630 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2631 break; 2632 case CCValAssign::ZExt: 2633 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 2634 DAG.getValueType(VA.getValVT())); 2635 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2636 break; 2637 } 2638 2639 InVals.push_back(ArgValue); 2640 2641 } else { // VA.isRegLoc() 2642 2643 // sanity check 2644 assert(VA.isMemLoc()); 2645 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered"); 2646 2647 int index = ArgLocs[i].getValNo(); 2648 2649 // Some Ins[] entries become multiple ArgLoc[] entries. 2650 // Process them only once. 2651 if (index != lastInsIndex) 2652 { 2653 ISD::ArgFlagsTy Flags = Ins[index].Flags; 2654 // FIXME: For now, all byval parameter objects are marked mutable. 2655 // This can be changed with more analysis. 2656 // In case of tail call optimization mark all arguments mutable. 2657 // Since they could be overwritten by lowering of arguments in case of 2658 // a tail call. 2659 if (Flags.isByVal()) { 2660 unsigned VARegSize, VARegSaveSize; 2661 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize); 2662 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, 0); 2663 unsigned Bytes = Flags.getByValSize() - VARegSize; 2664 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 2665 int FI = MFI->CreateFixedObject(Bytes, 2666 VA.getLocMemOffset(), false); 2667 InVals.push_back(DAG.getFrameIndex(FI, getPointerTy())); 2668 } else { 2669 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8, 2670 VA.getLocMemOffset(), true); 2671 2672 // Create load nodes to retrieve arguments from the stack. 2673 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2674 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 2675 MachinePointerInfo::getFixedStack(FI), 2676 false, false, false, 0)); 2677 } 2678 lastInsIndex = index; 2679 } 2680 } 2681 } 2682 2683 // varargs 2684 if (isVarArg) 2685 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, CCInfo.getNextStackOffset()); 2686 2687 return Chain; 2688} 2689 2690/// isFloatingPointZero - Return true if this is +0.0. 2691static bool isFloatingPointZero(SDValue Op) { 2692 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 2693 return CFP->getValueAPF().isPosZero(); 2694 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 2695 // Maybe this has already been legalized into the constant pool? 2696 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) { 2697 SDValue WrapperOp = Op.getOperand(1).getOperand(0); 2698 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp)) 2699 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 2700 return CFP->getValueAPF().isPosZero(); 2701 } 2702 } 2703 return false; 2704} 2705 2706/// Returns appropriate ARM CMP (cmp) and corresponding condition code for 2707/// the given operands. 2708SDValue 2709ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 2710 SDValue &ARMcc, SelectionDAG &DAG, 2711 DebugLoc dl) const { 2712 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) { 2713 unsigned C = RHSC->getZExtValue(); 2714 if (!isLegalICmpImmediate(C)) { 2715 // Constant does not fit, try adjusting it by one? 2716 switch (CC) { 2717 default: break; 2718 case ISD::SETLT: 2719 case ISD::SETGE: 2720 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) { 2721 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 2722 RHS = DAG.getConstant(C-1, MVT::i32); 2723 } 2724 break; 2725 case ISD::SETULT: 2726 case ISD::SETUGE: 2727 if (C != 0 && isLegalICmpImmediate(C-1)) { 2728 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 2729 RHS = DAG.getConstant(C-1, MVT::i32); 2730 } 2731 break; 2732 case ISD::SETLE: 2733 case ISD::SETGT: 2734 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) { 2735 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; 2736 RHS = DAG.getConstant(C+1, MVT::i32); 2737 } 2738 break; 2739 case ISD::SETULE: 2740 case ISD::SETUGT: 2741 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) { 2742 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 2743 RHS = DAG.getConstant(C+1, MVT::i32); 2744 } 2745 break; 2746 } 2747 } 2748 } 2749 2750 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 2751 ARMISD::NodeType CompareType; 2752 switch (CondCode) { 2753 default: 2754 CompareType = ARMISD::CMP; 2755 break; 2756 case ARMCC::EQ: 2757 case ARMCC::NE: 2758 // Uses only Z Flag 2759 CompareType = ARMISD::CMPZ; 2760 break; 2761 } 2762 ARMcc = DAG.getConstant(CondCode, MVT::i32); 2763 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS); 2764} 2765 2766/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands. 2767SDValue 2768ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, 2769 DebugLoc dl) const { 2770 SDValue Cmp; 2771 if (!isFloatingPointZero(RHS)) 2772 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS); 2773 else 2774 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS); 2775 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp); 2776} 2777 2778/// duplicateCmp - Glue values can have only one use, so this function 2779/// duplicates a comparison node. 2780SDValue 2781ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const { 2782 unsigned Opc = Cmp.getOpcode(); 2783 DebugLoc DL = Cmp.getDebugLoc(); 2784 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ) 2785 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1)); 2786 2787 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation"); 2788 Cmp = Cmp.getOperand(0); 2789 Opc = Cmp.getOpcode(); 2790 if (Opc == ARMISD::CMPFP) 2791 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1)); 2792 else { 2793 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT"); 2794 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0)); 2795 } 2796 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp); 2797} 2798 2799SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 2800 SDValue Cond = Op.getOperand(0); 2801 SDValue SelectTrue = Op.getOperand(1); 2802 SDValue SelectFalse = Op.getOperand(2); 2803 DebugLoc dl = Op.getDebugLoc(); 2804 2805 // Convert: 2806 // 2807 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond) 2808 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond) 2809 // 2810 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) { 2811 const ConstantSDNode *CMOVTrue = 2812 dyn_cast<ConstantSDNode>(Cond.getOperand(0)); 2813 const ConstantSDNode *CMOVFalse = 2814 dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 2815 2816 if (CMOVTrue && CMOVFalse) { 2817 unsigned CMOVTrueVal = CMOVTrue->getZExtValue(); 2818 unsigned CMOVFalseVal = CMOVFalse->getZExtValue(); 2819 2820 SDValue True; 2821 SDValue False; 2822 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) { 2823 True = SelectTrue; 2824 False = SelectFalse; 2825 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) { 2826 True = SelectFalse; 2827 False = SelectTrue; 2828 } 2829 2830 if (True.getNode() && False.getNode()) { 2831 EVT VT = Op.getValueType(); 2832 SDValue ARMcc = Cond.getOperand(2); 2833 SDValue CCR = Cond.getOperand(3); 2834 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG); 2835 assert(True.getValueType() == VT); 2836 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp); 2837 } 2838 } 2839 } 2840 2841 return DAG.getSelectCC(dl, Cond, 2842 DAG.getConstant(0, Cond.getValueType()), 2843 SelectTrue, SelectFalse, ISD::SETNE); 2844} 2845 2846SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 2847 EVT VT = Op.getValueType(); 2848 SDValue LHS = Op.getOperand(0); 2849 SDValue RHS = Op.getOperand(1); 2850 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 2851 SDValue TrueVal = Op.getOperand(2); 2852 SDValue FalseVal = Op.getOperand(3); 2853 DebugLoc dl = Op.getDebugLoc(); 2854 2855 if (LHS.getValueType() == MVT::i32) { 2856 SDValue ARMcc; 2857 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2858 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); 2859 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp); 2860 } 2861 2862 ARMCC::CondCodes CondCode, CondCode2; 2863 FPCCToARMCC(CC, CondCode, CondCode2); 2864 2865 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32); 2866 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); 2867 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2868 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, 2869 ARMcc, CCR, Cmp); 2870 if (CondCode2 != ARMCC::AL) { 2871 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32); 2872 // FIXME: Needs another CMP because flag can have but one use. 2873 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl); 2874 Result = DAG.getNode(ARMISD::CMOV, dl, VT, 2875 Result, TrueVal, ARMcc2, CCR, Cmp2); 2876 } 2877 return Result; 2878} 2879 2880/// canChangeToInt - Given the fp compare operand, return true if it is suitable 2881/// to morph to an integer compare sequence. 2882static bool canChangeToInt(SDValue Op, bool &SeenZero, 2883 const ARMSubtarget *Subtarget) { 2884 SDNode *N = Op.getNode(); 2885 if (!N->hasOneUse()) 2886 // Otherwise it requires moving the value from fp to integer registers. 2887 return false; 2888 if (!N->getNumValues()) 2889 return false; 2890 EVT VT = Op.getValueType(); 2891 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow()) 2892 // f32 case is generally profitable. f64 case only makes sense when vcmpe + 2893 // vmrs are very slow, e.g. cortex-a8. 2894 return false; 2895 2896 if (isFloatingPointZero(Op)) { 2897 SeenZero = true; 2898 return true; 2899 } 2900 return ISD::isNormalLoad(N); 2901} 2902 2903static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) { 2904 if (isFloatingPointZero(Op)) 2905 return DAG.getConstant(0, MVT::i32); 2906 2907 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) 2908 return DAG.getLoad(MVT::i32, Op.getDebugLoc(), 2909 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(), 2910 Ld->isVolatile(), Ld->isNonTemporal(), 2911 Ld->isInvariant(), Ld->getAlignment()); 2912 2913 llvm_unreachable("Unknown VFP cmp argument!"); 2914} 2915 2916static void expandf64Toi32(SDValue Op, SelectionDAG &DAG, 2917 SDValue &RetVal1, SDValue &RetVal2) { 2918 if (isFloatingPointZero(Op)) { 2919 RetVal1 = DAG.getConstant(0, MVT::i32); 2920 RetVal2 = DAG.getConstant(0, MVT::i32); 2921 return; 2922 } 2923 2924 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) { 2925 SDValue Ptr = Ld->getBasePtr(); 2926 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(), 2927 Ld->getChain(), Ptr, 2928 Ld->getPointerInfo(), 2929 Ld->isVolatile(), Ld->isNonTemporal(), 2930 Ld->isInvariant(), Ld->getAlignment()); 2931 2932 EVT PtrType = Ptr.getValueType(); 2933 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4); 2934 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(), 2935 PtrType, Ptr, DAG.getConstant(4, PtrType)); 2936 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(), 2937 Ld->getChain(), NewPtr, 2938 Ld->getPointerInfo().getWithOffset(4), 2939 Ld->isVolatile(), Ld->isNonTemporal(), 2940 Ld->isInvariant(), NewAlign); 2941 return; 2942 } 2943 2944 llvm_unreachable("Unknown VFP cmp argument!"); 2945} 2946 2947/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some 2948/// f32 and even f64 comparisons to integer ones. 2949SDValue 2950ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const { 2951 SDValue Chain = Op.getOperand(0); 2952 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 2953 SDValue LHS = Op.getOperand(2); 2954 SDValue RHS = Op.getOperand(3); 2955 SDValue Dest = Op.getOperand(4); 2956 DebugLoc dl = Op.getDebugLoc(); 2957 2958 bool SeenZero = false; 2959 if (canChangeToInt(LHS, SeenZero, Subtarget) && 2960 canChangeToInt(RHS, SeenZero, Subtarget) && 2961 // If one of the operand is zero, it's safe to ignore the NaN case since 2962 // we only care about equality comparisons. 2963 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) { 2964 // If unsafe fp math optimization is enabled and there are no other uses of 2965 // the CMP operands, and the condition code is EQ or NE, we can optimize it 2966 // to an integer comparison. 2967 if (CC == ISD::SETOEQ) 2968 CC = ISD::SETEQ; 2969 else if (CC == ISD::SETUNE) 2970 CC = ISD::SETNE; 2971 2972 SDValue ARMcc; 2973 if (LHS.getValueType() == MVT::f32) { 2974 LHS = bitcastf32Toi32(LHS, DAG); 2975 RHS = bitcastf32Toi32(RHS, DAG); 2976 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); 2977 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2978 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, 2979 Chain, Dest, ARMcc, CCR, Cmp); 2980 } 2981 2982 SDValue LHS1, LHS2; 2983 SDValue RHS1, RHS2; 2984 expandf64Toi32(LHS, DAG, LHS1, LHS2); 2985 expandf64Toi32(RHS, DAG, RHS1, RHS2); 2986 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 2987 ARMcc = DAG.getConstant(CondCode, MVT::i32); 2988 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); 2989 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; 2990 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7); 2991 } 2992 2993 return SDValue(); 2994} 2995 2996SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 2997 SDValue Chain = Op.getOperand(0); 2998 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 2999 SDValue LHS = Op.getOperand(2); 3000 SDValue RHS = Op.getOperand(3); 3001 SDValue Dest = Op.getOperand(4); 3002 DebugLoc dl = Op.getDebugLoc(); 3003 3004 if (LHS.getValueType() == MVT::i32) { 3005 SDValue ARMcc; 3006 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); 3007 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 3008 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, 3009 Chain, Dest, ARMcc, CCR, Cmp); 3010 } 3011 3012 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); 3013 3014 if (getTargetMachine().Options.UnsafeFPMath && 3015 (CC == ISD::SETEQ || CC == ISD::SETOEQ || 3016 CC == ISD::SETNE || CC == ISD::SETUNE)) { 3017 SDValue Result = OptimizeVFPBrcond(Op, DAG); 3018 if (Result.getNode()) 3019 return Result; 3020 } 3021 3022 ARMCC::CondCodes CondCode, CondCode2; 3023 FPCCToARMCC(CC, CondCode, CondCode2); 3024 3025 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32); 3026 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); 3027 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 3028 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); 3029 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp }; 3030 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); 3031 if (CondCode2 != ARMCC::AL) { 3032 ARMcc = DAG.getConstant(CondCode2, MVT::i32); 3033 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) }; 3034 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); 3035 } 3036 return Res; 3037} 3038 3039SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const { 3040 SDValue Chain = Op.getOperand(0); 3041 SDValue Table = Op.getOperand(1); 3042 SDValue Index = Op.getOperand(2); 3043 DebugLoc dl = Op.getDebugLoc(); 3044 3045 EVT PTy = getPointerTy(); 3046 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); 3047 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>(); 3048 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); 3049 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); 3050 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId); 3051 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy)); 3052 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 3053 if (Subtarget->isThumb2()) { 3054 // Thumb2 uses a two-level jump. That is, it jumps into the jump table 3055 // which does another jump to the destination. This also makes it easier 3056 // to translate it to TBB / TBH later. 3057 // FIXME: This might not work if the function is extremely large. 3058 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain, 3059 Addr, Op.getOperand(2), JTI, UId); 3060 } 3061 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 3062 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr, 3063 MachinePointerInfo::getJumpTable(), 3064 false, false, false, 0); 3065 Chain = Addr.getValue(1); 3066 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table); 3067 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); 3068 } else { 3069 Addr = DAG.getLoad(PTy, dl, Chain, Addr, 3070 MachinePointerInfo::getJumpTable(), 3071 false, false, false, 0); 3072 Chain = Addr.getValue(1); 3073 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); 3074 } 3075} 3076 3077static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) { 3078 EVT VT = Op.getValueType(); 3079 DebugLoc dl = Op.getDebugLoc(); 3080 3081 if (Op.getValueType().getVectorElementType() == MVT::i32) { 3082 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32) 3083 return Op; 3084 return DAG.UnrollVectorOp(Op.getNode()); 3085 } 3086 3087 assert(Op.getOperand(0).getValueType() == MVT::v4f32 && 3088 "Invalid type for custom lowering!"); 3089 if (VT != MVT::v4i16) 3090 return DAG.UnrollVectorOp(Op.getNode()); 3091 3092 Op = DAG.getNode(Op.getOpcode(), dl, MVT::v4i32, Op.getOperand(0)); 3093 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op); 3094} 3095 3096static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) { 3097 EVT VT = Op.getValueType(); 3098 if (VT.isVector()) 3099 return LowerVectorFP_TO_INT(Op, DAG); 3100 3101 DebugLoc dl = Op.getDebugLoc(); 3102 unsigned Opc; 3103 3104 switch (Op.getOpcode()) { 3105 default: llvm_unreachable("Invalid opcode!"); 3106 case ISD::FP_TO_SINT: 3107 Opc = ARMISD::FTOSI; 3108 break; 3109 case ISD::FP_TO_UINT: 3110 Opc = ARMISD::FTOUI; 3111 break; 3112 } 3113 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0)); 3114 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3115} 3116 3117static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 3118 EVT VT = Op.getValueType(); 3119 DebugLoc dl = Op.getDebugLoc(); 3120 3121 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) { 3122 if (VT.getVectorElementType() == MVT::f32) 3123 return Op; 3124 return DAG.UnrollVectorOp(Op.getNode()); 3125 } 3126 3127 assert(Op.getOperand(0).getValueType() == MVT::v4i16 && 3128 "Invalid type for custom lowering!"); 3129 if (VT != MVT::v4f32) 3130 return DAG.UnrollVectorOp(Op.getNode()); 3131 3132 unsigned CastOpc; 3133 unsigned Opc; 3134 switch (Op.getOpcode()) { 3135 default: llvm_unreachable("Invalid opcode!"); 3136 case ISD::SINT_TO_FP: 3137 CastOpc = ISD::SIGN_EXTEND; 3138 Opc = ISD::SINT_TO_FP; 3139 break; 3140 case ISD::UINT_TO_FP: 3141 CastOpc = ISD::ZERO_EXTEND; 3142 Opc = ISD::UINT_TO_FP; 3143 break; 3144 } 3145 3146 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0)); 3147 return DAG.getNode(Opc, dl, VT, Op); 3148} 3149 3150static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 3151 EVT VT = Op.getValueType(); 3152 if (VT.isVector()) 3153 return LowerVectorINT_TO_FP(Op, DAG); 3154 3155 DebugLoc dl = Op.getDebugLoc(); 3156 unsigned Opc; 3157 3158 switch (Op.getOpcode()) { 3159 default: llvm_unreachable("Invalid opcode!"); 3160 case ISD::SINT_TO_FP: 3161 Opc = ARMISD::SITOF; 3162 break; 3163 case ISD::UINT_TO_FP: 3164 Opc = ARMISD::UITOF; 3165 break; 3166 } 3167 3168 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0)); 3169 return DAG.getNode(Opc, dl, VT, Op); 3170} 3171 3172SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 3173 // Implement fcopysign with a fabs and a conditional fneg. 3174 SDValue Tmp0 = Op.getOperand(0); 3175 SDValue Tmp1 = Op.getOperand(1); 3176 DebugLoc dl = Op.getDebugLoc(); 3177 EVT VT = Op.getValueType(); 3178 EVT SrcVT = Tmp1.getValueType(); 3179 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST || 3180 Tmp0.getOpcode() == ARMISD::VMOVDRR; 3181 bool UseNEON = !InGPR && Subtarget->hasNEON(); 3182 3183 if (UseNEON) { 3184 // Use VBSL to copy the sign bit. 3185 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80); 3186 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32, 3187 DAG.getTargetConstant(EncodedVal, MVT::i32)); 3188 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64; 3189 if (VT == MVT::f64) 3190 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT, 3191 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask), 3192 DAG.getConstant(32, MVT::i32)); 3193 else /*if (VT == MVT::f32)*/ 3194 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0); 3195 if (SrcVT == MVT::f32) { 3196 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1); 3197 if (VT == MVT::f64) 3198 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT, 3199 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1), 3200 DAG.getConstant(32, MVT::i32)); 3201 } else if (VT == MVT::f32) 3202 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64, 3203 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1), 3204 DAG.getConstant(32, MVT::i32)); 3205 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0); 3206 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1); 3207 3208 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff), 3209 MVT::i32); 3210 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes); 3211 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask, 3212 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes)); 3213 3214 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT, 3215 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask), 3216 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot)); 3217 if (VT == MVT::f32) { 3218 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res); 3219 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res, 3220 DAG.getConstant(0, MVT::i32)); 3221 } else { 3222 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res); 3223 } 3224 3225 return Res; 3226 } 3227 3228 // Bitcast operand 1 to i32. 3229 if (SrcVT == MVT::f64) 3230 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), 3231 &Tmp1, 1).getValue(1); 3232 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1); 3233 3234 // Or in the signbit with integer operations. 3235 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32); 3236 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32); 3237 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1); 3238 if (VT == MVT::f32) { 3239 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32, 3240 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2); 3241 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, 3242 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1)); 3243 } 3244 3245 // f64: Or the high part with signbit and then combine two parts. 3246 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), 3247 &Tmp0, 1); 3248 SDValue Lo = Tmp0.getValue(0); 3249 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2); 3250 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1); 3251 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); 3252} 3253 3254SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{ 3255 MachineFunction &MF = DAG.getMachineFunction(); 3256 MachineFrameInfo *MFI = MF.getFrameInfo(); 3257 MFI->setReturnAddressIsTaken(true); 3258 3259 EVT VT = Op.getValueType(); 3260 DebugLoc dl = Op.getDebugLoc(); 3261 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 3262 if (Depth) { 3263 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 3264 SDValue Offset = DAG.getConstant(4, MVT::i32); 3265 return DAG.getLoad(VT, dl, DAG.getEntryNode(), 3266 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset), 3267 MachinePointerInfo(), false, false, false, 0); 3268 } 3269 3270 // Return LR, which contains the return address. Mark it an implicit live-in. 3271 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32)); 3272 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT); 3273} 3274 3275SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 3276 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3277 MFI->setFrameAddressIsTaken(true); 3278 3279 EVT VT = Op.getValueType(); 3280 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 3281 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 3282 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin()) 3283 ? ARM::R7 : ARM::R11; 3284 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 3285 while (Depth--) 3286 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 3287 MachinePointerInfo(), 3288 false, false, false, 0); 3289 return FrameAddr; 3290} 3291 3292/// ExpandBITCAST - If the target supports VFP, this function is called to 3293/// expand a bit convert where either the source or destination type is i64 to 3294/// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64 3295/// operand type is illegal (e.g., v2f32 for a target that doesn't support 3296/// vectors), since the legalizer won't know what to do with that. 3297static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) { 3298 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3299 DebugLoc dl = N->getDebugLoc(); 3300 SDValue Op = N->getOperand(0); 3301 3302 // This function is only supposed to be called for i64 types, either as the 3303 // source or destination of the bit convert. 3304 EVT SrcVT = Op.getValueType(); 3305 EVT DstVT = N->getValueType(0); 3306 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) && 3307 "ExpandBITCAST called for non-i64 type"); 3308 3309 // Turn i64->f64 into VMOVDRR. 3310 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) { 3311 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, 3312 DAG.getConstant(0, MVT::i32)); 3313 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, 3314 DAG.getConstant(1, MVT::i32)); 3315 return DAG.getNode(ISD::BITCAST, dl, DstVT, 3316 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi)); 3317 } 3318 3319 // Turn f64->i64 into VMOVRRD. 3320 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) { 3321 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, 3322 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1); 3323 // Merge the pieces into a single i64 value. 3324 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1)); 3325 } 3326 3327 return SDValue(); 3328} 3329 3330/// getZeroVector - Returns a vector of specified type with all zero elements. 3331/// Zero vectors are used to represent vector negation and in those cases 3332/// will be implemented with the NEON VNEG instruction. However, VNEG does 3333/// not support i64 elements, so sometimes the zero vectors will need to be 3334/// explicitly constructed. Regardless, use a canonical VMOV to create the 3335/// zero vector. 3336static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 3337 assert(VT.isVector() && "Expected a vector type"); 3338 // The canonical modified immediate encoding of a zero vector is....0! 3339 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32); 3340 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32; 3341 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal); 3342 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); 3343} 3344 3345/// LowerShiftRightParts - Lower SRA_PARTS, which returns two 3346/// i32 values and take a 2 x i32 value to shift plus a shift amount. 3347SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op, 3348 SelectionDAG &DAG) const { 3349 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 3350 EVT VT = Op.getValueType(); 3351 unsigned VTBits = VT.getSizeInBits(); 3352 DebugLoc dl = Op.getDebugLoc(); 3353 SDValue ShOpLo = Op.getOperand(0); 3354 SDValue ShOpHi = Op.getOperand(1); 3355 SDValue ShAmt = Op.getOperand(2); 3356 SDValue ARMcc; 3357 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL; 3358 3359 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS); 3360 3361 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, 3362 DAG.getConstant(VTBits, MVT::i32), ShAmt); 3363 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); 3364 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, 3365 DAG.getConstant(VTBits, MVT::i32)); 3366 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); 3367 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 3368 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt); 3369 3370 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 3371 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, 3372 ARMcc, DAG, dl); 3373 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt); 3374 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, 3375 CCR, Cmp); 3376 3377 SDValue Ops[2] = { Lo, Hi }; 3378 return DAG.getMergeValues(Ops, 2, dl); 3379} 3380 3381/// LowerShiftLeftParts - Lower SHL_PARTS, which returns two 3382/// i32 values and take a 2 x i32 value to shift plus a shift amount. 3383SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op, 3384 SelectionDAG &DAG) const { 3385 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 3386 EVT VT = Op.getValueType(); 3387 unsigned VTBits = VT.getSizeInBits(); 3388 DebugLoc dl = Op.getDebugLoc(); 3389 SDValue ShOpLo = Op.getOperand(0); 3390 SDValue ShOpHi = Op.getOperand(1); 3391 SDValue ShAmt = Op.getOperand(2); 3392 SDValue ARMcc; 3393 3394 assert(Op.getOpcode() == ISD::SHL_PARTS); 3395 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, 3396 DAG.getConstant(VTBits, MVT::i32), ShAmt); 3397 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); 3398 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, 3399 DAG.getConstant(VTBits, MVT::i32)); 3400 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); 3401 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); 3402 3403 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 3404 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 3405 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, 3406 ARMcc, DAG, dl); 3407 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 3408 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc, 3409 CCR, Cmp); 3410 3411 SDValue Ops[2] = { Lo, Hi }; 3412 return DAG.getMergeValues(Ops, 2, dl); 3413} 3414 3415SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op, 3416 SelectionDAG &DAG) const { 3417 // The rounding mode is in bits 23:22 of the FPSCR. 3418 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0 3419 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3) 3420 // so that the shift + and get folded into a bitfield extract. 3421 DebugLoc dl = Op.getDebugLoc(); 3422 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32, 3423 DAG.getConstant(Intrinsic::arm_get_fpscr, 3424 MVT::i32)); 3425 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR, 3426 DAG.getConstant(1U << 22, MVT::i32)); 3427 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds, 3428 DAG.getConstant(22, MVT::i32)); 3429 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE, 3430 DAG.getConstant(3, MVT::i32)); 3431} 3432 3433static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG, 3434 const ARMSubtarget *ST) { 3435 EVT VT = N->getValueType(0); 3436 DebugLoc dl = N->getDebugLoc(); 3437 3438 if (!ST->hasV6T2Ops()) 3439 return SDValue(); 3440 3441 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0)); 3442 return DAG.getNode(ISD::CTLZ, dl, VT, rbit); 3443} 3444 3445static SDValue LowerShift(SDNode *N, SelectionDAG &DAG, 3446 const ARMSubtarget *ST) { 3447 EVT VT = N->getValueType(0); 3448 DebugLoc dl = N->getDebugLoc(); 3449 3450 if (!VT.isVector()) 3451 return SDValue(); 3452 3453 // Lower vector shifts on NEON to use VSHL. 3454 assert(ST->hasNEON() && "unexpected vector shift"); 3455 3456 // Left shifts translate directly to the vshiftu intrinsic. 3457 if (N->getOpcode() == ISD::SHL) 3458 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 3459 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32), 3460 N->getOperand(0), N->getOperand(1)); 3461 3462 assert((N->getOpcode() == ISD::SRA || 3463 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode"); 3464 3465 // NEON uses the same intrinsics for both left and right shifts. For 3466 // right shifts, the shift amounts are negative, so negate the vector of 3467 // shift amounts. 3468 EVT ShiftVT = N->getOperand(1).getValueType(); 3469 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT, 3470 getZeroVector(ShiftVT, DAG, dl), 3471 N->getOperand(1)); 3472 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ? 3473 Intrinsic::arm_neon_vshifts : 3474 Intrinsic::arm_neon_vshiftu); 3475 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 3476 DAG.getConstant(vshiftInt, MVT::i32), 3477 N->getOperand(0), NegatedCount); 3478} 3479 3480static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG, 3481 const ARMSubtarget *ST) { 3482 EVT VT = N->getValueType(0); 3483 DebugLoc dl = N->getDebugLoc(); 3484 3485 // We can get here for a node like i32 = ISD::SHL i32, i64 3486 if (VT != MVT::i64) 3487 return SDValue(); 3488 3489 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && 3490 "Unknown shift to lower!"); 3491 3492 // We only lower SRA, SRL of 1 here, all others use generic lowering. 3493 if (!isa<ConstantSDNode>(N->getOperand(1)) || 3494 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1) 3495 return SDValue(); 3496 3497 // If we are in thumb mode, we don't have RRX. 3498 if (ST->isThumb1Only()) return SDValue(); 3499 3500 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr. 3501 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), 3502 DAG.getConstant(0, MVT::i32)); 3503 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), 3504 DAG.getConstant(1, MVT::i32)); 3505 3506 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and 3507 // captures the result into a carry flag. 3508 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG; 3509 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1); 3510 3511 // The low part is an ARMISD::RRX operand, which shifts the carry in. 3512 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1)); 3513 3514 // Merge the pieces into a single i64 value. 3515 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 3516} 3517 3518static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { 3519 SDValue TmpOp0, TmpOp1; 3520 bool Invert = false; 3521 bool Swap = false; 3522 unsigned Opc = 0; 3523 3524 SDValue Op0 = Op.getOperand(0); 3525 SDValue Op1 = Op.getOperand(1); 3526 SDValue CC = Op.getOperand(2); 3527 EVT VT = Op.getValueType(); 3528 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 3529 DebugLoc dl = Op.getDebugLoc(); 3530 3531 if (Op.getOperand(1).getValueType().isFloatingPoint()) { 3532 switch (SetCCOpcode) { 3533 default: llvm_unreachable("Illegal FP comparison"); 3534 case ISD::SETUNE: 3535 case ISD::SETNE: Invert = true; // Fallthrough 3536 case ISD::SETOEQ: 3537 case ISD::SETEQ: Opc = ARMISD::VCEQ; break; 3538 case ISD::SETOLT: 3539 case ISD::SETLT: Swap = true; // Fallthrough 3540 case ISD::SETOGT: 3541 case ISD::SETGT: Opc = ARMISD::VCGT; break; 3542 case ISD::SETOLE: 3543 case ISD::SETLE: Swap = true; // Fallthrough 3544 case ISD::SETOGE: 3545 case ISD::SETGE: Opc = ARMISD::VCGE; break; 3546 case ISD::SETUGE: Swap = true; // Fallthrough 3547 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break; 3548 case ISD::SETUGT: Swap = true; // Fallthrough 3549 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break; 3550 case ISD::SETUEQ: Invert = true; // Fallthrough 3551 case ISD::SETONE: 3552 // Expand this to (OLT | OGT). 3553 TmpOp0 = Op0; 3554 TmpOp1 = Op1; 3555 Opc = ISD::OR; 3556 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0); 3557 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1); 3558 break; 3559 case ISD::SETUO: Invert = true; // Fallthrough 3560 case ISD::SETO: 3561 // Expand this to (OLT | OGE). 3562 TmpOp0 = Op0; 3563 TmpOp1 = Op1; 3564 Opc = ISD::OR; 3565 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0); 3566 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1); 3567 break; 3568 } 3569 } else { 3570 // Integer comparisons. 3571 switch (SetCCOpcode) { 3572 default: llvm_unreachable("Illegal integer comparison"); 3573 case ISD::SETNE: Invert = true; 3574 case ISD::SETEQ: Opc = ARMISD::VCEQ; break; 3575 case ISD::SETLT: Swap = true; 3576 case ISD::SETGT: Opc = ARMISD::VCGT; break; 3577 case ISD::SETLE: Swap = true; 3578 case ISD::SETGE: Opc = ARMISD::VCGE; break; 3579 case ISD::SETULT: Swap = true; 3580 case ISD::SETUGT: Opc = ARMISD::VCGTU; break; 3581 case ISD::SETULE: Swap = true; 3582 case ISD::SETUGE: Opc = ARMISD::VCGEU; break; 3583 } 3584 3585 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero). 3586 if (Opc == ARMISD::VCEQ) { 3587 3588 SDValue AndOp; 3589 if (ISD::isBuildVectorAllZeros(Op1.getNode())) 3590 AndOp = Op0; 3591 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) 3592 AndOp = Op1; 3593 3594 // Ignore bitconvert. 3595 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST) 3596 AndOp = AndOp.getOperand(0); 3597 3598 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) { 3599 Opc = ARMISD::VTST; 3600 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0)); 3601 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1)); 3602 Invert = !Invert; 3603 } 3604 } 3605 } 3606 3607 if (Swap) 3608 std::swap(Op0, Op1); 3609 3610 // If one of the operands is a constant vector zero, attempt to fold the 3611 // comparison to a specialized compare-against-zero form. 3612 SDValue SingleOp; 3613 if (ISD::isBuildVectorAllZeros(Op1.getNode())) 3614 SingleOp = Op0; 3615 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) { 3616 if (Opc == ARMISD::VCGE) 3617 Opc = ARMISD::VCLEZ; 3618 else if (Opc == ARMISD::VCGT) 3619 Opc = ARMISD::VCLTZ; 3620 SingleOp = Op1; 3621 } 3622 3623 SDValue Result; 3624 if (SingleOp.getNode()) { 3625 switch (Opc) { 3626 case ARMISD::VCEQ: 3627 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break; 3628 case ARMISD::VCGE: 3629 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break; 3630 case ARMISD::VCLEZ: 3631 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break; 3632 case ARMISD::VCGT: 3633 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break; 3634 case ARMISD::VCLTZ: 3635 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break; 3636 default: 3637 Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 3638 } 3639 } else { 3640 Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 3641 } 3642 3643 if (Invert) 3644 Result = DAG.getNOT(dl, Result, VT); 3645 3646 return Result; 3647} 3648 3649/// isNEONModifiedImm - Check if the specified splat value corresponds to a 3650/// valid vector constant for a NEON instruction with a "modified immediate" 3651/// operand (e.g., VMOV). If so, return the encoded value. 3652static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef, 3653 unsigned SplatBitSize, SelectionDAG &DAG, 3654 EVT &VT, bool is128Bits, NEONModImmType type) { 3655 unsigned OpCmode, Imm; 3656 3657 // SplatBitSize is set to the smallest size that splats the vector, so a 3658 // zero vector will always have SplatBitSize == 8. However, NEON modified 3659 // immediate instructions others than VMOV do not support the 8-bit encoding 3660 // of a zero vector, and the default encoding of zero is supposed to be the 3661 // 32-bit version. 3662 if (SplatBits == 0) 3663 SplatBitSize = 32; 3664 3665 switch (SplatBitSize) { 3666 case 8: 3667 if (type != VMOVModImm) 3668 return SDValue(); 3669 // Any 1-byte value is OK. Op=0, Cmode=1110. 3670 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big"); 3671 OpCmode = 0xe; 3672 Imm = SplatBits; 3673 VT = is128Bits ? MVT::v16i8 : MVT::v8i8; 3674 break; 3675 3676 case 16: 3677 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero. 3678 VT = is128Bits ? MVT::v8i16 : MVT::v4i16; 3679 if ((SplatBits & ~0xff) == 0) { 3680 // Value = 0x00nn: Op=x, Cmode=100x. 3681 OpCmode = 0x8; 3682 Imm = SplatBits; 3683 break; 3684 } 3685 if ((SplatBits & ~0xff00) == 0) { 3686 // Value = 0xnn00: Op=x, Cmode=101x. 3687 OpCmode = 0xa; 3688 Imm = SplatBits >> 8; 3689 break; 3690 } 3691 return SDValue(); 3692 3693 case 32: 3694 // NEON's 32-bit VMOV supports splat values where: 3695 // * only one byte is nonzero, or 3696 // * the least significant byte is 0xff and the second byte is nonzero, or 3697 // * the least significant 2 bytes are 0xff and the third is nonzero. 3698 VT = is128Bits ? MVT::v4i32 : MVT::v2i32; 3699 if ((SplatBits & ~0xff) == 0) { 3700 // Value = 0x000000nn: Op=x, Cmode=000x. 3701 OpCmode = 0; 3702 Imm = SplatBits; 3703 break; 3704 } 3705 if ((SplatBits & ~0xff00) == 0) { 3706 // Value = 0x0000nn00: Op=x, Cmode=001x. 3707 OpCmode = 0x2; 3708 Imm = SplatBits >> 8; 3709 break; 3710 } 3711 if ((SplatBits & ~0xff0000) == 0) { 3712 // Value = 0x00nn0000: Op=x, Cmode=010x. 3713 OpCmode = 0x4; 3714 Imm = SplatBits >> 16; 3715 break; 3716 } 3717 if ((SplatBits & ~0xff000000) == 0) { 3718 // Value = 0xnn000000: Op=x, Cmode=011x. 3719 OpCmode = 0x6; 3720 Imm = SplatBits >> 24; 3721 break; 3722 } 3723 3724 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC 3725 if (type == OtherModImm) return SDValue(); 3726 3727 if ((SplatBits & ~0xffff) == 0 && 3728 ((SplatBits | SplatUndef) & 0xff) == 0xff) { 3729 // Value = 0x0000nnff: Op=x, Cmode=1100. 3730 OpCmode = 0xc; 3731 Imm = SplatBits >> 8; 3732 SplatBits |= 0xff; 3733 break; 3734 } 3735 3736 if ((SplatBits & ~0xffffff) == 0 && 3737 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) { 3738 // Value = 0x00nnffff: Op=x, Cmode=1101. 3739 OpCmode = 0xd; 3740 Imm = SplatBits >> 16; 3741 SplatBits |= 0xffff; 3742 break; 3743 } 3744 3745 // Note: there are a few 32-bit splat values (specifically: 00ffff00, 3746 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not 3747 // VMOV.I32. A (very) minor optimization would be to replicate the value 3748 // and fall through here to test for a valid 64-bit splat. But, then the 3749 // caller would also need to check and handle the change in size. 3750 return SDValue(); 3751 3752 case 64: { 3753 if (type != VMOVModImm) 3754 return SDValue(); 3755 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff. 3756 uint64_t BitMask = 0xff; 3757 uint64_t Val = 0; 3758 unsigned ImmMask = 1; 3759 Imm = 0; 3760 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) { 3761 if (((SplatBits | SplatUndef) & BitMask) == BitMask) { 3762 Val |= BitMask; 3763 Imm |= ImmMask; 3764 } else if ((SplatBits & BitMask) != 0) { 3765 return SDValue(); 3766 } 3767 BitMask <<= 8; 3768 ImmMask <<= 1; 3769 } 3770 // Op=1, Cmode=1110. 3771 OpCmode = 0x1e; 3772 SplatBits = Val; 3773 VT = is128Bits ? MVT::v2i64 : MVT::v1i64; 3774 break; 3775 } 3776 3777 default: 3778 llvm_unreachable("unexpected size for isNEONModifiedImm"); 3779 } 3780 3781 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm); 3782 return DAG.getTargetConstant(EncodedVal, MVT::i32); 3783} 3784 3785static bool isVEXTMask(ArrayRef<int> M, EVT VT, 3786 bool &ReverseVEXT, unsigned &Imm) { 3787 unsigned NumElts = VT.getVectorNumElements(); 3788 ReverseVEXT = false; 3789 3790 // Assume that the first shuffle index is not UNDEF. Fail if it is. 3791 if (M[0] < 0) 3792 return false; 3793 3794 Imm = M[0]; 3795 3796 // If this is a VEXT shuffle, the immediate value is the index of the first 3797 // element. The other shuffle indices must be the successive elements after 3798 // the first one. 3799 unsigned ExpectedElt = Imm; 3800 for (unsigned i = 1; i < NumElts; ++i) { 3801 // Increment the expected index. If it wraps around, it may still be 3802 // a VEXT but the source vectors must be swapped. 3803 ExpectedElt += 1; 3804 if (ExpectedElt == NumElts * 2) { 3805 ExpectedElt = 0; 3806 ReverseVEXT = true; 3807 } 3808 3809 if (M[i] < 0) continue; // ignore UNDEF indices 3810 if (ExpectedElt != static_cast<unsigned>(M[i])) 3811 return false; 3812 } 3813 3814 // Adjust the index value if the source operands will be swapped. 3815 if (ReverseVEXT) 3816 Imm -= NumElts; 3817 3818 return true; 3819} 3820 3821/// isVREVMask - Check if a vector shuffle corresponds to a VREV 3822/// instruction with the specified blocksize. (The order of the elements 3823/// within each block of the vector is reversed.) 3824static bool isVREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) { 3825 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) && 3826 "Only possible block sizes for VREV are: 16, 32, 64"); 3827 3828 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3829 if (EltSz == 64) 3830 return false; 3831 3832 unsigned NumElts = VT.getVectorNumElements(); 3833 unsigned BlockElts = M[0] + 1; 3834 // If the first shuffle index is UNDEF, be optimistic. 3835 if (M[0] < 0) 3836 BlockElts = BlockSize / EltSz; 3837 3838 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz) 3839 return false; 3840 3841 for (unsigned i = 0; i < NumElts; ++i) { 3842 if (M[i] < 0) continue; // ignore UNDEF indices 3843 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts)) 3844 return false; 3845 } 3846 3847 return true; 3848} 3849 3850static bool isVTBLMask(ArrayRef<int> M, EVT VT) { 3851 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of 3852 // range, then 0 is placed into the resulting vector. So pretty much any mask 3853 // of 8 elements can work here. 3854 return VT == MVT::v8i8 && M.size() == 8; 3855} 3856 3857static bool isVTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) { 3858 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3859 if (EltSz == 64) 3860 return false; 3861 3862 unsigned NumElts = VT.getVectorNumElements(); 3863 WhichResult = (M[0] == 0 ? 0 : 1); 3864 for (unsigned i = 0; i < NumElts; i += 2) { 3865 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) || 3866 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult)) 3867 return false; 3868 } 3869 return true; 3870} 3871 3872/// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of 3873/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 3874/// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>. 3875static bool isVTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){ 3876 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3877 if (EltSz == 64) 3878 return false; 3879 3880 unsigned NumElts = VT.getVectorNumElements(); 3881 WhichResult = (M[0] == 0 ? 0 : 1); 3882 for (unsigned i = 0; i < NumElts; i += 2) { 3883 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) || 3884 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult)) 3885 return false; 3886 } 3887 return true; 3888} 3889 3890static bool isVUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) { 3891 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3892 if (EltSz == 64) 3893 return false; 3894 3895 unsigned NumElts = VT.getVectorNumElements(); 3896 WhichResult = (M[0] == 0 ? 0 : 1); 3897 for (unsigned i = 0; i != NumElts; ++i) { 3898 if (M[i] < 0) continue; // ignore UNDEF indices 3899 if ((unsigned) M[i] != 2 * i + WhichResult) 3900 return false; 3901 } 3902 3903 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3904 if (VT.is64BitVector() && EltSz == 32) 3905 return false; 3906 3907 return true; 3908} 3909 3910/// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of 3911/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 3912/// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>, 3913static bool isVUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){ 3914 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3915 if (EltSz == 64) 3916 return false; 3917 3918 unsigned Half = VT.getVectorNumElements() / 2; 3919 WhichResult = (M[0] == 0 ? 0 : 1); 3920 for (unsigned j = 0; j != 2; ++j) { 3921 unsigned Idx = WhichResult; 3922 for (unsigned i = 0; i != Half; ++i) { 3923 int MIdx = M[i + j * Half]; 3924 if (MIdx >= 0 && (unsigned) MIdx != Idx) 3925 return false; 3926 Idx += 2; 3927 } 3928 } 3929 3930 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3931 if (VT.is64BitVector() && EltSz == 32) 3932 return false; 3933 3934 return true; 3935} 3936 3937static bool isVZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) { 3938 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3939 if (EltSz == 64) 3940 return false; 3941 3942 unsigned NumElts = VT.getVectorNumElements(); 3943 WhichResult = (M[0] == 0 ? 0 : 1); 3944 unsigned Idx = WhichResult * NumElts / 2; 3945 for (unsigned i = 0; i != NumElts; i += 2) { 3946 if ((M[i] >= 0 && (unsigned) M[i] != Idx) || 3947 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts)) 3948 return false; 3949 Idx += 1; 3950 } 3951 3952 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3953 if (VT.is64BitVector() && EltSz == 32) 3954 return false; 3955 3956 return true; 3957} 3958 3959/// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of 3960/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 3961/// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>. 3962static bool isVZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){ 3963 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3964 if (EltSz == 64) 3965 return false; 3966 3967 unsigned NumElts = VT.getVectorNumElements(); 3968 WhichResult = (M[0] == 0 ? 0 : 1); 3969 unsigned Idx = WhichResult * NumElts / 2; 3970 for (unsigned i = 0; i != NumElts; i += 2) { 3971 if ((M[i] >= 0 && (unsigned) M[i] != Idx) || 3972 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx)) 3973 return false; 3974 Idx += 1; 3975 } 3976 3977 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3978 if (VT.is64BitVector() && EltSz == 32) 3979 return false; 3980 3981 return true; 3982} 3983 3984// If N is an integer constant that can be moved into a register in one 3985// instruction, return an SDValue of such a constant (will become a MOV 3986// instruction). Otherwise return null. 3987static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG, 3988 const ARMSubtarget *ST, DebugLoc dl) { 3989 uint64_t Val; 3990 if (!isa<ConstantSDNode>(N)) 3991 return SDValue(); 3992 Val = cast<ConstantSDNode>(N)->getZExtValue(); 3993 3994 if (ST->isThumb1Only()) { 3995 if (Val <= 255 || ~Val <= 255) 3996 return DAG.getConstant(Val, MVT::i32); 3997 } else { 3998 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1) 3999 return DAG.getConstant(Val, MVT::i32); 4000 } 4001 return SDValue(); 4002} 4003 4004// If this is a case we can't handle, return null and let the default 4005// expansion code take care of it. 4006SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, 4007 const ARMSubtarget *ST) const { 4008 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode()); 4009 DebugLoc dl = Op.getDebugLoc(); 4010 EVT VT = Op.getValueType(); 4011 4012 APInt SplatBits, SplatUndef; 4013 unsigned SplatBitSize; 4014 bool HasAnyUndefs; 4015 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { 4016 if (SplatBitSize <= 64) { 4017 // Check if an immediate VMOV works. 4018 EVT VmovVT; 4019 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(), 4020 SplatUndef.getZExtValue(), SplatBitSize, 4021 DAG, VmovVT, VT.is128BitVector(), 4022 VMOVModImm); 4023 if (Val.getNode()) { 4024 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val); 4025 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); 4026 } 4027 4028 // Try an immediate VMVN. 4029 uint64_t NegatedImm = (~SplatBits).getZExtValue(); 4030 Val = isNEONModifiedImm(NegatedImm, 4031 SplatUndef.getZExtValue(), SplatBitSize, 4032 DAG, VmovVT, VT.is128BitVector(), 4033 VMVNModImm); 4034 if (Val.getNode()) { 4035 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val); 4036 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); 4037 } 4038 4039 // Use vmov.f32 to materialize other v2f32 and v4f32 splats. 4040 if ((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) { 4041 int ImmVal = ARM_AM::getFP32Imm(SplatBits); 4042 if (ImmVal != -1) { 4043 SDValue Val = DAG.getTargetConstant(ImmVal, MVT::i32); 4044 return DAG.getNode(ARMISD::VMOVFPIMM, dl, VT, Val); 4045 } 4046 } 4047 } 4048 } 4049 4050 // Scan through the operands to see if only one value is used. 4051 unsigned NumElts = VT.getVectorNumElements(); 4052 bool isOnlyLowElement = true; 4053 bool usesOnlyOneValue = true; 4054 bool isConstant = true; 4055 SDValue Value; 4056 for (unsigned i = 0; i < NumElts; ++i) { 4057 SDValue V = Op.getOperand(i); 4058 if (V.getOpcode() == ISD::UNDEF) 4059 continue; 4060 if (i > 0) 4061 isOnlyLowElement = false; 4062 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 4063 isConstant = false; 4064 4065 if (!Value.getNode()) 4066 Value = V; 4067 else if (V != Value) 4068 usesOnlyOneValue = false; 4069 } 4070 4071 if (!Value.getNode()) 4072 return DAG.getUNDEF(VT); 4073 4074 if (isOnlyLowElement) 4075 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value); 4076 4077 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 4078 4079 // Use VDUP for non-constant splats. For f32 constant splats, reduce to 4080 // i32 and try again. 4081 if (usesOnlyOneValue && EltSize <= 32) { 4082 if (!isConstant) 4083 return DAG.getNode(ARMISD::VDUP, dl, VT, Value); 4084 if (VT.getVectorElementType().isFloatingPoint()) { 4085 SmallVector<SDValue, 8> Ops; 4086 for (unsigned i = 0; i < NumElts; ++i) 4087 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32, 4088 Op.getOperand(i))); 4089 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts); 4090 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts); 4091 Val = LowerBUILD_VECTOR(Val, DAG, ST); 4092 if (Val.getNode()) 4093 return DAG.getNode(ISD::BITCAST, dl, VT, Val); 4094 } 4095 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl); 4096 if (Val.getNode()) 4097 return DAG.getNode(ARMISD::VDUP, dl, VT, Val); 4098 } 4099 4100 // If all elements are constants and the case above didn't get hit, fall back 4101 // to the default expansion, which will generate a load from the constant 4102 // pool. 4103 if (isConstant) 4104 return SDValue(); 4105 4106 // Empirical tests suggest this is rarely worth it for vectors of length <= 2. 4107 if (NumElts >= 4) { 4108 SDValue shuffle = ReconstructShuffle(Op, DAG); 4109 if (shuffle != SDValue()) 4110 return shuffle; 4111 } 4112 4113 // Vectors with 32- or 64-bit elements can be built by directly assigning 4114 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands 4115 // will be legalized. 4116 if (EltSize >= 32) { 4117 // Do the expansion with floating-point types, since that is what the VFP 4118 // registers are defined to use, and since i64 is not legal. 4119 EVT EltVT = EVT::getFloatingPointVT(EltSize); 4120 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); 4121 SmallVector<SDValue, 8> Ops; 4122 for (unsigned i = 0; i < NumElts; ++i) 4123 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i))); 4124 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts); 4125 return DAG.getNode(ISD::BITCAST, dl, VT, Val); 4126 } 4127 4128 return SDValue(); 4129} 4130 4131// Gather data to see if the operation can be modelled as a 4132// shuffle in combination with VEXTs. 4133SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op, 4134 SelectionDAG &DAG) const { 4135 DebugLoc dl = Op.getDebugLoc(); 4136 EVT VT = Op.getValueType(); 4137 unsigned NumElts = VT.getVectorNumElements(); 4138 4139 SmallVector<SDValue, 2> SourceVecs; 4140 SmallVector<unsigned, 2> MinElts; 4141 SmallVector<unsigned, 2> MaxElts; 4142 4143 for (unsigned i = 0; i < NumElts; ++i) { 4144 SDValue V = Op.getOperand(i); 4145 if (V.getOpcode() == ISD::UNDEF) 4146 continue; 4147 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) { 4148 // A shuffle can only come from building a vector from various 4149 // elements of other vectors. 4150 return SDValue(); 4151 } else if (V.getOperand(0).getValueType().getVectorElementType() != 4152 VT.getVectorElementType()) { 4153 // This code doesn't know how to handle shuffles where the vector 4154 // element types do not match (this happens because type legalization 4155 // promotes the return type of EXTRACT_VECTOR_ELT). 4156 // FIXME: It might be appropriate to extend this code to handle 4157 // mismatched types. 4158 return SDValue(); 4159 } 4160 4161 // Record this extraction against the appropriate vector if possible... 4162 SDValue SourceVec = V.getOperand(0); 4163 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue(); 4164 bool FoundSource = false; 4165 for (unsigned j = 0; j < SourceVecs.size(); ++j) { 4166 if (SourceVecs[j] == SourceVec) { 4167 if (MinElts[j] > EltNo) 4168 MinElts[j] = EltNo; 4169 if (MaxElts[j] < EltNo) 4170 MaxElts[j] = EltNo; 4171 FoundSource = true; 4172 break; 4173 } 4174 } 4175 4176 // Or record a new source if not... 4177 if (!FoundSource) { 4178 SourceVecs.push_back(SourceVec); 4179 MinElts.push_back(EltNo); 4180 MaxElts.push_back(EltNo); 4181 } 4182 } 4183 4184 // Currently only do something sane when at most two source vectors 4185 // involved. 4186 if (SourceVecs.size() > 2) 4187 return SDValue(); 4188 4189 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) }; 4190 int VEXTOffsets[2] = {0, 0}; 4191 4192 // This loop extracts the usage patterns of the source vectors 4193 // and prepares appropriate SDValues for a shuffle if possible. 4194 for (unsigned i = 0; i < SourceVecs.size(); ++i) { 4195 if (SourceVecs[i].getValueType() == VT) { 4196 // No VEXT necessary 4197 ShuffleSrcs[i] = SourceVecs[i]; 4198 VEXTOffsets[i] = 0; 4199 continue; 4200 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) { 4201 // It probably isn't worth padding out a smaller vector just to 4202 // break it down again in a shuffle. 4203 return SDValue(); 4204 } 4205 4206 // Since only 64-bit and 128-bit vectors are legal on ARM and 4207 // we've eliminated the other cases... 4208 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts && 4209 "unexpected vector sizes in ReconstructShuffle"); 4210 4211 if (MaxElts[i] - MinElts[i] >= NumElts) { 4212 // Span too large for a VEXT to cope 4213 return SDValue(); 4214 } 4215 4216 if (MinElts[i] >= NumElts) { 4217 // The extraction can just take the second half 4218 VEXTOffsets[i] = NumElts; 4219 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4220 SourceVecs[i], 4221 DAG.getIntPtrConstant(NumElts)); 4222 } else if (MaxElts[i] < NumElts) { 4223 // The extraction can just take the first half 4224 VEXTOffsets[i] = 0; 4225 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4226 SourceVecs[i], 4227 DAG.getIntPtrConstant(0)); 4228 } else { 4229 // An actual VEXT is needed 4230 VEXTOffsets[i] = MinElts[i]; 4231 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4232 SourceVecs[i], 4233 DAG.getIntPtrConstant(0)); 4234 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4235 SourceVecs[i], 4236 DAG.getIntPtrConstant(NumElts)); 4237 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2, 4238 DAG.getConstant(VEXTOffsets[i], MVT::i32)); 4239 } 4240 } 4241 4242 SmallVector<int, 8> Mask; 4243 4244 for (unsigned i = 0; i < NumElts; ++i) { 4245 SDValue Entry = Op.getOperand(i); 4246 if (Entry.getOpcode() == ISD::UNDEF) { 4247 Mask.push_back(-1); 4248 continue; 4249 } 4250 4251 SDValue ExtractVec = Entry.getOperand(0); 4252 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i) 4253 .getOperand(1))->getSExtValue(); 4254 if (ExtractVec == SourceVecs[0]) { 4255 Mask.push_back(ExtractElt - VEXTOffsets[0]); 4256 } else { 4257 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]); 4258 } 4259 } 4260 4261 // Final check before we try to produce nonsense... 4262 if (isShuffleMaskLegal(Mask, VT)) 4263 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1], 4264 &Mask[0]); 4265 4266 return SDValue(); 4267} 4268 4269/// isShuffleMaskLegal - Targets can use this to indicate that they only 4270/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 4271/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 4272/// are assumed to be legal. 4273bool 4274ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 4275 EVT VT) const { 4276 if (VT.getVectorNumElements() == 4 && 4277 (VT.is128BitVector() || VT.is64BitVector())) { 4278 unsigned PFIndexes[4]; 4279 for (unsigned i = 0; i != 4; ++i) { 4280 if (M[i] < 0) 4281 PFIndexes[i] = 8; 4282 else 4283 PFIndexes[i] = M[i]; 4284 } 4285 4286 // Compute the index in the perfect shuffle table. 4287 unsigned PFTableIndex = 4288 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 4289 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 4290 unsigned Cost = (PFEntry >> 30); 4291 4292 if (Cost <= 4) 4293 return true; 4294 } 4295 4296 bool ReverseVEXT; 4297 unsigned Imm, WhichResult; 4298 4299 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 4300 return (EltSize >= 32 || 4301 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 4302 isVREVMask(M, VT, 64) || 4303 isVREVMask(M, VT, 32) || 4304 isVREVMask(M, VT, 16) || 4305 isVEXTMask(M, VT, ReverseVEXT, Imm) || 4306 isVTBLMask(M, VT) || 4307 isVTRNMask(M, VT, WhichResult) || 4308 isVUZPMask(M, VT, WhichResult) || 4309 isVZIPMask(M, VT, WhichResult) || 4310 isVTRN_v_undef_Mask(M, VT, WhichResult) || 4311 isVUZP_v_undef_Mask(M, VT, WhichResult) || 4312 isVZIP_v_undef_Mask(M, VT, WhichResult)); 4313} 4314 4315/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 4316/// the specified operations to build the shuffle. 4317static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 4318 SDValue RHS, SelectionDAG &DAG, 4319 DebugLoc dl) { 4320 unsigned OpNum = (PFEntry >> 26) & 0x0F; 4321 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 4322 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 4323 4324 enum { 4325 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 4326 OP_VREV, 4327 OP_VDUP0, 4328 OP_VDUP1, 4329 OP_VDUP2, 4330 OP_VDUP3, 4331 OP_VEXT1, 4332 OP_VEXT2, 4333 OP_VEXT3, 4334 OP_VUZPL, // VUZP, left result 4335 OP_VUZPR, // VUZP, right result 4336 OP_VZIPL, // VZIP, left result 4337 OP_VZIPR, // VZIP, right result 4338 OP_VTRNL, // VTRN, left result 4339 OP_VTRNR // VTRN, right result 4340 }; 4341 4342 if (OpNum == OP_COPY) { 4343 if (LHSID == (1*9+2)*9+3) return LHS; 4344 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 4345 return RHS; 4346 } 4347 4348 SDValue OpLHS, OpRHS; 4349 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); 4350 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); 4351 EVT VT = OpLHS.getValueType(); 4352 4353 switch (OpNum) { 4354 default: llvm_unreachable("Unknown shuffle opcode!"); 4355 case OP_VREV: 4356 // VREV divides the vector in half and swaps within the half. 4357 if (VT.getVectorElementType() == MVT::i32 || 4358 VT.getVectorElementType() == MVT::f32) 4359 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); 4360 // vrev <4 x i16> -> VREV32 4361 if (VT.getVectorElementType() == MVT::i16) 4362 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS); 4363 // vrev <4 x i8> -> VREV16 4364 assert(VT.getVectorElementType() == MVT::i8); 4365 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS); 4366 case OP_VDUP0: 4367 case OP_VDUP1: 4368 case OP_VDUP2: 4369 case OP_VDUP3: 4370 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, 4371 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32)); 4372 case OP_VEXT1: 4373 case OP_VEXT2: 4374 case OP_VEXT3: 4375 return DAG.getNode(ARMISD::VEXT, dl, VT, 4376 OpLHS, OpRHS, 4377 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32)); 4378 case OP_VUZPL: 4379 case OP_VUZPR: 4380 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 4381 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL); 4382 case OP_VZIPL: 4383 case OP_VZIPR: 4384 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 4385 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL); 4386 case OP_VTRNL: 4387 case OP_VTRNR: 4388 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 4389 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL); 4390 } 4391} 4392 4393static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op, 4394 ArrayRef<int> ShuffleMask, 4395 SelectionDAG &DAG) { 4396 // Check to see if we can use the VTBL instruction. 4397 SDValue V1 = Op.getOperand(0); 4398 SDValue V2 = Op.getOperand(1); 4399 DebugLoc DL = Op.getDebugLoc(); 4400 4401 SmallVector<SDValue, 8> VTBLMask; 4402 for (ArrayRef<int>::iterator 4403 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I) 4404 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32)); 4405 4406 if (V2.getNode()->getOpcode() == ISD::UNDEF) 4407 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1, 4408 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, 4409 &VTBLMask[0], 8)); 4410 4411 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2, 4412 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, 4413 &VTBLMask[0], 8)); 4414} 4415 4416static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { 4417 SDValue V1 = Op.getOperand(0); 4418 SDValue V2 = Op.getOperand(1); 4419 DebugLoc dl = Op.getDebugLoc(); 4420 EVT VT = Op.getValueType(); 4421 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode()); 4422 4423 // Convert shuffles that are directly supported on NEON to target-specific 4424 // DAG nodes, instead of keeping them as shuffles and matching them again 4425 // during code selection. This is more efficient and avoids the possibility 4426 // of inconsistencies between legalization and selection. 4427 // FIXME: floating-point vectors should be canonicalized to integer vectors 4428 // of the same time so that they get CSEd properly. 4429 ArrayRef<int> ShuffleMask = SVN->getMask(); 4430 4431 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 4432 if (EltSize <= 32) { 4433 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) { 4434 int Lane = SVN->getSplatIndex(); 4435 // If this is undef splat, generate it via "just" vdup, if possible. 4436 if (Lane == -1) Lane = 0; 4437 4438 // Test if V1 is a SCALAR_TO_VECTOR. 4439 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) { 4440 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0)); 4441 } 4442 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR 4443 // (and probably will turn into a SCALAR_TO_VECTOR once legalization 4444 // reaches it). 4445 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR && 4446 !isa<ConstantSDNode>(V1.getOperand(0))) { 4447 bool IsScalarToVector = true; 4448 for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i) 4449 if (V1.getOperand(i).getOpcode() != ISD::UNDEF) { 4450 IsScalarToVector = false; 4451 break; 4452 } 4453 if (IsScalarToVector) 4454 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0)); 4455 } 4456 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1, 4457 DAG.getConstant(Lane, MVT::i32)); 4458 } 4459 4460 bool ReverseVEXT; 4461 unsigned Imm; 4462 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) { 4463 if (ReverseVEXT) 4464 std::swap(V1, V2); 4465 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2, 4466 DAG.getConstant(Imm, MVT::i32)); 4467 } 4468 4469 if (isVREVMask(ShuffleMask, VT, 64)) 4470 return DAG.getNode(ARMISD::VREV64, dl, VT, V1); 4471 if (isVREVMask(ShuffleMask, VT, 32)) 4472 return DAG.getNode(ARMISD::VREV32, dl, VT, V1); 4473 if (isVREVMask(ShuffleMask, VT, 16)) 4474 return DAG.getNode(ARMISD::VREV16, dl, VT, V1); 4475 4476 // Check for Neon shuffles that modify both input vectors in place. 4477 // If both results are used, i.e., if there are two shuffles with the same 4478 // source operands and with masks corresponding to both results of one of 4479 // these operations, DAG memoization will ensure that a single node is 4480 // used for both shuffles. 4481 unsigned WhichResult; 4482 if (isVTRNMask(ShuffleMask, VT, WhichResult)) 4483 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 4484 V1, V2).getValue(WhichResult); 4485 if (isVUZPMask(ShuffleMask, VT, WhichResult)) 4486 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 4487 V1, V2).getValue(WhichResult); 4488 if (isVZIPMask(ShuffleMask, VT, WhichResult)) 4489 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 4490 V1, V2).getValue(WhichResult); 4491 4492 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) 4493 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 4494 V1, V1).getValue(WhichResult); 4495 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) 4496 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 4497 V1, V1).getValue(WhichResult); 4498 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) 4499 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 4500 V1, V1).getValue(WhichResult); 4501 } 4502 4503 // If the shuffle is not directly supported and it has 4 elements, use 4504 // the PerfectShuffle-generated table to synthesize it from other shuffles. 4505 unsigned NumElts = VT.getVectorNumElements(); 4506 if (NumElts == 4) { 4507 unsigned PFIndexes[4]; 4508 for (unsigned i = 0; i != 4; ++i) { 4509 if (ShuffleMask[i] < 0) 4510 PFIndexes[i] = 8; 4511 else 4512 PFIndexes[i] = ShuffleMask[i]; 4513 } 4514 4515 // Compute the index in the perfect shuffle table. 4516 unsigned PFTableIndex = 4517 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 4518 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 4519 unsigned Cost = (PFEntry >> 30); 4520 4521 if (Cost <= 4) 4522 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); 4523 } 4524 4525 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs. 4526 if (EltSize >= 32) { 4527 // Do the expansion with floating-point types, since that is what the VFP 4528 // registers are defined to use, and since i64 is not legal. 4529 EVT EltVT = EVT::getFloatingPointVT(EltSize); 4530 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); 4531 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1); 4532 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2); 4533 SmallVector<SDValue, 8> Ops; 4534 for (unsigned i = 0; i < NumElts; ++i) { 4535 if (ShuffleMask[i] < 0) 4536 Ops.push_back(DAG.getUNDEF(EltVT)); 4537 else 4538 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 4539 ShuffleMask[i] < (int)NumElts ? V1 : V2, 4540 DAG.getConstant(ShuffleMask[i] & (NumElts-1), 4541 MVT::i32))); 4542 } 4543 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts); 4544 return DAG.getNode(ISD::BITCAST, dl, VT, Val); 4545 } 4546 4547 if (VT == MVT::v8i8) { 4548 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG); 4549 if (NewOp.getNode()) 4550 return NewOp; 4551 } 4552 4553 return SDValue(); 4554} 4555 4556static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4557 // INSERT_VECTOR_ELT is legal only for immediate indexes. 4558 SDValue Lane = Op.getOperand(2); 4559 if (!isa<ConstantSDNode>(Lane)) 4560 return SDValue(); 4561 4562 return Op; 4563} 4564 4565static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4566 // EXTRACT_VECTOR_ELT is legal only for immediate indexes. 4567 SDValue Lane = Op.getOperand(1); 4568 if (!isa<ConstantSDNode>(Lane)) 4569 return SDValue(); 4570 4571 SDValue Vec = Op.getOperand(0); 4572 if (Op.getValueType() == MVT::i32 && 4573 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) { 4574 DebugLoc dl = Op.getDebugLoc(); 4575 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane); 4576 } 4577 4578 return Op; 4579} 4580 4581static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 4582 // The only time a CONCAT_VECTORS operation can have legal types is when 4583 // two 64-bit vectors are concatenated to a 128-bit vector. 4584 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 && 4585 "unexpected CONCAT_VECTORS"); 4586 DebugLoc dl = Op.getDebugLoc(); 4587 SDValue Val = DAG.getUNDEF(MVT::v2f64); 4588 SDValue Op0 = Op.getOperand(0); 4589 SDValue Op1 = Op.getOperand(1); 4590 if (Op0.getOpcode() != ISD::UNDEF) 4591 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, 4592 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0), 4593 DAG.getIntPtrConstant(0)); 4594 if (Op1.getOpcode() != ISD::UNDEF) 4595 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, 4596 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1), 4597 DAG.getIntPtrConstant(1)); 4598 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val); 4599} 4600 4601/// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each 4602/// element has been zero/sign-extended, depending on the isSigned parameter, 4603/// from an integer type half its size. 4604static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG, 4605 bool isSigned) { 4606 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32. 4607 EVT VT = N->getValueType(0); 4608 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) { 4609 SDNode *BVN = N->getOperand(0).getNode(); 4610 if (BVN->getValueType(0) != MVT::v4i32 || 4611 BVN->getOpcode() != ISD::BUILD_VECTOR) 4612 return false; 4613 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0; 4614 unsigned HiElt = 1 - LoElt; 4615 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt)); 4616 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt)); 4617 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2)); 4618 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2)); 4619 if (!Lo0 || !Hi0 || !Lo1 || !Hi1) 4620 return false; 4621 if (isSigned) { 4622 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 && 4623 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32) 4624 return true; 4625 } else { 4626 if (Hi0->isNullValue() && Hi1->isNullValue()) 4627 return true; 4628 } 4629 return false; 4630 } 4631 4632 if (N->getOpcode() != ISD::BUILD_VECTOR) 4633 return false; 4634 4635 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 4636 SDNode *Elt = N->getOperand(i).getNode(); 4637 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) { 4638 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 4639 unsigned HalfSize = EltSize / 2; 4640 if (isSigned) { 4641 if (!isIntN(HalfSize, C->getSExtValue())) 4642 return false; 4643 } else { 4644 if (!isUIntN(HalfSize, C->getZExtValue())) 4645 return false; 4646 } 4647 continue; 4648 } 4649 return false; 4650 } 4651 4652 return true; 4653} 4654 4655/// isSignExtended - Check if a node is a vector value that is sign-extended 4656/// or a constant BUILD_VECTOR with sign-extended elements. 4657static bool isSignExtended(SDNode *N, SelectionDAG &DAG) { 4658 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N)) 4659 return true; 4660 if (isExtendedBUILD_VECTOR(N, DAG, true)) 4661 return true; 4662 return false; 4663} 4664 4665/// isZeroExtended - Check if a node is a vector value that is zero-extended 4666/// or a constant BUILD_VECTOR with zero-extended elements. 4667static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) { 4668 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N)) 4669 return true; 4670 if (isExtendedBUILD_VECTOR(N, DAG, false)) 4671 return true; 4672 return false; 4673} 4674 4675/// SkipExtension - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending 4676/// load, or BUILD_VECTOR with extended elements, return the unextended value. 4677static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) { 4678 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND) 4679 return N->getOperand(0); 4680 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) 4681 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(), 4682 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(), 4683 LD->isNonTemporal(), LD->isInvariant(), 4684 LD->getAlignment()); 4685 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will 4686 // have been legalized as a BITCAST from v4i32. 4687 if (N->getOpcode() == ISD::BITCAST) { 4688 SDNode *BVN = N->getOperand(0).getNode(); 4689 assert(BVN->getOpcode() == ISD::BUILD_VECTOR && 4690 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR"); 4691 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0; 4692 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32, 4693 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2)); 4694 } 4695 // Construct a new BUILD_VECTOR with elements truncated to half the size. 4696 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR"); 4697 EVT VT = N->getValueType(0); 4698 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2; 4699 unsigned NumElts = VT.getVectorNumElements(); 4700 MVT TruncVT = MVT::getIntegerVT(EltSize); 4701 SmallVector<SDValue, 8> Ops; 4702 for (unsigned i = 0; i != NumElts; ++i) { 4703 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i)); 4704 const APInt &CInt = C->getAPIntValue(); 4705 Ops.push_back(DAG.getConstant(CInt.trunc(EltSize), TruncVT)); 4706 } 4707 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 4708 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts); 4709} 4710 4711static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) { 4712 unsigned Opcode = N->getOpcode(); 4713 if (Opcode == ISD::ADD || Opcode == ISD::SUB) { 4714 SDNode *N0 = N->getOperand(0).getNode(); 4715 SDNode *N1 = N->getOperand(1).getNode(); 4716 return N0->hasOneUse() && N1->hasOneUse() && 4717 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); 4718 } 4719 return false; 4720} 4721 4722static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) { 4723 unsigned Opcode = N->getOpcode(); 4724 if (Opcode == ISD::ADD || Opcode == ISD::SUB) { 4725 SDNode *N0 = N->getOperand(0).getNode(); 4726 SDNode *N1 = N->getOperand(1).getNode(); 4727 return N0->hasOneUse() && N1->hasOneUse() && 4728 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); 4729 } 4730 return false; 4731} 4732 4733static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) { 4734 // Multiplications are only custom-lowered for 128-bit vectors so that 4735 // VMULL can be detected. Otherwise v2i64 multiplications are not legal. 4736 EVT VT = Op.getValueType(); 4737 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL"); 4738 SDNode *N0 = Op.getOperand(0).getNode(); 4739 SDNode *N1 = Op.getOperand(1).getNode(); 4740 unsigned NewOpc = 0; 4741 bool isMLA = false; 4742 bool isN0SExt = isSignExtended(N0, DAG); 4743 bool isN1SExt = isSignExtended(N1, DAG); 4744 if (isN0SExt && isN1SExt) 4745 NewOpc = ARMISD::VMULLs; 4746 else { 4747 bool isN0ZExt = isZeroExtended(N0, DAG); 4748 bool isN1ZExt = isZeroExtended(N1, DAG); 4749 if (isN0ZExt && isN1ZExt) 4750 NewOpc = ARMISD::VMULLu; 4751 else if (isN1SExt || isN1ZExt) { 4752 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these 4753 // into (s/zext A * s/zext C) + (s/zext B * s/zext C) 4754 if (isN1SExt && isAddSubSExt(N0, DAG)) { 4755 NewOpc = ARMISD::VMULLs; 4756 isMLA = true; 4757 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) { 4758 NewOpc = ARMISD::VMULLu; 4759 isMLA = true; 4760 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) { 4761 std::swap(N0, N1); 4762 NewOpc = ARMISD::VMULLu; 4763 isMLA = true; 4764 } 4765 } 4766 4767 if (!NewOpc) { 4768 if (VT == MVT::v2i64) 4769 // Fall through to expand this. It is not legal. 4770 return SDValue(); 4771 else 4772 // Other vector multiplications are legal. 4773 return Op; 4774 } 4775 } 4776 4777 // Legalize to a VMULL instruction. 4778 DebugLoc DL = Op.getDebugLoc(); 4779 SDValue Op0; 4780 SDValue Op1 = SkipExtension(N1, DAG); 4781 if (!isMLA) { 4782 Op0 = SkipExtension(N0, DAG); 4783 assert(Op0.getValueType().is64BitVector() && 4784 Op1.getValueType().is64BitVector() && 4785 "unexpected types for extended operands to VMULL"); 4786 return DAG.getNode(NewOpc, DL, VT, Op0, Op1); 4787 } 4788 4789 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during 4790 // isel lowering to take advantage of no-stall back to back vmul + vmla. 4791 // vmull q0, d4, d6 4792 // vmlal q0, d5, d6 4793 // is faster than 4794 // vaddl q0, d4, d5 4795 // vmovl q1, d6 4796 // vmul q0, q0, q1 4797 SDValue N00 = SkipExtension(N0->getOperand(0).getNode(), DAG); 4798 SDValue N01 = SkipExtension(N0->getOperand(1).getNode(), DAG); 4799 EVT Op1VT = Op1.getValueType(); 4800 return DAG.getNode(N0->getOpcode(), DL, VT, 4801 DAG.getNode(NewOpc, DL, VT, 4802 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1), 4803 DAG.getNode(NewOpc, DL, VT, 4804 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); 4805} 4806 4807static SDValue 4808LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) { 4809 // Convert to float 4810 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo)); 4811 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo)); 4812 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X); 4813 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y); 4814 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X); 4815 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y); 4816 // Get reciprocal estimate. 4817 // float4 recip = vrecpeq_f32(yf); 4818 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4819 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y); 4820 // Because char has a smaller range than uchar, we can actually get away 4821 // without any newton steps. This requires that we use a weird bias 4822 // of 0xb000, however (again, this has been exhaustively tested). 4823 // float4 result = as_float4(as_int4(xf*recip) + 0xb000); 4824 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y); 4825 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X); 4826 Y = DAG.getConstant(0xb000, MVT::i32); 4827 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y); 4828 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y); 4829 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X); 4830 // Convert back to short. 4831 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X); 4832 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X); 4833 return X; 4834} 4835 4836static SDValue 4837LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) { 4838 SDValue N2; 4839 // Convert to float. 4840 // float4 yf = vcvt_f32_s32(vmovl_s16(y)); 4841 // float4 xf = vcvt_f32_s32(vmovl_s16(x)); 4842 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0); 4843 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1); 4844 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); 4845 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1); 4846 4847 // Use reciprocal estimate and one refinement step. 4848 // float4 recip = vrecpeq_f32(yf); 4849 // recip *= vrecpsq_f32(yf, recip); 4850 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4851 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1); 4852 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4853 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32), 4854 N1, N2); 4855 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); 4856 // Because short has a smaller range than ushort, we can actually get away 4857 // with only a single newton step. This requires that we use a weird bias 4858 // of 89, however (again, this has been exhaustively tested). 4859 // float4 result = as_float4(as_int4(xf*recip) + 0x89); 4860 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); 4861 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); 4862 N1 = DAG.getConstant(0x89, MVT::i32); 4863 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1); 4864 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); 4865 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); 4866 // Convert back to integer and return. 4867 // return vmovn_s32(vcvt_s32_f32(result)); 4868 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); 4869 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); 4870 return N0; 4871} 4872 4873static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) { 4874 EVT VT = Op.getValueType(); 4875 assert((VT == MVT::v4i16 || VT == MVT::v8i8) && 4876 "unexpected type for custom-lowering ISD::SDIV"); 4877 4878 DebugLoc dl = Op.getDebugLoc(); 4879 SDValue N0 = Op.getOperand(0); 4880 SDValue N1 = Op.getOperand(1); 4881 SDValue N2, N3; 4882 4883 if (VT == MVT::v8i8) { 4884 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0); 4885 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1); 4886 4887 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, 4888 DAG.getIntPtrConstant(4)); 4889 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, 4890 DAG.getIntPtrConstant(4)); 4891 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, 4892 DAG.getIntPtrConstant(0)); 4893 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, 4894 DAG.getIntPtrConstant(0)); 4895 4896 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16 4897 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16 4898 4899 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); 4900 N0 = LowerCONCAT_VECTORS(N0, DAG); 4901 4902 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0); 4903 return N0; 4904 } 4905 return LowerSDIV_v4i16(N0, N1, dl, DAG); 4906} 4907 4908static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) { 4909 EVT VT = Op.getValueType(); 4910 assert((VT == MVT::v4i16 || VT == MVT::v8i8) && 4911 "unexpected type for custom-lowering ISD::UDIV"); 4912 4913 DebugLoc dl = Op.getDebugLoc(); 4914 SDValue N0 = Op.getOperand(0); 4915 SDValue N1 = Op.getOperand(1); 4916 SDValue N2, N3; 4917 4918 if (VT == MVT::v8i8) { 4919 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0); 4920 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1); 4921 4922 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, 4923 DAG.getIntPtrConstant(4)); 4924 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, 4925 DAG.getIntPtrConstant(4)); 4926 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, 4927 DAG.getIntPtrConstant(0)); 4928 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, 4929 DAG.getIntPtrConstant(0)); 4930 4931 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16 4932 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16 4933 4934 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); 4935 N0 = LowerCONCAT_VECTORS(N0, DAG); 4936 4937 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8, 4938 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32), 4939 N0); 4940 return N0; 4941 } 4942 4943 // v4i16 sdiv ... Convert to float. 4944 // float4 yf = vcvt_f32_s32(vmovl_u16(y)); 4945 // float4 xf = vcvt_f32_s32(vmovl_u16(x)); 4946 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0); 4947 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1); 4948 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); 4949 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1); 4950 4951 // Use reciprocal estimate and two refinement steps. 4952 // float4 recip = vrecpeq_f32(yf); 4953 // recip *= vrecpsq_f32(yf, recip); 4954 // recip *= vrecpsq_f32(yf, recip); 4955 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4956 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1); 4957 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4958 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32), 4959 BN1, N2); 4960 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); 4961 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4962 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32), 4963 BN1, N2); 4964 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); 4965 // Simply multiplying by the reciprocal estimate can leave us a few ulps 4966 // too low, so we add 2 ulps (exhaustive testing shows that this is enough, 4967 // and that it will never cause us to return an answer too large). 4968 // float4 result = as_float4(as_int4(xf*recip) + 2); 4969 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); 4970 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); 4971 N1 = DAG.getConstant(2, MVT::i32); 4972 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1); 4973 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); 4974 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); 4975 // Convert back to integer and return. 4976 // return vmovn_u32(vcvt_s32_f32(result)); 4977 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); 4978 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); 4979 return N0; 4980} 4981 4982static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 4983 EVT VT = Op.getNode()->getValueType(0); 4984 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 4985 4986 unsigned Opc; 4987 bool ExtraOp = false; 4988 switch (Op.getOpcode()) { 4989 default: llvm_unreachable("Invalid code"); 4990 case ISD::ADDC: Opc = ARMISD::ADDC; break; 4991 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break; 4992 case ISD::SUBC: Opc = ARMISD::SUBC; break; 4993 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break; 4994 } 4995 4996 if (!ExtraOp) 4997 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 4998 Op.getOperand(1)); 4999 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 5000 Op.getOperand(1), Op.getOperand(2)); 5001} 5002 5003static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) { 5004 // Monotonic load/store is legal for all targets 5005 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic) 5006 return Op; 5007 5008 // Aquire/Release load/store is not legal for targets without a 5009 // dmb or equivalent available. 5010 return SDValue(); 5011} 5012 5013 5014static void 5015ReplaceATOMIC_OP_64(SDNode *Node, SmallVectorImpl<SDValue>& Results, 5016 SelectionDAG &DAG, unsigned NewOp) { 5017 DebugLoc dl = Node->getDebugLoc(); 5018 assert (Node->getValueType(0) == MVT::i64 && 5019 "Only know how to expand i64 atomics"); 5020 5021 SmallVector<SDValue, 6> Ops; 5022 Ops.push_back(Node->getOperand(0)); // Chain 5023 Ops.push_back(Node->getOperand(1)); // Ptr 5024 // Low part of Val1 5025 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5026 Node->getOperand(2), DAG.getIntPtrConstant(0))); 5027 // High part of Val1 5028 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5029 Node->getOperand(2), DAG.getIntPtrConstant(1))); 5030 if (NewOp == ARMISD::ATOMCMPXCHG64_DAG) { 5031 // High part of Val1 5032 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5033 Node->getOperand(3), DAG.getIntPtrConstant(0))); 5034 // High part of Val2 5035 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 5036 Node->getOperand(3), DAG.getIntPtrConstant(1))); 5037 } 5038 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 5039 SDValue Result = 5040 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops.data(), Ops.size(), MVT::i64, 5041 cast<MemSDNode>(Node)->getMemOperand()); 5042 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1) }; 5043 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 5044 Results.push_back(Result.getValue(2)); 5045} 5046 5047SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 5048 switch (Op.getOpcode()) { 5049 default: llvm_unreachable("Don't know how to custom lower this!"); 5050 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 5051 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 5052 case ISD::GlobalAddress: 5053 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) : 5054 LowerGlobalAddressELF(Op, DAG); 5055 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 5056 case ISD::SELECT: return LowerSELECT(Op, DAG); 5057 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 5058 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 5059 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 5060 case ISD::VASTART: return LowerVASTART(Op, DAG); 5061 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget); 5062 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget); 5063 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget); 5064 case ISD::SINT_TO_FP: 5065 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); 5066 case ISD::FP_TO_SINT: 5067 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG); 5068 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 5069 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 5070 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 5071 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG); 5072 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG); 5073 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG); 5074 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG, 5075 Subtarget); 5076 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG); 5077 case ISD::SHL: 5078 case ISD::SRL: 5079 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget); 5080 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG); 5081 case ISD::SRL_PARTS: 5082 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG); 5083 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget); 5084 case ISD::SETCC: return LowerVSETCC(Op, DAG); 5085 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget); 5086 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 5087 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 5088 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 5089 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 5090 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 5091 case ISD::MUL: return LowerMUL(Op, DAG); 5092 case ISD::SDIV: return LowerSDIV(Op, DAG); 5093 case ISD::UDIV: return LowerUDIV(Op, DAG); 5094 case ISD::ADDC: 5095 case ISD::ADDE: 5096 case ISD::SUBC: 5097 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 5098 case ISD::ATOMIC_LOAD: 5099 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG); 5100 } 5101} 5102 5103/// ReplaceNodeResults - Replace the results of node with an illegal result 5104/// type with new values built out of custom code. 5105void ARMTargetLowering::ReplaceNodeResults(SDNode *N, 5106 SmallVectorImpl<SDValue>&Results, 5107 SelectionDAG &DAG) const { 5108 SDValue Res; 5109 switch (N->getOpcode()) { 5110 default: 5111 llvm_unreachable("Don't know how to custom expand this!"); 5112 case ISD::BITCAST: 5113 Res = ExpandBITCAST(N, DAG); 5114 break; 5115 case ISD::SRL: 5116 case ISD::SRA: 5117 Res = Expand64BitShift(N, DAG, Subtarget); 5118 break; 5119 case ISD::ATOMIC_LOAD_ADD: 5120 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMADD64_DAG); 5121 return; 5122 case ISD::ATOMIC_LOAD_AND: 5123 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMAND64_DAG); 5124 return; 5125 case ISD::ATOMIC_LOAD_NAND: 5126 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMNAND64_DAG); 5127 return; 5128 case ISD::ATOMIC_LOAD_OR: 5129 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMOR64_DAG); 5130 return; 5131 case ISD::ATOMIC_LOAD_SUB: 5132 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSUB64_DAG); 5133 return; 5134 case ISD::ATOMIC_LOAD_XOR: 5135 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMXOR64_DAG); 5136 return; 5137 case ISD::ATOMIC_SWAP: 5138 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSWAP64_DAG); 5139 return; 5140 case ISD::ATOMIC_CMP_SWAP: 5141 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMCMPXCHG64_DAG); 5142 return; 5143 } 5144 if (Res.getNode()) 5145 Results.push_back(Res); 5146} 5147 5148//===----------------------------------------------------------------------===// 5149// ARM Scheduler Hooks 5150//===----------------------------------------------------------------------===// 5151 5152MachineBasicBlock * 5153ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, 5154 MachineBasicBlock *BB, 5155 unsigned Size) const { 5156 unsigned dest = MI->getOperand(0).getReg(); 5157 unsigned ptr = MI->getOperand(1).getReg(); 5158 unsigned oldval = MI->getOperand(2).getReg(); 5159 unsigned newval = MI->getOperand(3).getReg(); 5160 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5161 DebugLoc dl = MI->getDebugLoc(); 5162 bool isThumb2 = Subtarget->isThumb2(); 5163 5164 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 5165 unsigned scratch = 5166 MRI.createVirtualRegister(isThumb2 ? ARM::rGPRRegisterClass 5167 : ARM::GPRRegisterClass); 5168 5169 if (isThumb2) { 5170 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass); 5171 MRI.constrainRegClass(oldval, ARM::rGPRRegisterClass); 5172 MRI.constrainRegClass(newval, ARM::rGPRRegisterClass); 5173 } 5174 5175 unsigned ldrOpc, strOpc; 5176 switch (Size) { 5177 default: llvm_unreachable("unsupported size for AtomicCmpSwap!"); 5178 case 1: 5179 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB; 5180 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB; 5181 break; 5182 case 2: 5183 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH; 5184 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH; 5185 break; 5186 case 4: 5187 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX; 5188 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX; 5189 break; 5190 } 5191 5192 MachineFunction *MF = BB->getParent(); 5193 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5194 MachineFunction::iterator It = BB; 5195 ++It; // insert the new blocks after the current block 5196 5197 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 5198 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 5199 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5200 MF->insert(It, loop1MBB); 5201 MF->insert(It, loop2MBB); 5202 MF->insert(It, exitMBB); 5203 5204 // Transfer the remainder of BB and its successor edges to exitMBB. 5205 exitMBB->splice(exitMBB->begin(), BB, 5206 llvm::next(MachineBasicBlock::iterator(MI)), 5207 BB->end()); 5208 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5209 5210 // thisMBB: 5211 // ... 5212 // fallthrough --> loop1MBB 5213 BB->addSuccessor(loop1MBB); 5214 5215 // loop1MBB: 5216 // ldrex dest, [ptr] 5217 // cmp dest, oldval 5218 // bne exitMBB 5219 BB = loop1MBB; 5220 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); 5221 if (ldrOpc == ARM::t2LDREX) 5222 MIB.addImm(0); 5223 AddDefaultPred(MIB); 5224 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 5225 .addReg(dest).addReg(oldval)); 5226 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5227 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5228 BB->addSuccessor(loop2MBB); 5229 BB->addSuccessor(exitMBB); 5230 5231 // loop2MBB: 5232 // strex scratch, newval, [ptr] 5233 // cmp scratch, #0 5234 // bne loop1MBB 5235 BB = loop2MBB; 5236 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval).addReg(ptr); 5237 if (strOpc == ARM::t2STREX) 5238 MIB.addImm(0); 5239 AddDefaultPred(MIB); 5240 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5241 .addReg(scratch).addImm(0)); 5242 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5243 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5244 BB->addSuccessor(loop1MBB); 5245 BB->addSuccessor(exitMBB); 5246 5247 // exitMBB: 5248 // ... 5249 BB = exitMBB; 5250 5251 MI->eraseFromParent(); // The instruction is gone now. 5252 5253 return BB; 5254} 5255 5256MachineBasicBlock * 5257ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 5258 unsigned Size, unsigned BinOpcode) const { 5259 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 5260 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5261 5262 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5263 MachineFunction *MF = BB->getParent(); 5264 MachineFunction::iterator It = BB; 5265 ++It; 5266 5267 unsigned dest = MI->getOperand(0).getReg(); 5268 unsigned ptr = MI->getOperand(1).getReg(); 5269 unsigned incr = MI->getOperand(2).getReg(); 5270 DebugLoc dl = MI->getDebugLoc(); 5271 bool isThumb2 = Subtarget->isThumb2(); 5272 5273 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 5274 if (isThumb2) { 5275 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass); 5276 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass); 5277 } 5278 5279 unsigned ldrOpc, strOpc; 5280 switch (Size) { 5281 default: llvm_unreachable("unsupported size for AtomicCmpSwap!"); 5282 case 1: 5283 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB; 5284 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB; 5285 break; 5286 case 2: 5287 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH; 5288 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH; 5289 break; 5290 case 4: 5291 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX; 5292 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX; 5293 break; 5294 } 5295 5296 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5297 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5298 MF->insert(It, loopMBB); 5299 MF->insert(It, exitMBB); 5300 5301 // Transfer the remainder of BB and its successor edges to exitMBB. 5302 exitMBB->splice(exitMBB->begin(), BB, 5303 llvm::next(MachineBasicBlock::iterator(MI)), 5304 BB->end()); 5305 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5306 5307 const TargetRegisterClass *TRC = 5308 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; 5309 unsigned scratch = MRI.createVirtualRegister(TRC); 5310 unsigned scratch2 = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC); 5311 5312 // thisMBB: 5313 // ... 5314 // fallthrough --> loopMBB 5315 BB->addSuccessor(loopMBB); 5316 5317 // loopMBB: 5318 // ldrex dest, ptr 5319 // <binop> scratch2, dest, incr 5320 // strex scratch, scratch2, ptr 5321 // cmp scratch, #0 5322 // bne- loopMBB 5323 // fallthrough --> exitMBB 5324 BB = loopMBB; 5325 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); 5326 if (ldrOpc == ARM::t2LDREX) 5327 MIB.addImm(0); 5328 AddDefaultPred(MIB); 5329 if (BinOpcode) { 5330 // operand order needs to go the other way for NAND 5331 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr) 5332 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2). 5333 addReg(incr).addReg(dest)).addReg(0); 5334 else 5335 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2). 5336 addReg(dest).addReg(incr)).addReg(0); 5337 } 5338 5339 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr); 5340 if (strOpc == ARM::t2STREX) 5341 MIB.addImm(0); 5342 AddDefaultPred(MIB); 5343 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5344 .addReg(scratch).addImm(0)); 5345 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5346 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5347 5348 BB->addSuccessor(loopMBB); 5349 BB->addSuccessor(exitMBB); 5350 5351 // exitMBB: 5352 // ... 5353 BB = exitMBB; 5354 5355 MI->eraseFromParent(); // The instruction is gone now. 5356 5357 return BB; 5358} 5359 5360MachineBasicBlock * 5361ARMTargetLowering::EmitAtomicBinaryMinMax(MachineInstr *MI, 5362 MachineBasicBlock *BB, 5363 unsigned Size, 5364 bool signExtend, 5365 ARMCC::CondCodes Cond) const { 5366 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5367 5368 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5369 MachineFunction *MF = BB->getParent(); 5370 MachineFunction::iterator It = BB; 5371 ++It; 5372 5373 unsigned dest = MI->getOperand(0).getReg(); 5374 unsigned ptr = MI->getOperand(1).getReg(); 5375 unsigned incr = MI->getOperand(2).getReg(); 5376 unsigned oldval = dest; 5377 DebugLoc dl = MI->getDebugLoc(); 5378 bool isThumb2 = Subtarget->isThumb2(); 5379 5380 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 5381 if (isThumb2) { 5382 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass); 5383 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass); 5384 } 5385 5386 unsigned ldrOpc, strOpc, extendOpc; 5387 switch (Size) { 5388 default: llvm_unreachable("unsupported size for AtomicCmpSwap!"); 5389 case 1: 5390 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB; 5391 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB; 5392 extendOpc = isThumb2 ? ARM::t2SXTB : ARM::SXTB; 5393 break; 5394 case 2: 5395 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH; 5396 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH; 5397 extendOpc = isThumb2 ? ARM::t2SXTH : ARM::SXTH; 5398 break; 5399 case 4: 5400 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX; 5401 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX; 5402 extendOpc = 0; 5403 break; 5404 } 5405 5406 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5407 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5408 MF->insert(It, loopMBB); 5409 MF->insert(It, exitMBB); 5410 5411 // Transfer the remainder of BB and its successor edges to exitMBB. 5412 exitMBB->splice(exitMBB->begin(), BB, 5413 llvm::next(MachineBasicBlock::iterator(MI)), 5414 BB->end()); 5415 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5416 5417 const TargetRegisterClass *TRC = 5418 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; 5419 unsigned scratch = MRI.createVirtualRegister(TRC); 5420 unsigned scratch2 = MRI.createVirtualRegister(TRC); 5421 5422 // thisMBB: 5423 // ... 5424 // fallthrough --> loopMBB 5425 BB->addSuccessor(loopMBB); 5426 5427 // loopMBB: 5428 // ldrex dest, ptr 5429 // (sign extend dest, if required) 5430 // cmp dest, incr 5431 // cmov.cond scratch2, dest, incr 5432 // strex scratch, scratch2, ptr 5433 // cmp scratch, #0 5434 // bne- loopMBB 5435 // fallthrough --> exitMBB 5436 BB = loopMBB; 5437 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); 5438 if (ldrOpc == ARM::t2LDREX) 5439 MIB.addImm(0); 5440 AddDefaultPred(MIB); 5441 5442 // Sign extend the value, if necessary. 5443 if (signExtend && extendOpc) { 5444 oldval = MRI.createVirtualRegister(ARM::GPRRegisterClass); 5445 AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval) 5446 .addReg(dest) 5447 .addImm(0)); 5448 } 5449 5450 // Build compare and cmov instructions. 5451 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 5452 .addReg(oldval).addReg(incr)); 5453 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr), scratch2) 5454 .addReg(oldval).addReg(incr).addImm(Cond).addReg(ARM::CPSR); 5455 5456 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr); 5457 if (strOpc == ARM::t2STREX) 5458 MIB.addImm(0); 5459 AddDefaultPred(MIB); 5460 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5461 .addReg(scratch).addImm(0)); 5462 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5463 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5464 5465 BB->addSuccessor(loopMBB); 5466 BB->addSuccessor(exitMBB); 5467 5468 // exitMBB: 5469 // ... 5470 BB = exitMBB; 5471 5472 MI->eraseFromParent(); // The instruction is gone now. 5473 5474 return BB; 5475} 5476 5477MachineBasicBlock * 5478ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB, 5479 unsigned Op1, unsigned Op2, 5480 bool NeedsCarry, bool IsCmpxchg) const { 5481 // This also handles ATOMIC_SWAP, indicated by Op1==0. 5482 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5483 5484 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5485 MachineFunction *MF = BB->getParent(); 5486 MachineFunction::iterator It = BB; 5487 ++It; 5488 5489 unsigned destlo = MI->getOperand(0).getReg(); 5490 unsigned desthi = MI->getOperand(1).getReg(); 5491 unsigned ptr = MI->getOperand(2).getReg(); 5492 unsigned vallo = MI->getOperand(3).getReg(); 5493 unsigned valhi = MI->getOperand(4).getReg(); 5494 DebugLoc dl = MI->getDebugLoc(); 5495 bool isThumb2 = Subtarget->isThumb2(); 5496 5497 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 5498 if (isThumb2) { 5499 MRI.constrainRegClass(destlo, ARM::rGPRRegisterClass); 5500 MRI.constrainRegClass(desthi, ARM::rGPRRegisterClass); 5501 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass); 5502 } 5503 5504 unsigned ldrOpc = isThumb2 ? ARM::t2LDREXD : ARM::LDREXD; 5505 unsigned strOpc = isThumb2 ? ARM::t2STREXD : ARM::STREXD; 5506 5507 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5508 MachineBasicBlock *contBB = 0, *cont2BB = 0; 5509 if (IsCmpxchg) { 5510 contBB = MF->CreateMachineBasicBlock(LLVM_BB); 5511 cont2BB = MF->CreateMachineBasicBlock(LLVM_BB); 5512 } 5513 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5514 MF->insert(It, loopMBB); 5515 if (IsCmpxchg) { 5516 MF->insert(It, contBB); 5517 MF->insert(It, cont2BB); 5518 } 5519 MF->insert(It, exitMBB); 5520 5521 // Transfer the remainder of BB and its successor edges to exitMBB. 5522 exitMBB->splice(exitMBB->begin(), BB, 5523 llvm::next(MachineBasicBlock::iterator(MI)), 5524 BB->end()); 5525 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5526 5527 const TargetRegisterClass *TRC = 5528 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; 5529 unsigned storesuccess = MRI.createVirtualRegister(TRC); 5530 5531 // thisMBB: 5532 // ... 5533 // fallthrough --> loopMBB 5534 BB->addSuccessor(loopMBB); 5535 5536 // loopMBB: 5537 // ldrexd r2, r3, ptr 5538 // <binopa> r0, r2, incr 5539 // <binopb> r1, r3, incr 5540 // strexd storesuccess, r0, r1, ptr 5541 // cmp storesuccess, #0 5542 // bne- loopMBB 5543 // fallthrough --> exitMBB 5544 // 5545 // Note that the registers are explicitly specified because there is not any 5546 // way to force the register allocator to allocate a register pair. 5547 // 5548 // FIXME: The hardcoded registers are not necessary for Thumb2, but we 5549 // need to properly enforce the restriction that the two output registers 5550 // for ldrexd must be different. 5551 BB = loopMBB; 5552 // Load 5553 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc)) 5554 .addReg(ARM::R2, RegState::Define) 5555 .addReg(ARM::R3, RegState::Define).addReg(ptr)); 5556 // Copy r2/r3 into dest. (This copy will normally be coalesced.) 5557 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), destlo).addReg(ARM::R2); 5558 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), desthi).addReg(ARM::R3); 5559 5560 if (IsCmpxchg) { 5561 // Add early exit 5562 for (unsigned i = 0; i < 2; i++) { 5563 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : 5564 ARM::CMPrr)) 5565 .addReg(i == 0 ? destlo : desthi) 5566 .addReg(i == 0 ? vallo : valhi)); 5567 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5568 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5569 BB->addSuccessor(exitMBB); 5570 BB->addSuccessor(i == 0 ? contBB : cont2BB); 5571 BB = (i == 0 ? contBB : cont2BB); 5572 } 5573 5574 // Copy to physregs for strexd 5575 unsigned setlo = MI->getOperand(5).getReg(); 5576 unsigned sethi = MI->getOperand(6).getReg(); 5577 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(setlo); 5578 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(sethi); 5579 } else if (Op1) { 5580 // Perform binary operation 5581 AddDefaultPred(BuildMI(BB, dl, TII->get(Op1), ARM::R0) 5582 .addReg(destlo).addReg(vallo)) 5583 .addReg(NeedsCarry ? ARM::CPSR : 0, getDefRegState(NeedsCarry)); 5584 AddDefaultPred(BuildMI(BB, dl, TII->get(Op2), ARM::R1) 5585 .addReg(desthi).addReg(valhi)).addReg(0); 5586 } else { 5587 // Copy to physregs for strexd 5588 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(vallo); 5589 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(valhi); 5590 } 5591 5592 // Store 5593 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), storesuccess) 5594 .addReg(ARM::R0).addReg(ARM::R1).addReg(ptr)); 5595 // Cmp+jump 5596 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5597 .addReg(storesuccess).addImm(0)); 5598 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5599 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5600 5601 BB->addSuccessor(loopMBB); 5602 BB->addSuccessor(exitMBB); 5603 5604 // exitMBB: 5605 // ... 5606 BB = exitMBB; 5607 5608 MI->eraseFromParent(); // The instruction is gone now. 5609 5610 return BB; 5611} 5612 5613/// SetupEntryBlockForSjLj - Insert code into the entry block that creates and 5614/// registers the function context. 5615void ARMTargetLowering:: 5616SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB, 5617 MachineBasicBlock *DispatchBB, int FI) const { 5618 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5619 DebugLoc dl = MI->getDebugLoc(); 5620 MachineFunction *MF = MBB->getParent(); 5621 MachineRegisterInfo *MRI = &MF->getRegInfo(); 5622 MachineConstantPool *MCP = MF->getConstantPool(); 5623 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>(); 5624 const Function *F = MF->getFunction(); 5625 5626 bool isThumb = Subtarget->isThumb(); 5627 bool isThumb2 = Subtarget->isThumb2(); 5628 5629 unsigned PCLabelId = AFI->createPICLabelUId(); 5630 unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8; 5631 ARMConstantPoolValue *CPV = 5632 ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj); 5633 unsigned CPI = MCP->getConstantPoolIndex(CPV, 4); 5634 5635 const TargetRegisterClass *TRC = 5636 isThumb ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; 5637 5638 // Grab constant pool and fixed stack memory operands. 5639 MachineMemOperand *CPMMO = 5640 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(), 5641 MachineMemOperand::MOLoad, 4, 4); 5642 5643 MachineMemOperand *FIMMOSt = 5644 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 5645 MachineMemOperand::MOStore, 4, 4); 5646 5647 // Load the address of the dispatch MBB into the jump buffer. 5648 if (isThumb2) { 5649 // Incoming value: jbuf 5650 // ldr.n r5, LCPI1_1 5651 // orr r5, r5, #1 5652 // add r5, pc 5653 // str r5, [$jbuf, #+4] ; &jbuf[1] 5654 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5655 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1) 5656 .addConstantPoolIndex(CPI) 5657 .addMemOperand(CPMMO)); 5658 // Set the low bit because of thumb mode. 5659 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5660 AddDefaultCC( 5661 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2) 5662 .addReg(NewVReg1, RegState::Kill) 5663 .addImm(0x01))); 5664 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 5665 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3) 5666 .addReg(NewVReg2, RegState::Kill) 5667 .addImm(PCLabelId); 5668 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12)) 5669 .addReg(NewVReg3, RegState::Kill) 5670 .addFrameIndex(FI) 5671 .addImm(36) // &jbuf[1] :: pc 5672 .addMemOperand(FIMMOSt)); 5673 } else if (isThumb) { 5674 // Incoming value: jbuf 5675 // ldr.n r1, LCPI1_4 5676 // add r1, pc 5677 // mov r2, #1 5678 // orrs r1, r2 5679 // add r2, $jbuf, #+4 ; &jbuf[1] 5680 // str r1, [r2] 5681 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5682 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1) 5683 .addConstantPoolIndex(CPI) 5684 .addMemOperand(CPMMO)); 5685 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5686 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2) 5687 .addReg(NewVReg1, RegState::Kill) 5688 .addImm(PCLabelId); 5689 // Set the low bit because of thumb mode. 5690 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 5691 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3) 5692 .addReg(ARM::CPSR, RegState::Define) 5693 .addImm(1)); 5694 unsigned NewVReg4 = MRI->createVirtualRegister(TRC); 5695 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4) 5696 .addReg(ARM::CPSR, RegState::Define) 5697 .addReg(NewVReg2, RegState::Kill) 5698 .addReg(NewVReg3, RegState::Kill)); 5699 unsigned NewVReg5 = MRI->createVirtualRegister(TRC); 5700 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tADDrSPi), NewVReg5) 5701 .addFrameIndex(FI) 5702 .addImm(36)); // &jbuf[1] :: pc 5703 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi)) 5704 .addReg(NewVReg4, RegState::Kill) 5705 .addReg(NewVReg5, RegState::Kill) 5706 .addImm(0) 5707 .addMemOperand(FIMMOSt)); 5708 } else { 5709 // Incoming value: jbuf 5710 // ldr r1, LCPI1_1 5711 // add r1, pc, r1 5712 // str r1, [$jbuf, #+4] ; &jbuf[1] 5713 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5714 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1) 5715 .addConstantPoolIndex(CPI) 5716 .addImm(0) 5717 .addMemOperand(CPMMO)); 5718 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5719 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2) 5720 .addReg(NewVReg1, RegState::Kill) 5721 .addImm(PCLabelId)); 5722 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12)) 5723 .addReg(NewVReg2, RegState::Kill) 5724 .addFrameIndex(FI) 5725 .addImm(36) // &jbuf[1] :: pc 5726 .addMemOperand(FIMMOSt)); 5727 } 5728} 5729 5730MachineBasicBlock *ARMTargetLowering:: 5731EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const { 5732 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5733 DebugLoc dl = MI->getDebugLoc(); 5734 MachineFunction *MF = MBB->getParent(); 5735 MachineRegisterInfo *MRI = &MF->getRegInfo(); 5736 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>(); 5737 MachineFrameInfo *MFI = MF->getFrameInfo(); 5738 int FI = MFI->getFunctionContextIndex(); 5739 5740 const TargetRegisterClass *TRC = 5741 Subtarget->isThumb() ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; 5742 5743 // Get a mapping of the call site numbers to all of the landing pads they're 5744 // associated with. 5745 DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2> > CallSiteNumToLPad; 5746 unsigned MaxCSNum = 0; 5747 MachineModuleInfo &MMI = MF->getMMI(); 5748 for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E; ++BB) { 5749 if (!BB->isLandingPad()) continue; 5750 5751 // FIXME: We should assert that the EH_LABEL is the first MI in the landing 5752 // pad. 5753 for (MachineBasicBlock::iterator 5754 II = BB->begin(), IE = BB->end(); II != IE; ++II) { 5755 if (!II->isEHLabel()) continue; 5756 5757 MCSymbol *Sym = II->getOperand(0).getMCSymbol(); 5758 if (!MMI.hasCallSiteLandingPad(Sym)) continue; 5759 5760 SmallVectorImpl<unsigned> &CallSiteIdxs = MMI.getCallSiteLandingPad(Sym); 5761 for (SmallVectorImpl<unsigned>::iterator 5762 CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end(); 5763 CSI != CSE; ++CSI) { 5764 CallSiteNumToLPad[*CSI].push_back(BB); 5765 MaxCSNum = std::max(MaxCSNum, *CSI); 5766 } 5767 break; 5768 } 5769 } 5770 5771 // Get an ordered list of the machine basic blocks for the jump table. 5772 std::vector<MachineBasicBlock*> LPadList; 5773 SmallPtrSet<MachineBasicBlock*, 64> InvokeBBs; 5774 LPadList.reserve(CallSiteNumToLPad.size()); 5775 for (unsigned I = 1; I <= MaxCSNum; ++I) { 5776 SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I]; 5777 for (SmallVectorImpl<MachineBasicBlock*>::iterator 5778 II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) { 5779 LPadList.push_back(*II); 5780 InvokeBBs.insert((*II)->pred_begin(), (*II)->pred_end()); 5781 } 5782 } 5783 5784 assert(!LPadList.empty() && 5785 "No landing pad destinations for the dispatch jump table!"); 5786 5787 // Create the jump table and associated information. 5788 MachineJumpTableInfo *JTI = 5789 MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline); 5790 unsigned MJTI = JTI->createJumpTableIndex(LPadList); 5791 unsigned UId = AFI->createJumpTableUId(); 5792 5793 // Create the MBBs for the dispatch code. 5794 5795 // Shove the dispatch's address into the return slot in the function context. 5796 MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock(); 5797 DispatchBB->setIsLandingPad(); 5798 5799 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock(); 5800 BuildMI(TrapBB, dl, TII->get(Subtarget->isThumb() ? ARM::tTRAP : ARM::TRAP)); 5801 DispatchBB->addSuccessor(TrapBB); 5802 5803 MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock(); 5804 DispatchBB->addSuccessor(DispContBB); 5805 5806 // Insert and MBBs. 5807 MF->insert(MF->end(), DispatchBB); 5808 MF->insert(MF->end(), DispContBB); 5809 MF->insert(MF->end(), TrapBB); 5810 5811 // Insert code into the entry block that creates and registers the function 5812 // context. 5813 SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI); 5814 5815 MachineMemOperand *FIMMOLd = 5816 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 5817 MachineMemOperand::MOLoad | 5818 MachineMemOperand::MOVolatile, 4, 4); 5819 5820 if (AFI->isThumb1OnlyFunction()) 5821 BuildMI(DispatchBB, dl, TII->get(ARM::tInt_eh_sjlj_dispatchsetup)); 5822 else if (!Subtarget->hasVFP2()) 5823 BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup_nofp)); 5824 else 5825 BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup)); 5826 5827 unsigned NumLPads = LPadList.size(); 5828 if (Subtarget->isThumb2()) { 5829 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5830 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1) 5831 .addFrameIndex(FI) 5832 .addImm(4) 5833 .addMemOperand(FIMMOLd)); 5834 5835 if (NumLPads < 256) { 5836 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri)) 5837 .addReg(NewVReg1) 5838 .addImm(LPadList.size())); 5839 } else { 5840 unsigned VReg1 = MRI->createVirtualRegister(TRC); 5841 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1) 5842 .addImm(NumLPads & 0xFFFF)); 5843 5844 unsigned VReg2 = VReg1; 5845 if ((NumLPads & 0xFFFF0000) != 0) { 5846 VReg2 = MRI->createVirtualRegister(TRC); 5847 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2) 5848 .addReg(VReg1) 5849 .addImm(NumLPads >> 16)); 5850 } 5851 5852 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr)) 5853 .addReg(NewVReg1) 5854 .addReg(VReg2)); 5855 } 5856 5857 BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc)) 5858 .addMBB(TrapBB) 5859 .addImm(ARMCC::HI) 5860 .addReg(ARM::CPSR); 5861 5862 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 5863 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg3) 5864 .addJumpTableIndex(MJTI) 5865 .addImm(UId)); 5866 5867 unsigned NewVReg4 = MRI->createVirtualRegister(TRC); 5868 AddDefaultCC( 5869 AddDefaultPred( 5870 BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4) 5871 .addReg(NewVReg3, RegState::Kill) 5872 .addReg(NewVReg1) 5873 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2)))); 5874 5875 BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT)) 5876 .addReg(NewVReg4, RegState::Kill) 5877 .addReg(NewVReg1) 5878 .addJumpTableIndex(MJTI) 5879 .addImm(UId); 5880 } else if (Subtarget->isThumb()) { 5881 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5882 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1) 5883 .addFrameIndex(FI) 5884 .addImm(1) 5885 .addMemOperand(FIMMOLd)); 5886 5887 if (NumLPads < 256) { 5888 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8)) 5889 .addReg(NewVReg1) 5890 .addImm(NumLPads)); 5891 } else { 5892 MachineConstantPool *ConstantPool = MF->getConstantPool(); 5893 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext()); 5894 const Constant *C = ConstantInt::get(Int32Ty, NumLPads); 5895 5896 // MachineConstantPool wants an explicit alignment. 5897 unsigned Align = getTargetData()->getPrefTypeAlignment(Int32Ty); 5898 if (Align == 0) 5899 Align = getTargetData()->getTypeAllocSize(C->getType()); 5900 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align); 5901 5902 unsigned VReg1 = MRI->createVirtualRegister(TRC); 5903 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci)) 5904 .addReg(VReg1, RegState::Define) 5905 .addConstantPoolIndex(Idx)); 5906 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPr)) 5907 .addReg(NewVReg1) 5908 .addReg(VReg1)); 5909 } 5910 5911 BuildMI(DispatchBB, dl, TII->get(ARM::tBcc)) 5912 .addMBB(TrapBB) 5913 .addImm(ARMCC::HI) 5914 .addReg(ARM::CPSR); 5915 5916 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5917 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2) 5918 .addReg(ARM::CPSR, RegState::Define) 5919 .addReg(NewVReg1) 5920 .addImm(2)); 5921 5922 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 5923 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3) 5924 .addJumpTableIndex(MJTI) 5925 .addImm(UId)); 5926 5927 unsigned NewVReg4 = MRI->createVirtualRegister(TRC); 5928 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4) 5929 .addReg(ARM::CPSR, RegState::Define) 5930 .addReg(NewVReg2, RegState::Kill) 5931 .addReg(NewVReg3)); 5932 5933 MachineMemOperand *JTMMOLd = 5934 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(), 5935 MachineMemOperand::MOLoad, 4, 4); 5936 5937 unsigned NewVReg5 = MRI->createVirtualRegister(TRC); 5938 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5) 5939 .addReg(NewVReg4, RegState::Kill) 5940 .addImm(0) 5941 .addMemOperand(JTMMOLd)); 5942 5943 unsigned NewVReg6 = MRI->createVirtualRegister(TRC); 5944 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6) 5945 .addReg(ARM::CPSR, RegState::Define) 5946 .addReg(NewVReg5, RegState::Kill) 5947 .addReg(NewVReg3)); 5948 5949 BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr)) 5950 .addReg(NewVReg6, RegState::Kill) 5951 .addJumpTableIndex(MJTI) 5952 .addImm(UId); 5953 } else { 5954 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5955 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1) 5956 .addFrameIndex(FI) 5957 .addImm(4) 5958 .addMemOperand(FIMMOLd)); 5959 5960 if (NumLPads < 256) { 5961 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri)) 5962 .addReg(NewVReg1) 5963 .addImm(NumLPads)); 5964 } else if (Subtarget->hasV6T2Ops() && isUInt<16>(NumLPads)) { 5965 unsigned VReg1 = MRI->createVirtualRegister(TRC); 5966 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1) 5967 .addImm(NumLPads & 0xFFFF)); 5968 5969 unsigned VReg2 = VReg1; 5970 if ((NumLPads & 0xFFFF0000) != 0) { 5971 VReg2 = MRI->createVirtualRegister(TRC); 5972 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2) 5973 .addReg(VReg1) 5974 .addImm(NumLPads >> 16)); 5975 } 5976 5977 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr)) 5978 .addReg(NewVReg1) 5979 .addReg(VReg2)); 5980 } else { 5981 MachineConstantPool *ConstantPool = MF->getConstantPool(); 5982 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext()); 5983 const Constant *C = ConstantInt::get(Int32Ty, NumLPads); 5984 5985 // MachineConstantPool wants an explicit alignment. 5986 unsigned Align = getTargetData()->getPrefTypeAlignment(Int32Ty); 5987 if (Align == 0) 5988 Align = getTargetData()->getTypeAllocSize(C->getType()); 5989 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align); 5990 5991 unsigned VReg1 = MRI->createVirtualRegister(TRC); 5992 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp)) 5993 .addReg(VReg1, RegState::Define) 5994 .addConstantPoolIndex(Idx) 5995 .addImm(0)); 5996 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr)) 5997 .addReg(NewVReg1) 5998 .addReg(VReg1, RegState::Kill)); 5999 } 6000 6001 BuildMI(DispatchBB, dl, TII->get(ARM::Bcc)) 6002 .addMBB(TrapBB) 6003 .addImm(ARMCC::HI) 6004 .addReg(ARM::CPSR); 6005 6006 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 6007 AddDefaultCC( 6008 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3) 6009 .addReg(NewVReg1) 6010 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2)))); 6011 unsigned NewVReg4 = MRI->createVirtualRegister(TRC); 6012 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4) 6013 .addJumpTableIndex(MJTI) 6014 .addImm(UId)); 6015 6016 MachineMemOperand *JTMMOLd = 6017 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(), 6018 MachineMemOperand::MOLoad, 4, 4); 6019 unsigned NewVReg5 = MRI->createVirtualRegister(TRC); 6020 AddDefaultPred( 6021 BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg5) 6022 .addReg(NewVReg3, RegState::Kill) 6023 .addReg(NewVReg4) 6024 .addImm(0) 6025 .addMemOperand(JTMMOLd)); 6026 6027 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd)) 6028 .addReg(NewVReg5, RegState::Kill) 6029 .addReg(NewVReg4) 6030 .addJumpTableIndex(MJTI) 6031 .addImm(UId); 6032 } 6033 6034 // Add the jump table entries as successors to the MBB. 6035 MachineBasicBlock *PrevMBB = 0; 6036 for (std::vector<MachineBasicBlock*>::iterator 6037 I = LPadList.begin(), E = LPadList.end(); I != E; ++I) { 6038 MachineBasicBlock *CurMBB = *I; 6039 if (PrevMBB != CurMBB) 6040 DispContBB->addSuccessor(CurMBB); 6041 PrevMBB = CurMBB; 6042 } 6043 6044 // N.B. the order the invoke BBs are processed in doesn't matter here. 6045 const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII); 6046 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo(); 6047 const unsigned *SavedRegs = RI.getCalleeSavedRegs(MF); 6048 SmallVector<MachineBasicBlock*, 64> MBBLPads; 6049 for (SmallPtrSet<MachineBasicBlock*, 64>::iterator 6050 I = InvokeBBs.begin(), E = InvokeBBs.end(); I != E; ++I) { 6051 MachineBasicBlock *BB = *I; 6052 6053 // Remove the landing pad successor from the invoke block and replace it 6054 // with the new dispatch block. 6055 SmallVector<MachineBasicBlock*, 4> Successors(BB->succ_begin(), 6056 BB->succ_end()); 6057 while (!Successors.empty()) { 6058 MachineBasicBlock *SMBB = Successors.pop_back_val(); 6059 if (SMBB->isLandingPad()) { 6060 BB->removeSuccessor(SMBB); 6061 MBBLPads.push_back(SMBB); 6062 } 6063 } 6064 6065 BB->addSuccessor(DispatchBB); 6066 6067 // Find the invoke call and mark all of the callee-saved registers as 6068 // 'implicit defined' so that they're spilled. This prevents code from 6069 // moving instructions to before the EH block, where they will never be 6070 // executed. 6071 for (MachineBasicBlock::reverse_iterator 6072 II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) { 6073 if (!II->isCall()) continue; 6074 6075 DenseMap<unsigned, bool> DefRegs; 6076 for (MachineInstr::mop_iterator 6077 OI = II->operands_begin(), OE = II->operands_end(); 6078 OI != OE; ++OI) { 6079 if (!OI->isReg()) continue; 6080 DefRegs[OI->getReg()] = true; 6081 } 6082 6083 MachineInstrBuilder MIB(&*II); 6084 6085 for (unsigned i = 0; SavedRegs[i] != 0; ++i) { 6086 unsigned Reg = SavedRegs[i]; 6087 if (Subtarget->isThumb2() && 6088 !ARM::tGPRRegisterClass->contains(Reg) && 6089 !ARM::hGPRRegisterClass->contains(Reg)) 6090 continue; 6091 else if (Subtarget->isThumb1Only() && 6092 !ARM::tGPRRegisterClass->contains(Reg)) 6093 continue; 6094 else if (!Subtarget->isThumb() && 6095 !ARM::GPRRegisterClass->contains(Reg)) 6096 continue; 6097 if (!DefRegs[Reg]) 6098 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead); 6099 } 6100 6101 break; 6102 } 6103 } 6104 6105 // Mark all former landing pads as non-landing pads. The dispatch is the only 6106 // landing pad now. 6107 for (SmallVectorImpl<MachineBasicBlock*>::iterator 6108 I = MBBLPads.begin(), E = MBBLPads.end(); I != E; ++I) 6109 (*I)->setIsLandingPad(false); 6110 6111 // The instruction is gone now. 6112 MI->eraseFromParent(); 6113 6114 return MBB; 6115} 6116 6117static 6118MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) { 6119 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(), 6120 E = MBB->succ_end(); I != E; ++I) 6121 if (*I != Succ) 6122 return *I; 6123 llvm_unreachable("Expecting a BB with two successors!"); 6124} 6125 6126MachineBasicBlock * 6127ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 6128 MachineBasicBlock *BB) const { 6129 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 6130 DebugLoc dl = MI->getDebugLoc(); 6131 bool isThumb2 = Subtarget->isThumb2(); 6132 switch (MI->getOpcode()) { 6133 default: { 6134 MI->dump(); 6135 llvm_unreachable("Unexpected instr type to insert"); 6136 } 6137 // The Thumb2 pre-indexed stores have the same MI operands, they just 6138 // define them differently in the .td files from the isel patterns, so 6139 // they need pseudos. 6140 case ARM::t2STR_preidx: 6141 MI->setDesc(TII->get(ARM::t2STR_PRE)); 6142 return BB; 6143 case ARM::t2STRB_preidx: 6144 MI->setDesc(TII->get(ARM::t2STRB_PRE)); 6145 return BB; 6146 case ARM::t2STRH_preidx: 6147 MI->setDesc(TII->get(ARM::t2STRH_PRE)); 6148 return BB; 6149 6150 case ARM::STRi_preidx: 6151 case ARM::STRBi_preidx: { 6152 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ? 6153 ARM::STR_PRE_IMM : ARM::STRB_PRE_IMM; 6154 // Decode the offset. 6155 unsigned Offset = MI->getOperand(4).getImm(); 6156 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub; 6157 Offset = ARM_AM::getAM2Offset(Offset); 6158 if (isSub) 6159 Offset = -Offset; 6160 6161 MachineMemOperand *MMO = *MI->memoperands_begin(); 6162 BuildMI(*BB, MI, dl, TII->get(NewOpc)) 6163 .addOperand(MI->getOperand(0)) // Rn_wb 6164 .addOperand(MI->getOperand(1)) // Rt 6165 .addOperand(MI->getOperand(2)) // Rn 6166 .addImm(Offset) // offset (skip GPR==zero_reg) 6167 .addOperand(MI->getOperand(5)) // pred 6168 .addOperand(MI->getOperand(6)) 6169 .addMemOperand(MMO); 6170 MI->eraseFromParent(); 6171 return BB; 6172 } 6173 case ARM::STRr_preidx: 6174 case ARM::STRBr_preidx: 6175 case ARM::STRH_preidx: { 6176 unsigned NewOpc; 6177 switch (MI->getOpcode()) { 6178 default: llvm_unreachable("unexpected opcode!"); 6179 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break; 6180 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break; 6181 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break; 6182 } 6183 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc)); 6184 for (unsigned i = 0; i < MI->getNumOperands(); ++i) 6185 MIB.addOperand(MI->getOperand(i)); 6186 MI->eraseFromParent(); 6187 return BB; 6188 } 6189 case ARM::ATOMIC_LOAD_ADD_I8: 6190 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 6191 case ARM::ATOMIC_LOAD_ADD_I16: 6192 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 6193 case ARM::ATOMIC_LOAD_ADD_I32: 6194 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 6195 6196 case ARM::ATOMIC_LOAD_AND_I8: 6197 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 6198 case ARM::ATOMIC_LOAD_AND_I16: 6199 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 6200 case ARM::ATOMIC_LOAD_AND_I32: 6201 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 6202 6203 case ARM::ATOMIC_LOAD_OR_I8: 6204 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 6205 case ARM::ATOMIC_LOAD_OR_I16: 6206 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 6207 case ARM::ATOMIC_LOAD_OR_I32: 6208 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 6209 6210 case ARM::ATOMIC_LOAD_XOR_I8: 6211 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 6212 case ARM::ATOMIC_LOAD_XOR_I16: 6213 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 6214 case ARM::ATOMIC_LOAD_XOR_I32: 6215 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 6216 6217 case ARM::ATOMIC_LOAD_NAND_I8: 6218 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 6219 case ARM::ATOMIC_LOAD_NAND_I16: 6220 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 6221 case ARM::ATOMIC_LOAD_NAND_I32: 6222 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 6223 6224 case ARM::ATOMIC_LOAD_SUB_I8: 6225 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 6226 case ARM::ATOMIC_LOAD_SUB_I16: 6227 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 6228 case ARM::ATOMIC_LOAD_SUB_I32: 6229 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 6230 6231 case ARM::ATOMIC_LOAD_MIN_I8: 6232 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::LT); 6233 case ARM::ATOMIC_LOAD_MIN_I16: 6234 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::LT); 6235 case ARM::ATOMIC_LOAD_MIN_I32: 6236 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::LT); 6237 6238 case ARM::ATOMIC_LOAD_MAX_I8: 6239 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::GT); 6240 case ARM::ATOMIC_LOAD_MAX_I16: 6241 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::GT); 6242 case ARM::ATOMIC_LOAD_MAX_I32: 6243 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::GT); 6244 6245 case ARM::ATOMIC_LOAD_UMIN_I8: 6246 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::LO); 6247 case ARM::ATOMIC_LOAD_UMIN_I16: 6248 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::LO); 6249 case ARM::ATOMIC_LOAD_UMIN_I32: 6250 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::LO); 6251 6252 case ARM::ATOMIC_LOAD_UMAX_I8: 6253 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::HI); 6254 case ARM::ATOMIC_LOAD_UMAX_I16: 6255 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::HI); 6256 case ARM::ATOMIC_LOAD_UMAX_I32: 6257 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::HI); 6258 6259 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0); 6260 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0); 6261 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0); 6262 6263 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1); 6264 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2); 6265 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4); 6266 6267 6268 case ARM::ATOMADD6432: 6269 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr, 6270 isThumb2 ? ARM::t2ADCrr : ARM::ADCrr, 6271 /*NeedsCarry*/ true); 6272 case ARM::ATOMSUB6432: 6273 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr, 6274 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr, 6275 /*NeedsCarry*/ true); 6276 case ARM::ATOMOR6432: 6277 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr, 6278 isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 6279 case ARM::ATOMXOR6432: 6280 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2EORrr : ARM::EORrr, 6281 isThumb2 ? ARM::t2EORrr : ARM::EORrr); 6282 case ARM::ATOMAND6432: 6283 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr, 6284 isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 6285 case ARM::ATOMSWAP6432: 6286 return EmitAtomicBinary64(MI, BB, 0, 0, false); 6287 case ARM::ATOMCMPXCHG6432: 6288 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr, 6289 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr, 6290 /*NeedsCarry*/ false, /*IsCmpxchg*/true); 6291 6292 case ARM::tMOVCCr_pseudo: { 6293 // To "insert" a SELECT_CC instruction, we actually have to insert the 6294 // diamond control-flow pattern. The incoming instruction knows the 6295 // destination vreg to set, the condition code register to branch on, the 6296 // true/false values to select between, and a branch opcode to use. 6297 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 6298 MachineFunction::iterator It = BB; 6299 ++It; 6300 6301 // thisMBB: 6302 // ... 6303 // TrueVal = ... 6304 // cmpTY ccX, r1, r2 6305 // bCC copy1MBB 6306 // fallthrough --> copy0MBB 6307 MachineBasicBlock *thisMBB = BB; 6308 MachineFunction *F = BB->getParent(); 6309 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 6310 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 6311 F->insert(It, copy0MBB); 6312 F->insert(It, sinkMBB); 6313 6314 // Transfer the remainder of BB and its successor edges to sinkMBB. 6315 sinkMBB->splice(sinkMBB->begin(), BB, 6316 llvm::next(MachineBasicBlock::iterator(MI)), 6317 BB->end()); 6318 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 6319 6320 BB->addSuccessor(copy0MBB); 6321 BB->addSuccessor(sinkMBB); 6322 6323 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB) 6324 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg()); 6325 6326 // copy0MBB: 6327 // %FalseValue = ... 6328 // # fallthrough to sinkMBB 6329 BB = copy0MBB; 6330 6331 // Update machine-CFG edges 6332 BB->addSuccessor(sinkMBB); 6333 6334 // sinkMBB: 6335 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 6336 // ... 6337 BB = sinkMBB; 6338 BuildMI(*BB, BB->begin(), dl, 6339 TII->get(ARM::PHI), MI->getOperand(0).getReg()) 6340 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 6341 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 6342 6343 MI->eraseFromParent(); // The pseudo instruction is gone now. 6344 return BB; 6345 } 6346 6347 case ARM::BCCi64: 6348 case ARM::BCCZi64: { 6349 // If there is an unconditional branch to the other successor, remove it. 6350 BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 6351 6352 // Compare both parts that make up the double comparison separately for 6353 // equality. 6354 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64; 6355 6356 unsigned LHS1 = MI->getOperand(1).getReg(); 6357 unsigned LHS2 = MI->getOperand(2).getReg(); 6358 if (RHSisZero) { 6359 AddDefaultPred(BuildMI(BB, dl, 6360 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 6361 .addReg(LHS1).addImm(0)); 6362 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 6363 .addReg(LHS2).addImm(0) 6364 .addImm(ARMCC::EQ).addReg(ARM::CPSR); 6365 } else { 6366 unsigned RHS1 = MI->getOperand(3).getReg(); 6367 unsigned RHS2 = MI->getOperand(4).getReg(); 6368 AddDefaultPred(BuildMI(BB, dl, 6369 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 6370 .addReg(LHS1).addReg(RHS1)); 6371 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 6372 .addReg(LHS2).addReg(RHS2) 6373 .addImm(ARMCC::EQ).addReg(ARM::CPSR); 6374 } 6375 6376 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB(); 6377 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB); 6378 if (MI->getOperand(0).getImm() == ARMCC::NE) 6379 std::swap(destMBB, exitMBB); 6380 6381 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 6382 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR); 6383 if (isThumb2) 6384 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB)); 6385 else 6386 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB); 6387 6388 MI->eraseFromParent(); // The pseudo instruction is gone now. 6389 return BB; 6390 } 6391 6392 case ARM::Int_eh_sjlj_setjmp: 6393 case ARM::Int_eh_sjlj_setjmp_nofp: 6394 case ARM::tInt_eh_sjlj_setjmp: 6395 case ARM::t2Int_eh_sjlj_setjmp: 6396 case ARM::t2Int_eh_sjlj_setjmp_nofp: 6397 EmitSjLjDispatchBlock(MI, BB); 6398 return BB; 6399 6400 case ARM::ABS: 6401 case ARM::t2ABS: { 6402 // To insert an ABS instruction, we have to insert the 6403 // diamond control-flow pattern. The incoming instruction knows the 6404 // source vreg to test against 0, the destination vreg to set, 6405 // the condition code register to branch on, the 6406 // true/false values to select between, and a branch opcode to use. 6407 // It transforms 6408 // V1 = ABS V0 6409 // into 6410 // V2 = MOVS V0 6411 // BCC (branch to SinkBB if V0 >= 0) 6412 // RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0) 6413 // SinkBB: V1 = PHI(V2, V3) 6414 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 6415 MachineFunction::iterator BBI = BB; 6416 ++BBI; 6417 MachineFunction *Fn = BB->getParent(); 6418 MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB); 6419 MachineBasicBlock *SinkBB = Fn->CreateMachineBasicBlock(LLVM_BB); 6420 Fn->insert(BBI, RSBBB); 6421 Fn->insert(BBI, SinkBB); 6422 6423 unsigned int ABSSrcReg = MI->getOperand(1).getReg(); 6424 unsigned int ABSDstReg = MI->getOperand(0).getReg(); 6425 bool isThumb2 = Subtarget->isThumb2(); 6426 MachineRegisterInfo &MRI = Fn->getRegInfo(); 6427 // In Thumb mode S must not be specified if source register is the SP or 6428 // PC and if destination register is the SP, so restrict register class 6429 unsigned NewMovDstReg = MRI.createVirtualRegister( 6430 isThumb2 ? ARM::rGPRRegisterClass : ARM::GPRRegisterClass); 6431 unsigned NewRsbDstReg = MRI.createVirtualRegister( 6432 isThumb2 ? ARM::rGPRRegisterClass : ARM::GPRRegisterClass); 6433 6434 // Transfer the remainder of BB and its successor edges to sinkMBB. 6435 SinkBB->splice(SinkBB->begin(), BB, 6436 llvm::next(MachineBasicBlock::iterator(MI)), 6437 BB->end()); 6438 SinkBB->transferSuccessorsAndUpdatePHIs(BB); 6439 6440 BB->addSuccessor(RSBBB); 6441 BB->addSuccessor(SinkBB); 6442 6443 // fall through to SinkMBB 6444 RSBBB->addSuccessor(SinkBB); 6445 6446 // insert a movs at the end of BB 6447 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVr : ARM::MOVr), 6448 NewMovDstReg) 6449 .addReg(ABSSrcReg, RegState::Kill) 6450 .addImm((unsigned)ARMCC::AL).addReg(0) 6451 .addReg(ARM::CPSR, RegState::Define); 6452 6453 // insert a bcc with opposite CC to ARMCC::MI at the end of BB 6454 BuildMI(BB, dl, 6455 TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB) 6456 .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR); 6457 6458 // insert rsbri in RSBBB 6459 // Note: BCC and rsbri will be converted into predicated rsbmi 6460 // by if-conversion pass 6461 BuildMI(*RSBBB, RSBBB->begin(), dl, 6462 TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg) 6463 .addReg(NewMovDstReg, RegState::Kill) 6464 .addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 6465 6466 // insert PHI in SinkBB, 6467 // reuse ABSDstReg to not change uses of ABS instruction 6468 BuildMI(*SinkBB, SinkBB->begin(), dl, 6469 TII->get(ARM::PHI), ABSDstReg) 6470 .addReg(NewRsbDstReg).addMBB(RSBBB) 6471 .addReg(NewMovDstReg).addMBB(BB); 6472 6473 // remove ABS instruction 6474 MI->eraseFromParent(); 6475 6476 // return last added BB 6477 return SinkBB; 6478 } 6479 } 6480} 6481 6482void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, 6483 SDNode *Node) const { 6484 if (!MI->hasPostISelHook()) { 6485 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) && 6486 "Pseudo flag-setting opcodes must be marked with 'hasPostISelHook'"); 6487 return; 6488 } 6489 6490 const MCInstrDesc *MCID = &MI->getDesc(); 6491 // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB, 6492 // RSC. Coming out of isel, they have an implicit CPSR def, but the optional 6493 // operand is still set to noreg. If needed, set the optional operand's 6494 // register to CPSR, and remove the redundant implicit def. 6495 // 6496 // e.g. ADCS (..., CPSR<imp-def>) -> ADC (... opt:CPSR<def>). 6497 6498 // Rename pseudo opcodes. 6499 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode()); 6500 if (NewOpc) { 6501 const ARMBaseInstrInfo *TII = 6502 static_cast<const ARMBaseInstrInfo*>(getTargetMachine().getInstrInfo()); 6503 MCID = &TII->get(NewOpc); 6504 6505 assert(MCID->getNumOperands() == MI->getDesc().getNumOperands() + 1 && 6506 "converted opcode should be the same except for cc_out"); 6507 6508 MI->setDesc(*MCID); 6509 6510 // Add the optional cc_out operand 6511 MI->addOperand(MachineOperand::CreateReg(0, /*isDef=*/true)); 6512 } 6513 unsigned ccOutIdx = MCID->getNumOperands() - 1; 6514 6515 // Any ARM instruction that sets the 's' bit should specify an optional 6516 // "cc_out" operand in the last operand position. 6517 if (!MI->hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) { 6518 assert(!NewOpc && "Optional cc_out operand required"); 6519 return; 6520 } 6521 // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it 6522 // since we already have an optional CPSR def. 6523 bool definesCPSR = false; 6524 bool deadCPSR = false; 6525 for (unsigned i = MCID->getNumOperands(), e = MI->getNumOperands(); 6526 i != e; ++i) { 6527 const MachineOperand &MO = MI->getOperand(i); 6528 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) { 6529 definesCPSR = true; 6530 if (MO.isDead()) 6531 deadCPSR = true; 6532 MI->RemoveOperand(i); 6533 break; 6534 } 6535 } 6536 if (!definesCPSR) { 6537 assert(!NewOpc && "Optional cc_out operand required"); 6538 return; 6539 } 6540 assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag"); 6541 if (deadCPSR) { 6542 assert(!MI->getOperand(ccOutIdx).getReg() && 6543 "expect uninitialized optional cc_out operand"); 6544 return; 6545 } 6546 6547 // If this instruction was defined with an optional CPSR def and its dag node 6548 // had a live implicit CPSR def, then activate the optional CPSR def. 6549 MachineOperand &MO = MI->getOperand(ccOutIdx); 6550 MO.setReg(ARM::CPSR); 6551 MO.setIsDef(true); 6552} 6553 6554//===----------------------------------------------------------------------===// 6555// ARM Optimization Hooks 6556//===----------------------------------------------------------------------===// 6557 6558static 6559SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, 6560 TargetLowering::DAGCombinerInfo &DCI) { 6561 SelectionDAG &DAG = DCI.DAG; 6562 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6563 EVT VT = N->getValueType(0); 6564 unsigned Opc = N->getOpcode(); 6565 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 6566 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 6567 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 6568 ISD::CondCode CC = ISD::SETCC_INVALID; 6569 6570 if (isSlctCC) { 6571 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 6572 } else { 6573 SDValue CCOp = Slct.getOperand(0); 6574 if (CCOp.getOpcode() == ISD::SETCC) 6575 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 6576 } 6577 6578 bool DoXform = false; 6579 bool InvCC = false; 6580 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 6581 "Bad input!"); 6582 6583 if (LHS.getOpcode() == ISD::Constant && 6584 cast<ConstantSDNode>(LHS)->isNullValue()) { 6585 DoXform = true; 6586 } else if (CC != ISD::SETCC_INVALID && 6587 RHS.getOpcode() == ISD::Constant && 6588 cast<ConstantSDNode>(RHS)->isNullValue()) { 6589 std::swap(LHS, RHS); 6590 SDValue Op0 = Slct.getOperand(0); 6591 EVT OpVT = isSlctCC ? Op0.getValueType() : 6592 Op0.getOperand(0).getValueType(); 6593 bool isInt = OpVT.isInteger(); 6594 CC = ISD::getSetCCInverse(CC, isInt); 6595 6596 if (!TLI.isCondCodeLegal(CC, OpVT)) 6597 return SDValue(); // Inverse operator isn't legal. 6598 6599 DoXform = true; 6600 InvCC = true; 6601 } 6602 6603 if (DoXform) { 6604 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS); 6605 if (isSlctCC) 6606 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result, 6607 Slct.getOperand(0), Slct.getOperand(1), CC); 6608 SDValue CCOp = Slct.getOperand(0); 6609 if (InvCC) 6610 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(), 6611 CCOp.getOperand(0), CCOp.getOperand(1), CC); 6612 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 6613 CCOp, OtherOp, Result); 6614 } 6615 return SDValue(); 6616} 6617 6618// AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction 6619// (only after legalization). 6620static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1, 6621 TargetLowering::DAGCombinerInfo &DCI, 6622 const ARMSubtarget *Subtarget) { 6623 6624 // Only perform optimization if after legalize, and if NEON is available. We 6625 // also expected both operands to be BUILD_VECTORs. 6626 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON() 6627 || N0.getOpcode() != ISD::BUILD_VECTOR 6628 || N1.getOpcode() != ISD::BUILD_VECTOR) 6629 return SDValue(); 6630 6631 // Check output type since VPADDL operand elements can only be 8, 16, or 32. 6632 EVT VT = N->getValueType(0); 6633 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64) 6634 return SDValue(); 6635 6636 // Check that the vector operands are of the right form. 6637 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR 6638 // operands, where N is the size of the formed vector. 6639 // Each EXTRACT_VECTOR should have the same input vector and odd or even 6640 // index such that we have a pair wise add pattern. 6641 6642 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing. 6643 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 6644 return SDValue(); 6645 SDValue Vec = N0->getOperand(0)->getOperand(0); 6646 SDNode *V = Vec.getNode(); 6647 unsigned nextIndex = 0; 6648 6649 // For each operands to the ADD which are BUILD_VECTORs, 6650 // check to see if each of their operands are an EXTRACT_VECTOR with 6651 // the same vector and appropriate index. 6652 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) { 6653 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT 6654 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) { 6655 6656 SDValue ExtVec0 = N0->getOperand(i); 6657 SDValue ExtVec1 = N1->getOperand(i); 6658 6659 // First operand is the vector, verify its the same. 6660 if (V != ExtVec0->getOperand(0).getNode() || 6661 V != ExtVec1->getOperand(0).getNode()) 6662 return SDValue(); 6663 6664 // Second is the constant, verify its correct. 6665 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1)); 6666 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1)); 6667 6668 // For the constant, we want to see all the even or all the odd. 6669 if (!C0 || !C1 || C0->getZExtValue() != nextIndex 6670 || C1->getZExtValue() != nextIndex+1) 6671 return SDValue(); 6672 6673 // Increment index. 6674 nextIndex+=2; 6675 } else 6676 return SDValue(); 6677 } 6678 6679 // Create VPADDL node. 6680 SelectionDAG &DAG = DCI.DAG; 6681 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6682 6683 // Build operand list. 6684 SmallVector<SDValue, 8> Ops; 6685 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls, 6686 TLI.getPointerTy())); 6687 6688 // Input is the vector. 6689 Ops.push_back(Vec); 6690 6691 // Get widened type and narrowed type. 6692 MVT widenType; 6693 unsigned numElem = VT.getVectorNumElements(); 6694 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) { 6695 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break; 6696 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break; 6697 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break; 6698 default: 6699 llvm_unreachable("Invalid vector element type for padd optimization."); 6700 } 6701 6702 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), 6703 widenType, &Ops[0], Ops.size()); 6704 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, tmp); 6705} 6706 6707/// PerformADDCombineWithOperands - Try DAG combinations for an ADD with 6708/// operands N0 and N1. This is a helper for PerformADDCombine that is 6709/// called with the default operands, and if that fails, with commuted 6710/// operands. 6711static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, 6712 TargetLowering::DAGCombinerInfo &DCI, 6713 const ARMSubtarget *Subtarget){ 6714 6715 // Attempt to create vpaddl for this add. 6716 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget); 6717 if (Result.getNode()) 6718 return Result; 6719 6720 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 6721 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) { 6722 SDValue Result = combineSelectAndUse(N, N0, N1, DCI); 6723 if (Result.getNode()) return Result; 6724 } 6725 return SDValue(); 6726} 6727 6728/// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD. 6729/// 6730static SDValue PerformADDCombine(SDNode *N, 6731 TargetLowering::DAGCombinerInfo &DCI, 6732 const ARMSubtarget *Subtarget) { 6733 SDValue N0 = N->getOperand(0); 6734 SDValue N1 = N->getOperand(1); 6735 6736 // First try with the default operand order. 6737 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget); 6738 if (Result.getNode()) 6739 return Result; 6740 6741 // If that didn't work, try again with the operands commuted. 6742 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget); 6743} 6744 6745/// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB. 6746/// 6747static SDValue PerformSUBCombine(SDNode *N, 6748 TargetLowering::DAGCombinerInfo &DCI) { 6749 SDValue N0 = N->getOperand(0); 6750 SDValue N1 = N->getOperand(1); 6751 6752 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 6753 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 6754 SDValue Result = combineSelectAndUse(N, N1, N0, DCI); 6755 if (Result.getNode()) return Result; 6756 } 6757 6758 return SDValue(); 6759} 6760 6761/// PerformVMULCombine 6762/// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the 6763/// special multiplier accumulator forwarding. 6764/// vmul d3, d0, d2 6765/// vmla d3, d1, d2 6766/// is faster than 6767/// vadd d3, d0, d1 6768/// vmul d3, d3, d2 6769static SDValue PerformVMULCombine(SDNode *N, 6770 TargetLowering::DAGCombinerInfo &DCI, 6771 const ARMSubtarget *Subtarget) { 6772 if (!Subtarget->hasVMLxForwarding()) 6773 return SDValue(); 6774 6775 SelectionDAG &DAG = DCI.DAG; 6776 SDValue N0 = N->getOperand(0); 6777 SDValue N1 = N->getOperand(1); 6778 unsigned Opcode = N0.getOpcode(); 6779 if (Opcode != ISD::ADD && Opcode != ISD::SUB && 6780 Opcode != ISD::FADD && Opcode != ISD::FSUB) { 6781 Opcode = N1.getOpcode(); 6782 if (Opcode != ISD::ADD && Opcode != ISD::SUB && 6783 Opcode != ISD::FADD && Opcode != ISD::FSUB) 6784 return SDValue(); 6785 std::swap(N0, N1); 6786 } 6787 6788 EVT VT = N->getValueType(0); 6789 DebugLoc DL = N->getDebugLoc(); 6790 SDValue N00 = N0->getOperand(0); 6791 SDValue N01 = N0->getOperand(1); 6792 return DAG.getNode(Opcode, DL, VT, 6793 DAG.getNode(ISD::MUL, DL, VT, N00, N1), 6794 DAG.getNode(ISD::MUL, DL, VT, N01, N1)); 6795} 6796 6797static SDValue PerformMULCombine(SDNode *N, 6798 TargetLowering::DAGCombinerInfo &DCI, 6799 const ARMSubtarget *Subtarget) { 6800 SelectionDAG &DAG = DCI.DAG; 6801 6802 if (Subtarget->isThumb1Only()) 6803 return SDValue(); 6804 6805 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 6806 return SDValue(); 6807 6808 EVT VT = N->getValueType(0); 6809 if (VT.is64BitVector() || VT.is128BitVector()) 6810 return PerformVMULCombine(N, DCI, Subtarget); 6811 if (VT != MVT::i32) 6812 return SDValue(); 6813 6814 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6815 if (!C) 6816 return SDValue(); 6817 6818 uint64_t MulAmt = C->getZExtValue(); 6819 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt); 6820 ShiftAmt = ShiftAmt & (32 - 1); 6821 SDValue V = N->getOperand(0); 6822 DebugLoc DL = N->getDebugLoc(); 6823 6824 SDValue Res; 6825 MulAmt >>= ShiftAmt; 6826 if (isPowerOf2_32(MulAmt - 1)) { 6827 // (mul x, 2^N + 1) => (add (shl x, N), x) 6828 Res = DAG.getNode(ISD::ADD, DL, VT, 6829 V, DAG.getNode(ISD::SHL, DL, VT, 6830 V, DAG.getConstant(Log2_32(MulAmt-1), 6831 MVT::i32))); 6832 } else if (isPowerOf2_32(MulAmt + 1)) { 6833 // (mul x, 2^N - 1) => (sub (shl x, N), x) 6834 Res = DAG.getNode(ISD::SUB, DL, VT, 6835 DAG.getNode(ISD::SHL, DL, VT, 6836 V, DAG.getConstant(Log2_32(MulAmt+1), 6837 MVT::i32)), 6838 V); 6839 } else 6840 return SDValue(); 6841 6842 if (ShiftAmt != 0) 6843 Res = DAG.getNode(ISD::SHL, DL, VT, Res, 6844 DAG.getConstant(ShiftAmt, MVT::i32)); 6845 6846 // Do not add new nodes to DAG combiner worklist. 6847 DCI.CombineTo(N, Res, false); 6848 return SDValue(); 6849} 6850 6851static bool isCMOVWithZeroOrAllOnesLHS(SDValue N, bool AllOnes) { 6852 if (N.getOpcode() != ARMISD::CMOV || !N.getNode()->hasOneUse()) 6853 return false; 6854 6855 SDValue FalseVal = N.getOperand(0); 6856 ConstantSDNode *C = dyn_cast<ConstantSDNode>(FalseVal); 6857 if (!C) 6858 return false; 6859 if (AllOnes) 6860 return C->isAllOnesValue(); 6861 return C->isNullValue(); 6862} 6863 6864/// formConditionalOp - Combine an operation with a conditional move operand 6865/// to form a conditional op. e.g. (or x, (cmov 0, y, cond)) => (or.cond x, y) 6866/// (and x, (cmov -1, y, cond)) => (and.cond, x, y) 6867static SDValue formConditionalOp(SDNode *N, SelectionDAG &DAG, 6868 bool Commutable) { 6869 SDValue N0 = N->getOperand(0); 6870 SDValue N1 = N->getOperand(1); 6871 6872 bool isAND = N->getOpcode() == ISD::AND; 6873 bool isCand = isCMOVWithZeroOrAllOnesLHS(N1, isAND); 6874 if (!isCand && Commutable) { 6875 isCand = isCMOVWithZeroOrAllOnesLHS(N0, isAND); 6876 if (isCand) 6877 std::swap(N0, N1); 6878 } 6879 if (!isCand) 6880 return SDValue(); 6881 6882 unsigned Opc = 0; 6883 switch (N->getOpcode()) { 6884 default: llvm_unreachable("Unexpected node"); 6885 case ISD::AND: Opc = ARMISD::CAND; break; 6886 case ISD::OR: Opc = ARMISD::COR; break; 6887 case ISD::XOR: Opc = ARMISD::CXOR; break; 6888 } 6889 return DAG.getNode(Opc, N->getDebugLoc(), N->getValueType(0), N0, 6890 N1.getOperand(1), N1.getOperand(2), N1.getOperand(3), 6891 N1.getOperand(4)); 6892} 6893 6894static SDValue PerformANDCombine(SDNode *N, 6895 TargetLowering::DAGCombinerInfo &DCI, 6896 const ARMSubtarget *Subtarget) { 6897 6898 // Attempt to use immediate-form VBIC 6899 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1)); 6900 DebugLoc dl = N->getDebugLoc(); 6901 EVT VT = N->getValueType(0); 6902 SelectionDAG &DAG = DCI.DAG; 6903 6904 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 6905 return SDValue(); 6906 6907 APInt SplatBits, SplatUndef; 6908 unsigned SplatBitSize; 6909 bool HasAnyUndefs; 6910 if (BVN && 6911 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { 6912 if (SplatBitSize <= 64) { 6913 EVT VbicVT; 6914 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(), 6915 SplatUndef.getZExtValue(), SplatBitSize, 6916 DAG, VbicVT, VT.is128BitVector(), 6917 OtherModImm); 6918 if (Val.getNode()) { 6919 SDValue Input = 6920 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0)); 6921 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val); 6922 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic); 6923 } 6924 } 6925 } 6926 6927 if (!Subtarget->isThumb1Only()) { 6928 // (and x, (cmov -1, y, cond)) => (and.cond x, y) 6929 SDValue CAND = formConditionalOp(N, DAG, true); 6930 if (CAND.getNode()) 6931 return CAND; 6932 } 6933 6934 return SDValue(); 6935} 6936 6937/// PerformORCombine - Target-specific dag combine xforms for ISD::OR 6938static SDValue PerformORCombine(SDNode *N, 6939 TargetLowering::DAGCombinerInfo &DCI, 6940 const ARMSubtarget *Subtarget) { 6941 // Attempt to use immediate-form VORR 6942 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1)); 6943 DebugLoc dl = N->getDebugLoc(); 6944 EVT VT = N->getValueType(0); 6945 SelectionDAG &DAG = DCI.DAG; 6946 6947 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 6948 return SDValue(); 6949 6950 APInt SplatBits, SplatUndef; 6951 unsigned SplatBitSize; 6952 bool HasAnyUndefs; 6953 if (BVN && Subtarget->hasNEON() && 6954 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { 6955 if (SplatBitSize <= 64) { 6956 EVT VorrVT; 6957 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(), 6958 SplatUndef.getZExtValue(), SplatBitSize, 6959 DAG, VorrVT, VT.is128BitVector(), 6960 OtherModImm); 6961 if (Val.getNode()) { 6962 SDValue Input = 6963 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0)); 6964 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val); 6965 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr); 6966 } 6967 } 6968 } 6969 6970 if (!Subtarget->isThumb1Only()) { 6971 // (or x, (cmov 0, y, cond)) => (or.cond x, y) 6972 SDValue COR = formConditionalOp(N, DAG, true); 6973 if (COR.getNode()) 6974 return COR; 6975 } 6976 6977 SDValue N0 = N->getOperand(0); 6978 if (N0.getOpcode() != ISD::AND) 6979 return SDValue(); 6980 SDValue N1 = N->getOperand(1); 6981 6982 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant. 6983 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() && 6984 DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 6985 APInt SplatUndef; 6986 unsigned SplatBitSize; 6987 bool HasAnyUndefs; 6988 6989 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1)); 6990 APInt SplatBits0; 6991 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize, 6992 HasAnyUndefs) && !HasAnyUndefs) { 6993 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1)); 6994 APInt SplatBits1; 6995 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize, 6996 HasAnyUndefs) && !HasAnyUndefs && 6997 SplatBits0 == ~SplatBits1) { 6998 // Canonicalize the vector type to make instruction selection simpler. 6999 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32; 7000 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT, 7001 N0->getOperand(1), N0->getOperand(0), 7002 N1->getOperand(0)); 7003 return DAG.getNode(ISD::BITCAST, dl, VT, Result); 7004 } 7005 } 7006 } 7007 7008 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when 7009 // reasonable. 7010 7011 // BFI is only available on V6T2+ 7012 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops()) 7013 return SDValue(); 7014 7015 DebugLoc DL = N->getDebugLoc(); 7016 // 1) or (and A, mask), val => ARMbfi A, val, mask 7017 // iff (val & mask) == val 7018 // 7019 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask 7020 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2) 7021 // && mask == ~mask2 7022 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2) 7023 // && ~mask == mask2 7024 // (i.e., copy a bitfield value into another bitfield of the same width) 7025 7026 if (VT != MVT::i32) 7027 return SDValue(); 7028 7029 SDValue N00 = N0.getOperand(0); 7030 7031 // The value and the mask need to be constants so we can verify this is 7032 // actually a bitfield set. If the mask is 0xffff, we can do better 7033 // via a movt instruction, so don't use BFI in that case. 7034 SDValue MaskOp = N0.getOperand(1); 7035 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp); 7036 if (!MaskC) 7037 return SDValue(); 7038 unsigned Mask = MaskC->getZExtValue(); 7039 if (Mask == 0xffff) 7040 return SDValue(); 7041 SDValue Res; 7042 // Case (1): or (and A, mask), val => ARMbfi A, val, mask 7043 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 7044 if (N1C) { 7045 unsigned Val = N1C->getZExtValue(); 7046 if ((Val & ~Mask) != Val) 7047 return SDValue(); 7048 7049 if (ARM::isBitFieldInvertedMask(Mask)) { 7050 Val >>= CountTrailingZeros_32(~Mask); 7051 7052 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, 7053 DAG.getConstant(Val, MVT::i32), 7054 DAG.getConstant(Mask, MVT::i32)); 7055 7056 // Do not add new nodes to DAG combiner worklist. 7057 DCI.CombineTo(N, Res, false); 7058 return SDValue(); 7059 } 7060 } else if (N1.getOpcode() == ISD::AND) { 7061 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask 7062 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 7063 if (!N11C) 7064 return SDValue(); 7065 unsigned Mask2 = N11C->getZExtValue(); 7066 7067 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern 7068 // as is to match. 7069 if (ARM::isBitFieldInvertedMask(Mask) && 7070 (Mask == ~Mask2)) { 7071 // The pack halfword instruction works better for masks that fit it, 7072 // so use that when it's available. 7073 if (Subtarget->hasT2ExtractPack() && 7074 (Mask == 0xffff || Mask == 0xffff0000)) 7075 return SDValue(); 7076 // 2a 7077 unsigned amt = CountTrailingZeros_32(Mask2); 7078 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0), 7079 DAG.getConstant(amt, MVT::i32)); 7080 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res, 7081 DAG.getConstant(Mask, MVT::i32)); 7082 // Do not add new nodes to DAG combiner worklist. 7083 DCI.CombineTo(N, Res, false); 7084 return SDValue(); 7085 } else if (ARM::isBitFieldInvertedMask(~Mask) && 7086 (~Mask == Mask2)) { 7087 // The pack halfword instruction works better for masks that fit it, 7088 // so use that when it's available. 7089 if (Subtarget->hasT2ExtractPack() && 7090 (Mask2 == 0xffff || Mask2 == 0xffff0000)) 7091 return SDValue(); 7092 // 2b 7093 unsigned lsb = CountTrailingZeros_32(Mask); 7094 Res = DAG.getNode(ISD::SRL, DL, VT, N00, 7095 DAG.getConstant(lsb, MVT::i32)); 7096 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res, 7097 DAG.getConstant(Mask2, MVT::i32)); 7098 // Do not add new nodes to DAG combiner worklist. 7099 DCI.CombineTo(N, Res, false); 7100 return SDValue(); 7101 } 7102 } 7103 7104 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) && 7105 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) && 7106 ARM::isBitFieldInvertedMask(~Mask)) { 7107 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask 7108 // where lsb(mask) == #shamt and masked bits of B are known zero. 7109 SDValue ShAmt = N00.getOperand(1); 7110 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 7111 unsigned LSB = CountTrailingZeros_32(Mask); 7112 if (ShAmtC != LSB) 7113 return SDValue(); 7114 7115 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0), 7116 DAG.getConstant(~Mask, MVT::i32)); 7117 7118 // Do not add new nodes to DAG combiner worklist. 7119 DCI.CombineTo(N, Res, false); 7120 } 7121 7122 return SDValue(); 7123} 7124 7125static SDValue PerformXORCombine(SDNode *N, 7126 TargetLowering::DAGCombinerInfo &DCI, 7127 const ARMSubtarget *Subtarget) { 7128 EVT VT = N->getValueType(0); 7129 SelectionDAG &DAG = DCI.DAG; 7130 7131 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 7132 return SDValue(); 7133 7134 if (!Subtarget->isThumb1Only()) { 7135 // (xor x, (cmov 0, y, cond)) => (xor.cond x, y) 7136 SDValue CXOR = formConditionalOp(N, DAG, true); 7137 if (CXOR.getNode()) 7138 return CXOR; 7139 } 7140 7141 return SDValue(); 7142} 7143 7144/// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff 7145/// the bits being cleared by the AND are not demanded by the BFI. 7146static SDValue PerformBFICombine(SDNode *N, 7147 TargetLowering::DAGCombinerInfo &DCI) { 7148 SDValue N1 = N->getOperand(1); 7149 if (N1.getOpcode() == ISD::AND) { 7150 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 7151 if (!N11C) 7152 return SDValue(); 7153 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue(); 7154 unsigned LSB = CountTrailingZeros_32(~InvMask); 7155 unsigned Width = (32 - CountLeadingZeros_32(~InvMask)) - LSB; 7156 unsigned Mask = (1 << Width)-1; 7157 unsigned Mask2 = N11C->getZExtValue(); 7158 if ((Mask & (~Mask2)) == 0) 7159 return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0), 7160 N->getOperand(0), N1.getOperand(0), 7161 N->getOperand(2)); 7162 } 7163 return SDValue(); 7164} 7165 7166/// PerformVMOVRRDCombine - Target-specific dag combine xforms for 7167/// ARMISD::VMOVRRD. 7168static SDValue PerformVMOVRRDCombine(SDNode *N, 7169 TargetLowering::DAGCombinerInfo &DCI) { 7170 // vmovrrd(vmovdrr x, y) -> x,y 7171 SDValue InDouble = N->getOperand(0); 7172 if (InDouble.getOpcode() == ARMISD::VMOVDRR) 7173 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1)); 7174 7175 // vmovrrd(load f64) -> (load i32), (load i32) 7176 SDNode *InNode = InDouble.getNode(); 7177 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() && 7178 InNode->getValueType(0) == MVT::f64 && 7179 InNode->getOperand(1).getOpcode() == ISD::FrameIndex && 7180 !cast<LoadSDNode>(InNode)->isVolatile()) { 7181 // TODO: Should this be done for non-FrameIndex operands? 7182 LoadSDNode *LD = cast<LoadSDNode>(InNode); 7183 7184 SelectionDAG &DAG = DCI.DAG; 7185 DebugLoc DL = LD->getDebugLoc(); 7186 SDValue BasePtr = LD->getBasePtr(); 7187 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr, 7188 LD->getPointerInfo(), LD->isVolatile(), 7189 LD->isNonTemporal(), LD->isInvariant(), 7190 LD->getAlignment()); 7191 7192 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, 7193 DAG.getConstant(4, MVT::i32)); 7194 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr, 7195 LD->getPointerInfo(), LD->isVolatile(), 7196 LD->isNonTemporal(), LD->isInvariant(), 7197 std::min(4U, LD->getAlignment() / 2)); 7198 7199 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1)); 7200 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2); 7201 DCI.RemoveFromWorklist(LD); 7202 DAG.DeleteNode(LD); 7203 return Result; 7204 } 7205 7206 return SDValue(); 7207} 7208 7209/// PerformVMOVDRRCombine - Target-specific dag combine xforms for 7210/// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands. 7211static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) { 7212 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X) 7213 SDValue Op0 = N->getOperand(0); 7214 SDValue Op1 = N->getOperand(1); 7215 if (Op0.getOpcode() == ISD::BITCAST) 7216 Op0 = Op0.getOperand(0); 7217 if (Op1.getOpcode() == ISD::BITCAST) 7218 Op1 = Op1.getOperand(0); 7219 if (Op0.getOpcode() == ARMISD::VMOVRRD && 7220 Op0.getNode() == Op1.getNode() && 7221 Op0.getResNo() == 0 && Op1.getResNo() == 1) 7222 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 7223 N->getValueType(0), Op0.getOperand(0)); 7224 return SDValue(); 7225} 7226 7227/// PerformSTORECombine - Target-specific dag combine xforms for 7228/// ISD::STORE. 7229static SDValue PerformSTORECombine(SDNode *N, 7230 TargetLowering::DAGCombinerInfo &DCI) { 7231 // Bitcast an i64 store extracted from a vector to f64. 7232 // Otherwise, the i64 value will be legalized to a pair of i32 values. 7233 StoreSDNode *St = cast<StoreSDNode>(N); 7234 SDValue StVal = St->getValue(); 7235 if (!ISD::isNormalStore(St) || St->isVolatile()) 7236 return SDValue(); 7237 7238 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR && 7239 StVal.getNode()->hasOneUse() && !St->isVolatile()) { 7240 SelectionDAG &DAG = DCI.DAG; 7241 DebugLoc DL = St->getDebugLoc(); 7242 SDValue BasePtr = St->getBasePtr(); 7243 SDValue NewST1 = DAG.getStore(St->getChain(), DL, 7244 StVal.getNode()->getOperand(0), BasePtr, 7245 St->getPointerInfo(), St->isVolatile(), 7246 St->isNonTemporal(), St->getAlignment()); 7247 7248 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, 7249 DAG.getConstant(4, MVT::i32)); 7250 return DAG.getStore(NewST1.getValue(0), DL, StVal.getNode()->getOperand(1), 7251 OffsetPtr, St->getPointerInfo(), St->isVolatile(), 7252 St->isNonTemporal(), 7253 std::min(4U, St->getAlignment() / 2)); 7254 } 7255 7256 if (StVal.getValueType() != MVT::i64 || 7257 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 7258 return SDValue(); 7259 7260 SelectionDAG &DAG = DCI.DAG; 7261 DebugLoc dl = StVal.getDebugLoc(); 7262 SDValue IntVec = StVal.getOperand(0); 7263 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, 7264 IntVec.getValueType().getVectorNumElements()); 7265 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec); 7266 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7267 Vec, StVal.getOperand(1)); 7268 dl = N->getDebugLoc(); 7269 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt); 7270 // Make the DAGCombiner fold the bitcasts. 7271 DCI.AddToWorklist(Vec.getNode()); 7272 DCI.AddToWorklist(ExtElt.getNode()); 7273 DCI.AddToWorklist(V.getNode()); 7274 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(), 7275 St->getPointerInfo(), St->isVolatile(), 7276 St->isNonTemporal(), St->getAlignment(), 7277 St->getTBAAInfo()); 7278} 7279 7280/// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node 7281/// are normal, non-volatile loads. If so, it is profitable to bitcast an 7282/// i64 vector to have f64 elements, since the value can then be loaded 7283/// directly into a VFP register. 7284static bool hasNormalLoadOperand(SDNode *N) { 7285 unsigned NumElts = N->getValueType(0).getVectorNumElements(); 7286 for (unsigned i = 0; i < NumElts; ++i) { 7287 SDNode *Elt = N->getOperand(i).getNode(); 7288 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile()) 7289 return true; 7290 } 7291 return false; 7292} 7293 7294/// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for 7295/// ISD::BUILD_VECTOR. 7296static SDValue PerformBUILD_VECTORCombine(SDNode *N, 7297 TargetLowering::DAGCombinerInfo &DCI){ 7298 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X): 7299 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value 7300 // into a pair of GPRs, which is fine when the value is used as a scalar, 7301 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD. 7302 SelectionDAG &DAG = DCI.DAG; 7303 if (N->getNumOperands() == 2) { 7304 SDValue RV = PerformVMOVDRRCombine(N, DAG); 7305 if (RV.getNode()) 7306 return RV; 7307 } 7308 7309 // Load i64 elements as f64 values so that type legalization does not split 7310 // them up into i32 values. 7311 EVT VT = N->getValueType(0); 7312 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N)) 7313 return SDValue(); 7314 DebugLoc dl = N->getDebugLoc(); 7315 SmallVector<SDValue, 8> Ops; 7316 unsigned NumElts = VT.getVectorNumElements(); 7317 for (unsigned i = 0; i < NumElts; ++i) { 7318 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i)); 7319 Ops.push_back(V); 7320 // Make the DAGCombiner fold the bitcast. 7321 DCI.AddToWorklist(V.getNode()); 7322 } 7323 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts); 7324 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts); 7325 return DAG.getNode(ISD::BITCAST, dl, VT, BV); 7326} 7327 7328/// PerformInsertEltCombine - Target-specific dag combine xforms for 7329/// ISD::INSERT_VECTOR_ELT. 7330static SDValue PerformInsertEltCombine(SDNode *N, 7331 TargetLowering::DAGCombinerInfo &DCI) { 7332 // Bitcast an i64 load inserted into a vector to f64. 7333 // Otherwise, the i64 value will be legalized to a pair of i32 values. 7334 EVT VT = N->getValueType(0); 7335 SDNode *Elt = N->getOperand(1).getNode(); 7336 if (VT.getVectorElementType() != MVT::i64 || 7337 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile()) 7338 return SDValue(); 7339 7340 SelectionDAG &DAG = DCI.DAG; 7341 DebugLoc dl = N->getDebugLoc(); 7342 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, 7343 VT.getVectorNumElements()); 7344 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0)); 7345 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1)); 7346 // Make the DAGCombiner fold the bitcasts. 7347 DCI.AddToWorklist(Vec.getNode()); 7348 DCI.AddToWorklist(V.getNode()); 7349 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT, 7350 Vec, V, N->getOperand(2)); 7351 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt); 7352} 7353 7354/// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for 7355/// ISD::VECTOR_SHUFFLE. 7356static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) { 7357 // The LLVM shufflevector instruction does not require the shuffle mask 7358 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does 7359 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the 7360 // operands do not match the mask length, they are extended by concatenating 7361 // them with undef vectors. That is probably the right thing for other 7362 // targets, but for NEON it is better to concatenate two double-register 7363 // size vector operands into a single quad-register size vector. Do that 7364 // transformation here: 7365 // shuffle(concat(v1, undef), concat(v2, undef)) -> 7366 // shuffle(concat(v1, v2), undef) 7367 SDValue Op0 = N->getOperand(0); 7368 SDValue Op1 = N->getOperand(1); 7369 if (Op0.getOpcode() != ISD::CONCAT_VECTORS || 7370 Op1.getOpcode() != ISD::CONCAT_VECTORS || 7371 Op0.getNumOperands() != 2 || 7372 Op1.getNumOperands() != 2) 7373 return SDValue(); 7374 SDValue Concat0Op1 = Op0.getOperand(1); 7375 SDValue Concat1Op1 = Op1.getOperand(1); 7376 if (Concat0Op1.getOpcode() != ISD::UNDEF || 7377 Concat1Op1.getOpcode() != ISD::UNDEF) 7378 return SDValue(); 7379 // Skip the transformation if any of the types are illegal. 7380 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 7381 EVT VT = N->getValueType(0); 7382 if (!TLI.isTypeLegal(VT) || 7383 !TLI.isTypeLegal(Concat0Op1.getValueType()) || 7384 !TLI.isTypeLegal(Concat1Op1.getValueType())) 7385 return SDValue(); 7386 7387 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, 7388 Op0.getOperand(0), Op1.getOperand(0)); 7389 // Translate the shuffle mask. 7390 SmallVector<int, 16> NewMask; 7391 unsigned NumElts = VT.getVectorNumElements(); 7392 unsigned HalfElts = NumElts/2; 7393 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 7394 for (unsigned n = 0; n < NumElts; ++n) { 7395 int MaskElt = SVN->getMaskElt(n); 7396 int NewElt = -1; 7397 if (MaskElt < (int)HalfElts) 7398 NewElt = MaskElt; 7399 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts)) 7400 NewElt = HalfElts + MaskElt - NumElts; 7401 NewMask.push_back(NewElt); 7402 } 7403 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat, 7404 DAG.getUNDEF(VT), NewMask.data()); 7405} 7406 7407/// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and 7408/// NEON load/store intrinsics to merge base address updates. 7409static SDValue CombineBaseUpdate(SDNode *N, 7410 TargetLowering::DAGCombinerInfo &DCI) { 7411 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 7412 return SDValue(); 7413 7414 SelectionDAG &DAG = DCI.DAG; 7415 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID || 7416 N->getOpcode() == ISD::INTRINSIC_W_CHAIN); 7417 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1); 7418 SDValue Addr = N->getOperand(AddrOpIdx); 7419 7420 // Search for a use of the address operand that is an increment. 7421 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), 7422 UE = Addr.getNode()->use_end(); UI != UE; ++UI) { 7423 SDNode *User = *UI; 7424 if (User->getOpcode() != ISD::ADD || 7425 UI.getUse().getResNo() != Addr.getResNo()) 7426 continue; 7427 7428 // Check that the add is independent of the load/store. Otherwise, folding 7429 // it would create a cycle. 7430 if (User->isPredecessorOf(N) || N->isPredecessorOf(User)) 7431 continue; 7432 7433 // Find the new opcode for the updating load/store. 7434 bool isLoad = true; 7435 bool isLaneOp = false; 7436 unsigned NewOpc = 0; 7437 unsigned NumVecs = 0; 7438 if (isIntrinsic) { 7439 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 7440 switch (IntNo) { 7441 default: llvm_unreachable("unexpected intrinsic for Neon base update"); 7442 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD; 7443 NumVecs = 1; break; 7444 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD; 7445 NumVecs = 2; break; 7446 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD; 7447 NumVecs = 3; break; 7448 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD; 7449 NumVecs = 4; break; 7450 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD; 7451 NumVecs = 2; isLaneOp = true; break; 7452 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD; 7453 NumVecs = 3; isLaneOp = true; break; 7454 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD; 7455 NumVecs = 4; isLaneOp = true; break; 7456 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD; 7457 NumVecs = 1; isLoad = false; break; 7458 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD; 7459 NumVecs = 2; isLoad = false; break; 7460 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD; 7461 NumVecs = 3; isLoad = false; break; 7462 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD; 7463 NumVecs = 4; isLoad = false; break; 7464 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD; 7465 NumVecs = 2; isLoad = false; isLaneOp = true; break; 7466 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD; 7467 NumVecs = 3; isLoad = false; isLaneOp = true; break; 7468 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD; 7469 NumVecs = 4; isLoad = false; isLaneOp = true; break; 7470 } 7471 } else { 7472 isLaneOp = true; 7473 switch (N->getOpcode()) { 7474 default: llvm_unreachable("unexpected opcode for Neon base update"); 7475 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break; 7476 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break; 7477 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break; 7478 } 7479 } 7480 7481 // Find the size of memory referenced by the load/store. 7482 EVT VecTy; 7483 if (isLoad) 7484 VecTy = N->getValueType(0); 7485 else 7486 VecTy = N->getOperand(AddrOpIdx+1).getValueType(); 7487 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8; 7488 if (isLaneOp) 7489 NumBytes /= VecTy.getVectorNumElements(); 7490 7491 // If the increment is a constant, it must match the memory ref size. 7492 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0); 7493 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) { 7494 uint64_t IncVal = CInc->getZExtValue(); 7495 if (IncVal != NumBytes) 7496 continue; 7497 } else if (NumBytes >= 3 * 16) { 7498 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two 7499 // separate instructions that make it harder to use a non-constant update. 7500 continue; 7501 } 7502 7503 // Create the new updating load/store node. 7504 EVT Tys[6]; 7505 unsigned NumResultVecs = (isLoad ? NumVecs : 0); 7506 unsigned n; 7507 for (n = 0; n < NumResultVecs; ++n) 7508 Tys[n] = VecTy; 7509 Tys[n++] = MVT::i32; 7510 Tys[n] = MVT::Other; 7511 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs+2); 7512 SmallVector<SDValue, 8> Ops; 7513 Ops.push_back(N->getOperand(0)); // incoming chain 7514 Ops.push_back(N->getOperand(AddrOpIdx)); 7515 Ops.push_back(Inc); 7516 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) { 7517 Ops.push_back(N->getOperand(i)); 7518 } 7519 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N); 7520 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, N->getDebugLoc(), SDTys, 7521 Ops.data(), Ops.size(), 7522 MemInt->getMemoryVT(), 7523 MemInt->getMemOperand()); 7524 7525 // Update the uses. 7526 std::vector<SDValue> NewResults; 7527 for (unsigned i = 0; i < NumResultVecs; ++i) { 7528 NewResults.push_back(SDValue(UpdN.getNode(), i)); 7529 } 7530 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain 7531 DCI.CombineTo(N, NewResults); 7532 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs)); 7533 7534 break; 7535 } 7536 return SDValue(); 7537} 7538 7539/// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a 7540/// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic 7541/// are also VDUPLANEs. If so, combine them to a vldN-dup operation and 7542/// return true. 7543static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { 7544 SelectionDAG &DAG = DCI.DAG; 7545 EVT VT = N->getValueType(0); 7546 // vldN-dup instructions only support 64-bit vectors for N > 1. 7547 if (!VT.is64BitVector()) 7548 return false; 7549 7550 // Check if the VDUPLANE operand is a vldN-dup intrinsic. 7551 SDNode *VLD = N->getOperand(0).getNode(); 7552 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN) 7553 return false; 7554 unsigned NumVecs = 0; 7555 unsigned NewOpc = 0; 7556 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue(); 7557 if (IntNo == Intrinsic::arm_neon_vld2lane) { 7558 NumVecs = 2; 7559 NewOpc = ARMISD::VLD2DUP; 7560 } else if (IntNo == Intrinsic::arm_neon_vld3lane) { 7561 NumVecs = 3; 7562 NewOpc = ARMISD::VLD3DUP; 7563 } else if (IntNo == Intrinsic::arm_neon_vld4lane) { 7564 NumVecs = 4; 7565 NewOpc = ARMISD::VLD4DUP; 7566 } else { 7567 return false; 7568 } 7569 7570 // First check that all the vldN-lane uses are VDUPLANEs and that the lane 7571 // numbers match the load. 7572 unsigned VLDLaneNo = 7573 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue(); 7574 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); 7575 UI != UE; ++UI) { 7576 // Ignore uses of the chain result. 7577 if (UI.getUse().getResNo() == NumVecs) 7578 continue; 7579 SDNode *User = *UI; 7580 if (User->getOpcode() != ARMISD::VDUPLANE || 7581 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue()) 7582 return false; 7583 } 7584 7585 // Create the vldN-dup node. 7586 EVT Tys[5]; 7587 unsigned n; 7588 for (n = 0; n < NumVecs; ++n) 7589 Tys[n] = VT; 7590 Tys[n] = MVT::Other; 7591 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1); 7592 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) }; 7593 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD); 7594 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys, 7595 Ops, 2, VLDMemInt->getMemoryVT(), 7596 VLDMemInt->getMemOperand()); 7597 7598 // Update the uses. 7599 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); 7600 UI != UE; ++UI) { 7601 unsigned ResNo = UI.getUse().getResNo(); 7602 // Ignore uses of the chain result. 7603 if (ResNo == NumVecs) 7604 continue; 7605 SDNode *User = *UI; 7606 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo)); 7607 } 7608 7609 // Now the vldN-lane intrinsic is dead except for its chain result. 7610 // Update uses of the chain. 7611 std::vector<SDValue> VLDDupResults; 7612 for (unsigned n = 0; n < NumVecs; ++n) 7613 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n)); 7614 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs)); 7615 DCI.CombineTo(VLD, VLDDupResults); 7616 7617 return true; 7618} 7619 7620/// PerformVDUPLANECombine - Target-specific dag combine xforms for 7621/// ARMISD::VDUPLANE. 7622static SDValue PerformVDUPLANECombine(SDNode *N, 7623 TargetLowering::DAGCombinerInfo &DCI) { 7624 SDValue Op = N->getOperand(0); 7625 7626 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses 7627 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation. 7628 if (CombineVLDDUP(N, DCI)) 7629 return SDValue(N, 0); 7630 7631 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is 7632 // redundant. Ignore bit_converts for now; element sizes are checked below. 7633 while (Op.getOpcode() == ISD::BITCAST) 7634 Op = Op.getOperand(0); 7635 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM) 7636 return SDValue(); 7637 7638 // Make sure the VMOV element size is not bigger than the VDUPLANE elements. 7639 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits(); 7640 // The canonical VMOV for a zero vector uses a 32-bit element size. 7641 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 7642 unsigned EltBits; 7643 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0) 7644 EltSize = 8; 7645 EVT VT = N->getValueType(0); 7646 if (EltSize > VT.getVectorElementType().getSizeInBits()) 7647 return SDValue(); 7648 7649 return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 7650} 7651 7652// isConstVecPow2 - Return true if each vector element is a power of 2, all 7653// elements are the same constant, C, and Log2(C) ranges from 1 to 32. 7654static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C) 7655{ 7656 integerPart cN; 7657 integerPart c0 = 0; 7658 for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements(); 7659 I != E; I++) { 7660 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I)); 7661 if (!C) 7662 return false; 7663 7664 bool isExact; 7665 APFloat APF = C->getValueAPF(); 7666 if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact) 7667 != APFloat::opOK || !isExact) 7668 return false; 7669 7670 c0 = (I == 0) ? cN : c0; 7671 if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32) 7672 return false; 7673 } 7674 C = c0; 7675 return true; 7676} 7677 7678/// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD) 7679/// can replace combinations of VMUL and VCVT (floating-point to integer) 7680/// when the VMUL has a constant operand that is a power of 2. 7681/// 7682/// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): 7683/// vmul.f32 d16, d17, d16 7684/// vcvt.s32.f32 d16, d16 7685/// becomes: 7686/// vcvt.s32.f32 d16, d16, #3 7687static SDValue PerformVCVTCombine(SDNode *N, 7688 TargetLowering::DAGCombinerInfo &DCI, 7689 const ARMSubtarget *Subtarget) { 7690 SelectionDAG &DAG = DCI.DAG; 7691 SDValue Op = N->getOperand(0); 7692 7693 if (!Subtarget->hasNEON() || !Op.getValueType().isVector() || 7694 Op.getOpcode() != ISD::FMUL) 7695 return SDValue(); 7696 7697 uint64_t C; 7698 SDValue N0 = Op->getOperand(0); 7699 SDValue ConstVec = Op->getOperand(1); 7700 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT; 7701 7702 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR || 7703 !isConstVecPow2(ConstVec, isSigned, C)) 7704 return SDValue(); 7705 7706 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs : 7707 Intrinsic::arm_neon_vcvtfp2fxu; 7708 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), 7709 N->getValueType(0), 7710 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0, 7711 DAG.getConstant(Log2_64(C), MVT::i32)); 7712} 7713 7714/// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD) 7715/// can replace combinations of VCVT (integer to floating-point) and VDIV 7716/// when the VDIV has a constant operand that is a power of 2. 7717/// 7718/// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): 7719/// vcvt.f32.s32 d16, d16 7720/// vdiv.f32 d16, d17, d16 7721/// becomes: 7722/// vcvt.f32.s32 d16, d16, #3 7723static SDValue PerformVDIVCombine(SDNode *N, 7724 TargetLowering::DAGCombinerInfo &DCI, 7725 const ARMSubtarget *Subtarget) { 7726 SelectionDAG &DAG = DCI.DAG; 7727 SDValue Op = N->getOperand(0); 7728 unsigned OpOpcode = Op.getNode()->getOpcode(); 7729 7730 if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() || 7731 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP)) 7732 return SDValue(); 7733 7734 uint64_t C; 7735 SDValue ConstVec = N->getOperand(1); 7736 bool isSigned = OpOpcode == ISD::SINT_TO_FP; 7737 7738 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR || 7739 !isConstVecPow2(ConstVec, isSigned, C)) 7740 return SDValue(); 7741 7742 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp : 7743 Intrinsic::arm_neon_vcvtfxu2fp; 7744 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), 7745 Op.getValueType(), 7746 DAG.getConstant(IntrinsicOpcode, MVT::i32), 7747 Op.getOperand(0), DAG.getConstant(Log2_64(C), MVT::i32)); 7748} 7749 7750/// Getvshiftimm - Check if this is a valid build_vector for the immediate 7751/// operand of a vector shift operation, where all the elements of the 7752/// build_vector must have the same constant integer value. 7753static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) { 7754 // Ignore bit_converts. 7755 while (Op.getOpcode() == ISD::BITCAST) 7756 Op = Op.getOperand(0); 7757 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); 7758 APInt SplatBits, SplatUndef; 7759 unsigned SplatBitSize; 7760 bool HasAnyUndefs; 7761 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, 7762 HasAnyUndefs, ElementBits) || 7763 SplatBitSize > ElementBits) 7764 return false; 7765 Cnt = SplatBits.getSExtValue(); 7766 return true; 7767} 7768 7769/// isVShiftLImm - Check if this is a valid build_vector for the immediate 7770/// operand of a vector shift left operation. That value must be in the range: 7771/// 0 <= Value < ElementBits for a left shift; or 7772/// 0 <= Value <= ElementBits for a long left shift. 7773static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) { 7774 assert(VT.isVector() && "vector shift count is not a vector type"); 7775 unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); 7776 if (! getVShiftImm(Op, ElementBits, Cnt)) 7777 return false; 7778 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits); 7779} 7780 7781/// isVShiftRImm - Check if this is a valid build_vector for the immediate 7782/// operand of a vector shift right operation. For a shift opcode, the value 7783/// is positive, but for an intrinsic the value count must be negative. The 7784/// absolute value must be in the range: 7785/// 1 <= |Value| <= ElementBits for a right shift; or 7786/// 1 <= |Value| <= ElementBits/2 for a narrow right shift. 7787static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic, 7788 int64_t &Cnt) { 7789 assert(VT.isVector() && "vector shift count is not a vector type"); 7790 unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); 7791 if (! getVShiftImm(Op, ElementBits, Cnt)) 7792 return false; 7793 if (isIntrinsic) 7794 Cnt = -Cnt; 7795 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits)); 7796} 7797 7798/// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics. 7799static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { 7800 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); 7801 switch (IntNo) { 7802 default: 7803 // Don't do anything for most intrinsics. 7804 break; 7805 7806 // Vector shifts: check for immediate versions and lower them. 7807 // Note: This is done during DAG combining instead of DAG legalizing because 7808 // the build_vectors for 64-bit vector element shift counts are generally 7809 // not legal, and it is hard to see their values after they get legalized to 7810 // loads from a constant pool. 7811 case Intrinsic::arm_neon_vshifts: 7812 case Intrinsic::arm_neon_vshiftu: 7813 case Intrinsic::arm_neon_vshiftls: 7814 case Intrinsic::arm_neon_vshiftlu: 7815 case Intrinsic::arm_neon_vshiftn: 7816 case Intrinsic::arm_neon_vrshifts: 7817 case Intrinsic::arm_neon_vrshiftu: 7818 case Intrinsic::arm_neon_vrshiftn: 7819 case Intrinsic::arm_neon_vqshifts: 7820 case Intrinsic::arm_neon_vqshiftu: 7821 case Intrinsic::arm_neon_vqshiftsu: 7822 case Intrinsic::arm_neon_vqshiftns: 7823 case Intrinsic::arm_neon_vqshiftnu: 7824 case Intrinsic::arm_neon_vqshiftnsu: 7825 case Intrinsic::arm_neon_vqrshiftns: 7826 case Intrinsic::arm_neon_vqrshiftnu: 7827 case Intrinsic::arm_neon_vqrshiftnsu: { 7828 EVT VT = N->getOperand(1).getValueType(); 7829 int64_t Cnt; 7830 unsigned VShiftOpc = 0; 7831 7832 switch (IntNo) { 7833 case Intrinsic::arm_neon_vshifts: 7834 case Intrinsic::arm_neon_vshiftu: 7835 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) { 7836 VShiftOpc = ARMISD::VSHL; 7837 break; 7838 } 7839 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) { 7840 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ? 7841 ARMISD::VSHRs : ARMISD::VSHRu); 7842 break; 7843 } 7844 return SDValue(); 7845 7846 case Intrinsic::arm_neon_vshiftls: 7847 case Intrinsic::arm_neon_vshiftlu: 7848 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt)) 7849 break; 7850 llvm_unreachable("invalid shift count for vshll intrinsic"); 7851 7852 case Intrinsic::arm_neon_vrshifts: 7853 case Intrinsic::arm_neon_vrshiftu: 7854 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) 7855 break; 7856 return SDValue(); 7857 7858 case Intrinsic::arm_neon_vqshifts: 7859 case Intrinsic::arm_neon_vqshiftu: 7860 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) 7861 break; 7862 return SDValue(); 7863 7864 case Intrinsic::arm_neon_vqshiftsu: 7865 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) 7866 break; 7867 llvm_unreachable("invalid shift count for vqshlu intrinsic"); 7868 7869 case Intrinsic::arm_neon_vshiftn: 7870 case Intrinsic::arm_neon_vrshiftn: 7871 case Intrinsic::arm_neon_vqshiftns: 7872 case Intrinsic::arm_neon_vqshiftnu: 7873 case Intrinsic::arm_neon_vqshiftnsu: 7874 case Intrinsic::arm_neon_vqrshiftns: 7875 case Intrinsic::arm_neon_vqrshiftnu: 7876 case Intrinsic::arm_neon_vqrshiftnsu: 7877 // Narrowing shifts require an immediate right shift. 7878 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt)) 7879 break; 7880 llvm_unreachable("invalid shift count for narrowing vector shift " 7881 "intrinsic"); 7882 7883 default: 7884 llvm_unreachable("unhandled vector shift"); 7885 } 7886 7887 switch (IntNo) { 7888 case Intrinsic::arm_neon_vshifts: 7889 case Intrinsic::arm_neon_vshiftu: 7890 // Opcode already set above. 7891 break; 7892 case Intrinsic::arm_neon_vshiftls: 7893 case Intrinsic::arm_neon_vshiftlu: 7894 if (Cnt == VT.getVectorElementType().getSizeInBits()) 7895 VShiftOpc = ARMISD::VSHLLi; 7896 else 7897 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ? 7898 ARMISD::VSHLLs : ARMISD::VSHLLu); 7899 break; 7900 case Intrinsic::arm_neon_vshiftn: 7901 VShiftOpc = ARMISD::VSHRN; break; 7902 case Intrinsic::arm_neon_vrshifts: 7903 VShiftOpc = ARMISD::VRSHRs; break; 7904 case Intrinsic::arm_neon_vrshiftu: 7905 VShiftOpc = ARMISD::VRSHRu; break; 7906 case Intrinsic::arm_neon_vrshiftn: 7907 VShiftOpc = ARMISD::VRSHRN; break; 7908 case Intrinsic::arm_neon_vqshifts: 7909 VShiftOpc = ARMISD::VQSHLs; break; 7910 case Intrinsic::arm_neon_vqshiftu: 7911 VShiftOpc = ARMISD::VQSHLu; break; 7912 case Intrinsic::arm_neon_vqshiftsu: 7913 VShiftOpc = ARMISD::VQSHLsu; break; 7914 case Intrinsic::arm_neon_vqshiftns: 7915 VShiftOpc = ARMISD::VQSHRNs; break; 7916 case Intrinsic::arm_neon_vqshiftnu: 7917 VShiftOpc = ARMISD::VQSHRNu; break; 7918 case Intrinsic::arm_neon_vqshiftnsu: 7919 VShiftOpc = ARMISD::VQSHRNsu; break; 7920 case Intrinsic::arm_neon_vqrshiftns: 7921 VShiftOpc = ARMISD::VQRSHRNs; break; 7922 case Intrinsic::arm_neon_vqrshiftnu: 7923 VShiftOpc = ARMISD::VQRSHRNu; break; 7924 case Intrinsic::arm_neon_vqrshiftnsu: 7925 VShiftOpc = ARMISD::VQRSHRNsu; break; 7926 } 7927 7928 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), 7929 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32)); 7930 } 7931 7932 case Intrinsic::arm_neon_vshiftins: { 7933 EVT VT = N->getOperand(1).getValueType(); 7934 int64_t Cnt; 7935 unsigned VShiftOpc = 0; 7936 7937 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt)) 7938 VShiftOpc = ARMISD::VSLI; 7939 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt)) 7940 VShiftOpc = ARMISD::VSRI; 7941 else { 7942 llvm_unreachable("invalid shift count for vsli/vsri intrinsic"); 7943 } 7944 7945 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), 7946 N->getOperand(1), N->getOperand(2), 7947 DAG.getConstant(Cnt, MVT::i32)); 7948 } 7949 7950 case Intrinsic::arm_neon_vqrshifts: 7951 case Intrinsic::arm_neon_vqrshiftu: 7952 // No immediate versions of these to check for. 7953 break; 7954 } 7955 7956 return SDValue(); 7957} 7958 7959/// PerformShiftCombine - Checks for immediate versions of vector shifts and 7960/// lowers them. As with the vector shift intrinsics, this is done during DAG 7961/// combining instead of DAG legalizing because the build_vectors for 64-bit 7962/// vector element shift counts are generally not legal, and it is hard to see 7963/// their values after they get legalized to loads from a constant pool. 7964static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG, 7965 const ARMSubtarget *ST) { 7966 EVT VT = N->getValueType(0); 7967 7968 // Nothing to be done for scalar shifts. 7969 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 7970 if (!VT.isVector() || !TLI.isTypeLegal(VT)) 7971 return SDValue(); 7972 7973 assert(ST->hasNEON() && "unexpected vector shift"); 7974 int64_t Cnt; 7975 7976 switch (N->getOpcode()) { 7977 default: llvm_unreachable("unexpected shift opcode"); 7978 7979 case ISD::SHL: 7980 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt)) 7981 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0), 7982 DAG.getConstant(Cnt, MVT::i32)); 7983 break; 7984 7985 case ISD::SRA: 7986 case ISD::SRL: 7987 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) { 7988 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ? 7989 ARMISD::VSHRs : ARMISD::VSHRu); 7990 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0), 7991 DAG.getConstant(Cnt, MVT::i32)); 7992 } 7993 } 7994 return SDValue(); 7995} 7996 7997/// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND, 7998/// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND. 7999static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG, 8000 const ARMSubtarget *ST) { 8001 SDValue N0 = N->getOperand(0); 8002 8003 // Check for sign- and zero-extensions of vector extract operations of 8- 8004 // and 16-bit vector elements. NEON supports these directly. They are 8005 // handled during DAG combining because type legalization will promote them 8006 // to 32-bit types and it is messy to recognize the operations after that. 8007 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { 8008 SDValue Vec = N0.getOperand(0); 8009 SDValue Lane = N0.getOperand(1); 8010 EVT VT = N->getValueType(0); 8011 EVT EltVT = N0.getValueType(); 8012 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 8013 8014 if (VT == MVT::i32 && 8015 (EltVT == MVT::i8 || EltVT == MVT::i16) && 8016 TLI.isTypeLegal(Vec.getValueType()) && 8017 isa<ConstantSDNode>(Lane)) { 8018 8019 unsigned Opc = 0; 8020 switch (N->getOpcode()) { 8021 default: llvm_unreachable("unexpected opcode"); 8022 case ISD::SIGN_EXTEND: 8023 Opc = ARMISD::VGETLANEs; 8024 break; 8025 case ISD::ZERO_EXTEND: 8026 case ISD::ANY_EXTEND: 8027 Opc = ARMISD::VGETLANEu; 8028 break; 8029 } 8030 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane); 8031 } 8032 } 8033 8034 return SDValue(); 8035} 8036 8037/// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC 8038/// to match f32 max/min patterns to use NEON vmax/vmin instructions. 8039static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG, 8040 const ARMSubtarget *ST) { 8041 // If the target supports NEON, try to use vmax/vmin instructions for f32 8042 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set, 8043 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is 8044 // a NaN; only do the transformation when it matches that behavior. 8045 8046 // For now only do this when using NEON for FP operations; if using VFP, it 8047 // is not obvious that the benefit outweighs the cost of switching to the 8048 // NEON pipeline. 8049 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() || 8050 N->getValueType(0) != MVT::f32) 8051 return SDValue(); 8052 8053 SDValue CondLHS = N->getOperand(0); 8054 SDValue CondRHS = N->getOperand(1); 8055 SDValue LHS = N->getOperand(2); 8056 SDValue RHS = N->getOperand(3); 8057 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get(); 8058 8059 unsigned Opcode = 0; 8060 bool IsReversed; 8061 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) { 8062 IsReversed = false; // x CC y ? x : y 8063 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) { 8064 IsReversed = true ; // x CC y ? y : x 8065 } else { 8066 return SDValue(); 8067 } 8068 8069 bool IsUnordered; 8070 switch (CC) { 8071 default: break; 8072 case ISD::SETOLT: 8073 case ISD::SETOLE: 8074 case ISD::SETLT: 8075 case ISD::SETLE: 8076 case ISD::SETULT: 8077 case ISD::SETULE: 8078 // If LHS is NaN, an ordered comparison will be false and the result will 8079 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS 8080 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN. 8081 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE); 8082 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS)) 8083 break; 8084 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin 8085 // will return -0, so vmin can only be used for unsafe math or if one of 8086 // the operands is known to be nonzero. 8087 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) && 8088 !DAG.getTarget().Options.UnsafeFPMath && 8089 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 8090 break; 8091 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN; 8092 break; 8093 8094 case ISD::SETOGT: 8095 case ISD::SETOGE: 8096 case ISD::SETGT: 8097 case ISD::SETGE: 8098 case ISD::SETUGT: 8099 case ISD::SETUGE: 8100 // If LHS is NaN, an ordered comparison will be false and the result will 8101 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS 8102 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN. 8103 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE); 8104 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS)) 8105 break; 8106 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax 8107 // will return +0, so vmax can only be used for unsafe math or if one of 8108 // the operands is known to be nonzero. 8109 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) && 8110 !DAG.getTarget().Options.UnsafeFPMath && 8111 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 8112 break; 8113 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX; 8114 break; 8115 } 8116 8117 if (!Opcode) 8118 return SDValue(); 8119 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS); 8120} 8121 8122/// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV. 8123SDValue 8124ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const { 8125 SDValue Cmp = N->getOperand(4); 8126 if (Cmp.getOpcode() != ARMISD::CMPZ) 8127 // Only looking at EQ and NE cases. 8128 return SDValue(); 8129 8130 EVT VT = N->getValueType(0); 8131 DebugLoc dl = N->getDebugLoc(); 8132 SDValue LHS = Cmp.getOperand(0); 8133 SDValue RHS = Cmp.getOperand(1); 8134 SDValue FalseVal = N->getOperand(0); 8135 SDValue TrueVal = N->getOperand(1); 8136 SDValue ARMcc = N->getOperand(2); 8137 ARMCC::CondCodes CC = 8138 (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue(); 8139 8140 // Simplify 8141 // mov r1, r0 8142 // cmp r1, x 8143 // mov r0, y 8144 // moveq r0, x 8145 // to 8146 // cmp r0, x 8147 // movne r0, y 8148 // 8149 // mov r1, r0 8150 // cmp r1, x 8151 // mov r0, x 8152 // movne r0, y 8153 // to 8154 // cmp r0, x 8155 // movne r0, y 8156 /// FIXME: Turn this into a target neutral optimization? 8157 SDValue Res; 8158 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) { 8159 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc, 8160 N->getOperand(3), Cmp); 8161 } else if (CC == ARMCC::EQ && TrueVal == RHS) { 8162 SDValue ARMcc; 8163 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl); 8164 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc, 8165 N->getOperand(3), NewCmp); 8166 } 8167 8168 if (Res.getNode()) { 8169 APInt KnownZero, KnownOne; 8170 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 8171 DAG.ComputeMaskedBits(SDValue(N,0), Mask, KnownZero, KnownOne); 8172 // Capture demanded bits information that would be otherwise lost. 8173 if (KnownZero == 0xfffffffe) 8174 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, 8175 DAG.getValueType(MVT::i1)); 8176 else if (KnownZero == 0xffffff00) 8177 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, 8178 DAG.getValueType(MVT::i8)); 8179 else if (KnownZero == 0xffff0000) 8180 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, 8181 DAG.getValueType(MVT::i16)); 8182 } 8183 8184 return Res; 8185} 8186 8187SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N, 8188 DAGCombinerInfo &DCI) const { 8189 switch (N->getOpcode()) { 8190 default: break; 8191 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget); 8192 case ISD::SUB: return PerformSUBCombine(N, DCI); 8193 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget); 8194 case ISD::OR: return PerformORCombine(N, DCI, Subtarget); 8195 case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget); 8196 case ISD::AND: return PerformANDCombine(N, DCI, Subtarget); 8197 case ARMISD::BFI: return PerformBFICombine(N, DCI); 8198 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI); 8199 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG); 8200 case ISD::STORE: return PerformSTORECombine(N, DCI); 8201 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI); 8202 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI); 8203 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG); 8204 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI); 8205 case ISD::FP_TO_SINT: 8206 case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget); 8207 case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget); 8208 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG); 8209 case ISD::SHL: 8210 case ISD::SRA: 8211 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget); 8212 case ISD::SIGN_EXTEND: 8213 case ISD::ZERO_EXTEND: 8214 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget); 8215 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget); 8216 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG); 8217 case ARMISD::VLD2DUP: 8218 case ARMISD::VLD3DUP: 8219 case ARMISD::VLD4DUP: 8220 return CombineBaseUpdate(N, DCI); 8221 case ISD::INTRINSIC_VOID: 8222 case ISD::INTRINSIC_W_CHAIN: 8223 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) { 8224 case Intrinsic::arm_neon_vld1: 8225 case Intrinsic::arm_neon_vld2: 8226 case Intrinsic::arm_neon_vld3: 8227 case Intrinsic::arm_neon_vld4: 8228 case Intrinsic::arm_neon_vld2lane: 8229 case Intrinsic::arm_neon_vld3lane: 8230 case Intrinsic::arm_neon_vld4lane: 8231 case Intrinsic::arm_neon_vst1: 8232 case Intrinsic::arm_neon_vst2: 8233 case Intrinsic::arm_neon_vst3: 8234 case Intrinsic::arm_neon_vst4: 8235 case Intrinsic::arm_neon_vst2lane: 8236 case Intrinsic::arm_neon_vst3lane: 8237 case Intrinsic::arm_neon_vst4lane: 8238 return CombineBaseUpdate(N, DCI); 8239 default: break; 8240 } 8241 break; 8242 } 8243 return SDValue(); 8244} 8245 8246bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc, 8247 EVT VT) const { 8248 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE); 8249} 8250 8251bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { 8252 if (!Subtarget->allowsUnalignedMem()) 8253 return false; 8254 8255 switch (VT.getSimpleVT().SimpleTy) { 8256 default: 8257 return false; 8258 case MVT::i8: 8259 case MVT::i16: 8260 case MVT::i32: 8261 return true; 8262 // FIXME: VLD1 etc with standard alignment is legal. 8263 } 8264} 8265 8266static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign, 8267 unsigned AlignCheck) { 8268 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) && 8269 (DstAlign == 0 || DstAlign % AlignCheck == 0)); 8270} 8271 8272EVT ARMTargetLowering::getOptimalMemOpType(uint64_t Size, 8273 unsigned DstAlign, unsigned SrcAlign, 8274 bool IsZeroVal, 8275 bool MemcpyStrSrc, 8276 MachineFunction &MF) const { 8277 const Function *F = MF.getFunction(); 8278 8279 // See if we can use NEON instructions for this... 8280 if (IsZeroVal && 8281 !F->hasFnAttr(Attribute::NoImplicitFloat) && 8282 Subtarget->hasNEON()) { 8283 if (memOpAlign(SrcAlign, DstAlign, 16) && Size >= 16) { 8284 return MVT::v4i32; 8285 } else if (memOpAlign(SrcAlign, DstAlign, 8) && Size >= 8) { 8286 return MVT::v2i32; 8287 } 8288 } 8289 8290 // Lowering to i32/i16 if the size permits. 8291 if (Size >= 4) { 8292 return MVT::i32; 8293 } else if (Size >= 2) { 8294 return MVT::i16; 8295 } 8296 8297 // Let the target-independent logic figure it out. 8298 return MVT::Other; 8299} 8300 8301static bool isLegalT1AddressImmediate(int64_t V, EVT VT) { 8302 if (V < 0) 8303 return false; 8304 8305 unsigned Scale = 1; 8306 switch (VT.getSimpleVT().SimpleTy) { 8307 default: return false; 8308 case MVT::i1: 8309 case MVT::i8: 8310 // Scale == 1; 8311 break; 8312 case MVT::i16: 8313 // Scale == 2; 8314 Scale = 2; 8315 break; 8316 case MVT::i32: 8317 // Scale == 4; 8318 Scale = 4; 8319 break; 8320 } 8321 8322 if ((V & (Scale - 1)) != 0) 8323 return false; 8324 V /= Scale; 8325 return V == (V & ((1LL << 5) - 1)); 8326} 8327 8328static bool isLegalT2AddressImmediate(int64_t V, EVT VT, 8329 const ARMSubtarget *Subtarget) { 8330 bool isNeg = false; 8331 if (V < 0) { 8332 isNeg = true; 8333 V = - V; 8334 } 8335 8336 switch (VT.getSimpleVT().SimpleTy) { 8337 default: return false; 8338 case MVT::i1: 8339 case MVT::i8: 8340 case MVT::i16: 8341 case MVT::i32: 8342 // + imm12 or - imm8 8343 if (isNeg) 8344 return V == (V & ((1LL << 8) - 1)); 8345 return V == (V & ((1LL << 12) - 1)); 8346 case MVT::f32: 8347 case MVT::f64: 8348 // Same as ARM mode. FIXME: NEON? 8349 if (!Subtarget->hasVFP2()) 8350 return false; 8351 if ((V & 3) != 0) 8352 return false; 8353 V >>= 2; 8354 return V == (V & ((1LL << 8) - 1)); 8355 } 8356} 8357 8358/// isLegalAddressImmediate - Return true if the integer value can be used 8359/// as the offset of the target addressing mode for load / store of the 8360/// given type. 8361static bool isLegalAddressImmediate(int64_t V, EVT VT, 8362 const ARMSubtarget *Subtarget) { 8363 if (V == 0) 8364 return true; 8365 8366 if (!VT.isSimple()) 8367 return false; 8368 8369 if (Subtarget->isThumb1Only()) 8370 return isLegalT1AddressImmediate(V, VT); 8371 else if (Subtarget->isThumb2()) 8372 return isLegalT2AddressImmediate(V, VT, Subtarget); 8373 8374 // ARM mode. 8375 if (V < 0) 8376 V = - V; 8377 switch (VT.getSimpleVT().SimpleTy) { 8378 default: return false; 8379 case MVT::i1: 8380 case MVT::i8: 8381 case MVT::i32: 8382 // +- imm12 8383 return V == (V & ((1LL << 12) - 1)); 8384 case MVT::i16: 8385 // +- imm8 8386 return V == (V & ((1LL << 8) - 1)); 8387 case MVT::f32: 8388 case MVT::f64: 8389 if (!Subtarget->hasVFP2()) // FIXME: NEON? 8390 return false; 8391 if ((V & 3) != 0) 8392 return false; 8393 V >>= 2; 8394 return V == (V & ((1LL << 8) - 1)); 8395 } 8396} 8397 8398bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM, 8399 EVT VT) const { 8400 int Scale = AM.Scale; 8401 if (Scale < 0) 8402 return false; 8403 8404 switch (VT.getSimpleVT().SimpleTy) { 8405 default: return false; 8406 case MVT::i1: 8407 case MVT::i8: 8408 case MVT::i16: 8409 case MVT::i32: 8410 if (Scale == 1) 8411 return true; 8412 // r + r << imm 8413 Scale = Scale & ~1; 8414 return Scale == 2 || Scale == 4 || Scale == 8; 8415 case MVT::i64: 8416 // r + r 8417 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 8418 return true; 8419 return false; 8420 case MVT::isVoid: 8421 // Note, we allow "void" uses (basically, uses that aren't loads or 8422 // stores), because arm allows folding a scale into many arithmetic 8423 // operations. This should be made more precise and revisited later. 8424 8425 // Allow r << imm, but the imm has to be a multiple of two. 8426 if (Scale & 1) return false; 8427 return isPowerOf2_32(Scale); 8428 } 8429} 8430 8431/// isLegalAddressingMode - Return true if the addressing mode represented 8432/// by AM is legal for this target, for a load/store of the specified type. 8433bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM, 8434 Type *Ty) const { 8435 EVT VT = getValueType(Ty, true); 8436 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget)) 8437 return false; 8438 8439 // Can never fold addr of global into load/store. 8440 if (AM.BaseGV) 8441 return false; 8442 8443 switch (AM.Scale) { 8444 case 0: // no scale reg, must be "r+i" or "r", or "i". 8445 break; 8446 case 1: 8447 if (Subtarget->isThumb1Only()) 8448 return false; 8449 // FALL THROUGH. 8450 default: 8451 // ARM doesn't support any R+R*scale+imm addr modes. 8452 if (AM.BaseOffs) 8453 return false; 8454 8455 if (!VT.isSimple()) 8456 return false; 8457 8458 if (Subtarget->isThumb2()) 8459 return isLegalT2ScaledAddressingMode(AM, VT); 8460 8461 int Scale = AM.Scale; 8462 switch (VT.getSimpleVT().SimpleTy) { 8463 default: return false; 8464 case MVT::i1: 8465 case MVT::i8: 8466 case MVT::i32: 8467 if (Scale < 0) Scale = -Scale; 8468 if (Scale == 1) 8469 return true; 8470 // r + r << imm 8471 return isPowerOf2_32(Scale & ~1); 8472 case MVT::i16: 8473 case MVT::i64: 8474 // r + r 8475 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 8476 return true; 8477 return false; 8478 8479 case MVT::isVoid: 8480 // Note, we allow "void" uses (basically, uses that aren't loads or 8481 // stores), because arm allows folding a scale into many arithmetic 8482 // operations. This should be made more precise and revisited later. 8483 8484 // Allow r << imm, but the imm has to be a multiple of two. 8485 if (Scale & 1) return false; 8486 return isPowerOf2_32(Scale); 8487 } 8488 } 8489 return true; 8490} 8491 8492/// isLegalICmpImmediate - Return true if the specified immediate is legal 8493/// icmp immediate, that is the target has icmp instructions which can compare 8494/// a register against the immediate without having to materialize the 8495/// immediate into a register. 8496bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const { 8497 if (!Subtarget->isThumb()) 8498 return ARM_AM::getSOImmVal(Imm) != -1; 8499 if (Subtarget->isThumb2()) 8500 return ARM_AM::getT2SOImmVal(Imm) != -1; 8501 return Imm >= 0 && Imm <= 255; 8502} 8503 8504/// isLegalAddImmediate - Return true if the specified immediate is legal 8505/// add immediate, that is the target has add instructions which can add 8506/// a register with the immediate without having to materialize the 8507/// immediate into a register. 8508bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const { 8509 return ARM_AM::getSOImmVal(Imm) != -1; 8510} 8511 8512static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT, 8513 bool isSEXTLoad, SDValue &Base, 8514 SDValue &Offset, bool &isInc, 8515 SelectionDAG &DAG) { 8516 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 8517 return false; 8518 8519 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { 8520 // AddressingMode 3 8521 Base = Ptr->getOperand(0); 8522 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 8523 int RHSC = (int)RHS->getZExtValue(); 8524 if (RHSC < 0 && RHSC > -256) { 8525 assert(Ptr->getOpcode() == ISD::ADD); 8526 isInc = false; 8527 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 8528 return true; 8529 } 8530 } 8531 isInc = (Ptr->getOpcode() == ISD::ADD); 8532 Offset = Ptr->getOperand(1); 8533 return true; 8534 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) { 8535 // AddressingMode 2 8536 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 8537 int RHSC = (int)RHS->getZExtValue(); 8538 if (RHSC < 0 && RHSC > -0x1000) { 8539 assert(Ptr->getOpcode() == ISD::ADD); 8540 isInc = false; 8541 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 8542 Base = Ptr->getOperand(0); 8543 return true; 8544 } 8545 } 8546 8547 if (Ptr->getOpcode() == ISD::ADD) { 8548 isInc = true; 8549 ARM_AM::ShiftOpc ShOpcVal= 8550 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode()); 8551 if (ShOpcVal != ARM_AM::no_shift) { 8552 Base = Ptr->getOperand(1); 8553 Offset = Ptr->getOperand(0); 8554 } else { 8555 Base = Ptr->getOperand(0); 8556 Offset = Ptr->getOperand(1); 8557 } 8558 return true; 8559 } 8560 8561 isInc = (Ptr->getOpcode() == ISD::ADD); 8562 Base = Ptr->getOperand(0); 8563 Offset = Ptr->getOperand(1); 8564 return true; 8565 } 8566 8567 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store. 8568 return false; 8569} 8570 8571static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT, 8572 bool isSEXTLoad, SDValue &Base, 8573 SDValue &Offset, bool &isInc, 8574 SelectionDAG &DAG) { 8575 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 8576 return false; 8577 8578 Base = Ptr->getOperand(0); 8579 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 8580 int RHSC = (int)RHS->getZExtValue(); 8581 if (RHSC < 0 && RHSC > -0x100) { // 8 bits. 8582 assert(Ptr->getOpcode() == ISD::ADD); 8583 isInc = false; 8584 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 8585 return true; 8586 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero. 8587 isInc = Ptr->getOpcode() == ISD::ADD; 8588 Offset = DAG.getConstant(RHSC, RHS->getValueType(0)); 8589 return true; 8590 } 8591 } 8592 8593 return false; 8594} 8595 8596/// getPreIndexedAddressParts - returns true by value, base pointer and 8597/// offset pointer and addressing mode by reference if the node's address 8598/// can be legally represented as pre-indexed load / store address. 8599bool 8600ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 8601 SDValue &Offset, 8602 ISD::MemIndexedMode &AM, 8603 SelectionDAG &DAG) const { 8604 if (Subtarget->isThumb1Only()) 8605 return false; 8606 8607 EVT VT; 8608 SDValue Ptr; 8609 bool isSEXTLoad = false; 8610 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 8611 Ptr = LD->getBasePtr(); 8612 VT = LD->getMemoryVT(); 8613 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 8614 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 8615 Ptr = ST->getBasePtr(); 8616 VT = ST->getMemoryVT(); 8617 } else 8618 return false; 8619 8620 bool isInc; 8621 bool isLegal = false; 8622 if (Subtarget->isThumb2()) 8623 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, 8624 Offset, isInc, DAG); 8625 else 8626 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, 8627 Offset, isInc, DAG); 8628 if (!isLegal) 8629 return false; 8630 8631 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC; 8632 return true; 8633} 8634 8635/// getPostIndexedAddressParts - returns true by value, base pointer and 8636/// offset pointer and addressing mode by reference if this node can be 8637/// combined with a load / store to form a post-indexed load / store. 8638bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 8639 SDValue &Base, 8640 SDValue &Offset, 8641 ISD::MemIndexedMode &AM, 8642 SelectionDAG &DAG) const { 8643 if (Subtarget->isThumb1Only()) 8644 return false; 8645 8646 EVT VT; 8647 SDValue Ptr; 8648 bool isSEXTLoad = false; 8649 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 8650 VT = LD->getMemoryVT(); 8651 Ptr = LD->getBasePtr(); 8652 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 8653 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 8654 VT = ST->getMemoryVT(); 8655 Ptr = ST->getBasePtr(); 8656 } else 8657 return false; 8658 8659 bool isInc; 8660 bool isLegal = false; 8661 if (Subtarget->isThumb2()) 8662 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 8663 isInc, DAG); 8664 else 8665 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 8666 isInc, DAG); 8667 if (!isLegal) 8668 return false; 8669 8670 if (Ptr != Base) { 8671 // Swap base ptr and offset to catch more post-index load / store when 8672 // it's legal. In Thumb2 mode, offset must be an immediate. 8673 if (Ptr == Offset && Op->getOpcode() == ISD::ADD && 8674 !Subtarget->isThumb2()) 8675 std::swap(Base, Offset); 8676 8677 // Post-indexed load / store update the base pointer. 8678 if (Ptr != Base) 8679 return false; 8680 } 8681 8682 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; 8683 return true; 8684} 8685 8686void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 8687 const APInt &Mask, 8688 APInt &KnownZero, 8689 APInt &KnownOne, 8690 const SelectionDAG &DAG, 8691 unsigned Depth) const { 8692 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 8693 switch (Op.getOpcode()) { 8694 default: break; 8695 case ARMISD::CMOV: { 8696 // Bits are known zero/one if known on the LHS and RHS. 8697 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 8698 if (KnownZero == 0 && KnownOne == 0) return; 8699 8700 APInt KnownZeroRHS, KnownOneRHS; 8701 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, 8702 KnownZeroRHS, KnownOneRHS, Depth+1); 8703 KnownZero &= KnownZeroRHS; 8704 KnownOne &= KnownOneRHS; 8705 return; 8706 } 8707 } 8708} 8709 8710//===----------------------------------------------------------------------===// 8711// ARM Inline Assembly Support 8712//===----------------------------------------------------------------------===// 8713 8714bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const { 8715 // Looking for "rev" which is V6+. 8716 if (!Subtarget->hasV6Ops()) 8717 return false; 8718 8719 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 8720 std::string AsmStr = IA->getAsmString(); 8721 SmallVector<StringRef, 4> AsmPieces; 8722 SplitString(AsmStr, AsmPieces, ";\n"); 8723 8724 switch (AsmPieces.size()) { 8725 default: return false; 8726 case 1: 8727 AsmStr = AsmPieces[0]; 8728 AsmPieces.clear(); 8729 SplitString(AsmStr, AsmPieces, " \t,"); 8730 8731 // rev $0, $1 8732 if (AsmPieces.size() == 3 && 8733 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" && 8734 IA->getConstraintString().compare(0, 4, "=l,l") == 0) { 8735 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 8736 if (Ty && Ty->getBitWidth() == 32) 8737 return IntrinsicLowering::LowerToByteSwap(CI); 8738 } 8739 break; 8740 } 8741 8742 return false; 8743} 8744 8745/// getConstraintType - Given a constraint letter, return the type of 8746/// constraint it is for this target. 8747ARMTargetLowering::ConstraintType 8748ARMTargetLowering::getConstraintType(const std::string &Constraint) const { 8749 if (Constraint.size() == 1) { 8750 switch (Constraint[0]) { 8751 default: break; 8752 case 'l': return C_RegisterClass; 8753 case 'w': return C_RegisterClass; 8754 case 'h': return C_RegisterClass; 8755 case 'x': return C_RegisterClass; 8756 case 't': return C_RegisterClass; 8757 case 'j': return C_Other; // Constant for movw. 8758 // An address with a single base register. Due to the way we 8759 // currently handle addresses it is the same as an 'r' memory constraint. 8760 case 'Q': return C_Memory; 8761 } 8762 } else if (Constraint.size() == 2) { 8763 switch (Constraint[0]) { 8764 default: break; 8765 // All 'U+' constraints are addresses. 8766 case 'U': return C_Memory; 8767 } 8768 } 8769 return TargetLowering::getConstraintType(Constraint); 8770} 8771 8772/// Examine constraint type and operand type and determine a weight value. 8773/// This object must already have been set up with the operand type 8774/// and the current alternative constraint selected. 8775TargetLowering::ConstraintWeight 8776ARMTargetLowering::getSingleConstraintMatchWeight( 8777 AsmOperandInfo &info, const char *constraint) const { 8778 ConstraintWeight weight = CW_Invalid; 8779 Value *CallOperandVal = info.CallOperandVal; 8780 // If we don't have a value, we can't do a match, 8781 // but allow it at the lowest weight. 8782 if (CallOperandVal == NULL) 8783 return CW_Default; 8784 Type *type = CallOperandVal->getType(); 8785 // Look at the constraint type. 8786 switch (*constraint) { 8787 default: 8788 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 8789 break; 8790 case 'l': 8791 if (type->isIntegerTy()) { 8792 if (Subtarget->isThumb()) 8793 weight = CW_SpecificReg; 8794 else 8795 weight = CW_Register; 8796 } 8797 break; 8798 case 'w': 8799 if (type->isFloatingPointTy()) 8800 weight = CW_Register; 8801 break; 8802 } 8803 return weight; 8804} 8805 8806typedef std::pair<unsigned, const TargetRegisterClass*> RCPair; 8807RCPair 8808ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 8809 EVT VT) const { 8810 if (Constraint.size() == 1) { 8811 // GCC ARM Constraint Letters 8812 switch (Constraint[0]) { 8813 case 'l': // Low regs or general regs. 8814 if (Subtarget->isThumb()) 8815 return RCPair(0U, ARM::tGPRRegisterClass); 8816 else 8817 return RCPair(0U, ARM::GPRRegisterClass); 8818 case 'h': // High regs or no regs. 8819 if (Subtarget->isThumb()) 8820 return RCPair(0U, ARM::hGPRRegisterClass); 8821 break; 8822 case 'r': 8823 return RCPair(0U, ARM::GPRRegisterClass); 8824 case 'w': 8825 if (VT == MVT::f32) 8826 return RCPair(0U, ARM::SPRRegisterClass); 8827 if (VT.getSizeInBits() == 64) 8828 return RCPair(0U, ARM::DPRRegisterClass); 8829 if (VT.getSizeInBits() == 128) 8830 return RCPair(0U, ARM::QPRRegisterClass); 8831 break; 8832 case 'x': 8833 if (VT == MVT::f32) 8834 return RCPair(0U, ARM::SPR_8RegisterClass); 8835 if (VT.getSizeInBits() == 64) 8836 return RCPair(0U, ARM::DPR_8RegisterClass); 8837 if (VT.getSizeInBits() == 128) 8838 return RCPair(0U, ARM::QPR_8RegisterClass); 8839 break; 8840 case 't': 8841 if (VT == MVT::f32) 8842 return RCPair(0U, ARM::SPRRegisterClass); 8843 break; 8844 } 8845 } 8846 if (StringRef("{cc}").equals_lower(Constraint)) 8847 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass); 8848 8849 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 8850} 8851 8852/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 8853/// vector. If it is invalid, don't add anything to Ops. 8854void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 8855 std::string &Constraint, 8856 std::vector<SDValue>&Ops, 8857 SelectionDAG &DAG) const { 8858 SDValue Result(0, 0); 8859 8860 // Currently only support length 1 constraints. 8861 if (Constraint.length() != 1) return; 8862 8863 char ConstraintLetter = Constraint[0]; 8864 switch (ConstraintLetter) { 8865 default: break; 8866 case 'j': 8867 case 'I': case 'J': case 'K': case 'L': 8868 case 'M': case 'N': case 'O': 8869 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 8870 if (!C) 8871 return; 8872 8873 int64_t CVal64 = C->getSExtValue(); 8874 int CVal = (int) CVal64; 8875 // None of these constraints allow values larger than 32 bits. Check 8876 // that the value fits in an int. 8877 if (CVal != CVal64) 8878 return; 8879 8880 switch (ConstraintLetter) { 8881 case 'j': 8882 // Constant suitable for movw, must be between 0 and 8883 // 65535. 8884 if (Subtarget->hasV6T2Ops()) 8885 if (CVal >= 0 && CVal <= 65535) 8886 break; 8887 return; 8888 case 'I': 8889 if (Subtarget->isThumb1Only()) { 8890 // This must be a constant between 0 and 255, for ADD 8891 // immediates. 8892 if (CVal >= 0 && CVal <= 255) 8893 break; 8894 } else if (Subtarget->isThumb2()) { 8895 // A constant that can be used as an immediate value in a 8896 // data-processing instruction. 8897 if (ARM_AM::getT2SOImmVal(CVal) != -1) 8898 break; 8899 } else { 8900 // A constant that can be used as an immediate value in a 8901 // data-processing instruction. 8902 if (ARM_AM::getSOImmVal(CVal) != -1) 8903 break; 8904 } 8905 return; 8906 8907 case 'J': 8908 if (Subtarget->isThumb()) { // FIXME thumb2 8909 // This must be a constant between -255 and -1, for negated ADD 8910 // immediates. This can be used in GCC with an "n" modifier that 8911 // prints the negated value, for use with SUB instructions. It is 8912 // not useful otherwise but is implemented for compatibility. 8913 if (CVal >= -255 && CVal <= -1) 8914 break; 8915 } else { 8916 // This must be a constant between -4095 and 4095. It is not clear 8917 // what this constraint is intended for. Implemented for 8918 // compatibility with GCC. 8919 if (CVal >= -4095 && CVal <= 4095) 8920 break; 8921 } 8922 return; 8923 8924 case 'K': 8925 if (Subtarget->isThumb1Only()) { 8926 // A 32-bit value where only one byte has a nonzero value. Exclude 8927 // zero to match GCC. This constraint is used by GCC internally for 8928 // constants that can be loaded with a move/shift combination. 8929 // It is not useful otherwise but is implemented for compatibility. 8930 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal)) 8931 break; 8932 } else if (Subtarget->isThumb2()) { 8933 // A constant whose bitwise inverse can be used as an immediate 8934 // value in a data-processing instruction. This can be used in GCC 8935 // with a "B" modifier that prints the inverted value, for use with 8936 // BIC and MVN instructions. It is not useful otherwise but is 8937 // implemented for compatibility. 8938 if (ARM_AM::getT2SOImmVal(~CVal) != -1) 8939 break; 8940 } else { 8941 // A constant whose bitwise inverse can be used as an immediate 8942 // value in a data-processing instruction. This can be used in GCC 8943 // with a "B" modifier that prints the inverted value, for use with 8944 // BIC and MVN instructions. It is not useful otherwise but is 8945 // implemented for compatibility. 8946 if (ARM_AM::getSOImmVal(~CVal) != -1) 8947 break; 8948 } 8949 return; 8950 8951 case 'L': 8952 if (Subtarget->isThumb1Only()) { 8953 // This must be a constant between -7 and 7, 8954 // for 3-operand ADD/SUB immediate instructions. 8955 if (CVal >= -7 && CVal < 7) 8956 break; 8957 } else if (Subtarget->isThumb2()) { 8958 // A constant whose negation can be used as an immediate value in a 8959 // data-processing instruction. This can be used in GCC with an "n" 8960 // modifier that prints the negated value, for use with SUB 8961 // instructions. It is not useful otherwise but is implemented for 8962 // compatibility. 8963 if (ARM_AM::getT2SOImmVal(-CVal) != -1) 8964 break; 8965 } else { 8966 // A constant whose negation can be used as an immediate value in a 8967 // data-processing instruction. This can be used in GCC with an "n" 8968 // modifier that prints the negated value, for use with SUB 8969 // instructions. It is not useful otherwise but is implemented for 8970 // compatibility. 8971 if (ARM_AM::getSOImmVal(-CVal) != -1) 8972 break; 8973 } 8974 return; 8975 8976 case 'M': 8977 if (Subtarget->isThumb()) { // FIXME thumb2 8978 // This must be a multiple of 4 between 0 and 1020, for 8979 // ADD sp + immediate. 8980 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0)) 8981 break; 8982 } else { 8983 // A power of two or a constant between 0 and 32. This is used in 8984 // GCC for the shift amount on shifted register operands, but it is 8985 // useful in general for any shift amounts. 8986 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0)) 8987 break; 8988 } 8989 return; 8990 8991 case 'N': 8992 if (Subtarget->isThumb()) { // FIXME thumb2 8993 // This must be a constant between 0 and 31, for shift amounts. 8994 if (CVal >= 0 && CVal <= 31) 8995 break; 8996 } 8997 return; 8998 8999 case 'O': 9000 if (Subtarget->isThumb()) { // FIXME thumb2 9001 // This must be a multiple of 4 between -508 and 508, for 9002 // ADD/SUB sp = sp + immediate. 9003 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0)) 9004 break; 9005 } 9006 return; 9007 } 9008 Result = DAG.getTargetConstant(CVal, Op.getValueType()); 9009 break; 9010 } 9011 9012 if (Result.getNode()) { 9013 Ops.push_back(Result); 9014 return; 9015 } 9016 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 9017} 9018 9019bool 9020ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 9021 // The ARM target isn't yet aware of offsets. 9022 return false; 9023} 9024 9025bool ARM::isBitFieldInvertedMask(unsigned v) { 9026 if (v == 0xffffffff) 9027 return 0; 9028 // there can be 1's on either or both "outsides", all the "inside" 9029 // bits must be 0's 9030 unsigned int lsb = 0, msb = 31; 9031 while (v & (1 << msb)) --msb; 9032 while (v & (1 << lsb)) ++lsb; 9033 for (unsigned int i = lsb; i <= msb; ++i) { 9034 if (v & (1 << i)) 9035 return 0; 9036 } 9037 return 1; 9038} 9039 9040/// isFPImmLegal - Returns true if the target can instruction select the 9041/// specified FP immediate natively. If false, the legalizer will 9042/// materialize the FP immediate as a load from a constant pool. 9043bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 9044 if (!Subtarget->hasVFP3()) 9045 return false; 9046 if (VT == MVT::f32) 9047 return ARM_AM::getFP32Imm(Imm) != -1; 9048 if (VT == MVT::f64) 9049 return ARM_AM::getFP64Imm(Imm) != -1; 9050 return false; 9051} 9052 9053/// getTgtMemIntrinsic - Represent NEON load and store intrinsics as 9054/// MemIntrinsicNodes. The associated MachineMemOperands record the alignment 9055/// specified in the intrinsic calls. 9056bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, 9057 const CallInst &I, 9058 unsigned Intrinsic) const { 9059 switch (Intrinsic) { 9060 case Intrinsic::arm_neon_vld1: 9061 case Intrinsic::arm_neon_vld2: 9062 case Intrinsic::arm_neon_vld3: 9063 case Intrinsic::arm_neon_vld4: 9064 case Intrinsic::arm_neon_vld2lane: 9065 case Intrinsic::arm_neon_vld3lane: 9066 case Intrinsic::arm_neon_vld4lane: { 9067 Info.opc = ISD::INTRINSIC_W_CHAIN; 9068 // Conservatively set memVT to the entire set of vectors loaded. 9069 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8; 9070 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); 9071 Info.ptrVal = I.getArgOperand(0); 9072 Info.offset = 0; 9073 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1); 9074 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue(); 9075 Info.vol = false; // volatile loads with NEON intrinsics not supported 9076 Info.readMem = true; 9077 Info.writeMem = false; 9078 return true; 9079 } 9080 case Intrinsic::arm_neon_vst1: 9081 case Intrinsic::arm_neon_vst2: 9082 case Intrinsic::arm_neon_vst3: 9083 case Intrinsic::arm_neon_vst4: 9084 case Intrinsic::arm_neon_vst2lane: 9085 case Intrinsic::arm_neon_vst3lane: 9086 case Intrinsic::arm_neon_vst4lane: { 9087 Info.opc = ISD::INTRINSIC_VOID; 9088 // Conservatively set memVT to the entire set of vectors stored. 9089 unsigned NumElts = 0; 9090 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) { 9091 Type *ArgTy = I.getArgOperand(ArgI)->getType(); 9092 if (!ArgTy->isVectorTy()) 9093 break; 9094 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8; 9095 } 9096 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); 9097 Info.ptrVal = I.getArgOperand(0); 9098 Info.offset = 0; 9099 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1); 9100 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue(); 9101 Info.vol = false; // volatile stores with NEON intrinsics not supported 9102 Info.readMem = false; 9103 Info.writeMem = true; 9104 return true; 9105 } 9106 case Intrinsic::arm_strexd: { 9107 Info.opc = ISD::INTRINSIC_W_CHAIN; 9108 Info.memVT = MVT::i64; 9109 Info.ptrVal = I.getArgOperand(2); 9110 Info.offset = 0; 9111 Info.align = 8; 9112 Info.vol = true; 9113 Info.readMem = false; 9114 Info.writeMem = true; 9115 return true; 9116 } 9117 case Intrinsic::arm_ldrexd: { 9118 Info.opc = ISD::INTRINSIC_W_CHAIN; 9119 Info.memVT = MVT::i64; 9120 Info.ptrVal = I.getArgOperand(0); 9121 Info.offset = 0; 9122 Info.align = 8; 9123 Info.vol = true; 9124 Info.readMem = true; 9125 Info.writeMem = false; 9126 return true; 9127 } 9128 default: 9129 break; 9130 } 9131 9132 return false; 9133} 9134