ARMISelLowering.cpp revision f1083d4139720b41457528f81919d9587e442862
1//===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "arm-isel" 16#include "ARM.h" 17#include "ARMCallingConv.h" 18#include "ARMConstantPoolValue.h" 19#include "ARMISelLowering.h" 20#include "ARMMachineFunctionInfo.h" 21#include "ARMPerfectShuffle.h" 22#include "ARMRegisterInfo.h" 23#include "ARMSubtarget.h" 24#include "ARMTargetMachine.h" 25#include "ARMTargetObjectFile.h" 26#include "MCTargetDesc/ARMAddressingModes.h" 27#include "llvm/CallingConv.h" 28#include "llvm/Constants.h" 29#include "llvm/Function.h" 30#include "llvm/GlobalValue.h" 31#include "llvm/Instruction.h" 32#include "llvm/Instructions.h" 33#include "llvm/Intrinsics.h" 34#include "llvm/Type.h" 35#include "llvm/CodeGen/CallingConvLower.h" 36#include "llvm/CodeGen/IntrinsicLowering.h" 37#include "llvm/CodeGen/MachineBasicBlock.h" 38#include "llvm/CodeGen/MachineFrameInfo.h" 39#include "llvm/CodeGen/MachineFunction.h" 40#include "llvm/CodeGen/MachineInstrBuilder.h" 41#include "llvm/CodeGen/MachineModuleInfo.h" 42#include "llvm/CodeGen/MachineRegisterInfo.h" 43#include "llvm/CodeGen/PseudoSourceValue.h" 44#include "llvm/CodeGen/SelectionDAG.h" 45#include "llvm/MC/MCSectionMachO.h" 46#include "llvm/Target/TargetOptions.h" 47#include "llvm/ADT/VectorExtras.h" 48#include "llvm/ADT/StringExtras.h" 49#include "llvm/ADT/Statistic.h" 50#include "llvm/Support/CommandLine.h" 51#include "llvm/Support/ErrorHandling.h" 52#include "llvm/Support/MathExtras.h" 53#include "llvm/Support/raw_ostream.h" 54#include <sstream> 55using namespace llvm; 56 57STATISTIC(NumTailCalls, "Number of tail calls"); 58STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt"); 59 60// This option should go away when tail calls fully work. 61static cl::opt<bool> 62EnableARMTailCalls("arm-tail-calls", cl::Hidden, 63 cl::desc("Generate tail calls (TEMPORARY OPTION)."), 64 cl::init(false)); 65 66cl::opt<bool> 67EnableARMLongCalls("arm-long-calls", cl::Hidden, 68 cl::desc("Generate calls via indirect call instructions"), 69 cl::init(false)); 70 71static cl::opt<bool> 72ARMInterworking("arm-interworking", cl::Hidden, 73 cl::desc("Enable / disable ARM interworking (for debugging only)"), 74 cl::init(true)); 75 76namespace llvm { 77 class ARMCCState : public CCState { 78 public: 79 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF, 80 const TargetMachine &TM, SmallVector<CCValAssign, 16> &locs, 81 LLVMContext &C, ParmContext PC) 82 : CCState(CC, isVarArg, MF, TM, locs, C) { 83 assert(((PC == Call) || (PC == Prologue)) && 84 "ARMCCState users must specify whether their context is call" 85 "or prologue generation."); 86 CallOrPrologue = PC; 87 } 88 }; 89} 90 91// The APCS parameter registers. 92static const unsigned GPRArgRegs[] = { 93 ARM::R0, ARM::R1, ARM::R2, ARM::R3 94}; 95 96void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT, 97 EVT PromotedBitwiseVT) { 98 if (VT != PromotedLdStVT) { 99 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote); 100 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(), 101 PromotedLdStVT.getSimpleVT()); 102 103 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote); 104 AddPromotedToType (ISD::STORE, VT.getSimpleVT(), 105 PromotedLdStVT.getSimpleVT()); 106 } 107 108 EVT ElemTy = VT.getVectorElementType(); 109 if (ElemTy != MVT::i64 && ElemTy != MVT::f64) 110 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom); 111 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom); 112 if (ElemTy != MVT::i32) { 113 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand); 114 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand); 115 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand); 116 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand); 117 } 118 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom); 119 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom); 120 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal); 121 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Legal); 122 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand); 123 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand); 124 if (VT.isInteger()) { 125 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom); 126 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom); 127 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom); 128 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand); 129 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand); 130 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 131 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 132 setTruncStoreAction(VT.getSimpleVT(), 133 (MVT::SimpleValueType)InnerVT, Expand); 134 } 135 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand); 136 137 // Promote all bit-wise operations. 138 if (VT.isInteger() && VT != PromotedBitwiseVT) { 139 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote); 140 AddPromotedToType (ISD::AND, VT.getSimpleVT(), 141 PromotedBitwiseVT.getSimpleVT()); 142 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote); 143 AddPromotedToType (ISD::OR, VT.getSimpleVT(), 144 PromotedBitwiseVT.getSimpleVT()); 145 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote); 146 AddPromotedToType (ISD::XOR, VT.getSimpleVT(), 147 PromotedBitwiseVT.getSimpleVT()); 148 } 149 150 // Neon does not support vector divide/remainder operations. 151 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand); 152 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand); 153 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand); 154 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand); 155 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand); 156 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand); 157} 158 159void ARMTargetLowering::addDRTypeForNEON(EVT VT) { 160 addRegisterClass(VT, ARM::DPRRegisterClass); 161 addTypeForNEON(VT, MVT::f64, MVT::v2i32); 162} 163 164void ARMTargetLowering::addQRTypeForNEON(EVT VT) { 165 addRegisterClass(VT, ARM::QPRRegisterClass); 166 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32); 167} 168 169static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) { 170 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin()) 171 return new TargetLoweringObjectFileMachO(); 172 173 return new ARMElfTargetObjectFile(); 174} 175 176ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) 177 : TargetLowering(TM, createTLOF(TM)) { 178 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 179 RegInfo = TM.getRegisterInfo(); 180 Itins = TM.getInstrItineraryData(); 181 182 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 183 184 if (Subtarget->isTargetDarwin()) { 185 // Uses VFP for Thumb libfuncs if available. 186 if (Subtarget->isThumb() && Subtarget->hasVFP2()) { 187 // Single-precision floating-point arithmetic. 188 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp"); 189 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp"); 190 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp"); 191 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp"); 192 193 // Double-precision floating-point arithmetic. 194 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp"); 195 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp"); 196 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp"); 197 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp"); 198 199 // Single-precision comparisons. 200 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp"); 201 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp"); 202 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp"); 203 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp"); 204 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp"); 205 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp"); 206 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp"); 207 setLibcallName(RTLIB::O_F32, "__unordsf2vfp"); 208 209 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 210 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE); 211 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 212 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 213 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 214 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 215 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 216 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 217 218 // Double-precision comparisons. 219 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp"); 220 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp"); 221 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp"); 222 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp"); 223 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp"); 224 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp"); 225 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp"); 226 setLibcallName(RTLIB::O_F64, "__unorddf2vfp"); 227 228 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 229 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE); 230 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 231 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 232 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 233 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 234 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 235 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 236 237 // Floating-point to integer conversions. 238 // i64 conversions are done via library routines even when generating VFP 239 // instructions, so use the same ones. 240 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp"); 241 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp"); 242 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp"); 243 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp"); 244 245 // Conversions between floating types. 246 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp"); 247 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp"); 248 249 // Integer to floating-point conversions. 250 // i64 conversions are done via library routines even when generating VFP 251 // instructions, so use the same ones. 252 // FIXME: There appears to be some naming inconsistency in ARM libgcc: 253 // e.g., __floatunsidf vs. __floatunssidfvfp. 254 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp"); 255 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp"); 256 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp"); 257 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp"); 258 } 259 } 260 261 // These libcalls are not available in 32-bit. 262 setLibcallName(RTLIB::SHL_I128, 0); 263 setLibcallName(RTLIB::SRL_I128, 0); 264 setLibcallName(RTLIB::SRA_I128, 0); 265 266 if (Subtarget->isAAPCS_ABI()) { 267 // Double-precision floating-point arithmetic helper functions 268 // RTABI chapter 4.1.2, Table 2 269 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd"); 270 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv"); 271 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul"); 272 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub"); 273 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS); 274 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS); 275 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS); 276 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS); 277 278 // Double-precision floating-point comparison helper functions 279 // RTABI chapter 4.1.2, Table 3 280 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq"); 281 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 282 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq"); 283 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ); 284 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt"); 285 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 286 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple"); 287 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 288 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge"); 289 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 290 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt"); 291 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 292 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun"); 293 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 294 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun"); 295 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 296 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS); 297 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS); 298 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS); 299 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS); 300 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS); 301 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS); 302 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS); 303 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS); 304 305 // Single-precision floating-point arithmetic helper functions 306 // RTABI chapter 4.1.2, Table 4 307 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd"); 308 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv"); 309 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul"); 310 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub"); 311 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS); 312 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS); 313 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS); 314 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS); 315 316 // Single-precision floating-point comparison helper functions 317 // RTABI chapter 4.1.2, Table 5 318 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq"); 319 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 320 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq"); 321 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ); 322 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt"); 323 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 324 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple"); 325 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 326 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge"); 327 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 328 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt"); 329 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 330 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun"); 331 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 332 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun"); 333 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 334 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS); 335 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS); 336 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS); 337 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS); 338 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS); 339 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS); 340 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS); 341 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS); 342 343 // Floating-point to integer conversions. 344 // RTABI chapter 4.1.2, Table 6 345 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz"); 346 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz"); 347 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz"); 348 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz"); 349 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz"); 350 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz"); 351 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz"); 352 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz"); 353 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS); 354 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS); 355 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS); 356 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS); 357 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS); 358 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS); 359 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS); 360 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS); 361 362 // Conversions between floating types. 363 // RTABI chapter 4.1.2, Table 7 364 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f"); 365 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d"); 366 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS); 367 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS); 368 369 // Integer to floating-point conversions. 370 // RTABI chapter 4.1.2, Table 8 371 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d"); 372 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d"); 373 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d"); 374 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d"); 375 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f"); 376 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f"); 377 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f"); 378 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f"); 379 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS); 380 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS); 381 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS); 382 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS); 383 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS); 384 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS); 385 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS); 386 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS); 387 388 // Long long helper functions 389 // RTABI chapter 4.2, Table 9 390 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul"); 391 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod"); 392 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod"); 393 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl"); 394 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr"); 395 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr"); 396 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS); 397 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS); 398 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS); 399 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS); 400 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS); 401 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS); 402 403 // Integer division functions 404 // RTABI chapter 4.3.1 405 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv"); 406 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv"); 407 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv"); 408 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv"); 409 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv"); 410 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv"); 411 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS); 412 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS); 413 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS); 414 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS); 415 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS); 416 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS); 417 418 // Memory operations 419 // RTABI chapter 4.3.4 420 setLibcallName(RTLIB::MEMCPY, "__aeabi_memcpy"); 421 setLibcallName(RTLIB::MEMMOVE, "__aeabi_memmove"); 422 setLibcallName(RTLIB::MEMSET, "__aeabi_memset"); 423 } 424 425 // Use divmod compiler-rt calls for iOS 5.0 and later. 426 if (Subtarget->getTargetTriple().getOS() == Triple::IOS && 427 !Subtarget->getTargetTriple().isOSVersionLT(5, 0)) { 428 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4"); 429 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4"); 430 } 431 432 if (Subtarget->isThumb1Only()) 433 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass); 434 else 435 addRegisterClass(MVT::i32, ARM::GPRRegisterClass); 436 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { 437 addRegisterClass(MVT::f32, ARM::SPRRegisterClass); 438 if (!Subtarget->isFPOnlySP()) 439 addRegisterClass(MVT::f64, ARM::DPRRegisterClass); 440 441 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 442 } 443 444 if (Subtarget->hasNEON()) { 445 addDRTypeForNEON(MVT::v2f32); 446 addDRTypeForNEON(MVT::v8i8); 447 addDRTypeForNEON(MVT::v4i16); 448 addDRTypeForNEON(MVT::v2i32); 449 addDRTypeForNEON(MVT::v1i64); 450 451 addQRTypeForNEON(MVT::v4f32); 452 addQRTypeForNEON(MVT::v2f64); 453 addQRTypeForNEON(MVT::v16i8); 454 addQRTypeForNEON(MVT::v8i16); 455 addQRTypeForNEON(MVT::v4i32); 456 addQRTypeForNEON(MVT::v2i64); 457 458 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but 459 // neither Neon nor VFP support any arithmetic operations on it. 460 setOperationAction(ISD::FADD, MVT::v2f64, Expand); 461 setOperationAction(ISD::FSUB, MVT::v2f64, Expand); 462 setOperationAction(ISD::FMUL, MVT::v2f64, Expand); 463 setOperationAction(ISD::FDIV, MVT::v2f64, Expand); 464 setOperationAction(ISD::FREM, MVT::v2f64, Expand); 465 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand); 466 setOperationAction(ISD::SETCC, MVT::v2f64, Expand); 467 setOperationAction(ISD::FNEG, MVT::v2f64, Expand); 468 setOperationAction(ISD::FABS, MVT::v2f64, Expand); 469 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand); 470 setOperationAction(ISD::FSIN, MVT::v2f64, Expand); 471 setOperationAction(ISD::FCOS, MVT::v2f64, Expand); 472 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand); 473 setOperationAction(ISD::FPOW, MVT::v2f64, Expand); 474 setOperationAction(ISD::FLOG, MVT::v2f64, Expand); 475 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand); 476 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand); 477 setOperationAction(ISD::FEXP, MVT::v2f64, Expand); 478 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand); 479 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand); 480 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand); 481 setOperationAction(ISD::FRINT, MVT::v2f64, Expand); 482 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand); 483 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand); 484 485 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand); 486 487 // Neon does not support some operations on v1i64 and v2i64 types. 488 setOperationAction(ISD::MUL, MVT::v1i64, Expand); 489 // Custom handling for some quad-vector types to detect VMULL. 490 setOperationAction(ISD::MUL, MVT::v8i16, Custom); 491 setOperationAction(ISD::MUL, MVT::v4i32, Custom); 492 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 493 // Custom handling for some vector types to avoid expensive expansions 494 setOperationAction(ISD::SDIV, MVT::v4i16, Custom); 495 setOperationAction(ISD::SDIV, MVT::v8i8, Custom); 496 setOperationAction(ISD::UDIV, MVT::v4i16, Custom); 497 setOperationAction(ISD::UDIV, MVT::v8i8, Custom); 498 setOperationAction(ISD::SETCC, MVT::v1i64, Expand); 499 setOperationAction(ISD::SETCC, MVT::v2i64, Expand); 500 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with 501 // a destination type that is wider than the source. 502 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom); 503 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom); 504 505 setTargetDAGCombine(ISD::INTRINSIC_VOID); 506 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN); 507 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); 508 setTargetDAGCombine(ISD::SHL); 509 setTargetDAGCombine(ISD::SRL); 510 setTargetDAGCombine(ISD::SRA); 511 setTargetDAGCombine(ISD::SIGN_EXTEND); 512 setTargetDAGCombine(ISD::ZERO_EXTEND); 513 setTargetDAGCombine(ISD::ANY_EXTEND); 514 setTargetDAGCombine(ISD::SELECT_CC); 515 setTargetDAGCombine(ISD::BUILD_VECTOR); 516 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 517 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT); 518 setTargetDAGCombine(ISD::STORE); 519 setTargetDAGCombine(ISD::FP_TO_SINT); 520 setTargetDAGCombine(ISD::FP_TO_UINT); 521 setTargetDAGCombine(ISD::FDIV); 522 } 523 524 computeRegisterProperties(); 525 526 // ARM does not have f32 extending load. 527 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 528 529 // ARM does not have i1 sign extending load. 530 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 531 532 // ARM supports all 4 flavors of integer indexed load / store. 533 if (!Subtarget->isThumb1Only()) { 534 for (unsigned im = (unsigned)ISD::PRE_INC; 535 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { 536 setIndexedLoadAction(im, MVT::i1, Legal); 537 setIndexedLoadAction(im, MVT::i8, Legal); 538 setIndexedLoadAction(im, MVT::i16, Legal); 539 setIndexedLoadAction(im, MVT::i32, Legal); 540 setIndexedStoreAction(im, MVT::i1, Legal); 541 setIndexedStoreAction(im, MVT::i8, Legal); 542 setIndexedStoreAction(im, MVT::i16, Legal); 543 setIndexedStoreAction(im, MVT::i32, Legal); 544 } 545 } 546 547 // i64 operation support. 548 setOperationAction(ISD::MUL, MVT::i64, Expand); 549 setOperationAction(ISD::MULHU, MVT::i32, Expand); 550 if (Subtarget->isThumb1Only()) { 551 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 552 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 553 } 554 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops() 555 || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP())) 556 setOperationAction(ISD::MULHS, MVT::i32, Expand); 557 558 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); 559 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); 560 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); 561 setOperationAction(ISD::SRL, MVT::i64, Custom); 562 setOperationAction(ISD::SRA, MVT::i64, Custom); 563 564 if (!Subtarget->isThumb1Only()) { 565 // FIXME: We should do this for Thumb1 as well. 566 setOperationAction(ISD::ADDC, MVT::i32, Custom); 567 setOperationAction(ISD::ADDE, MVT::i32, Custom); 568 setOperationAction(ISD::SUBC, MVT::i32, Custom); 569 setOperationAction(ISD::SUBE, MVT::i32, Custom); 570 } 571 572 // ARM does not have ROTL. 573 setOperationAction(ISD::ROTL, MVT::i32, Expand); 574 setOperationAction(ISD::CTTZ, MVT::i32, Custom); 575 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 576 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) 577 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 578 579 // Only ARMv6 has BSWAP. 580 if (!Subtarget->hasV6Ops()) 581 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 582 583 // These are expanded into libcalls. 584 if (!Subtarget->hasDivide() || !Subtarget->isThumb2()) { 585 // v7M has a hardware divider 586 setOperationAction(ISD::SDIV, MVT::i32, Expand); 587 setOperationAction(ISD::UDIV, MVT::i32, Expand); 588 } 589 setOperationAction(ISD::SREM, MVT::i32, Expand); 590 setOperationAction(ISD::UREM, MVT::i32, Expand); 591 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 592 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 593 594 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 595 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 596 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom); 597 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 598 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 599 600 setOperationAction(ISD::TRAP, MVT::Other, Legal); 601 602 // Use the default implementation. 603 setOperationAction(ISD::VASTART, MVT::Other, Custom); 604 setOperationAction(ISD::VAARG, MVT::Other, Expand); 605 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 606 setOperationAction(ISD::VAEND, MVT::Other, Expand); 607 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 608 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 609 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 610 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 611 setExceptionPointerRegister(ARM::R0); 612 setExceptionSelectorRegister(ARM::R1); 613 614 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); 615 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use 616 // the default expansion. 617 // FIXME: This should be checking for v6k, not just v6. 618 if (Subtarget->hasDataBarrier() || 619 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) { 620 // membarrier needs custom lowering; the rest are legal and handled 621 // normally. 622 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); 623 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 624 // Custom lowering for 64-bit ops 625 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 626 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 627 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 628 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 629 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 630 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 631 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom); 632 // Automatically insert fences (dmb ist) around ATOMIC_SWAP etc. 633 setInsertFencesForAtomic(true); 634 } else { 635 // Set them all for expansion, which will force libcalls. 636 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 637 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); 638 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand); 639 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand); 640 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand); 641 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand); 642 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand); 643 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand); 644 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand); 645 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand); 646 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand); 647 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand); 648 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand); 649 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand); 650 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the 651 // Unordered/Monotonic case. 652 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom); 653 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom); 654 // Since the libcalls include locking, fold in the fences 655 setShouldFoldAtomicFences(true); 656 } 657 658 setOperationAction(ISD::PREFETCH, MVT::Other, Custom); 659 660 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes. 661 if (!Subtarget->hasV6Ops()) { 662 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 663 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 664 } 665 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 666 667 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { 668 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR 669 // iff target supports vfp2. 670 setOperationAction(ISD::BITCAST, MVT::i64, Custom); 671 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); 672 } 673 674 // We want to custom lower some of our intrinsics. 675 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 676 if (Subtarget->isTargetDarwin()) { 677 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom); 678 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom); 679 setOperationAction(ISD::EH_SJLJ_DISPATCHSETUP, MVT::Other, Custom); 680 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume"); 681 } 682 683 setOperationAction(ISD::SETCC, MVT::i32, Expand); 684 setOperationAction(ISD::SETCC, MVT::f32, Expand); 685 setOperationAction(ISD::SETCC, MVT::f64, Expand); 686 setOperationAction(ISD::SELECT, MVT::i32, Custom); 687 setOperationAction(ISD::SELECT, MVT::f32, Custom); 688 setOperationAction(ISD::SELECT, MVT::f64, Custom); 689 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 690 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 691 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 692 693 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 694 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 695 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 696 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 697 setOperationAction(ISD::BR_JT, MVT::Other, Custom); 698 699 // We don't support sin/cos/fmod/copysign/pow 700 setOperationAction(ISD::FSIN, MVT::f64, Expand); 701 setOperationAction(ISD::FSIN, MVT::f32, Expand); 702 setOperationAction(ISD::FCOS, MVT::f32, Expand); 703 setOperationAction(ISD::FCOS, MVT::f64, Expand); 704 setOperationAction(ISD::FREM, MVT::f64, Expand); 705 setOperationAction(ISD::FREM, MVT::f32, Expand); 706 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { 707 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 708 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 709 } 710 setOperationAction(ISD::FPOW, MVT::f64, Expand); 711 setOperationAction(ISD::FPOW, MVT::f32, Expand); 712 713 setOperationAction(ISD::FMA, MVT::f64, Expand); 714 setOperationAction(ISD::FMA, MVT::f32, Expand); 715 716 // Various VFP goodness 717 if (!UseSoftFloat && !Subtarget->isThumb1Only()) { 718 // int <-> fp are custom expanded into bit_convert + ARMISD ops. 719 if (Subtarget->hasVFP2()) { 720 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 721 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 722 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 723 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 724 } 725 // Special handling for half-precision FP. 726 if (!Subtarget->hasFP16()) { 727 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand); 728 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand); 729 } 730 } 731 732 // We have target-specific dag combine patterns for the following nodes: 733 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine 734 setTargetDAGCombine(ISD::ADD); 735 setTargetDAGCombine(ISD::SUB); 736 setTargetDAGCombine(ISD::MUL); 737 738 if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON()) 739 setTargetDAGCombine(ISD::OR); 740 if (Subtarget->hasNEON()) 741 setTargetDAGCombine(ISD::AND); 742 743 setStackPointerRegisterToSaveRestore(ARM::SP); 744 745 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2()) 746 setSchedulingPreference(Sched::RegPressure); 747 else 748 setSchedulingPreference(Sched::Hybrid); 749 750 //// temporary - rewrite interface to use type 751 maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 1; 752 753 // On ARM arguments smaller than 4 bytes are extended, so all arguments 754 // are at least 4 bytes aligned. 755 setMinStackArgumentAlignment(4); 756 757 benefitFromCodePlacementOpt = true; 758 759 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2); 760} 761 762// FIXME: It might make sense to define the representative register class as the 763// nearest super-register that has a non-null superset. For example, DPR_VFP2 is 764// a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently, 765// SPR's representative would be DPR_VFP2. This should work well if register 766// pressure tracking were modified such that a register use would increment the 767// pressure of the register class's representative and all of it's super 768// classes' representatives transitively. We have not implemented this because 769// of the difficulty prior to coalescing of modeling operand register classes 770// due to the common occurrence of cross class copies and subregister insertions 771// and extractions. 772std::pair<const TargetRegisterClass*, uint8_t> 773ARMTargetLowering::findRepresentativeClass(EVT VT) const{ 774 const TargetRegisterClass *RRC = 0; 775 uint8_t Cost = 1; 776 switch (VT.getSimpleVT().SimpleTy) { 777 default: 778 return TargetLowering::findRepresentativeClass(VT); 779 // Use DPR as representative register class for all floating point 780 // and vector types. Since there are 32 SPR registers and 32 DPR registers so 781 // the cost is 1 for both f32 and f64. 782 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16: 783 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32: 784 RRC = ARM::DPRRegisterClass; 785 // When NEON is used for SP, only half of the register file is available 786 // because operations that define both SP and DP results will be constrained 787 // to the VFP2 class (D0-D15). We currently model this constraint prior to 788 // coalescing by double-counting the SP regs. See the FIXME above. 789 if (Subtarget->useNEONForSinglePrecisionFP()) 790 Cost = 2; 791 break; 792 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 793 case MVT::v4f32: case MVT::v2f64: 794 RRC = ARM::DPRRegisterClass; 795 Cost = 2; 796 break; 797 case MVT::v4i64: 798 RRC = ARM::DPRRegisterClass; 799 Cost = 4; 800 break; 801 case MVT::v8i64: 802 RRC = ARM::DPRRegisterClass; 803 Cost = 8; 804 break; 805 } 806 return std::make_pair(RRC, Cost); 807} 808 809const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { 810 switch (Opcode) { 811 default: return 0; 812 case ARMISD::Wrapper: return "ARMISD::Wrapper"; 813 case ARMISD::WrapperDYN: return "ARMISD::WrapperDYN"; 814 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC"; 815 case ARMISD::WrapperJT: return "ARMISD::WrapperJT"; 816 case ARMISD::CALL: return "ARMISD::CALL"; 817 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED"; 818 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK"; 819 case ARMISD::tCALL: return "ARMISD::tCALL"; 820 case ARMISD::BRCOND: return "ARMISD::BRCOND"; 821 case ARMISD::BR_JT: return "ARMISD::BR_JT"; 822 case ARMISD::BR2_JT: return "ARMISD::BR2_JT"; 823 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; 824 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD"; 825 case ARMISD::CMP: return "ARMISD::CMP"; 826 case ARMISD::CMPZ: return "ARMISD::CMPZ"; 827 case ARMISD::CMPFP: return "ARMISD::CMPFP"; 828 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0"; 829 case ARMISD::BCC_i64: return "ARMISD::BCC_i64"; 830 case ARMISD::FMSTAT: return "ARMISD::FMSTAT"; 831 case ARMISD::CMOV: return "ARMISD::CMOV"; 832 833 case ARMISD::RBIT: return "ARMISD::RBIT"; 834 835 case ARMISD::FTOSI: return "ARMISD::FTOSI"; 836 case ARMISD::FTOUI: return "ARMISD::FTOUI"; 837 case ARMISD::SITOF: return "ARMISD::SITOF"; 838 case ARMISD::UITOF: return "ARMISD::UITOF"; 839 840 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG"; 841 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG"; 842 case ARMISD::RRX: return "ARMISD::RRX"; 843 844 case ARMISD::ADDC: return "ARMISD::ADDC"; 845 case ARMISD::ADDE: return "ARMISD::ADDE"; 846 case ARMISD::SUBC: return "ARMISD::SUBC"; 847 case ARMISD::SUBE: return "ARMISD::SUBE"; 848 849 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD"; 850 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR"; 851 852 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP"; 853 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP"; 854 case ARMISD::EH_SJLJ_DISPATCHSETUP:return "ARMISD::EH_SJLJ_DISPATCHSETUP"; 855 856 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN"; 857 858 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER"; 859 860 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC"; 861 862 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER"; 863 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR"; 864 865 case ARMISD::PRELOAD: return "ARMISD::PRELOAD"; 866 867 case ARMISD::VCEQ: return "ARMISD::VCEQ"; 868 case ARMISD::VCEQZ: return "ARMISD::VCEQZ"; 869 case ARMISD::VCGE: return "ARMISD::VCGE"; 870 case ARMISD::VCGEZ: return "ARMISD::VCGEZ"; 871 case ARMISD::VCLEZ: return "ARMISD::VCLEZ"; 872 case ARMISD::VCGEU: return "ARMISD::VCGEU"; 873 case ARMISD::VCGT: return "ARMISD::VCGT"; 874 case ARMISD::VCGTZ: return "ARMISD::VCGTZ"; 875 case ARMISD::VCLTZ: return "ARMISD::VCLTZ"; 876 case ARMISD::VCGTU: return "ARMISD::VCGTU"; 877 case ARMISD::VTST: return "ARMISD::VTST"; 878 879 case ARMISD::VSHL: return "ARMISD::VSHL"; 880 case ARMISD::VSHRs: return "ARMISD::VSHRs"; 881 case ARMISD::VSHRu: return "ARMISD::VSHRu"; 882 case ARMISD::VSHLLs: return "ARMISD::VSHLLs"; 883 case ARMISD::VSHLLu: return "ARMISD::VSHLLu"; 884 case ARMISD::VSHLLi: return "ARMISD::VSHLLi"; 885 case ARMISD::VSHRN: return "ARMISD::VSHRN"; 886 case ARMISD::VRSHRs: return "ARMISD::VRSHRs"; 887 case ARMISD::VRSHRu: return "ARMISD::VRSHRu"; 888 case ARMISD::VRSHRN: return "ARMISD::VRSHRN"; 889 case ARMISD::VQSHLs: return "ARMISD::VQSHLs"; 890 case ARMISD::VQSHLu: return "ARMISD::VQSHLu"; 891 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu"; 892 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs"; 893 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu"; 894 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu"; 895 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs"; 896 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu"; 897 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu"; 898 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu"; 899 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs"; 900 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM"; 901 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM"; 902 case ARMISD::VDUP: return "ARMISD::VDUP"; 903 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE"; 904 case ARMISD::VEXT: return "ARMISD::VEXT"; 905 case ARMISD::VREV64: return "ARMISD::VREV64"; 906 case ARMISD::VREV32: return "ARMISD::VREV32"; 907 case ARMISD::VREV16: return "ARMISD::VREV16"; 908 case ARMISD::VZIP: return "ARMISD::VZIP"; 909 case ARMISD::VUZP: return "ARMISD::VUZP"; 910 case ARMISD::VTRN: return "ARMISD::VTRN"; 911 case ARMISD::VTBL1: return "ARMISD::VTBL1"; 912 case ARMISD::VTBL2: return "ARMISD::VTBL2"; 913 case ARMISD::VMULLs: return "ARMISD::VMULLs"; 914 case ARMISD::VMULLu: return "ARMISD::VMULLu"; 915 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR"; 916 case ARMISD::FMAX: return "ARMISD::FMAX"; 917 case ARMISD::FMIN: return "ARMISD::FMIN"; 918 case ARMISD::BFI: return "ARMISD::BFI"; 919 case ARMISD::VORRIMM: return "ARMISD::VORRIMM"; 920 case ARMISD::VBICIMM: return "ARMISD::VBICIMM"; 921 case ARMISD::VBSL: return "ARMISD::VBSL"; 922 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP"; 923 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP"; 924 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP"; 925 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD"; 926 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD"; 927 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD"; 928 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD"; 929 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD"; 930 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD"; 931 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD"; 932 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD"; 933 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD"; 934 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD"; 935 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD"; 936 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD"; 937 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD"; 938 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD"; 939 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD"; 940 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD"; 941 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD"; 942 } 943} 944 945EVT ARMTargetLowering::getSetCCResultType(EVT VT) const { 946 if (!VT.isVector()) return getPointerTy(); 947 return VT.changeVectorElementTypeToInteger(); 948} 949 950/// getRegClassFor - Return the register class that should be used for the 951/// specified value type. 952TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const { 953 // Map v4i64 to QQ registers but do not make the type legal. Similarly map 954 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to 955 // load / store 4 to 8 consecutive D registers. 956 if (Subtarget->hasNEON()) { 957 if (VT == MVT::v4i64) 958 return ARM::QQPRRegisterClass; 959 else if (VT == MVT::v8i64) 960 return ARM::QQQQPRRegisterClass; 961 } 962 return TargetLowering::getRegClassFor(VT); 963} 964 965// Create a fast isel object. 966FastISel * 967ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 968 return ARM::createFastISel(funcInfo); 969} 970 971/// getMaximalGlobalOffset - Returns the maximal possible offset which can 972/// be used for loads / stores from the global. 973unsigned ARMTargetLowering::getMaximalGlobalOffset() const { 974 return (Subtarget->isThumb1Only() ? 127 : 4095); 975} 976 977Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const { 978 unsigned NumVals = N->getNumValues(); 979 if (!NumVals) 980 return Sched::RegPressure; 981 982 for (unsigned i = 0; i != NumVals; ++i) { 983 EVT VT = N->getValueType(i); 984 if (VT == MVT::Glue || VT == MVT::Other) 985 continue; 986 if (VT.isFloatingPoint() || VT.isVector()) 987 return Sched::Latency; 988 } 989 990 if (!N->isMachineOpcode()) 991 return Sched::RegPressure; 992 993 // Load are scheduled for latency even if there instruction itinerary 994 // is not available. 995 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 996 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); 997 998 if (MCID.getNumDefs() == 0) 999 return Sched::RegPressure; 1000 if (!Itins->isEmpty() && 1001 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2) 1002 return Sched::Latency; 1003 1004 return Sched::RegPressure; 1005} 1006 1007//===----------------------------------------------------------------------===// 1008// Lowering Code 1009//===----------------------------------------------------------------------===// 1010 1011/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC 1012static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { 1013 switch (CC) { 1014 default: llvm_unreachable("Unknown condition code!"); 1015 case ISD::SETNE: return ARMCC::NE; 1016 case ISD::SETEQ: return ARMCC::EQ; 1017 case ISD::SETGT: return ARMCC::GT; 1018 case ISD::SETGE: return ARMCC::GE; 1019 case ISD::SETLT: return ARMCC::LT; 1020 case ISD::SETLE: return ARMCC::LE; 1021 case ISD::SETUGT: return ARMCC::HI; 1022 case ISD::SETUGE: return ARMCC::HS; 1023 case ISD::SETULT: return ARMCC::LO; 1024 case ISD::SETULE: return ARMCC::LS; 1025 } 1026} 1027 1028/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. 1029static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, 1030 ARMCC::CondCodes &CondCode2) { 1031 CondCode2 = ARMCC::AL; 1032 switch (CC) { 1033 default: llvm_unreachable("Unknown FP condition!"); 1034 case ISD::SETEQ: 1035 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; 1036 case ISD::SETGT: 1037 case ISD::SETOGT: CondCode = ARMCC::GT; break; 1038 case ISD::SETGE: 1039 case ISD::SETOGE: CondCode = ARMCC::GE; break; 1040 case ISD::SETOLT: CondCode = ARMCC::MI; break; 1041 case ISD::SETOLE: CondCode = ARMCC::LS; break; 1042 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break; 1043 case ISD::SETO: CondCode = ARMCC::VC; break; 1044 case ISD::SETUO: CondCode = ARMCC::VS; break; 1045 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break; 1046 case ISD::SETUGT: CondCode = ARMCC::HI; break; 1047 case ISD::SETUGE: CondCode = ARMCC::PL; break; 1048 case ISD::SETLT: 1049 case ISD::SETULT: CondCode = ARMCC::LT; break; 1050 case ISD::SETLE: 1051 case ISD::SETULE: CondCode = ARMCC::LE; break; 1052 case ISD::SETNE: 1053 case ISD::SETUNE: CondCode = ARMCC::NE; break; 1054 } 1055} 1056 1057//===----------------------------------------------------------------------===// 1058// Calling Convention Implementation 1059//===----------------------------------------------------------------------===// 1060 1061#include "ARMGenCallingConv.inc" 1062 1063/// CCAssignFnForNode - Selects the correct CCAssignFn for a the 1064/// given CallingConvention value. 1065CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC, 1066 bool Return, 1067 bool isVarArg) const { 1068 switch (CC) { 1069 default: 1070 llvm_unreachable("Unsupported calling convention"); 1071 case CallingConv::Fast: 1072 if (Subtarget->hasVFP2() && !isVarArg) { 1073 if (!Subtarget->isAAPCS_ABI()) 1074 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS); 1075 // For AAPCS ABI targets, just use VFP variant of the calling convention. 1076 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP); 1077 } 1078 // Fallthrough 1079 case CallingConv::C: { 1080 // Use target triple & subtarget features to do actual dispatch. 1081 if (!Subtarget->isAAPCS_ABI()) 1082 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS); 1083 else if (Subtarget->hasVFP2() && 1084 FloatABIType == FloatABI::Hard && !isVarArg) 1085 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP); 1086 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS); 1087 } 1088 case CallingConv::ARM_AAPCS_VFP: 1089 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP); 1090 case CallingConv::ARM_AAPCS: 1091 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS); 1092 case CallingConv::ARM_APCS: 1093 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS); 1094 } 1095} 1096 1097/// LowerCallResult - Lower the result values of a call into the 1098/// appropriate copies out of appropriate physical registers. 1099SDValue 1100ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1101 CallingConv::ID CallConv, bool isVarArg, 1102 const SmallVectorImpl<ISD::InputArg> &Ins, 1103 DebugLoc dl, SelectionDAG &DAG, 1104 SmallVectorImpl<SDValue> &InVals) const { 1105 1106 // Assign locations to each value returned by this call. 1107 SmallVector<CCValAssign, 16> RVLocs; 1108 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1109 getTargetMachine(), RVLocs, *DAG.getContext(), Call); 1110 CCInfo.AnalyzeCallResult(Ins, 1111 CCAssignFnForNode(CallConv, /* Return*/ true, 1112 isVarArg)); 1113 1114 // Copy all of the result registers out of their specified physreg. 1115 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1116 CCValAssign VA = RVLocs[i]; 1117 1118 SDValue Val; 1119 if (VA.needsCustom()) { 1120 // Handle f64 or half of a v2f64. 1121 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 1122 InFlag); 1123 Chain = Lo.getValue(1); 1124 InFlag = Lo.getValue(2); 1125 VA = RVLocs[++i]; // skip ahead to next loc 1126 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, 1127 InFlag); 1128 Chain = Hi.getValue(1); 1129 InFlag = Hi.getValue(2); 1130 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); 1131 1132 if (VA.getLocVT() == MVT::v2f64) { 1133 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); 1134 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 1135 DAG.getConstant(0, MVT::i32)); 1136 1137 VA = RVLocs[++i]; // skip ahead to next loc 1138 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); 1139 Chain = Lo.getValue(1); 1140 InFlag = Lo.getValue(2); 1141 VA = RVLocs[++i]; // skip ahead to next loc 1142 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); 1143 Chain = Hi.getValue(1); 1144 InFlag = Hi.getValue(2); 1145 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); 1146 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, 1147 DAG.getConstant(1, MVT::i32)); 1148 } 1149 } else { 1150 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), 1151 InFlag); 1152 Chain = Val.getValue(1); 1153 InFlag = Val.getValue(2); 1154 } 1155 1156 switch (VA.getLocInfo()) { 1157 default: llvm_unreachable("Unknown loc info!"); 1158 case CCValAssign::Full: break; 1159 case CCValAssign::BCvt: 1160 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val); 1161 break; 1162 } 1163 1164 InVals.push_back(Val); 1165 } 1166 1167 return Chain; 1168} 1169 1170/// LowerMemOpCallTo - Store the argument to the stack. 1171SDValue 1172ARMTargetLowering::LowerMemOpCallTo(SDValue Chain, 1173 SDValue StackPtr, SDValue Arg, 1174 DebugLoc dl, SelectionDAG &DAG, 1175 const CCValAssign &VA, 1176 ISD::ArgFlagsTy Flags) const { 1177 unsigned LocMemOffset = VA.getLocMemOffset(); 1178 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1179 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1180 return DAG.getStore(Chain, dl, Arg, PtrOff, 1181 MachinePointerInfo::getStack(LocMemOffset), 1182 false, false, 0); 1183} 1184 1185void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, 1186 SDValue Chain, SDValue &Arg, 1187 RegsToPassVector &RegsToPass, 1188 CCValAssign &VA, CCValAssign &NextVA, 1189 SDValue &StackPtr, 1190 SmallVector<SDValue, 8> &MemOpChains, 1191 ISD::ArgFlagsTy Flags) const { 1192 1193 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, 1194 DAG.getVTList(MVT::i32, MVT::i32), Arg); 1195 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd)); 1196 1197 if (NextVA.isRegLoc()) 1198 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1))); 1199 else { 1200 assert(NextVA.isMemLoc()); 1201 if (StackPtr.getNode() == 0) 1202 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); 1203 1204 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1), 1205 dl, DAG, NextVA, 1206 Flags)); 1207 } 1208} 1209 1210/// LowerCall - Lowering a call into a callseq_start <- 1211/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter 1212/// nodes. 1213SDValue 1214ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 1215 CallingConv::ID CallConv, bool isVarArg, 1216 bool &isTailCall, 1217 const SmallVectorImpl<ISD::OutputArg> &Outs, 1218 const SmallVectorImpl<SDValue> &OutVals, 1219 const SmallVectorImpl<ISD::InputArg> &Ins, 1220 DebugLoc dl, SelectionDAG &DAG, 1221 SmallVectorImpl<SDValue> &InVals) const { 1222 MachineFunction &MF = DAG.getMachineFunction(); 1223 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet(); 1224 bool IsSibCall = false; 1225 // Disable tail calls if they're not supported. 1226 if (!EnableARMTailCalls && !Subtarget->supportsTailCall()) 1227 isTailCall = false; 1228 if (isTailCall) { 1229 // Check if it's really possible to do a tail call. 1230 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 1231 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 1232 Outs, OutVals, Ins, DAG); 1233 // We don't support GuaranteedTailCallOpt for ARM, only automatically 1234 // detected sibcalls. 1235 if (isTailCall) { 1236 ++NumTailCalls; 1237 IsSibCall = true; 1238 } 1239 } 1240 1241 // Analyze operands of the call, assigning locations to each operand. 1242 SmallVector<CCValAssign, 16> ArgLocs; 1243 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1244 getTargetMachine(), ArgLocs, *DAG.getContext(), Call); 1245 CCInfo.AnalyzeCallOperands(Outs, 1246 CCAssignFnForNode(CallConv, /* Return*/ false, 1247 isVarArg)); 1248 1249 // Get a count of how many bytes are to be pushed on the stack. 1250 unsigned NumBytes = CCInfo.getNextStackOffset(); 1251 1252 // For tail calls, memory operands are available in our caller's stack. 1253 if (IsSibCall) 1254 NumBytes = 0; 1255 1256 // Adjust the stack pointer for the new arguments... 1257 // These operations are automatically eliminated by the prolog/epilog pass 1258 if (!IsSibCall) 1259 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 1260 1261 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy()); 1262 1263 RegsToPassVector RegsToPass; 1264 SmallVector<SDValue, 8> MemOpChains; 1265 1266 // Walk the register/memloc assignments, inserting copies/loads. In the case 1267 // of tail call optimization, arguments are handled later. 1268 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); 1269 i != e; 1270 ++i, ++realArgIdx) { 1271 CCValAssign &VA = ArgLocs[i]; 1272 SDValue Arg = OutVals[realArgIdx]; 1273 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 1274 bool isByVal = Flags.isByVal(); 1275 1276 // Promote the value if needed. 1277 switch (VA.getLocInfo()) { 1278 default: llvm_unreachable("Unknown loc info!"); 1279 case CCValAssign::Full: break; 1280 case CCValAssign::SExt: 1281 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 1282 break; 1283 case CCValAssign::ZExt: 1284 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 1285 break; 1286 case CCValAssign::AExt: 1287 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 1288 break; 1289 case CCValAssign::BCvt: 1290 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 1291 break; 1292 } 1293 1294 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces 1295 if (VA.needsCustom()) { 1296 if (VA.getLocVT() == MVT::v2f64) { 1297 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1298 DAG.getConstant(0, MVT::i32)); 1299 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1300 DAG.getConstant(1, MVT::i32)); 1301 1302 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass, 1303 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); 1304 1305 VA = ArgLocs[++i]; // skip ahead to next loc 1306 if (VA.isRegLoc()) { 1307 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass, 1308 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); 1309 } else { 1310 assert(VA.isMemLoc()); 1311 1312 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1, 1313 dl, DAG, VA, Flags)); 1314 } 1315 } else { 1316 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i], 1317 StackPtr, MemOpChains, Flags); 1318 } 1319 } else if (VA.isRegLoc()) { 1320 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 1321 } else if (isByVal) { 1322 assert(VA.isMemLoc()); 1323 unsigned offset = 0; 1324 1325 // True if this byval aggregate will be split between registers 1326 // and memory. 1327 if (CCInfo.isFirstByValRegValid()) { 1328 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 1329 unsigned int i, j; 1330 for (i = 0, j = CCInfo.getFirstByValReg(); j < ARM::R4; i++, j++) { 1331 SDValue Const = DAG.getConstant(4*i, MVT::i32); 1332 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); 1333 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, 1334 MachinePointerInfo(), 1335 false, false, 0); 1336 MemOpChains.push_back(Load.getValue(1)); 1337 RegsToPass.push_back(std::make_pair(j, Load)); 1338 } 1339 offset = ARM::R4 - CCInfo.getFirstByValReg(); 1340 CCInfo.clearFirstByValReg(); 1341 } 1342 1343 unsigned LocMemOffset = VA.getLocMemOffset(); 1344 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset); 1345 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, 1346 StkPtrOff); 1347 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset); 1348 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset); 1349 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, 1350 MVT::i32); 1351 // TODO: Disable AlwaysInline when it becomes possible 1352 // to emit a nested call sequence. 1353 MemOpChains.push_back(DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, 1354 Flags.getByValAlign(), 1355 /*isVolatile=*/false, 1356 /*AlwaysInline=*/true, 1357 MachinePointerInfo(0), 1358 MachinePointerInfo(0))); 1359 1360 } else if (!IsSibCall) { 1361 assert(VA.isMemLoc()); 1362 1363 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 1364 dl, DAG, VA, Flags)); 1365 } 1366 } 1367 1368 if (!MemOpChains.empty()) 1369 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1370 &MemOpChains[0], MemOpChains.size()); 1371 1372 // Build a sequence of copy-to-reg nodes chained together with token chain 1373 // and flag operands which copy the outgoing args into the appropriate regs. 1374 SDValue InFlag; 1375 // Tail call byval lowering might overwrite argument registers so in case of 1376 // tail call optimization the copies to registers are lowered later. 1377 if (!isTailCall) 1378 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1379 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1380 RegsToPass[i].second, InFlag); 1381 InFlag = Chain.getValue(1); 1382 } 1383 1384 // For tail calls lower the arguments to the 'real' stack slot. 1385 if (isTailCall) { 1386 // Force all the incoming stack arguments to be loaded from the stack 1387 // before any new outgoing arguments are stored to the stack, because the 1388 // outgoing stack slots may alias the incoming argument stack slots, and 1389 // the alias isn't otherwise explicit. This is slightly more conservative 1390 // than necessary, because it means that each store effectively depends 1391 // on every argument instead of just those arguments it would clobber. 1392 1393 // Do not flag preceding copytoreg stuff together with the following stuff. 1394 InFlag = SDValue(); 1395 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1396 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 1397 RegsToPass[i].second, InFlag); 1398 InFlag = Chain.getValue(1); 1399 } 1400 InFlag =SDValue(); 1401 } 1402 1403 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 1404 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 1405 // node so that legalize doesn't hack it. 1406 bool isDirect = false; 1407 bool isARMFunc = false; 1408 bool isLocalARMFunc = false; 1409 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1410 1411 if (EnableARMLongCalls) { 1412 assert (getTargetMachine().getRelocationModel() == Reloc::Static 1413 && "long-calls with non-static relocation model!"); 1414 // Handle a global address or an external symbol. If it's not one of 1415 // those, the target's already in a register, so we don't need to do 1416 // anything extra. 1417 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1418 const GlobalValue *GV = G->getGlobal(); 1419 // Create a constant pool entry for the callee address 1420 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1421 ARMConstantPoolValue *CPV = 1422 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0); 1423 1424 // Get the address of the callee into a register 1425 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1426 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1427 Callee = DAG.getLoad(getPointerTy(), dl, 1428 DAG.getEntryNode(), CPAddr, 1429 MachinePointerInfo::getConstantPool(), 1430 false, false, 0); 1431 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) { 1432 const char *Sym = S->getSymbol(); 1433 1434 // Create a constant pool entry for the callee address 1435 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1436 ARMConstantPoolValue *CPV = 1437 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym, 1438 ARMPCLabelIndex, 0); 1439 // Get the address of the callee into a register 1440 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1441 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1442 Callee = DAG.getLoad(getPointerTy(), dl, 1443 DAG.getEntryNode(), CPAddr, 1444 MachinePointerInfo::getConstantPool(), 1445 false, false, 0); 1446 } 1447 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 1448 const GlobalValue *GV = G->getGlobal(); 1449 isDirect = true; 1450 bool isExt = GV->isDeclaration() || GV->isWeakForLinker(); 1451 bool isStub = (isExt && Subtarget->isTargetDarwin()) && 1452 getTargetMachine().getRelocationModel() != Reloc::Static; 1453 isARMFunc = !Subtarget->isThumb() || isStub; 1454 // ARM call to a local ARM function is predicable. 1455 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking); 1456 // tBX takes a register source operand. 1457 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { 1458 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1459 ARMConstantPoolValue *CPV = 1460 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 4); 1461 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1462 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1463 Callee = DAG.getLoad(getPointerTy(), dl, 1464 DAG.getEntryNode(), CPAddr, 1465 MachinePointerInfo::getConstantPool(), 1466 false, false, 0); 1467 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1468 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, 1469 getPointerTy(), Callee, PICLabel); 1470 } else { 1471 // On ELF targets for PIC code, direct calls should go through the PLT 1472 unsigned OpFlags = 0; 1473 if (Subtarget->isTargetELF() && 1474 getTargetMachine().getRelocationModel() == Reloc::PIC_) 1475 OpFlags = ARMII::MO_PLT; 1476 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 1477 } 1478 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 1479 isDirect = true; 1480 bool isStub = Subtarget->isTargetDarwin() && 1481 getTargetMachine().getRelocationModel() != Reloc::Static; 1482 isARMFunc = !Subtarget->isThumb() || isStub; 1483 // tBX takes a register source operand. 1484 const char *Sym = S->getSymbol(); 1485 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) { 1486 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1487 ARMConstantPoolValue *CPV = 1488 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym, 1489 ARMPCLabelIndex, 4); 1490 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); 1491 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 1492 Callee = DAG.getLoad(getPointerTy(), dl, 1493 DAG.getEntryNode(), CPAddr, 1494 MachinePointerInfo::getConstantPool(), 1495 false, false, 0); 1496 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1497 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, 1498 getPointerTy(), Callee, PICLabel); 1499 } else { 1500 unsigned OpFlags = 0; 1501 // On ELF targets for PIC code, direct calls should go through the PLT 1502 if (Subtarget->isTargetELF() && 1503 getTargetMachine().getRelocationModel() == Reloc::PIC_) 1504 OpFlags = ARMII::MO_PLT; 1505 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags); 1506 } 1507 } 1508 1509 // FIXME: handle tail calls differently. 1510 unsigned CallOpc; 1511 if (Subtarget->isThumb()) { 1512 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps()) 1513 CallOpc = ARMISD::CALL_NOLINK; 1514 else 1515 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL; 1516 } else { 1517 CallOpc = (isDirect || Subtarget->hasV5TOps()) 1518 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL) 1519 : ARMISD::CALL_NOLINK; 1520 } 1521 1522 std::vector<SDValue> Ops; 1523 Ops.push_back(Chain); 1524 Ops.push_back(Callee); 1525 1526 // Add argument registers to the end of the list so that they are known live 1527 // into the call. 1528 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1529 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1530 RegsToPass[i].second.getValueType())); 1531 1532 if (InFlag.getNode()) 1533 Ops.push_back(InFlag); 1534 1535 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 1536 if (isTailCall) 1537 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size()); 1538 1539 // Returns a chain and a flag for retval copy to use. 1540 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); 1541 InFlag = Chain.getValue(1); 1542 1543 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 1544 DAG.getIntPtrConstant(0, true), InFlag); 1545 if (!Ins.empty()) 1546 InFlag = Chain.getValue(1); 1547 1548 // Handle result values, copying them out of physregs into vregs that we 1549 // return. 1550 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, 1551 dl, DAG, InVals); 1552} 1553 1554/// HandleByVal - Every parameter *after* a byval parameter is passed 1555/// on the stack. Remember the next parameter register to allocate, 1556/// and then confiscate the rest of the parameter registers to insure 1557/// this. 1558void 1559llvm::ARMTargetLowering::HandleByVal(CCState *State, unsigned &size) const { 1560 unsigned reg = State->AllocateReg(GPRArgRegs, 4); 1561 assert((State->getCallOrPrologue() == Prologue || 1562 State->getCallOrPrologue() == Call) && 1563 "unhandled ParmContext"); 1564 if ((!State->isFirstByValRegValid()) && 1565 (ARM::R0 <= reg) && (reg <= ARM::R3)) { 1566 State->setFirstByValReg(reg); 1567 // At a call site, a byval parameter that is split between 1568 // registers and memory needs its size truncated here. In a 1569 // function prologue, such byval parameters are reassembled in 1570 // memory, and are not truncated. 1571 if (State->getCallOrPrologue() == Call) { 1572 unsigned excess = 4 * (ARM::R4 - reg); 1573 assert(size >= excess && "expected larger existing stack allocation"); 1574 size -= excess; 1575 } 1576 } 1577 // Confiscate any remaining parameter registers to preclude their 1578 // assignment to subsequent parameters. 1579 while (State->AllocateReg(GPRArgRegs, 4)) 1580 ; 1581} 1582 1583/// MatchingStackOffset - Return true if the given stack call argument is 1584/// already available in the same position (relatively) of the caller's 1585/// incoming argument stack. 1586static 1587bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 1588 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 1589 const ARMInstrInfo *TII) { 1590 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 1591 int FI = INT_MAX; 1592 if (Arg.getOpcode() == ISD::CopyFromReg) { 1593 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 1594 if (!TargetRegisterInfo::isVirtualRegister(VR)) 1595 return false; 1596 MachineInstr *Def = MRI->getVRegDef(VR); 1597 if (!Def) 1598 return false; 1599 if (!Flags.isByVal()) { 1600 if (!TII->isLoadFromStackSlot(Def, FI)) 1601 return false; 1602 } else { 1603 return false; 1604 } 1605 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 1606 if (Flags.isByVal()) 1607 // ByVal argument is passed in as a pointer but it's now being 1608 // dereferenced. e.g. 1609 // define @foo(%struct.X* %A) { 1610 // tail call @bar(%struct.X* byval %A) 1611 // } 1612 return false; 1613 SDValue Ptr = Ld->getBasePtr(); 1614 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 1615 if (!FINode) 1616 return false; 1617 FI = FINode->getIndex(); 1618 } else 1619 return false; 1620 1621 assert(FI != INT_MAX); 1622 if (!MFI->isFixedObjectIndex(FI)) 1623 return false; 1624 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 1625} 1626 1627/// IsEligibleForTailCallOptimization - Check whether the call is eligible 1628/// for tail call optimization. Targets which want to do tail call 1629/// optimization should implement this function. 1630bool 1631ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 1632 CallingConv::ID CalleeCC, 1633 bool isVarArg, 1634 bool isCalleeStructRet, 1635 bool isCallerStructRet, 1636 const SmallVectorImpl<ISD::OutputArg> &Outs, 1637 const SmallVectorImpl<SDValue> &OutVals, 1638 const SmallVectorImpl<ISD::InputArg> &Ins, 1639 SelectionDAG& DAG) const { 1640 const Function *CallerF = DAG.getMachineFunction().getFunction(); 1641 CallingConv::ID CallerCC = CallerF->getCallingConv(); 1642 bool CCMatch = CallerCC == CalleeCC; 1643 1644 // Look for obvious safe cases to perform tail call optimization that do not 1645 // require ABI changes. This is what gcc calls sibcall. 1646 1647 // Do not sibcall optimize vararg calls unless the call site is not passing 1648 // any arguments. 1649 if (isVarArg && !Outs.empty()) 1650 return false; 1651 1652 // Also avoid sibcall optimization if either caller or callee uses struct 1653 // return semantics. 1654 if (isCalleeStructRet || isCallerStructRet) 1655 return false; 1656 1657 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo:: 1658 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as 1659 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation 1660 // support in the assembler and linker to be used. This would need to be 1661 // fixed to fully support tail calls in Thumb1. 1662 // 1663 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take 1664 // LR. This means if we need to reload LR, it takes an extra instructions, 1665 // which outweighs the value of the tail call; but here we don't know yet 1666 // whether LR is going to be used. Probably the right approach is to 1667 // generate the tail call here and turn it back into CALL/RET in 1668 // emitEpilogue if LR is used. 1669 1670 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls, 1671 // but we need to make sure there are enough registers; the only valid 1672 // registers are the 4 used for parameters. We don't currently do this 1673 // case. 1674 if (Subtarget->isThumb1Only()) 1675 return false; 1676 1677 // If the calling conventions do not match, then we'd better make sure the 1678 // results are returned in the same way as what the caller expects. 1679 if (!CCMatch) { 1680 SmallVector<CCValAssign, 16> RVLocs1; 1681 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 1682 getTargetMachine(), RVLocs1, *DAG.getContext(), Call); 1683 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg)); 1684 1685 SmallVector<CCValAssign, 16> RVLocs2; 1686 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 1687 getTargetMachine(), RVLocs2, *DAG.getContext(), Call); 1688 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg)); 1689 1690 if (RVLocs1.size() != RVLocs2.size()) 1691 return false; 1692 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 1693 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 1694 return false; 1695 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 1696 return false; 1697 if (RVLocs1[i].isRegLoc()) { 1698 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 1699 return false; 1700 } else { 1701 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 1702 return false; 1703 } 1704 } 1705 } 1706 1707 // If the callee takes no arguments then go on to check the results of the 1708 // call. 1709 if (!Outs.empty()) { 1710 // Check if stack adjustment is needed. For now, do not do this if any 1711 // argument is passed on the stack. 1712 SmallVector<CCValAssign, 16> ArgLocs; 1713 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 1714 getTargetMachine(), ArgLocs, *DAG.getContext(), Call); 1715 CCInfo.AnalyzeCallOperands(Outs, 1716 CCAssignFnForNode(CalleeCC, false, isVarArg)); 1717 if (CCInfo.getNextStackOffset()) { 1718 MachineFunction &MF = DAG.getMachineFunction(); 1719 1720 // Check if the arguments are already laid out in the right way as 1721 // the caller's fixed stack objects. 1722 MachineFrameInfo *MFI = MF.getFrameInfo(); 1723 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 1724 const ARMInstrInfo *TII = 1725 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo(); 1726 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size(); 1727 i != e; 1728 ++i, ++realArgIdx) { 1729 CCValAssign &VA = ArgLocs[i]; 1730 EVT RegVT = VA.getLocVT(); 1731 SDValue Arg = OutVals[realArgIdx]; 1732 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 1733 if (VA.getLocInfo() == CCValAssign::Indirect) 1734 return false; 1735 if (VA.needsCustom()) { 1736 // f64 and vector types are split into multiple registers or 1737 // register/stack-slot combinations. The types will not match 1738 // the registers; give up on memory f64 refs until we figure 1739 // out what to do about this. 1740 if (!VA.isRegLoc()) 1741 return false; 1742 if (!ArgLocs[++i].isRegLoc()) 1743 return false; 1744 if (RegVT == MVT::v2f64) { 1745 if (!ArgLocs[++i].isRegLoc()) 1746 return false; 1747 if (!ArgLocs[++i].isRegLoc()) 1748 return false; 1749 } 1750 } else if (!VA.isRegLoc()) { 1751 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 1752 MFI, MRI, TII)) 1753 return false; 1754 } 1755 } 1756 } 1757 } 1758 1759 return true; 1760} 1761 1762SDValue 1763ARMTargetLowering::LowerReturn(SDValue Chain, 1764 CallingConv::ID CallConv, bool isVarArg, 1765 const SmallVectorImpl<ISD::OutputArg> &Outs, 1766 const SmallVectorImpl<SDValue> &OutVals, 1767 DebugLoc dl, SelectionDAG &DAG) const { 1768 1769 // CCValAssign - represent the assignment of the return value to a location. 1770 SmallVector<CCValAssign, 16> RVLocs; 1771 1772 // CCState - Info about the registers and stack slots. 1773 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1774 getTargetMachine(), RVLocs, *DAG.getContext(), Call); 1775 1776 // Analyze outgoing return values. 1777 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true, 1778 isVarArg)); 1779 1780 // If this is the first return lowered for this function, add 1781 // the regs to the liveout set for the function. 1782 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 1783 for (unsigned i = 0; i != RVLocs.size(); ++i) 1784 if (RVLocs[i].isRegLoc()) 1785 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 1786 } 1787 1788 SDValue Flag; 1789 1790 // Copy the result values into the output registers. 1791 for (unsigned i = 0, realRVLocIdx = 0; 1792 i != RVLocs.size(); 1793 ++i, ++realRVLocIdx) { 1794 CCValAssign &VA = RVLocs[i]; 1795 assert(VA.isRegLoc() && "Can only return in registers!"); 1796 1797 SDValue Arg = OutVals[realRVLocIdx]; 1798 1799 switch (VA.getLocInfo()) { 1800 default: llvm_unreachable("Unknown loc info!"); 1801 case CCValAssign::Full: break; 1802 case CCValAssign::BCvt: 1803 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 1804 break; 1805 } 1806 1807 if (VA.needsCustom()) { 1808 if (VA.getLocVT() == MVT::v2f64) { 1809 // Extract the first half and return it in two registers. 1810 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1811 DAG.getConstant(0, MVT::i32)); 1812 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl, 1813 DAG.getVTList(MVT::i32, MVT::i32), Half); 1814 1815 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag); 1816 Flag = Chain.getValue(1); 1817 VA = RVLocs[++i]; // skip ahead to next loc 1818 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 1819 HalfGPRs.getValue(1), Flag); 1820 Flag = Chain.getValue(1); 1821 VA = RVLocs[++i]; // skip ahead to next loc 1822 1823 // Extract the 2nd half and fall through to handle it as an f64 value. 1824 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, 1825 DAG.getConstant(1, MVT::i32)); 1826 } 1827 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is 1828 // available. 1829 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl, 1830 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1); 1831 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag); 1832 Flag = Chain.getValue(1); 1833 VA = RVLocs[++i]; // skip ahead to next loc 1834 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1), 1835 Flag); 1836 } else 1837 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag); 1838 1839 // Guarantee that all emitted copies are 1840 // stuck together, avoiding something bad. 1841 Flag = Chain.getValue(1); 1842 } 1843 1844 SDValue result; 1845 if (Flag.getNode()) 1846 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag); 1847 else // Return Void 1848 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain); 1849 1850 return result; 1851} 1852 1853bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N) const { 1854 if (N->getNumValues() != 1) 1855 return false; 1856 if (!N->hasNUsesOfValue(1, 0)) 1857 return false; 1858 1859 unsigned NumCopies = 0; 1860 SDNode* Copies[2]; 1861 SDNode *Use = *N->use_begin(); 1862 if (Use->getOpcode() == ISD::CopyToReg) { 1863 Copies[NumCopies++] = Use; 1864 } else if (Use->getOpcode() == ARMISD::VMOVRRD) { 1865 // f64 returned in a pair of GPRs. 1866 for (SDNode::use_iterator UI = Use->use_begin(), UE = Use->use_end(); 1867 UI != UE; ++UI) { 1868 if (UI->getOpcode() != ISD::CopyToReg) 1869 return false; 1870 Copies[UI.getUse().getResNo()] = *UI; 1871 ++NumCopies; 1872 } 1873 } else if (Use->getOpcode() == ISD::BITCAST) { 1874 // f32 returned in a single GPR. 1875 if (!Use->hasNUsesOfValue(1, 0)) 1876 return false; 1877 Use = *Use->use_begin(); 1878 if (Use->getOpcode() != ISD::CopyToReg || !Use->hasNUsesOfValue(1, 0)) 1879 return false; 1880 Copies[NumCopies++] = Use; 1881 } else { 1882 return false; 1883 } 1884 1885 if (NumCopies != 1 && NumCopies != 2) 1886 return false; 1887 1888 bool HasRet = false; 1889 for (unsigned i = 0; i < NumCopies; ++i) { 1890 SDNode *Copy = Copies[i]; 1891 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1892 UI != UE; ++UI) { 1893 if (UI->getOpcode() == ISD::CopyToReg) { 1894 SDNode *Use = *UI; 1895 if (Use == Copies[0] || Use == Copies[1]) 1896 continue; 1897 return false; 1898 } 1899 if (UI->getOpcode() != ARMISD::RET_FLAG) 1900 return false; 1901 HasRet = true; 1902 } 1903 } 1904 1905 return HasRet; 1906} 1907 1908bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1909 if (!EnableARMTailCalls) 1910 return false; 1911 1912 if (!CI->isTailCall()) 1913 return false; 1914 1915 return !Subtarget->isThumb1Only(); 1916} 1917 1918// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 1919// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is 1920// one of the above mentioned nodes. It has to be wrapped because otherwise 1921// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 1922// be used to form addressing mode. These wrapped nodes will be selected 1923// into MOVi. 1924static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) { 1925 EVT PtrVT = Op.getValueType(); 1926 // FIXME there is no actual debug info here 1927 DebugLoc dl = Op.getDebugLoc(); 1928 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 1929 SDValue Res; 1930 if (CP->isMachineConstantPoolEntry()) 1931 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, 1932 CP->getAlignment()); 1933 else 1934 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, 1935 CP->getAlignment()); 1936 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res); 1937} 1938 1939unsigned ARMTargetLowering::getJumpTableEncoding() const { 1940 return MachineJumpTableInfo::EK_Inline; 1941} 1942 1943SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op, 1944 SelectionDAG &DAG) const { 1945 MachineFunction &MF = DAG.getMachineFunction(); 1946 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1947 unsigned ARMPCLabelIndex = 0; 1948 DebugLoc DL = Op.getDebugLoc(); 1949 EVT PtrVT = getPointerTy(); 1950 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1951 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 1952 SDValue CPAddr; 1953 if (RelocM == Reloc::Static) { 1954 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4); 1955 } else { 1956 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 1957 ARMPCLabelIndex = AFI->createPICLabelUId(); 1958 ARMConstantPoolValue *CPV = 1959 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex, 1960 ARMCP::CPBlockAddress, PCAdj); 1961 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1962 } 1963 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr); 1964 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr, 1965 MachinePointerInfo::getConstantPool(), 1966 false, false, 0); 1967 if (RelocM == Reloc::Static) 1968 return Result; 1969 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1970 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel); 1971} 1972 1973// Lower ISD::GlobalTLSAddress using the "general dynamic" model 1974SDValue 1975ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 1976 SelectionDAG &DAG) const { 1977 DebugLoc dl = GA->getDebugLoc(); 1978 EVT PtrVT = getPointerTy(); 1979 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 1980 MachineFunction &MF = DAG.getMachineFunction(); 1981 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1982 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 1983 ARMConstantPoolValue *CPV = 1984 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex, 1985 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true); 1986 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4); 1987 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument); 1988 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, 1989 MachinePointerInfo::getConstantPool(), 1990 false, false, 0); 1991 SDValue Chain = Argument.getValue(1); 1992 1993 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 1994 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel); 1995 1996 // call __tls_get_addr. 1997 ArgListTy Args; 1998 ArgListEntry Entry; 1999 Entry.Node = Argument; 2000 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext()); 2001 Args.push_back(Entry); 2002 // FIXME: is there useful debug info available here? 2003 std::pair<SDValue, SDValue> CallResult = 2004 LowerCallTo(Chain, (Type *) Type::getInt32Ty(*DAG.getContext()), 2005 false, false, false, false, 2006 0, CallingConv::C, false, /*isReturnValueUsed=*/true, 2007 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl); 2008 return CallResult.first; 2009} 2010 2011// Lower ISD::GlobalTLSAddress using the "initial exec" or 2012// "local exec" model. 2013SDValue 2014ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, 2015 SelectionDAG &DAG) const { 2016 const GlobalValue *GV = GA->getGlobal(); 2017 DebugLoc dl = GA->getDebugLoc(); 2018 SDValue Offset; 2019 SDValue Chain = DAG.getEntryNode(); 2020 EVT PtrVT = getPointerTy(); 2021 // Get the Thread Pointer 2022 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); 2023 2024 if (GV->isDeclaration()) { 2025 MachineFunction &MF = DAG.getMachineFunction(); 2026 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2027 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 2028 // Initial exec model. 2029 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 2030 ARMConstantPoolValue *CPV = 2031 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex, 2032 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF, 2033 true); 2034 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2035 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); 2036 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 2037 MachinePointerInfo::getConstantPool(), 2038 false, false, 0); 2039 Chain = Offset.getValue(1); 2040 2041 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2042 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel); 2043 2044 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 2045 MachinePointerInfo::getConstantPool(), 2046 false, false, 0); 2047 } else { 2048 // local exec model 2049 ARMConstantPoolValue *CPV = 2050 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF); 2051 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2052 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); 2053 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, 2054 MachinePointerInfo::getConstantPool(), 2055 false, false, 0); 2056 } 2057 2058 // The address of the thread local variable is the add of the thread 2059 // pointer with the offset of the variable. 2060 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 2061} 2062 2063SDValue 2064ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 2065 // TODO: implement the "local dynamic" model 2066 assert(Subtarget->isTargetELF() && 2067 "TLS not implemented for non-ELF targets"); 2068 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 2069 // If the relocation model is PIC, use the "General Dynamic" TLS Model, 2070 // otherwise use the "Local Exec" TLS Model 2071 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) 2072 return LowerToTLSGeneralDynamicModel(GA, DAG); 2073 else 2074 return LowerToTLSExecModels(GA, DAG); 2075} 2076 2077SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, 2078 SelectionDAG &DAG) const { 2079 EVT PtrVT = getPointerTy(); 2080 DebugLoc dl = Op.getDebugLoc(); 2081 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 2082 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 2083 if (RelocM == Reloc::PIC_) { 2084 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility(); 2085 ARMConstantPoolValue *CPV = 2086 ARMConstantPoolConstant::Create(GV, 2087 UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT); 2088 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2089 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2090 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 2091 CPAddr, 2092 MachinePointerInfo::getConstantPool(), 2093 false, false, 0); 2094 SDValue Chain = Result.getValue(1); 2095 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT); 2096 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT); 2097 if (!UseGOTOFF) 2098 Result = DAG.getLoad(PtrVT, dl, Chain, Result, 2099 MachinePointerInfo::getGOT(), false, false, 0); 2100 return Result; 2101 } 2102 2103 // If we have T2 ops, we can materialize the address directly via movt/movw 2104 // pair. This is always cheaper. 2105 if (Subtarget->useMovt()) { 2106 ++NumMovwMovt; 2107 // FIXME: Once remat is capable of dealing with instructions with register 2108 // operands, expand this into two nodes. 2109 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT, 2110 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); 2111 } else { 2112 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); 2113 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2114 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2115 MachinePointerInfo::getConstantPool(), 2116 false, false, 0); 2117 } 2118} 2119 2120SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op, 2121 SelectionDAG &DAG) const { 2122 EVT PtrVT = getPointerTy(); 2123 DebugLoc dl = Op.getDebugLoc(); 2124 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 2125 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 2126 MachineFunction &MF = DAG.getMachineFunction(); 2127 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2128 2129 // FIXME: Enable this for static codegen when tool issues are fixed. 2130 if (Subtarget->useMovt() && RelocM != Reloc::Static) { 2131 ++NumMovwMovt; 2132 // FIXME: Once remat is capable of dealing with instructions with register 2133 // operands, expand this into two nodes. 2134 if (RelocM == Reloc::Static) 2135 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT, 2136 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); 2137 2138 unsigned Wrapper = (RelocM == Reloc::PIC_) 2139 ? ARMISD::WrapperPIC : ARMISD::WrapperDYN; 2140 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, 2141 DAG.getTargetGlobalAddress(GV, dl, PtrVT)); 2142 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) 2143 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result, 2144 MachinePointerInfo::getGOT(), false, false, 0); 2145 return Result; 2146 } 2147 2148 unsigned ARMPCLabelIndex = 0; 2149 SDValue CPAddr; 2150 if (RelocM == Reloc::Static) { 2151 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); 2152 } else { 2153 ARMPCLabelIndex = AFI->createPICLabelUId(); 2154 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8); 2155 ARMConstantPoolValue *CPV = 2156 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 2157 PCAdj); 2158 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2159 } 2160 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2161 2162 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2163 MachinePointerInfo::getConstantPool(), 2164 false, false, 0); 2165 SDValue Chain = Result.getValue(1); 2166 2167 if (RelocM == Reloc::PIC_) { 2168 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2169 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 2170 } 2171 2172 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) 2173 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(), 2174 false, false, 0); 2175 2176 return Result; 2177} 2178 2179SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, 2180 SelectionDAG &DAG) const { 2181 assert(Subtarget->isTargetELF() && 2182 "GLOBAL OFFSET TABLE not implemented for non-ELF targets"); 2183 MachineFunction &MF = DAG.getMachineFunction(); 2184 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2185 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 2186 EVT PtrVT = getPointerTy(); 2187 DebugLoc dl = Op.getDebugLoc(); 2188 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 2189 ARMConstantPoolValue *CPV = 2190 ARMConstantPoolSymbol::Create(*DAG.getContext(), "_GLOBAL_OFFSET_TABLE_", 2191 ARMPCLabelIndex, PCAdj); 2192 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2193 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2194 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2195 MachinePointerInfo::getConstantPool(), 2196 false, false, 0); 2197 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2198 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 2199} 2200 2201SDValue 2202ARMTargetLowering::LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG) 2203 const { 2204 DebugLoc dl = Op.getDebugLoc(); 2205 return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other, 2206 Op.getOperand(0), Op.getOperand(1)); 2207} 2208 2209SDValue 2210ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const { 2211 DebugLoc dl = Op.getDebugLoc(); 2212 SDValue Val = DAG.getConstant(0, MVT::i32); 2213 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, 2214 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0), 2215 Op.getOperand(1), Val); 2216} 2217 2218SDValue 2219ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const { 2220 DebugLoc dl = Op.getDebugLoc(); 2221 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0), 2222 Op.getOperand(1), DAG.getConstant(0, MVT::i32)); 2223} 2224 2225SDValue 2226ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 2227 const ARMSubtarget *Subtarget) const { 2228 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 2229 DebugLoc dl = Op.getDebugLoc(); 2230 switch (IntNo) { 2231 default: return SDValue(); // Don't custom lower most intrinsics. 2232 case Intrinsic::arm_thread_pointer: { 2233 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2234 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); 2235 } 2236 case Intrinsic::eh_sjlj_lsda: { 2237 MachineFunction &MF = DAG.getMachineFunction(); 2238 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2239 unsigned ARMPCLabelIndex = AFI->createPICLabelUId(); 2240 EVT PtrVT = getPointerTy(); 2241 DebugLoc dl = Op.getDebugLoc(); 2242 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 2243 SDValue CPAddr; 2244 unsigned PCAdj = (RelocM != Reloc::PIC_) 2245 ? 0 : (Subtarget->isThumb() ? 4 : 8); 2246 ARMConstantPoolValue *CPV = 2247 ARMConstantPoolConstant::Create(MF.getFunction(), ARMPCLabelIndex, 2248 ARMCP::CPLSDA, PCAdj); 2249 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); 2250 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); 2251 SDValue Result = 2252 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, 2253 MachinePointerInfo::getConstantPool(), 2254 false, false, 0); 2255 2256 if (RelocM == Reloc::PIC_) { 2257 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32); 2258 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); 2259 } 2260 return Result; 2261 } 2262 case Intrinsic::arm_neon_vmulls: 2263 case Intrinsic::arm_neon_vmullu: { 2264 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls) 2265 ? ARMISD::VMULLs : ARMISD::VMULLu; 2266 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(), 2267 Op.getOperand(1), Op.getOperand(2)); 2268 } 2269 } 2270} 2271 2272static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG, 2273 const ARMSubtarget *Subtarget) { 2274 DebugLoc dl = Op.getDebugLoc(); 2275 if (!Subtarget->hasDataBarrier()) { 2276 // Some ARMv6 cpus can support data barriers with an mcr instruction. 2277 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get 2278 // here. 2279 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() && 2280 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!"); 2281 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0), 2282 DAG.getConstant(0, MVT::i32)); 2283 } 2284 2285 SDValue Op5 = Op.getOperand(5); 2286 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0; 2287 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 2288 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 2289 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0); 2290 2291 ARM_MB::MemBOpt DMBOpt; 2292 if (isDeviceBarrier) 2293 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY; 2294 else 2295 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH; 2296 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0), 2297 DAG.getConstant(DMBOpt, MVT::i32)); 2298} 2299 2300 2301static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG, 2302 const ARMSubtarget *Subtarget) { 2303 // FIXME: handle "fence singlethread" more efficiently. 2304 DebugLoc dl = Op.getDebugLoc(); 2305 if (!Subtarget->hasDataBarrier()) { 2306 // Some ARMv6 cpus can support data barriers with an mcr instruction. 2307 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get 2308 // here. 2309 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() && 2310 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!"); 2311 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0), 2312 DAG.getConstant(0, MVT::i32)); 2313 } 2314 2315 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0), 2316 DAG.getConstant(ARM_MB::ISH, MVT::i32)); 2317} 2318 2319static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG, 2320 const ARMSubtarget *Subtarget) { 2321 // ARM pre v5TE and Thumb1 does not have preload instructions. 2322 if (!(Subtarget->isThumb2() || 2323 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps()))) 2324 // Just preserve the chain. 2325 return Op.getOperand(0); 2326 2327 DebugLoc dl = Op.getDebugLoc(); 2328 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1; 2329 if (!isRead && 2330 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension())) 2331 // ARMv7 with MP extension has PLDW. 2332 return Op.getOperand(0); 2333 2334 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 2335 if (Subtarget->isThumb()) { 2336 // Invert the bits. 2337 isRead = ~isRead & 1; 2338 isData = ~isData & 1; 2339 } 2340 2341 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0), 2342 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32), 2343 DAG.getConstant(isData, MVT::i32)); 2344} 2345 2346static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) { 2347 MachineFunction &MF = DAG.getMachineFunction(); 2348 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>(); 2349 2350 // vastart just stores the address of the VarArgsFrameIndex slot into the 2351 // memory location argument. 2352 DebugLoc dl = Op.getDebugLoc(); 2353 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 2354 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); 2355 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 2356 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), 2357 MachinePointerInfo(SV), false, false, 0); 2358} 2359 2360SDValue 2361ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 2362 SDValue &Root, SelectionDAG &DAG, 2363 DebugLoc dl) const { 2364 MachineFunction &MF = DAG.getMachineFunction(); 2365 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2366 2367 TargetRegisterClass *RC; 2368 if (AFI->isThumb1OnlyFunction()) 2369 RC = ARM::tGPRRegisterClass; 2370 else 2371 RC = ARM::GPRRegisterClass; 2372 2373 // Transform the arguments stored in physical registers into virtual ones. 2374 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 2375 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); 2376 2377 SDValue ArgValue2; 2378 if (NextVA.isMemLoc()) { 2379 MachineFrameInfo *MFI = MF.getFrameInfo(); 2380 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true); 2381 2382 // Create load node to retrieve arguments from the stack. 2383 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2384 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, 2385 MachinePointerInfo::getFixedStack(FI), 2386 false, false, 0); 2387 } else { 2388 Reg = MF.addLiveIn(NextVA.getLocReg(), RC); 2389 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); 2390 } 2391 2392 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2); 2393} 2394 2395void 2396ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF, 2397 unsigned &VARegSize, unsigned &VARegSaveSize) 2398 const { 2399 unsigned NumGPRs; 2400 if (CCInfo.isFirstByValRegValid()) 2401 NumGPRs = ARM::R4 - CCInfo.getFirstByValReg(); 2402 else { 2403 unsigned int firstUnalloced; 2404 firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs, 2405 sizeof(GPRArgRegs) / 2406 sizeof(GPRArgRegs[0])); 2407 NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0; 2408 } 2409 2410 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment(); 2411 VARegSize = NumGPRs * 4; 2412 VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1); 2413} 2414 2415// The remaining GPRs hold either the beginning of variable-argument 2416// data, or the beginning of an aggregate passed by value (usuall 2417// byval). Either way, we allocate stack slots adjacent to the data 2418// provided by our caller, and store the unallocated registers there. 2419// If this is a variadic function, the va_list pointer will begin with 2420// these values; otherwise, this reassembles a (byval) structure that 2421// was split between registers and memory. 2422void 2423ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, 2424 DebugLoc dl, SDValue &Chain, 2425 unsigned ArgOffset) const { 2426 MachineFunction &MF = DAG.getMachineFunction(); 2427 MachineFrameInfo *MFI = MF.getFrameInfo(); 2428 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2429 unsigned firstRegToSaveIndex; 2430 if (CCInfo.isFirstByValRegValid()) 2431 firstRegToSaveIndex = CCInfo.getFirstByValReg() - ARM::R0; 2432 else { 2433 firstRegToSaveIndex = CCInfo.getFirstUnallocated 2434 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0])); 2435 } 2436 2437 unsigned VARegSize, VARegSaveSize; 2438 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize); 2439 if (VARegSaveSize) { 2440 // If this function is vararg, store any remaining integer argument regs 2441 // to their spots on the stack so that they may be loaded by deferencing 2442 // the result of va_next. 2443 AFI->setVarArgsRegSaveSize(VARegSaveSize); 2444 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(VARegSaveSize, 2445 ArgOffset + VARegSaveSize 2446 - VARegSize, 2447 false)); 2448 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(), 2449 getPointerTy()); 2450 2451 SmallVector<SDValue, 4> MemOps; 2452 for (; firstRegToSaveIndex < 4; ++firstRegToSaveIndex) { 2453 TargetRegisterClass *RC; 2454 if (AFI->isThumb1OnlyFunction()) 2455 RC = ARM::tGPRRegisterClass; 2456 else 2457 RC = ARM::GPRRegisterClass; 2458 2459 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC); 2460 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 2461 SDValue Store = 2462 DAG.getStore(Val.getValue(1), dl, Val, FIN, 2463 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()), 2464 false, false, 0); 2465 MemOps.push_back(Store); 2466 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN, 2467 DAG.getConstant(4, getPointerTy())); 2468 } 2469 if (!MemOps.empty()) 2470 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2471 &MemOps[0], MemOps.size()); 2472 } else 2473 // This will point to the next argument passed via stack. 2474 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true)); 2475} 2476 2477SDValue 2478ARMTargetLowering::LowerFormalArguments(SDValue Chain, 2479 CallingConv::ID CallConv, bool isVarArg, 2480 const SmallVectorImpl<ISD::InputArg> 2481 &Ins, 2482 DebugLoc dl, SelectionDAG &DAG, 2483 SmallVectorImpl<SDValue> &InVals) 2484 const { 2485 MachineFunction &MF = DAG.getMachineFunction(); 2486 MachineFrameInfo *MFI = MF.getFrameInfo(); 2487 2488 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 2489 2490 // Assign locations to all of the incoming arguments. 2491 SmallVector<CCValAssign, 16> ArgLocs; 2492 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2493 getTargetMachine(), ArgLocs, *DAG.getContext(), Prologue); 2494 CCInfo.AnalyzeFormalArguments(Ins, 2495 CCAssignFnForNode(CallConv, /* Return*/ false, 2496 isVarArg)); 2497 2498 SmallVector<SDValue, 16> ArgValues; 2499 int lastInsIndex = -1; 2500 2501 SDValue ArgValue; 2502 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2503 CCValAssign &VA = ArgLocs[i]; 2504 2505 // Arguments stored in registers. 2506 if (VA.isRegLoc()) { 2507 EVT RegVT = VA.getLocVT(); 2508 2509 if (VA.needsCustom()) { 2510 // f64 and vector types are split up into multiple registers or 2511 // combinations of registers and stack slots. 2512 if (VA.getLocVT() == MVT::v2f64) { 2513 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i], 2514 Chain, DAG, dl); 2515 VA = ArgLocs[++i]; // skip ahead to next loc 2516 SDValue ArgValue2; 2517 if (VA.isMemLoc()) { 2518 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true); 2519 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2520 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN, 2521 MachinePointerInfo::getFixedStack(FI), 2522 false, false, 0); 2523 } else { 2524 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], 2525 Chain, DAG, dl); 2526 } 2527 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); 2528 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, 2529 ArgValue, ArgValue1, DAG.getIntPtrConstant(0)); 2530 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, 2531 ArgValue, ArgValue2, DAG.getIntPtrConstant(1)); 2532 } else 2533 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl); 2534 2535 } else { 2536 TargetRegisterClass *RC; 2537 2538 if (RegVT == MVT::f32) 2539 RC = ARM::SPRRegisterClass; 2540 else if (RegVT == MVT::f64) 2541 RC = ARM::DPRRegisterClass; 2542 else if (RegVT == MVT::v2f64) 2543 RC = ARM::QPRRegisterClass; 2544 else if (RegVT == MVT::i32) 2545 RC = (AFI->isThumb1OnlyFunction() ? 2546 ARM::tGPRRegisterClass : ARM::GPRRegisterClass); 2547 else 2548 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering"); 2549 2550 // Transform the arguments in physical registers into virtual ones. 2551 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 2552 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 2553 } 2554 2555 // If this is an 8 or 16-bit value, it is really passed promoted 2556 // to 32 bits. Insert an assert[sz]ext to capture this, then 2557 // truncate to the right size. 2558 switch (VA.getLocInfo()) { 2559 default: llvm_unreachable("Unknown loc info!"); 2560 case CCValAssign::Full: break; 2561 case CCValAssign::BCvt: 2562 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 2563 break; 2564 case CCValAssign::SExt: 2565 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 2566 DAG.getValueType(VA.getValVT())); 2567 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2568 break; 2569 case CCValAssign::ZExt: 2570 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 2571 DAG.getValueType(VA.getValVT())); 2572 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2573 break; 2574 } 2575 2576 InVals.push_back(ArgValue); 2577 2578 } else { // VA.isRegLoc() 2579 2580 // sanity check 2581 assert(VA.isMemLoc()); 2582 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered"); 2583 2584 int index = ArgLocs[i].getValNo(); 2585 2586 // Some Ins[] entries become multiple ArgLoc[] entries. 2587 // Process them only once. 2588 if (index != lastInsIndex) 2589 { 2590 ISD::ArgFlagsTy Flags = Ins[index].Flags; 2591 // FIXME: For now, all byval parameter objects are marked mutable. 2592 // This can be changed with more analysis. 2593 // In case of tail call optimization mark all arguments mutable. 2594 // Since they could be overwritten by lowering of arguments in case of 2595 // a tail call. 2596 if (Flags.isByVal()) { 2597 unsigned VARegSize, VARegSaveSize; 2598 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize); 2599 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, 0); 2600 unsigned Bytes = Flags.getByValSize() - VARegSize; 2601 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 2602 int FI = MFI->CreateFixedObject(Bytes, 2603 VA.getLocMemOffset(), false); 2604 InVals.push_back(DAG.getFrameIndex(FI, getPointerTy())); 2605 } else { 2606 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8, 2607 VA.getLocMemOffset(), true); 2608 2609 // Create load nodes to retrieve arguments from the stack. 2610 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 2611 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 2612 MachinePointerInfo::getFixedStack(FI), 2613 false, false, 0)); 2614 } 2615 lastInsIndex = index; 2616 } 2617 } 2618 } 2619 2620 // varargs 2621 if (isVarArg) 2622 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, CCInfo.getNextStackOffset()); 2623 2624 return Chain; 2625} 2626 2627/// isFloatingPointZero - Return true if this is +0.0. 2628static bool isFloatingPointZero(SDValue Op) { 2629 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 2630 return CFP->getValueAPF().isPosZero(); 2631 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 2632 // Maybe this has already been legalized into the constant pool? 2633 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) { 2634 SDValue WrapperOp = Op.getOperand(1).getOperand(0); 2635 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp)) 2636 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 2637 return CFP->getValueAPF().isPosZero(); 2638 } 2639 } 2640 return false; 2641} 2642 2643/// Returns appropriate ARM CMP (cmp) and corresponding condition code for 2644/// the given operands. 2645SDValue 2646ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 2647 SDValue &ARMcc, SelectionDAG &DAG, 2648 DebugLoc dl) const { 2649 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) { 2650 unsigned C = RHSC->getZExtValue(); 2651 if (!isLegalICmpImmediate(C)) { 2652 // Constant does not fit, try adjusting it by one? 2653 switch (CC) { 2654 default: break; 2655 case ISD::SETLT: 2656 case ISD::SETGE: 2657 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) { 2658 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 2659 RHS = DAG.getConstant(C-1, MVT::i32); 2660 } 2661 break; 2662 case ISD::SETULT: 2663 case ISD::SETUGE: 2664 if (C != 0 && isLegalICmpImmediate(C-1)) { 2665 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 2666 RHS = DAG.getConstant(C-1, MVT::i32); 2667 } 2668 break; 2669 case ISD::SETLE: 2670 case ISD::SETGT: 2671 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) { 2672 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; 2673 RHS = DAG.getConstant(C+1, MVT::i32); 2674 } 2675 break; 2676 case ISD::SETULE: 2677 case ISD::SETUGT: 2678 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) { 2679 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 2680 RHS = DAG.getConstant(C+1, MVT::i32); 2681 } 2682 break; 2683 } 2684 } 2685 } 2686 2687 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 2688 ARMISD::NodeType CompareType; 2689 switch (CondCode) { 2690 default: 2691 CompareType = ARMISD::CMP; 2692 break; 2693 case ARMCC::EQ: 2694 case ARMCC::NE: 2695 // Uses only Z Flag 2696 CompareType = ARMISD::CMPZ; 2697 break; 2698 } 2699 ARMcc = DAG.getConstant(CondCode, MVT::i32); 2700 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS); 2701} 2702 2703/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands. 2704SDValue 2705ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, 2706 DebugLoc dl) const { 2707 SDValue Cmp; 2708 if (!isFloatingPointZero(RHS)) 2709 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS); 2710 else 2711 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS); 2712 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp); 2713} 2714 2715/// duplicateCmp - Glue values can have only one use, so this function 2716/// duplicates a comparison node. 2717SDValue 2718ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const { 2719 unsigned Opc = Cmp.getOpcode(); 2720 DebugLoc DL = Cmp.getDebugLoc(); 2721 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ) 2722 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1)); 2723 2724 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation"); 2725 Cmp = Cmp.getOperand(0); 2726 Opc = Cmp.getOpcode(); 2727 if (Opc == ARMISD::CMPFP) 2728 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1)); 2729 else { 2730 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT"); 2731 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0)); 2732 } 2733 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp); 2734} 2735 2736SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 2737 SDValue Cond = Op.getOperand(0); 2738 SDValue SelectTrue = Op.getOperand(1); 2739 SDValue SelectFalse = Op.getOperand(2); 2740 DebugLoc dl = Op.getDebugLoc(); 2741 2742 // Convert: 2743 // 2744 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond) 2745 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond) 2746 // 2747 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) { 2748 const ConstantSDNode *CMOVTrue = 2749 dyn_cast<ConstantSDNode>(Cond.getOperand(0)); 2750 const ConstantSDNode *CMOVFalse = 2751 dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 2752 2753 if (CMOVTrue && CMOVFalse) { 2754 unsigned CMOVTrueVal = CMOVTrue->getZExtValue(); 2755 unsigned CMOVFalseVal = CMOVFalse->getZExtValue(); 2756 2757 SDValue True; 2758 SDValue False; 2759 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) { 2760 True = SelectTrue; 2761 False = SelectFalse; 2762 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) { 2763 True = SelectFalse; 2764 False = SelectTrue; 2765 } 2766 2767 if (True.getNode() && False.getNode()) { 2768 EVT VT = Op.getValueType(); 2769 SDValue ARMcc = Cond.getOperand(2); 2770 SDValue CCR = Cond.getOperand(3); 2771 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG); 2772 assert(True.getValueType() == VT); 2773 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp); 2774 } 2775 } 2776 } 2777 2778 return DAG.getSelectCC(dl, Cond, 2779 DAG.getConstant(0, Cond.getValueType()), 2780 SelectTrue, SelectFalse, ISD::SETNE); 2781} 2782 2783SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 2784 EVT VT = Op.getValueType(); 2785 SDValue LHS = Op.getOperand(0); 2786 SDValue RHS = Op.getOperand(1); 2787 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 2788 SDValue TrueVal = Op.getOperand(2); 2789 SDValue FalseVal = Op.getOperand(3); 2790 DebugLoc dl = Op.getDebugLoc(); 2791 2792 if (LHS.getValueType() == MVT::i32) { 2793 SDValue ARMcc; 2794 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2795 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); 2796 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp); 2797 } 2798 2799 ARMCC::CondCodes CondCode, CondCode2; 2800 FPCCToARMCC(CC, CondCode, CondCode2); 2801 2802 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32); 2803 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); 2804 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2805 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, 2806 ARMcc, CCR, Cmp); 2807 if (CondCode2 != ARMCC::AL) { 2808 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32); 2809 // FIXME: Needs another CMP because flag can have but one use. 2810 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl); 2811 Result = DAG.getNode(ARMISD::CMOV, dl, VT, 2812 Result, TrueVal, ARMcc2, CCR, Cmp2); 2813 } 2814 return Result; 2815} 2816 2817/// canChangeToInt - Given the fp compare operand, return true if it is suitable 2818/// to morph to an integer compare sequence. 2819static bool canChangeToInt(SDValue Op, bool &SeenZero, 2820 const ARMSubtarget *Subtarget) { 2821 SDNode *N = Op.getNode(); 2822 if (!N->hasOneUse()) 2823 // Otherwise it requires moving the value from fp to integer registers. 2824 return false; 2825 if (!N->getNumValues()) 2826 return false; 2827 EVT VT = Op.getValueType(); 2828 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow()) 2829 // f32 case is generally profitable. f64 case only makes sense when vcmpe + 2830 // vmrs are very slow, e.g. cortex-a8. 2831 return false; 2832 2833 if (isFloatingPointZero(Op)) { 2834 SeenZero = true; 2835 return true; 2836 } 2837 return ISD::isNormalLoad(N); 2838} 2839 2840static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) { 2841 if (isFloatingPointZero(Op)) 2842 return DAG.getConstant(0, MVT::i32); 2843 2844 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) 2845 return DAG.getLoad(MVT::i32, Op.getDebugLoc(), 2846 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(), 2847 Ld->isVolatile(), Ld->isNonTemporal(), 2848 Ld->getAlignment()); 2849 2850 llvm_unreachable("Unknown VFP cmp argument!"); 2851} 2852 2853static void expandf64Toi32(SDValue Op, SelectionDAG &DAG, 2854 SDValue &RetVal1, SDValue &RetVal2) { 2855 if (isFloatingPointZero(Op)) { 2856 RetVal1 = DAG.getConstant(0, MVT::i32); 2857 RetVal2 = DAG.getConstant(0, MVT::i32); 2858 return; 2859 } 2860 2861 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) { 2862 SDValue Ptr = Ld->getBasePtr(); 2863 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(), 2864 Ld->getChain(), Ptr, 2865 Ld->getPointerInfo(), 2866 Ld->isVolatile(), Ld->isNonTemporal(), 2867 Ld->getAlignment()); 2868 2869 EVT PtrType = Ptr.getValueType(); 2870 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4); 2871 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(), 2872 PtrType, Ptr, DAG.getConstant(4, PtrType)); 2873 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(), 2874 Ld->getChain(), NewPtr, 2875 Ld->getPointerInfo().getWithOffset(4), 2876 Ld->isVolatile(), Ld->isNonTemporal(), 2877 NewAlign); 2878 return; 2879 } 2880 2881 llvm_unreachable("Unknown VFP cmp argument!"); 2882} 2883 2884/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some 2885/// f32 and even f64 comparisons to integer ones. 2886SDValue 2887ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const { 2888 SDValue Chain = Op.getOperand(0); 2889 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 2890 SDValue LHS = Op.getOperand(2); 2891 SDValue RHS = Op.getOperand(3); 2892 SDValue Dest = Op.getOperand(4); 2893 DebugLoc dl = Op.getDebugLoc(); 2894 2895 bool SeenZero = false; 2896 if (canChangeToInt(LHS, SeenZero, Subtarget) && 2897 canChangeToInt(RHS, SeenZero, Subtarget) && 2898 // If one of the operand is zero, it's safe to ignore the NaN case since 2899 // we only care about equality comparisons. 2900 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) { 2901 // If unsafe fp math optimization is enabled and there are no other uses of 2902 // the CMP operands, and the condition code is EQ or NE, we can optimize it 2903 // to an integer comparison. 2904 if (CC == ISD::SETOEQ) 2905 CC = ISD::SETEQ; 2906 else if (CC == ISD::SETUNE) 2907 CC = ISD::SETNE; 2908 2909 SDValue ARMcc; 2910 if (LHS.getValueType() == MVT::f32) { 2911 LHS = bitcastf32Toi32(LHS, DAG); 2912 RHS = bitcastf32Toi32(RHS, DAG); 2913 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); 2914 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2915 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, 2916 Chain, Dest, ARMcc, CCR, Cmp); 2917 } 2918 2919 SDValue LHS1, LHS2; 2920 SDValue RHS1, RHS2; 2921 expandf64Toi32(LHS, DAG, LHS1, LHS2); 2922 expandf64Toi32(RHS, DAG, RHS1, RHS2); 2923 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 2924 ARMcc = DAG.getConstant(CondCode, MVT::i32); 2925 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); 2926 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest }; 2927 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7); 2928 } 2929 2930 return SDValue(); 2931} 2932 2933SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const { 2934 SDValue Chain = Op.getOperand(0); 2935 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 2936 SDValue LHS = Op.getOperand(2); 2937 SDValue RHS = Op.getOperand(3); 2938 SDValue Dest = Op.getOperand(4); 2939 DebugLoc dl = Op.getDebugLoc(); 2940 2941 if (LHS.getValueType() == MVT::i32) { 2942 SDValue ARMcc; 2943 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); 2944 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2945 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, 2946 Chain, Dest, ARMcc, CCR, Cmp); 2947 } 2948 2949 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); 2950 2951 if (UnsafeFPMath && 2952 (CC == ISD::SETEQ || CC == ISD::SETOEQ || 2953 CC == ISD::SETNE || CC == ISD::SETUNE)) { 2954 SDValue Result = OptimizeVFPBrcond(Op, DAG); 2955 if (Result.getNode()) 2956 return Result; 2957 } 2958 2959 ARMCC::CondCodes CondCode, CondCode2; 2960 FPCCToARMCC(CC, CondCode, CondCode2); 2961 2962 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32); 2963 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); 2964 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 2965 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue); 2966 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp }; 2967 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); 2968 if (CondCode2 != ARMCC::AL) { 2969 ARMcc = DAG.getConstant(CondCode2, MVT::i32); 2970 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) }; 2971 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); 2972 } 2973 return Res; 2974} 2975 2976SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const { 2977 SDValue Chain = Op.getOperand(0); 2978 SDValue Table = Op.getOperand(1); 2979 SDValue Index = Op.getOperand(2); 2980 DebugLoc dl = Op.getDebugLoc(); 2981 2982 EVT PTy = getPointerTy(); 2983 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); 2984 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>(); 2985 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); 2986 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); 2987 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId); 2988 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy)); 2989 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 2990 if (Subtarget->isThumb2()) { 2991 // Thumb2 uses a two-level jump. That is, it jumps into the jump table 2992 // which does another jump to the destination. This also makes it easier 2993 // to translate it to TBB / TBH later. 2994 // FIXME: This might not work if the function is extremely large. 2995 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain, 2996 Addr, Op.getOperand(2), JTI, UId); 2997 } 2998 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2999 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr, 3000 MachinePointerInfo::getJumpTable(), 3001 false, false, 0); 3002 Chain = Addr.getValue(1); 3003 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table); 3004 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); 3005 } else { 3006 Addr = DAG.getLoad(PTy, dl, Chain, Addr, 3007 MachinePointerInfo::getJumpTable(), false, false, 0); 3008 Chain = Addr.getValue(1); 3009 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); 3010 } 3011} 3012 3013static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) { 3014 DebugLoc dl = Op.getDebugLoc(); 3015 unsigned Opc; 3016 3017 switch (Op.getOpcode()) { 3018 default: 3019 assert(0 && "Invalid opcode!"); 3020 case ISD::FP_TO_SINT: 3021 Opc = ARMISD::FTOSI; 3022 break; 3023 case ISD::FP_TO_UINT: 3024 Opc = ARMISD::FTOUI; 3025 break; 3026 } 3027 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0)); 3028 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3029} 3030 3031static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 3032 EVT VT = Op.getValueType(); 3033 DebugLoc dl = Op.getDebugLoc(); 3034 3035 assert(Op.getOperand(0).getValueType() == MVT::v4i16 && 3036 "Invalid type for custom lowering!"); 3037 if (VT != MVT::v4f32) 3038 return DAG.UnrollVectorOp(Op.getNode()); 3039 3040 unsigned CastOpc; 3041 unsigned Opc; 3042 switch (Op.getOpcode()) { 3043 default: 3044 assert(0 && "Invalid opcode!"); 3045 case ISD::SINT_TO_FP: 3046 CastOpc = ISD::SIGN_EXTEND; 3047 Opc = ISD::SINT_TO_FP; 3048 break; 3049 case ISD::UINT_TO_FP: 3050 CastOpc = ISD::ZERO_EXTEND; 3051 Opc = ISD::UINT_TO_FP; 3052 break; 3053 } 3054 3055 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0)); 3056 return DAG.getNode(Opc, dl, VT, Op); 3057} 3058 3059static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 3060 EVT VT = Op.getValueType(); 3061 if (VT.isVector()) 3062 return LowerVectorINT_TO_FP(Op, DAG); 3063 3064 DebugLoc dl = Op.getDebugLoc(); 3065 unsigned Opc; 3066 3067 switch (Op.getOpcode()) { 3068 default: 3069 assert(0 && "Invalid opcode!"); 3070 case ISD::SINT_TO_FP: 3071 Opc = ARMISD::SITOF; 3072 break; 3073 case ISD::UINT_TO_FP: 3074 Opc = ARMISD::UITOF; 3075 break; 3076 } 3077 3078 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0)); 3079 return DAG.getNode(Opc, dl, VT, Op); 3080} 3081 3082SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 3083 // Implement fcopysign with a fabs and a conditional fneg. 3084 SDValue Tmp0 = Op.getOperand(0); 3085 SDValue Tmp1 = Op.getOperand(1); 3086 DebugLoc dl = Op.getDebugLoc(); 3087 EVT VT = Op.getValueType(); 3088 EVT SrcVT = Tmp1.getValueType(); 3089 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST || 3090 Tmp0.getOpcode() == ARMISD::VMOVDRR; 3091 bool UseNEON = !InGPR && Subtarget->hasNEON(); 3092 3093 if (UseNEON) { 3094 // Use VBSL to copy the sign bit. 3095 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80); 3096 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32, 3097 DAG.getTargetConstant(EncodedVal, MVT::i32)); 3098 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64; 3099 if (VT == MVT::f64) 3100 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT, 3101 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask), 3102 DAG.getConstant(32, MVT::i32)); 3103 else /*if (VT == MVT::f32)*/ 3104 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0); 3105 if (SrcVT == MVT::f32) { 3106 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1); 3107 if (VT == MVT::f64) 3108 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT, 3109 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1), 3110 DAG.getConstant(32, MVT::i32)); 3111 } else if (VT == MVT::f32) 3112 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64, 3113 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1), 3114 DAG.getConstant(32, MVT::i32)); 3115 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0); 3116 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1); 3117 3118 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff), 3119 MVT::i32); 3120 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes); 3121 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask, 3122 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes)); 3123 3124 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT, 3125 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask), 3126 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot)); 3127 if (VT == MVT::f32) { 3128 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res); 3129 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res, 3130 DAG.getConstant(0, MVT::i32)); 3131 } else { 3132 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res); 3133 } 3134 3135 return Res; 3136 } 3137 3138 // Bitcast operand 1 to i32. 3139 if (SrcVT == MVT::f64) 3140 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), 3141 &Tmp1, 1).getValue(1); 3142 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1); 3143 3144 // Or in the signbit with integer operations. 3145 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32); 3146 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32); 3147 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1); 3148 if (VT == MVT::f32) { 3149 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32, 3150 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2); 3151 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, 3152 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1)); 3153 } 3154 3155 // f64: Or the high part with signbit and then combine two parts. 3156 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32), 3157 &Tmp0, 1); 3158 SDValue Lo = Tmp0.getValue(0); 3159 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2); 3160 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1); 3161 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi); 3162} 3163 3164SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{ 3165 MachineFunction &MF = DAG.getMachineFunction(); 3166 MachineFrameInfo *MFI = MF.getFrameInfo(); 3167 MFI->setReturnAddressIsTaken(true); 3168 3169 EVT VT = Op.getValueType(); 3170 DebugLoc dl = Op.getDebugLoc(); 3171 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 3172 if (Depth) { 3173 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 3174 SDValue Offset = DAG.getConstant(4, MVT::i32); 3175 return DAG.getLoad(VT, dl, DAG.getEntryNode(), 3176 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset), 3177 MachinePointerInfo(), false, false, 0); 3178 } 3179 3180 // Return LR, which contains the return address. Mark it an implicit live-in. 3181 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32)); 3182 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT); 3183} 3184 3185SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 3186 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3187 MFI->setFrameAddressIsTaken(true); 3188 3189 EVT VT = Op.getValueType(); 3190 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 3191 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 3192 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin()) 3193 ? ARM::R7 : ARM::R11; 3194 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 3195 while (Depth--) 3196 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 3197 MachinePointerInfo(), 3198 false, false, 0); 3199 return FrameAddr; 3200} 3201 3202/// ExpandBITCAST - If the target supports VFP, this function is called to 3203/// expand a bit convert where either the source or destination type is i64 to 3204/// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64 3205/// operand type is illegal (e.g., v2f32 for a target that doesn't support 3206/// vectors), since the legalizer won't know what to do with that. 3207static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) { 3208 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 3209 DebugLoc dl = N->getDebugLoc(); 3210 SDValue Op = N->getOperand(0); 3211 3212 // This function is only supposed to be called for i64 types, either as the 3213 // source or destination of the bit convert. 3214 EVT SrcVT = Op.getValueType(); 3215 EVT DstVT = N->getValueType(0); 3216 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) && 3217 "ExpandBITCAST called for non-i64 type"); 3218 3219 // Turn i64->f64 into VMOVDRR. 3220 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) { 3221 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, 3222 DAG.getConstant(0, MVT::i32)); 3223 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, 3224 DAG.getConstant(1, MVT::i32)); 3225 return DAG.getNode(ISD::BITCAST, dl, DstVT, 3226 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi)); 3227 } 3228 3229 // Turn f64->i64 into VMOVRRD. 3230 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) { 3231 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl, 3232 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1); 3233 // Merge the pieces into a single i64 value. 3234 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1)); 3235 } 3236 3237 return SDValue(); 3238} 3239 3240/// getZeroVector - Returns a vector of specified type with all zero elements. 3241/// Zero vectors are used to represent vector negation and in those cases 3242/// will be implemented with the NEON VNEG instruction. However, VNEG does 3243/// not support i64 elements, so sometimes the zero vectors will need to be 3244/// explicitly constructed. Regardless, use a canonical VMOV to create the 3245/// zero vector. 3246static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 3247 assert(VT.isVector() && "Expected a vector type"); 3248 // The canonical modified immediate encoding of a zero vector is....0! 3249 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32); 3250 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32; 3251 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal); 3252 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); 3253} 3254 3255/// LowerShiftRightParts - Lower SRA_PARTS, which returns two 3256/// i32 values and take a 2 x i32 value to shift plus a shift amount. 3257SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op, 3258 SelectionDAG &DAG) const { 3259 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 3260 EVT VT = Op.getValueType(); 3261 unsigned VTBits = VT.getSizeInBits(); 3262 DebugLoc dl = Op.getDebugLoc(); 3263 SDValue ShOpLo = Op.getOperand(0); 3264 SDValue ShOpHi = Op.getOperand(1); 3265 SDValue ShAmt = Op.getOperand(2); 3266 SDValue ARMcc; 3267 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL; 3268 3269 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS); 3270 3271 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, 3272 DAG.getConstant(VTBits, MVT::i32), ShAmt); 3273 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); 3274 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, 3275 DAG.getConstant(VTBits, MVT::i32)); 3276 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); 3277 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 3278 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt); 3279 3280 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 3281 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, 3282 ARMcc, DAG, dl); 3283 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt); 3284 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, 3285 CCR, Cmp); 3286 3287 SDValue Ops[2] = { Lo, Hi }; 3288 return DAG.getMergeValues(Ops, 2, dl); 3289} 3290 3291/// LowerShiftLeftParts - Lower SHL_PARTS, which returns two 3292/// i32 values and take a 2 x i32 value to shift plus a shift amount. 3293SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op, 3294 SelectionDAG &DAG) const { 3295 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 3296 EVT VT = Op.getValueType(); 3297 unsigned VTBits = VT.getSizeInBits(); 3298 DebugLoc dl = Op.getDebugLoc(); 3299 SDValue ShOpLo = Op.getOperand(0); 3300 SDValue ShOpHi = Op.getOperand(1); 3301 SDValue ShAmt = Op.getOperand(2); 3302 SDValue ARMcc; 3303 3304 assert(Op.getOpcode() == ISD::SHL_PARTS); 3305 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, 3306 DAG.getConstant(VTBits, MVT::i32), ShAmt); 3307 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); 3308 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt, 3309 DAG.getConstant(VTBits, MVT::i32)); 3310 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); 3311 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); 3312 3313 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 3314 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 3315 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE, 3316 ARMcc, DAG, dl); 3317 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 3318 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc, 3319 CCR, Cmp); 3320 3321 SDValue Ops[2] = { Lo, Hi }; 3322 return DAG.getMergeValues(Ops, 2, dl); 3323} 3324 3325SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op, 3326 SelectionDAG &DAG) const { 3327 // The rounding mode is in bits 23:22 of the FPSCR. 3328 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0 3329 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3) 3330 // so that the shift + and get folded into a bitfield extract. 3331 DebugLoc dl = Op.getDebugLoc(); 3332 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32, 3333 DAG.getConstant(Intrinsic::arm_get_fpscr, 3334 MVT::i32)); 3335 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR, 3336 DAG.getConstant(1U << 22, MVT::i32)); 3337 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds, 3338 DAG.getConstant(22, MVT::i32)); 3339 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE, 3340 DAG.getConstant(3, MVT::i32)); 3341} 3342 3343static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG, 3344 const ARMSubtarget *ST) { 3345 EVT VT = N->getValueType(0); 3346 DebugLoc dl = N->getDebugLoc(); 3347 3348 if (!ST->hasV6T2Ops()) 3349 return SDValue(); 3350 3351 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0)); 3352 return DAG.getNode(ISD::CTLZ, dl, VT, rbit); 3353} 3354 3355static SDValue LowerShift(SDNode *N, SelectionDAG &DAG, 3356 const ARMSubtarget *ST) { 3357 EVT VT = N->getValueType(0); 3358 DebugLoc dl = N->getDebugLoc(); 3359 3360 if (!VT.isVector()) 3361 return SDValue(); 3362 3363 // Lower vector shifts on NEON to use VSHL. 3364 assert(ST->hasNEON() && "unexpected vector shift"); 3365 3366 // Left shifts translate directly to the vshiftu intrinsic. 3367 if (N->getOpcode() == ISD::SHL) 3368 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 3369 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32), 3370 N->getOperand(0), N->getOperand(1)); 3371 3372 assert((N->getOpcode() == ISD::SRA || 3373 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode"); 3374 3375 // NEON uses the same intrinsics for both left and right shifts. For 3376 // right shifts, the shift amounts are negative, so negate the vector of 3377 // shift amounts. 3378 EVT ShiftVT = N->getOperand(1).getValueType(); 3379 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT, 3380 getZeroVector(ShiftVT, DAG, dl), 3381 N->getOperand(1)); 3382 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ? 3383 Intrinsic::arm_neon_vshifts : 3384 Intrinsic::arm_neon_vshiftu); 3385 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 3386 DAG.getConstant(vshiftInt, MVT::i32), 3387 N->getOperand(0), NegatedCount); 3388} 3389 3390static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG, 3391 const ARMSubtarget *ST) { 3392 EVT VT = N->getValueType(0); 3393 DebugLoc dl = N->getDebugLoc(); 3394 3395 // We can get here for a node like i32 = ISD::SHL i32, i64 3396 if (VT != MVT::i64) 3397 return SDValue(); 3398 3399 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && 3400 "Unknown shift to lower!"); 3401 3402 // We only lower SRA, SRL of 1 here, all others use generic lowering. 3403 if (!isa<ConstantSDNode>(N->getOperand(1)) || 3404 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1) 3405 return SDValue(); 3406 3407 // If we are in thumb mode, we don't have RRX. 3408 if (ST->isThumb1Only()) return SDValue(); 3409 3410 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr. 3411 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), 3412 DAG.getConstant(0, MVT::i32)); 3413 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), 3414 DAG.getConstant(1, MVT::i32)); 3415 3416 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and 3417 // captures the result into a carry flag. 3418 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG; 3419 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1); 3420 3421 // The low part is an ARMISD::RRX operand, which shifts the carry in. 3422 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1)); 3423 3424 // Merge the pieces into a single i64 value. 3425 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); 3426} 3427 3428static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { 3429 SDValue TmpOp0, TmpOp1; 3430 bool Invert = false; 3431 bool Swap = false; 3432 unsigned Opc = 0; 3433 3434 SDValue Op0 = Op.getOperand(0); 3435 SDValue Op1 = Op.getOperand(1); 3436 SDValue CC = Op.getOperand(2); 3437 EVT VT = Op.getValueType(); 3438 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 3439 DebugLoc dl = Op.getDebugLoc(); 3440 3441 if (Op.getOperand(1).getValueType().isFloatingPoint()) { 3442 switch (SetCCOpcode) { 3443 default: llvm_unreachable("Illegal FP comparison"); break; 3444 case ISD::SETUNE: 3445 case ISD::SETNE: Invert = true; // Fallthrough 3446 case ISD::SETOEQ: 3447 case ISD::SETEQ: Opc = ARMISD::VCEQ; break; 3448 case ISD::SETOLT: 3449 case ISD::SETLT: Swap = true; // Fallthrough 3450 case ISD::SETOGT: 3451 case ISD::SETGT: Opc = ARMISD::VCGT; break; 3452 case ISD::SETOLE: 3453 case ISD::SETLE: Swap = true; // Fallthrough 3454 case ISD::SETOGE: 3455 case ISD::SETGE: Opc = ARMISD::VCGE; break; 3456 case ISD::SETUGE: Swap = true; // Fallthrough 3457 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break; 3458 case ISD::SETUGT: Swap = true; // Fallthrough 3459 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break; 3460 case ISD::SETUEQ: Invert = true; // Fallthrough 3461 case ISD::SETONE: 3462 // Expand this to (OLT | OGT). 3463 TmpOp0 = Op0; 3464 TmpOp1 = Op1; 3465 Opc = ISD::OR; 3466 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0); 3467 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1); 3468 break; 3469 case ISD::SETUO: Invert = true; // Fallthrough 3470 case ISD::SETO: 3471 // Expand this to (OLT | OGE). 3472 TmpOp0 = Op0; 3473 TmpOp1 = Op1; 3474 Opc = ISD::OR; 3475 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0); 3476 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1); 3477 break; 3478 } 3479 } else { 3480 // Integer comparisons. 3481 switch (SetCCOpcode) { 3482 default: llvm_unreachable("Illegal integer comparison"); break; 3483 case ISD::SETNE: Invert = true; 3484 case ISD::SETEQ: Opc = ARMISD::VCEQ; break; 3485 case ISD::SETLT: Swap = true; 3486 case ISD::SETGT: Opc = ARMISD::VCGT; break; 3487 case ISD::SETLE: Swap = true; 3488 case ISD::SETGE: Opc = ARMISD::VCGE; break; 3489 case ISD::SETULT: Swap = true; 3490 case ISD::SETUGT: Opc = ARMISD::VCGTU; break; 3491 case ISD::SETULE: Swap = true; 3492 case ISD::SETUGE: Opc = ARMISD::VCGEU; break; 3493 } 3494 3495 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero). 3496 if (Opc == ARMISD::VCEQ) { 3497 3498 SDValue AndOp; 3499 if (ISD::isBuildVectorAllZeros(Op1.getNode())) 3500 AndOp = Op0; 3501 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) 3502 AndOp = Op1; 3503 3504 // Ignore bitconvert. 3505 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST) 3506 AndOp = AndOp.getOperand(0); 3507 3508 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) { 3509 Opc = ARMISD::VTST; 3510 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0)); 3511 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1)); 3512 Invert = !Invert; 3513 } 3514 } 3515 } 3516 3517 if (Swap) 3518 std::swap(Op0, Op1); 3519 3520 // If one of the operands is a constant vector zero, attempt to fold the 3521 // comparison to a specialized compare-against-zero form. 3522 SDValue SingleOp; 3523 if (ISD::isBuildVectorAllZeros(Op1.getNode())) 3524 SingleOp = Op0; 3525 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) { 3526 if (Opc == ARMISD::VCGE) 3527 Opc = ARMISD::VCLEZ; 3528 else if (Opc == ARMISD::VCGT) 3529 Opc = ARMISD::VCLTZ; 3530 SingleOp = Op1; 3531 } 3532 3533 SDValue Result; 3534 if (SingleOp.getNode()) { 3535 switch (Opc) { 3536 case ARMISD::VCEQ: 3537 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break; 3538 case ARMISD::VCGE: 3539 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break; 3540 case ARMISD::VCLEZ: 3541 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break; 3542 case ARMISD::VCGT: 3543 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break; 3544 case ARMISD::VCLTZ: 3545 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break; 3546 default: 3547 Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 3548 } 3549 } else { 3550 Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 3551 } 3552 3553 if (Invert) 3554 Result = DAG.getNOT(dl, Result, VT); 3555 3556 return Result; 3557} 3558 3559/// isNEONModifiedImm - Check if the specified splat value corresponds to a 3560/// valid vector constant for a NEON instruction with a "modified immediate" 3561/// operand (e.g., VMOV). If so, return the encoded value. 3562static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef, 3563 unsigned SplatBitSize, SelectionDAG &DAG, 3564 EVT &VT, bool is128Bits, NEONModImmType type) { 3565 unsigned OpCmode, Imm; 3566 3567 // SplatBitSize is set to the smallest size that splats the vector, so a 3568 // zero vector will always have SplatBitSize == 8. However, NEON modified 3569 // immediate instructions others than VMOV do not support the 8-bit encoding 3570 // of a zero vector, and the default encoding of zero is supposed to be the 3571 // 32-bit version. 3572 if (SplatBits == 0) 3573 SplatBitSize = 32; 3574 3575 switch (SplatBitSize) { 3576 case 8: 3577 if (type != VMOVModImm) 3578 return SDValue(); 3579 // Any 1-byte value is OK. Op=0, Cmode=1110. 3580 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big"); 3581 OpCmode = 0xe; 3582 Imm = SplatBits; 3583 VT = is128Bits ? MVT::v16i8 : MVT::v8i8; 3584 break; 3585 3586 case 16: 3587 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero. 3588 VT = is128Bits ? MVT::v8i16 : MVT::v4i16; 3589 if ((SplatBits & ~0xff) == 0) { 3590 // Value = 0x00nn: Op=x, Cmode=100x. 3591 OpCmode = 0x8; 3592 Imm = SplatBits; 3593 break; 3594 } 3595 if ((SplatBits & ~0xff00) == 0) { 3596 // Value = 0xnn00: Op=x, Cmode=101x. 3597 OpCmode = 0xa; 3598 Imm = SplatBits >> 8; 3599 break; 3600 } 3601 return SDValue(); 3602 3603 case 32: 3604 // NEON's 32-bit VMOV supports splat values where: 3605 // * only one byte is nonzero, or 3606 // * the least significant byte is 0xff and the second byte is nonzero, or 3607 // * the least significant 2 bytes are 0xff and the third is nonzero. 3608 VT = is128Bits ? MVT::v4i32 : MVT::v2i32; 3609 if ((SplatBits & ~0xff) == 0) { 3610 // Value = 0x000000nn: Op=x, Cmode=000x. 3611 OpCmode = 0; 3612 Imm = SplatBits; 3613 break; 3614 } 3615 if ((SplatBits & ~0xff00) == 0) { 3616 // Value = 0x0000nn00: Op=x, Cmode=001x. 3617 OpCmode = 0x2; 3618 Imm = SplatBits >> 8; 3619 break; 3620 } 3621 if ((SplatBits & ~0xff0000) == 0) { 3622 // Value = 0x00nn0000: Op=x, Cmode=010x. 3623 OpCmode = 0x4; 3624 Imm = SplatBits >> 16; 3625 break; 3626 } 3627 if ((SplatBits & ~0xff000000) == 0) { 3628 // Value = 0xnn000000: Op=x, Cmode=011x. 3629 OpCmode = 0x6; 3630 Imm = SplatBits >> 24; 3631 break; 3632 } 3633 3634 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC 3635 if (type == OtherModImm) return SDValue(); 3636 3637 if ((SplatBits & ~0xffff) == 0 && 3638 ((SplatBits | SplatUndef) & 0xff) == 0xff) { 3639 // Value = 0x0000nnff: Op=x, Cmode=1100. 3640 OpCmode = 0xc; 3641 Imm = SplatBits >> 8; 3642 SplatBits |= 0xff; 3643 break; 3644 } 3645 3646 if ((SplatBits & ~0xffffff) == 0 && 3647 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) { 3648 // Value = 0x00nnffff: Op=x, Cmode=1101. 3649 OpCmode = 0xd; 3650 Imm = SplatBits >> 16; 3651 SplatBits |= 0xffff; 3652 break; 3653 } 3654 3655 // Note: there are a few 32-bit splat values (specifically: 00ffff00, 3656 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not 3657 // VMOV.I32. A (very) minor optimization would be to replicate the value 3658 // and fall through here to test for a valid 64-bit splat. But, then the 3659 // caller would also need to check and handle the change in size. 3660 return SDValue(); 3661 3662 case 64: { 3663 if (type != VMOVModImm) 3664 return SDValue(); 3665 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff. 3666 uint64_t BitMask = 0xff; 3667 uint64_t Val = 0; 3668 unsigned ImmMask = 1; 3669 Imm = 0; 3670 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) { 3671 if (((SplatBits | SplatUndef) & BitMask) == BitMask) { 3672 Val |= BitMask; 3673 Imm |= ImmMask; 3674 } else if ((SplatBits & BitMask) != 0) { 3675 return SDValue(); 3676 } 3677 BitMask <<= 8; 3678 ImmMask <<= 1; 3679 } 3680 // Op=1, Cmode=1110. 3681 OpCmode = 0x1e; 3682 SplatBits = Val; 3683 VT = is128Bits ? MVT::v2i64 : MVT::v1i64; 3684 break; 3685 } 3686 3687 default: 3688 llvm_unreachable("unexpected size for isNEONModifiedImm"); 3689 return SDValue(); 3690 } 3691 3692 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm); 3693 return DAG.getTargetConstant(EncodedVal, MVT::i32); 3694} 3695 3696static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT, 3697 bool &ReverseVEXT, unsigned &Imm) { 3698 unsigned NumElts = VT.getVectorNumElements(); 3699 ReverseVEXT = false; 3700 3701 // Assume that the first shuffle index is not UNDEF. Fail if it is. 3702 if (M[0] < 0) 3703 return false; 3704 3705 Imm = M[0]; 3706 3707 // If this is a VEXT shuffle, the immediate value is the index of the first 3708 // element. The other shuffle indices must be the successive elements after 3709 // the first one. 3710 unsigned ExpectedElt = Imm; 3711 for (unsigned i = 1; i < NumElts; ++i) { 3712 // Increment the expected index. If it wraps around, it may still be 3713 // a VEXT but the source vectors must be swapped. 3714 ExpectedElt += 1; 3715 if (ExpectedElt == NumElts * 2) { 3716 ExpectedElt = 0; 3717 ReverseVEXT = true; 3718 } 3719 3720 if (M[i] < 0) continue; // ignore UNDEF indices 3721 if (ExpectedElt != static_cast<unsigned>(M[i])) 3722 return false; 3723 } 3724 3725 // Adjust the index value if the source operands will be swapped. 3726 if (ReverseVEXT) 3727 Imm -= NumElts; 3728 3729 return true; 3730} 3731 3732/// isVREVMask - Check if a vector shuffle corresponds to a VREV 3733/// instruction with the specified blocksize. (The order of the elements 3734/// within each block of the vector is reversed.) 3735static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT, 3736 unsigned BlockSize) { 3737 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) && 3738 "Only possible block sizes for VREV are: 16, 32, 64"); 3739 3740 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3741 if (EltSz == 64) 3742 return false; 3743 3744 unsigned NumElts = VT.getVectorNumElements(); 3745 unsigned BlockElts = M[0] + 1; 3746 // If the first shuffle index is UNDEF, be optimistic. 3747 if (M[0] < 0) 3748 BlockElts = BlockSize / EltSz; 3749 3750 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz) 3751 return false; 3752 3753 for (unsigned i = 0; i < NumElts; ++i) { 3754 if (M[i] < 0) continue; // ignore UNDEF indices 3755 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts)) 3756 return false; 3757 } 3758 3759 return true; 3760} 3761 3762static bool isVTBLMask(const SmallVectorImpl<int> &M, EVT VT) { 3763 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of 3764 // range, then 0 is placed into the resulting vector. So pretty much any mask 3765 // of 8 elements can work here. 3766 return VT == MVT::v8i8 && M.size() == 8; 3767} 3768 3769static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT, 3770 unsigned &WhichResult) { 3771 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3772 if (EltSz == 64) 3773 return false; 3774 3775 unsigned NumElts = VT.getVectorNumElements(); 3776 WhichResult = (M[0] == 0 ? 0 : 1); 3777 for (unsigned i = 0; i < NumElts; i += 2) { 3778 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) || 3779 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult)) 3780 return false; 3781 } 3782 return true; 3783} 3784 3785/// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of 3786/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 3787/// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>. 3788static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT, 3789 unsigned &WhichResult) { 3790 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3791 if (EltSz == 64) 3792 return false; 3793 3794 unsigned NumElts = VT.getVectorNumElements(); 3795 WhichResult = (M[0] == 0 ? 0 : 1); 3796 for (unsigned i = 0; i < NumElts; i += 2) { 3797 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) || 3798 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult)) 3799 return false; 3800 } 3801 return true; 3802} 3803 3804static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT, 3805 unsigned &WhichResult) { 3806 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3807 if (EltSz == 64) 3808 return false; 3809 3810 unsigned NumElts = VT.getVectorNumElements(); 3811 WhichResult = (M[0] == 0 ? 0 : 1); 3812 for (unsigned i = 0; i != NumElts; ++i) { 3813 if (M[i] < 0) continue; // ignore UNDEF indices 3814 if ((unsigned) M[i] != 2 * i + WhichResult) 3815 return false; 3816 } 3817 3818 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3819 if (VT.is64BitVector() && EltSz == 32) 3820 return false; 3821 3822 return true; 3823} 3824 3825/// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of 3826/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 3827/// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>, 3828static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT, 3829 unsigned &WhichResult) { 3830 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3831 if (EltSz == 64) 3832 return false; 3833 3834 unsigned Half = VT.getVectorNumElements() / 2; 3835 WhichResult = (M[0] == 0 ? 0 : 1); 3836 for (unsigned j = 0; j != 2; ++j) { 3837 unsigned Idx = WhichResult; 3838 for (unsigned i = 0; i != Half; ++i) { 3839 int MIdx = M[i + j * Half]; 3840 if (MIdx >= 0 && (unsigned) MIdx != Idx) 3841 return false; 3842 Idx += 2; 3843 } 3844 } 3845 3846 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3847 if (VT.is64BitVector() && EltSz == 32) 3848 return false; 3849 3850 return true; 3851} 3852 3853static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT, 3854 unsigned &WhichResult) { 3855 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3856 if (EltSz == 64) 3857 return false; 3858 3859 unsigned NumElts = VT.getVectorNumElements(); 3860 WhichResult = (M[0] == 0 ? 0 : 1); 3861 unsigned Idx = WhichResult * NumElts / 2; 3862 for (unsigned i = 0; i != NumElts; i += 2) { 3863 if ((M[i] >= 0 && (unsigned) M[i] != Idx) || 3864 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts)) 3865 return false; 3866 Idx += 1; 3867 } 3868 3869 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3870 if (VT.is64BitVector() && EltSz == 32) 3871 return false; 3872 3873 return true; 3874} 3875 3876/// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of 3877/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef". 3878/// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>. 3879static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT, 3880 unsigned &WhichResult) { 3881 unsigned EltSz = VT.getVectorElementType().getSizeInBits(); 3882 if (EltSz == 64) 3883 return false; 3884 3885 unsigned NumElts = VT.getVectorNumElements(); 3886 WhichResult = (M[0] == 0 ? 0 : 1); 3887 unsigned Idx = WhichResult * NumElts / 2; 3888 for (unsigned i = 0; i != NumElts; i += 2) { 3889 if ((M[i] >= 0 && (unsigned) M[i] != Idx) || 3890 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx)) 3891 return false; 3892 Idx += 1; 3893 } 3894 3895 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32. 3896 if (VT.is64BitVector() && EltSz == 32) 3897 return false; 3898 3899 return true; 3900} 3901 3902// If N is an integer constant that can be moved into a register in one 3903// instruction, return an SDValue of such a constant (will become a MOV 3904// instruction). Otherwise return null. 3905static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG, 3906 const ARMSubtarget *ST, DebugLoc dl) { 3907 uint64_t Val; 3908 if (!isa<ConstantSDNode>(N)) 3909 return SDValue(); 3910 Val = cast<ConstantSDNode>(N)->getZExtValue(); 3911 3912 if (ST->isThumb1Only()) { 3913 if (Val <= 255 || ~Val <= 255) 3914 return DAG.getConstant(Val, MVT::i32); 3915 } else { 3916 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1) 3917 return DAG.getConstant(Val, MVT::i32); 3918 } 3919 return SDValue(); 3920} 3921 3922// If this is a case we can't handle, return null and let the default 3923// expansion code take care of it. 3924SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, 3925 const ARMSubtarget *ST) const { 3926 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode()); 3927 DebugLoc dl = Op.getDebugLoc(); 3928 EVT VT = Op.getValueType(); 3929 3930 APInt SplatBits, SplatUndef; 3931 unsigned SplatBitSize; 3932 bool HasAnyUndefs; 3933 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { 3934 if (SplatBitSize <= 64) { 3935 // Check if an immediate VMOV works. 3936 EVT VmovVT; 3937 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(), 3938 SplatUndef.getZExtValue(), SplatBitSize, 3939 DAG, VmovVT, VT.is128BitVector(), 3940 VMOVModImm); 3941 if (Val.getNode()) { 3942 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val); 3943 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); 3944 } 3945 3946 // Try an immediate VMVN. 3947 uint64_t NegatedImm = (SplatBits.getZExtValue() ^ 3948 ((1LL << SplatBitSize) - 1)); 3949 Val = isNEONModifiedImm(NegatedImm, 3950 SplatUndef.getZExtValue(), SplatBitSize, 3951 DAG, VmovVT, VT.is128BitVector(), 3952 VMVNModImm); 3953 if (Val.getNode()) { 3954 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val); 3955 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov); 3956 } 3957 } 3958 } 3959 3960 // Scan through the operands to see if only one value is used. 3961 unsigned NumElts = VT.getVectorNumElements(); 3962 bool isOnlyLowElement = true; 3963 bool usesOnlyOneValue = true; 3964 bool isConstant = true; 3965 SDValue Value; 3966 for (unsigned i = 0; i < NumElts; ++i) { 3967 SDValue V = Op.getOperand(i); 3968 if (V.getOpcode() == ISD::UNDEF) 3969 continue; 3970 if (i > 0) 3971 isOnlyLowElement = false; 3972 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 3973 isConstant = false; 3974 3975 if (!Value.getNode()) 3976 Value = V; 3977 else if (V != Value) 3978 usesOnlyOneValue = false; 3979 } 3980 3981 if (!Value.getNode()) 3982 return DAG.getUNDEF(VT); 3983 3984 if (isOnlyLowElement) 3985 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value); 3986 3987 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 3988 3989 // Use VDUP for non-constant splats. For f32 constant splats, reduce to 3990 // i32 and try again. 3991 if (usesOnlyOneValue && EltSize <= 32) { 3992 if (!isConstant) 3993 return DAG.getNode(ARMISD::VDUP, dl, VT, Value); 3994 if (VT.getVectorElementType().isFloatingPoint()) { 3995 SmallVector<SDValue, 8> Ops; 3996 for (unsigned i = 0; i < NumElts; ++i) 3997 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32, 3998 Op.getOperand(i))); 3999 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts); 4000 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts); 4001 Val = LowerBUILD_VECTOR(Val, DAG, ST); 4002 if (Val.getNode()) 4003 return DAG.getNode(ISD::BITCAST, dl, VT, Val); 4004 } 4005 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl); 4006 if (Val.getNode()) 4007 return DAG.getNode(ARMISD::VDUP, dl, VT, Val); 4008 } 4009 4010 // If all elements are constants and the case above didn't get hit, fall back 4011 // to the default expansion, which will generate a load from the constant 4012 // pool. 4013 if (isConstant) 4014 return SDValue(); 4015 4016 // Empirical tests suggest this is rarely worth it for vectors of length <= 2. 4017 if (NumElts >= 4) { 4018 SDValue shuffle = ReconstructShuffle(Op, DAG); 4019 if (shuffle != SDValue()) 4020 return shuffle; 4021 } 4022 4023 // Vectors with 32- or 64-bit elements can be built by directly assigning 4024 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands 4025 // will be legalized. 4026 if (EltSize >= 32) { 4027 // Do the expansion with floating-point types, since that is what the VFP 4028 // registers are defined to use, and since i64 is not legal. 4029 EVT EltVT = EVT::getFloatingPointVT(EltSize); 4030 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); 4031 SmallVector<SDValue, 8> Ops; 4032 for (unsigned i = 0; i < NumElts; ++i) 4033 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i))); 4034 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts); 4035 return DAG.getNode(ISD::BITCAST, dl, VT, Val); 4036 } 4037 4038 return SDValue(); 4039} 4040 4041// Gather data to see if the operation can be modelled as a 4042// shuffle in combination with VEXTs. 4043SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op, 4044 SelectionDAG &DAG) const { 4045 DebugLoc dl = Op.getDebugLoc(); 4046 EVT VT = Op.getValueType(); 4047 unsigned NumElts = VT.getVectorNumElements(); 4048 4049 SmallVector<SDValue, 2> SourceVecs; 4050 SmallVector<unsigned, 2> MinElts; 4051 SmallVector<unsigned, 2> MaxElts; 4052 4053 for (unsigned i = 0; i < NumElts; ++i) { 4054 SDValue V = Op.getOperand(i); 4055 if (V.getOpcode() == ISD::UNDEF) 4056 continue; 4057 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) { 4058 // A shuffle can only come from building a vector from various 4059 // elements of other vectors. 4060 return SDValue(); 4061 } 4062 4063 // Record this extraction against the appropriate vector if possible... 4064 SDValue SourceVec = V.getOperand(0); 4065 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue(); 4066 bool FoundSource = false; 4067 for (unsigned j = 0; j < SourceVecs.size(); ++j) { 4068 if (SourceVecs[j] == SourceVec) { 4069 if (MinElts[j] > EltNo) 4070 MinElts[j] = EltNo; 4071 if (MaxElts[j] < EltNo) 4072 MaxElts[j] = EltNo; 4073 FoundSource = true; 4074 break; 4075 } 4076 } 4077 4078 // Or record a new source if not... 4079 if (!FoundSource) { 4080 SourceVecs.push_back(SourceVec); 4081 MinElts.push_back(EltNo); 4082 MaxElts.push_back(EltNo); 4083 } 4084 } 4085 4086 // Currently only do something sane when at most two source vectors 4087 // involved. 4088 if (SourceVecs.size() > 2) 4089 return SDValue(); 4090 4091 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) }; 4092 int VEXTOffsets[2] = {0, 0}; 4093 4094 // This loop extracts the usage patterns of the source vectors 4095 // and prepares appropriate SDValues for a shuffle if possible. 4096 for (unsigned i = 0; i < SourceVecs.size(); ++i) { 4097 if (SourceVecs[i].getValueType() == VT) { 4098 // No VEXT necessary 4099 ShuffleSrcs[i] = SourceVecs[i]; 4100 VEXTOffsets[i] = 0; 4101 continue; 4102 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) { 4103 // It probably isn't worth padding out a smaller vector just to 4104 // break it down again in a shuffle. 4105 return SDValue(); 4106 } 4107 4108 // Since only 64-bit and 128-bit vectors are legal on ARM and 4109 // we've eliminated the other cases... 4110 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts && 4111 "unexpected vector sizes in ReconstructShuffle"); 4112 4113 if (MaxElts[i] - MinElts[i] >= NumElts) { 4114 // Span too large for a VEXT to cope 4115 return SDValue(); 4116 } 4117 4118 if (MinElts[i] >= NumElts) { 4119 // The extraction can just take the second half 4120 VEXTOffsets[i] = NumElts; 4121 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4122 SourceVecs[i], 4123 DAG.getIntPtrConstant(NumElts)); 4124 } else if (MaxElts[i] < NumElts) { 4125 // The extraction can just take the first half 4126 VEXTOffsets[i] = 0; 4127 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4128 SourceVecs[i], 4129 DAG.getIntPtrConstant(0)); 4130 } else { 4131 // An actual VEXT is needed 4132 VEXTOffsets[i] = MinElts[i]; 4133 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4134 SourceVecs[i], 4135 DAG.getIntPtrConstant(0)); 4136 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, 4137 SourceVecs[i], 4138 DAG.getIntPtrConstant(NumElts)); 4139 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2, 4140 DAG.getConstant(VEXTOffsets[i], MVT::i32)); 4141 } 4142 } 4143 4144 SmallVector<int, 8> Mask; 4145 4146 for (unsigned i = 0; i < NumElts; ++i) { 4147 SDValue Entry = Op.getOperand(i); 4148 if (Entry.getOpcode() == ISD::UNDEF) { 4149 Mask.push_back(-1); 4150 continue; 4151 } 4152 4153 SDValue ExtractVec = Entry.getOperand(0); 4154 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i) 4155 .getOperand(1))->getSExtValue(); 4156 if (ExtractVec == SourceVecs[0]) { 4157 Mask.push_back(ExtractElt - VEXTOffsets[0]); 4158 } else { 4159 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]); 4160 } 4161 } 4162 4163 // Final check before we try to produce nonsense... 4164 if (isShuffleMaskLegal(Mask, VT)) 4165 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1], 4166 &Mask[0]); 4167 4168 return SDValue(); 4169} 4170 4171/// isShuffleMaskLegal - Targets can use this to indicate that they only 4172/// support *some* VECTOR_SHUFFLE operations, those with specific masks. 4173/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 4174/// are assumed to be legal. 4175bool 4176ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 4177 EVT VT) const { 4178 if (VT.getVectorNumElements() == 4 && 4179 (VT.is128BitVector() || VT.is64BitVector())) { 4180 unsigned PFIndexes[4]; 4181 for (unsigned i = 0; i != 4; ++i) { 4182 if (M[i] < 0) 4183 PFIndexes[i] = 8; 4184 else 4185 PFIndexes[i] = M[i]; 4186 } 4187 4188 // Compute the index in the perfect shuffle table. 4189 unsigned PFTableIndex = 4190 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 4191 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 4192 unsigned Cost = (PFEntry >> 30); 4193 4194 if (Cost <= 4) 4195 return true; 4196 } 4197 4198 bool ReverseVEXT; 4199 unsigned Imm, WhichResult; 4200 4201 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 4202 return (EltSize >= 32 || 4203 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 4204 isVREVMask(M, VT, 64) || 4205 isVREVMask(M, VT, 32) || 4206 isVREVMask(M, VT, 16) || 4207 isVEXTMask(M, VT, ReverseVEXT, Imm) || 4208 isVTBLMask(M, VT) || 4209 isVTRNMask(M, VT, WhichResult) || 4210 isVUZPMask(M, VT, WhichResult) || 4211 isVZIPMask(M, VT, WhichResult) || 4212 isVTRN_v_undef_Mask(M, VT, WhichResult) || 4213 isVUZP_v_undef_Mask(M, VT, WhichResult) || 4214 isVZIP_v_undef_Mask(M, VT, WhichResult)); 4215} 4216 4217/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit 4218/// the specified operations to build the shuffle. 4219static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, 4220 SDValue RHS, SelectionDAG &DAG, 4221 DebugLoc dl) { 4222 unsigned OpNum = (PFEntry >> 26) & 0x0F; 4223 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); 4224 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); 4225 4226 enum { 4227 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> 4228 OP_VREV, 4229 OP_VDUP0, 4230 OP_VDUP1, 4231 OP_VDUP2, 4232 OP_VDUP3, 4233 OP_VEXT1, 4234 OP_VEXT2, 4235 OP_VEXT3, 4236 OP_VUZPL, // VUZP, left result 4237 OP_VUZPR, // VUZP, right result 4238 OP_VZIPL, // VZIP, left result 4239 OP_VZIPR, // VZIP, right result 4240 OP_VTRNL, // VTRN, left result 4241 OP_VTRNR // VTRN, right result 4242 }; 4243 4244 if (OpNum == OP_COPY) { 4245 if (LHSID == (1*9+2)*9+3) return LHS; 4246 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); 4247 return RHS; 4248 } 4249 4250 SDValue OpLHS, OpRHS; 4251 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl); 4252 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl); 4253 EVT VT = OpLHS.getValueType(); 4254 4255 switch (OpNum) { 4256 default: llvm_unreachable("Unknown shuffle opcode!"); 4257 case OP_VREV: 4258 // VREV divides the vector in half and swaps within the half. 4259 if (VT.getVectorElementType() == MVT::i32 || 4260 VT.getVectorElementType() == MVT::f32) 4261 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); 4262 // vrev <4 x i16> -> VREV32 4263 if (VT.getVectorElementType() == MVT::i16) 4264 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS); 4265 // vrev <4 x i8> -> VREV16 4266 assert(VT.getVectorElementType() == MVT::i8); 4267 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS); 4268 case OP_VDUP0: 4269 case OP_VDUP1: 4270 case OP_VDUP2: 4271 case OP_VDUP3: 4272 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, 4273 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32)); 4274 case OP_VEXT1: 4275 case OP_VEXT2: 4276 case OP_VEXT3: 4277 return DAG.getNode(ARMISD::VEXT, dl, VT, 4278 OpLHS, OpRHS, 4279 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32)); 4280 case OP_VUZPL: 4281 case OP_VUZPR: 4282 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 4283 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL); 4284 case OP_VZIPL: 4285 case OP_VZIPR: 4286 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 4287 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL); 4288 case OP_VTRNL: 4289 case OP_VTRNR: 4290 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 4291 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL); 4292 } 4293} 4294 4295static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op, 4296 SmallVectorImpl<int> &ShuffleMask, 4297 SelectionDAG &DAG) { 4298 // Check to see if we can use the VTBL instruction. 4299 SDValue V1 = Op.getOperand(0); 4300 SDValue V2 = Op.getOperand(1); 4301 DebugLoc DL = Op.getDebugLoc(); 4302 4303 SmallVector<SDValue, 8> VTBLMask; 4304 for (SmallVectorImpl<int>::iterator 4305 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I) 4306 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32)); 4307 4308 if (V2.getNode()->getOpcode() == ISD::UNDEF) 4309 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1, 4310 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, 4311 &VTBLMask[0], 8)); 4312 4313 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2, 4314 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, 4315 &VTBLMask[0], 8)); 4316} 4317 4318static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { 4319 SDValue V1 = Op.getOperand(0); 4320 SDValue V2 = Op.getOperand(1); 4321 DebugLoc dl = Op.getDebugLoc(); 4322 EVT VT = Op.getValueType(); 4323 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode()); 4324 SmallVector<int, 8> ShuffleMask; 4325 4326 // Convert shuffles that are directly supported on NEON to target-specific 4327 // DAG nodes, instead of keeping them as shuffles and matching them again 4328 // during code selection. This is more efficient and avoids the possibility 4329 // of inconsistencies between legalization and selection. 4330 // FIXME: floating-point vectors should be canonicalized to integer vectors 4331 // of the same time so that they get CSEd properly. 4332 SVN->getMask(ShuffleMask); 4333 4334 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 4335 if (EltSize <= 32) { 4336 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) { 4337 int Lane = SVN->getSplatIndex(); 4338 // If this is undef splat, generate it via "just" vdup, if possible. 4339 if (Lane == -1) Lane = 0; 4340 4341 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) { 4342 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0)); 4343 } 4344 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1, 4345 DAG.getConstant(Lane, MVT::i32)); 4346 } 4347 4348 bool ReverseVEXT; 4349 unsigned Imm; 4350 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) { 4351 if (ReverseVEXT) 4352 std::swap(V1, V2); 4353 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2, 4354 DAG.getConstant(Imm, MVT::i32)); 4355 } 4356 4357 if (isVREVMask(ShuffleMask, VT, 64)) 4358 return DAG.getNode(ARMISD::VREV64, dl, VT, V1); 4359 if (isVREVMask(ShuffleMask, VT, 32)) 4360 return DAG.getNode(ARMISD::VREV32, dl, VT, V1); 4361 if (isVREVMask(ShuffleMask, VT, 16)) 4362 return DAG.getNode(ARMISD::VREV16, dl, VT, V1); 4363 4364 // Check for Neon shuffles that modify both input vectors in place. 4365 // If both results are used, i.e., if there are two shuffles with the same 4366 // source operands and with masks corresponding to both results of one of 4367 // these operations, DAG memoization will ensure that a single node is 4368 // used for both shuffles. 4369 unsigned WhichResult; 4370 if (isVTRNMask(ShuffleMask, VT, WhichResult)) 4371 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 4372 V1, V2).getValue(WhichResult); 4373 if (isVUZPMask(ShuffleMask, VT, WhichResult)) 4374 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 4375 V1, V2).getValue(WhichResult); 4376 if (isVZIPMask(ShuffleMask, VT, WhichResult)) 4377 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 4378 V1, V2).getValue(WhichResult); 4379 4380 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) 4381 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT), 4382 V1, V1).getValue(WhichResult); 4383 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) 4384 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), 4385 V1, V1).getValue(WhichResult); 4386 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) 4387 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), 4388 V1, V1).getValue(WhichResult); 4389 } 4390 4391 // If the shuffle is not directly supported and it has 4 elements, use 4392 // the PerfectShuffle-generated table to synthesize it from other shuffles. 4393 unsigned NumElts = VT.getVectorNumElements(); 4394 if (NumElts == 4) { 4395 unsigned PFIndexes[4]; 4396 for (unsigned i = 0; i != 4; ++i) { 4397 if (ShuffleMask[i] < 0) 4398 PFIndexes[i] = 8; 4399 else 4400 PFIndexes[i] = ShuffleMask[i]; 4401 } 4402 4403 // Compute the index in the perfect shuffle table. 4404 unsigned PFTableIndex = 4405 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3]; 4406 unsigned PFEntry = PerfectShuffleTable[PFTableIndex]; 4407 unsigned Cost = (PFEntry >> 30); 4408 4409 if (Cost <= 4) 4410 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl); 4411 } 4412 4413 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs. 4414 if (EltSize >= 32) { 4415 // Do the expansion with floating-point types, since that is what the VFP 4416 // registers are defined to use, and since i64 is not legal. 4417 EVT EltVT = EVT::getFloatingPointVT(EltSize); 4418 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts); 4419 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1); 4420 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2); 4421 SmallVector<SDValue, 8> Ops; 4422 for (unsigned i = 0; i < NumElts; ++i) { 4423 if (ShuffleMask[i] < 0) 4424 Ops.push_back(DAG.getUNDEF(EltVT)); 4425 else 4426 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 4427 ShuffleMask[i] < (int)NumElts ? V1 : V2, 4428 DAG.getConstant(ShuffleMask[i] & (NumElts-1), 4429 MVT::i32))); 4430 } 4431 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts); 4432 return DAG.getNode(ISD::BITCAST, dl, VT, Val); 4433 } 4434 4435 if (VT == MVT::v8i8) { 4436 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG); 4437 if (NewOp.getNode()) 4438 return NewOp; 4439 } 4440 4441 return SDValue(); 4442} 4443 4444static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { 4445 // EXTRACT_VECTOR_ELT is legal only for immediate indexes. 4446 SDValue Lane = Op.getOperand(1); 4447 if (!isa<ConstantSDNode>(Lane)) 4448 return SDValue(); 4449 4450 SDValue Vec = Op.getOperand(0); 4451 if (Op.getValueType() == MVT::i32 && 4452 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) { 4453 DebugLoc dl = Op.getDebugLoc(); 4454 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane); 4455 } 4456 4457 return Op; 4458} 4459 4460static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 4461 // The only time a CONCAT_VECTORS operation can have legal types is when 4462 // two 64-bit vectors are concatenated to a 128-bit vector. 4463 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 && 4464 "unexpected CONCAT_VECTORS"); 4465 DebugLoc dl = Op.getDebugLoc(); 4466 SDValue Val = DAG.getUNDEF(MVT::v2f64); 4467 SDValue Op0 = Op.getOperand(0); 4468 SDValue Op1 = Op.getOperand(1); 4469 if (Op0.getOpcode() != ISD::UNDEF) 4470 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, 4471 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0), 4472 DAG.getIntPtrConstant(0)); 4473 if (Op1.getOpcode() != ISD::UNDEF) 4474 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, 4475 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1), 4476 DAG.getIntPtrConstant(1)); 4477 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val); 4478} 4479 4480/// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each 4481/// element has been zero/sign-extended, depending on the isSigned parameter, 4482/// from an integer type half its size. 4483static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG, 4484 bool isSigned) { 4485 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32. 4486 EVT VT = N->getValueType(0); 4487 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) { 4488 SDNode *BVN = N->getOperand(0).getNode(); 4489 if (BVN->getValueType(0) != MVT::v4i32 || 4490 BVN->getOpcode() != ISD::BUILD_VECTOR) 4491 return false; 4492 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0; 4493 unsigned HiElt = 1 - LoElt; 4494 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt)); 4495 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt)); 4496 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2)); 4497 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2)); 4498 if (!Lo0 || !Hi0 || !Lo1 || !Hi1) 4499 return false; 4500 if (isSigned) { 4501 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 && 4502 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32) 4503 return true; 4504 } else { 4505 if (Hi0->isNullValue() && Hi1->isNullValue()) 4506 return true; 4507 } 4508 return false; 4509 } 4510 4511 if (N->getOpcode() != ISD::BUILD_VECTOR) 4512 return false; 4513 4514 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 4515 SDNode *Elt = N->getOperand(i).getNode(); 4516 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) { 4517 unsigned EltSize = VT.getVectorElementType().getSizeInBits(); 4518 unsigned HalfSize = EltSize / 2; 4519 if (isSigned) { 4520 int64_t SExtVal = C->getSExtValue(); 4521 if ((SExtVal >> HalfSize) != (SExtVal >> EltSize)) 4522 return false; 4523 } else { 4524 if ((C->getZExtValue() >> HalfSize) != 0) 4525 return false; 4526 } 4527 continue; 4528 } 4529 return false; 4530 } 4531 4532 return true; 4533} 4534 4535/// isSignExtended - Check if a node is a vector value that is sign-extended 4536/// or a constant BUILD_VECTOR with sign-extended elements. 4537static bool isSignExtended(SDNode *N, SelectionDAG &DAG) { 4538 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N)) 4539 return true; 4540 if (isExtendedBUILD_VECTOR(N, DAG, true)) 4541 return true; 4542 return false; 4543} 4544 4545/// isZeroExtended - Check if a node is a vector value that is zero-extended 4546/// or a constant BUILD_VECTOR with zero-extended elements. 4547static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) { 4548 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N)) 4549 return true; 4550 if (isExtendedBUILD_VECTOR(N, DAG, false)) 4551 return true; 4552 return false; 4553} 4554 4555/// SkipExtension - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending 4556/// load, or BUILD_VECTOR with extended elements, return the unextended value. 4557static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) { 4558 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND) 4559 return N->getOperand(0); 4560 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) 4561 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(), 4562 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(), 4563 LD->isNonTemporal(), LD->getAlignment()); 4564 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will 4565 // have been legalized as a BITCAST from v4i32. 4566 if (N->getOpcode() == ISD::BITCAST) { 4567 SDNode *BVN = N->getOperand(0).getNode(); 4568 assert(BVN->getOpcode() == ISD::BUILD_VECTOR && 4569 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR"); 4570 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0; 4571 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32, 4572 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2)); 4573 } 4574 // Construct a new BUILD_VECTOR with elements truncated to half the size. 4575 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR"); 4576 EVT VT = N->getValueType(0); 4577 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2; 4578 unsigned NumElts = VT.getVectorNumElements(); 4579 MVT TruncVT = MVT::getIntegerVT(EltSize); 4580 SmallVector<SDValue, 8> Ops; 4581 for (unsigned i = 0; i != NumElts; ++i) { 4582 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i)); 4583 const APInt &CInt = C->getAPIntValue(); 4584 Ops.push_back(DAG.getConstant(CInt.trunc(EltSize), TruncVT)); 4585 } 4586 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 4587 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts); 4588} 4589 4590static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) { 4591 unsigned Opcode = N->getOpcode(); 4592 if (Opcode == ISD::ADD || Opcode == ISD::SUB) { 4593 SDNode *N0 = N->getOperand(0).getNode(); 4594 SDNode *N1 = N->getOperand(1).getNode(); 4595 return N0->hasOneUse() && N1->hasOneUse() && 4596 isSignExtended(N0, DAG) && isSignExtended(N1, DAG); 4597 } 4598 return false; 4599} 4600 4601static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) { 4602 unsigned Opcode = N->getOpcode(); 4603 if (Opcode == ISD::ADD || Opcode == ISD::SUB) { 4604 SDNode *N0 = N->getOperand(0).getNode(); 4605 SDNode *N1 = N->getOperand(1).getNode(); 4606 return N0->hasOneUse() && N1->hasOneUse() && 4607 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG); 4608 } 4609 return false; 4610} 4611 4612static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) { 4613 // Multiplications are only custom-lowered for 128-bit vectors so that 4614 // VMULL can be detected. Otherwise v2i64 multiplications are not legal. 4615 EVT VT = Op.getValueType(); 4616 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL"); 4617 SDNode *N0 = Op.getOperand(0).getNode(); 4618 SDNode *N1 = Op.getOperand(1).getNode(); 4619 unsigned NewOpc = 0; 4620 bool isMLA = false; 4621 bool isN0SExt = isSignExtended(N0, DAG); 4622 bool isN1SExt = isSignExtended(N1, DAG); 4623 if (isN0SExt && isN1SExt) 4624 NewOpc = ARMISD::VMULLs; 4625 else { 4626 bool isN0ZExt = isZeroExtended(N0, DAG); 4627 bool isN1ZExt = isZeroExtended(N1, DAG); 4628 if (isN0ZExt && isN1ZExt) 4629 NewOpc = ARMISD::VMULLu; 4630 else if (isN1SExt || isN1ZExt) { 4631 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these 4632 // into (s/zext A * s/zext C) + (s/zext B * s/zext C) 4633 if (isN1SExt && isAddSubSExt(N0, DAG)) { 4634 NewOpc = ARMISD::VMULLs; 4635 isMLA = true; 4636 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) { 4637 NewOpc = ARMISD::VMULLu; 4638 isMLA = true; 4639 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) { 4640 std::swap(N0, N1); 4641 NewOpc = ARMISD::VMULLu; 4642 isMLA = true; 4643 } 4644 } 4645 4646 if (!NewOpc) { 4647 if (VT == MVT::v2i64) 4648 // Fall through to expand this. It is not legal. 4649 return SDValue(); 4650 else 4651 // Other vector multiplications are legal. 4652 return Op; 4653 } 4654 } 4655 4656 // Legalize to a VMULL instruction. 4657 DebugLoc DL = Op.getDebugLoc(); 4658 SDValue Op0; 4659 SDValue Op1 = SkipExtension(N1, DAG); 4660 if (!isMLA) { 4661 Op0 = SkipExtension(N0, DAG); 4662 assert(Op0.getValueType().is64BitVector() && 4663 Op1.getValueType().is64BitVector() && 4664 "unexpected types for extended operands to VMULL"); 4665 return DAG.getNode(NewOpc, DL, VT, Op0, Op1); 4666 } 4667 4668 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during 4669 // isel lowering to take advantage of no-stall back to back vmul + vmla. 4670 // vmull q0, d4, d6 4671 // vmlal q0, d5, d6 4672 // is faster than 4673 // vaddl q0, d4, d5 4674 // vmovl q1, d6 4675 // vmul q0, q0, q1 4676 SDValue N00 = SkipExtension(N0->getOperand(0).getNode(), DAG); 4677 SDValue N01 = SkipExtension(N0->getOperand(1).getNode(), DAG); 4678 EVT Op1VT = Op1.getValueType(); 4679 return DAG.getNode(N0->getOpcode(), DL, VT, 4680 DAG.getNode(NewOpc, DL, VT, 4681 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1), 4682 DAG.getNode(NewOpc, DL, VT, 4683 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1)); 4684} 4685 4686static SDValue 4687LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) { 4688 // Convert to float 4689 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo)); 4690 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo)); 4691 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X); 4692 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y); 4693 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X); 4694 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y); 4695 // Get reciprocal estimate. 4696 // float4 recip = vrecpeq_f32(yf); 4697 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4698 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y); 4699 // Because char has a smaller range than uchar, we can actually get away 4700 // without any newton steps. This requires that we use a weird bias 4701 // of 0xb000, however (again, this has been exhaustively tested). 4702 // float4 result = as_float4(as_int4(xf*recip) + 0xb000); 4703 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y); 4704 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X); 4705 Y = DAG.getConstant(0xb000, MVT::i32); 4706 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y); 4707 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y); 4708 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X); 4709 // Convert back to short. 4710 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X); 4711 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X); 4712 return X; 4713} 4714 4715static SDValue 4716LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) { 4717 SDValue N2; 4718 // Convert to float. 4719 // float4 yf = vcvt_f32_s32(vmovl_s16(y)); 4720 // float4 xf = vcvt_f32_s32(vmovl_s16(x)); 4721 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0); 4722 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1); 4723 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); 4724 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1); 4725 4726 // Use reciprocal estimate and one refinement step. 4727 // float4 recip = vrecpeq_f32(yf); 4728 // recip *= vrecpsq_f32(yf, recip); 4729 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4730 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1); 4731 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4732 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32), 4733 N1, N2); 4734 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); 4735 // Because short has a smaller range than ushort, we can actually get away 4736 // with only a single newton step. This requires that we use a weird bias 4737 // of 89, however (again, this has been exhaustively tested). 4738 // float4 result = as_float4(as_int4(xf*recip) + 0x89); 4739 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); 4740 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); 4741 N1 = DAG.getConstant(0x89, MVT::i32); 4742 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1); 4743 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); 4744 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); 4745 // Convert back to integer and return. 4746 // return vmovn_s32(vcvt_s32_f32(result)); 4747 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); 4748 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); 4749 return N0; 4750} 4751 4752static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) { 4753 EVT VT = Op.getValueType(); 4754 assert((VT == MVT::v4i16 || VT == MVT::v8i8) && 4755 "unexpected type for custom-lowering ISD::SDIV"); 4756 4757 DebugLoc dl = Op.getDebugLoc(); 4758 SDValue N0 = Op.getOperand(0); 4759 SDValue N1 = Op.getOperand(1); 4760 SDValue N2, N3; 4761 4762 if (VT == MVT::v8i8) { 4763 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0); 4764 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1); 4765 4766 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, 4767 DAG.getIntPtrConstant(4)); 4768 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, 4769 DAG.getIntPtrConstant(4)); 4770 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, 4771 DAG.getIntPtrConstant(0)); 4772 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, 4773 DAG.getIntPtrConstant(0)); 4774 4775 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16 4776 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16 4777 4778 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); 4779 N0 = LowerCONCAT_VECTORS(N0, DAG); 4780 4781 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0); 4782 return N0; 4783 } 4784 return LowerSDIV_v4i16(N0, N1, dl, DAG); 4785} 4786 4787static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) { 4788 EVT VT = Op.getValueType(); 4789 assert((VT == MVT::v4i16 || VT == MVT::v8i8) && 4790 "unexpected type for custom-lowering ISD::UDIV"); 4791 4792 DebugLoc dl = Op.getDebugLoc(); 4793 SDValue N0 = Op.getOperand(0); 4794 SDValue N1 = Op.getOperand(1); 4795 SDValue N2, N3; 4796 4797 if (VT == MVT::v8i8) { 4798 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0); 4799 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1); 4800 4801 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, 4802 DAG.getIntPtrConstant(4)); 4803 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, 4804 DAG.getIntPtrConstant(4)); 4805 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, 4806 DAG.getIntPtrConstant(0)); 4807 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, 4808 DAG.getIntPtrConstant(0)); 4809 4810 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16 4811 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16 4812 4813 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2); 4814 N0 = LowerCONCAT_VECTORS(N0, DAG); 4815 4816 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8, 4817 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32), 4818 N0); 4819 return N0; 4820 } 4821 4822 // v4i16 sdiv ... Convert to float. 4823 // float4 yf = vcvt_f32_s32(vmovl_u16(y)); 4824 // float4 xf = vcvt_f32_s32(vmovl_u16(x)); 4825 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0); 4826 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1); 4827 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); 4828 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1); 4829 4830 // Use reciprocal estimate and two refinement steps. 4831 // float4 recip = vrecpeq_f32(yf); 4832 // recip *= vrecpsq_f32(yf, recip); 4833 // recip *= vrecpsq_f32(yf, recip); 4834 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4835 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1); 4836 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4837 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32), 4838 BN1, N2); 4839 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); 4840 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 4841 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32), 4842 BN1, N2); 4843 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); 4844 // Simply multiplying by the reciprocal estimate can leave us a few ulps 4845 // too low, so we add 2 ulps (exhaustive testing shows that this is enough, 4846 // and that it will never cause us to return an answer too large). 4847 // float4 result = as_float4(as_int4(xf*recip) + 2); 4848 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); 4849 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); 4850 N1 = DAG.getConstant(2, MVT::i32); 4851 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1); 4852 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); 4853 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); 4854 // Convert back to integer and return. 4855 // return vmovn_u32(vcvt_s32_f32(result)); 4856 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); 4857 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0); 4858 return N0; 4859} 4860 4861static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 4862 EVT VT = Op.getNode()->getValueType(0); 4863 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 4864 4865 unsigned Opc; 4866 bool ExtraOp = false; 4867 switch (Op.getOpcode()) { 4868 default: assert(0 && "Invalid code"); 4869 case ISD::ADDC: Opc = ARMISD::ADDC; break; 4870 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break; 4871 case ISD::SUBC: Opc = ARMISD::SUBC; break; 4872 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break; 4873 } 4874 4875 if (!ExtraOp) 4876 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 4877 Op.getOperand(1)); 4878 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 4879 Op.getOperand(1), Op.getOperand(2)); 4880} 4881 4882static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) { 4883 // Monotonic load/store is legal for all targets 4884 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic) 4885 return Op; 4886 4887 // Aquire/Release load/store is not legal for targets without a 4888 // dmb or equivalent available. 4889 return SDValue(); 4890} 4891 4892 4893static void 4894ReplaceATOMIC_OP_64(SDNode *Node, SmallVectorImpl<SDValue>& Results, 4895 SelectionDAG &DAG, unsigned NewOp) { 4896 EVT T = Node->getValueType(0); 4897 DebugLoc dl = Node->getDebugLoc(); 4898 assert (T == MVT::i64 && "Only know how to expand i64 atomics"); 4899 4900 SmallVector<SDValue, 6> Ops; 4901 Ops.push_back(Node->getOperand(0)); // Chain 4902 Ops.push_back(Node->getOperand(1)); // Ptr 4903 // Low part of Val1 4904 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 4905 Node->getOperand(2), DAG.getIntPtrConstant(0))); 4906 // High part of Val1 4907 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 4908 Node->getOperand(2), DAG.getIntPtrConstant(1))); 4909 if (NewOp == ARMISD::ATOMCMPXCHG64_DAG) { 4910 // High part of Val1 4911 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 4912 Node->getOperand(3), DAG.getIntPtrConstant(0))); 4913 // High part of Val2 4914 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 4915 Node->getOperand(3), DAG.getIntPtrConstant(1))); 4916 } 4917 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 4918 SDValue Result = 4919 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops.data(), Ops.size(), MVT::i64, 4920 cast<MemSDNode>(Node)->getMemOperand()); 4921 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1) }; 4922 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 4923 Results.push_back(Result.getValue(2)); 4924} 4925 4926SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 4927 switch (Op.getOpcode()) { 4928 default: llvm_unreachable("Don't know how to custom lower this!"); 4929 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 4930 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 4931 case ISD::GlobalAddress: 4932 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) : 4933 LowerGlobalAddressELF(Op, DAG); 4934 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 4935 case ISD::SELECT: return LowerSELECT(Op, DAG); 4936 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 4937 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 4938 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 4939 case ISD::VASTART: return LowerVASTART(Op, DAG); 4940 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget); 4941 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget); 4942 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget); 4943 case ISD::SINT_TO_FP: 4944 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); 4945 case ISD::FP_TO_SINT: 4946 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG); 4947 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 4948 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 4949 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 4950 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG); 4951 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG); 4952 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG); 4953 case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG); 4954 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG, 4955 Subtarget); 4956 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG); 4957 case ISD::SHL: 4958 case ISD::SRL: 4959 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget); 4960 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG); 4961 case ISD::SRL_PARTS: 4962 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG); 4963 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget); 4964 case ISD::SETCC: return LowerVSETCC(Op, DAG); 4965 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget); 4966 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 4967 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 4968 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 4969 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 4970 case ISD::MUL: return LowerMUL(Op, DAG); 4971 case ISD::SDIV: return LowerSDIV(Op, DAG); 4972 case ISD::UDIV: return LowerUDIV(Op, DAG); 4973 case ISD::ADDC: 4974 case ISD::ADDE: 4975 case ISD::SUBC: 4976 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 4977 case ISD::ATOMIC_LOAD: 4978 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG); 4979 } 4980 return SDValue(); 4981} 4982 4983/// ReplaceNodeResults - Replace the results of node with an illegal result 4984/// type with new values built out of custom code. 4985void ARMTargetLowering::ReplaceNodeResults(SDNode *N, 4986 SmallVectorImpl<SDValue>&Results, 4987 SelectionDAG &DAG) const { 4988 SDValue Res; 4989 switch (N->getOpcode()) { 4990 default: 4991 llvm_unreachable("Don't know how to custom expand this!"); 4992 break; 4993 case ISD::BITCAST: 4994 Res = ExpandBITCAST(N, DAG); 4995 break; 4996 case ISD::SRL: 4997 case ISD::SRA: 4998 Res = Expand64BitShift(N, DAG, Subtarget); 4999 break; 5000 case ISD::ATOMIC_LOAD_ADD: 5001 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMADD64_DAG); 5002 return; 5003 case ISD::ATOMIC_LOAD_AND: 5004 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMAND64_DAG); 5005 return; 5006 case ISD::ATOMIC_LOAD_NAND: 5007 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMNAND64_DAG); 5008 return; 5009 case ISD::ATOMIC_LOAD_OR: 5010 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMOR64_DAG); 5011 return; 5012 case ISD::ATOMIC_LOAD_SUB: 5013 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSUB64_DAG); 5014 return; 5015 case ISD::ATOMIC_LOAD_XOR: 5016 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMXOR64_DAG); 5017 return; 5018 case ISD::ATOMIC_SWAP: 5019 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSWAP64_DAG); 5020 return; 5021 case ISD::ATOMIC_CMP_SWAP: 5022 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMCMPXCHG64_DAG); 5023 return; 5024 } 5025 if (Res.getNode()) 5026 Results.push_back(Res); 5027} 5028 5029//===----------------------------------------------------------------------===// 5030// ARM Scheduler Hooks 5031//===----------------------------------------------------------------------===// 5032 5033MachineBasicBlock * 5034ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, 5035 MachineBasicBlock *BB, 5036 unsigned Size) const { 5037 unsigned dest = MI->getOperand(0).getReg(); 5038 unsigned ptr = MI->getOperand(1).getReg(); 5039 unsigned oldval = MI->getOperand(2).getReg(); 5040 unsigned newval = MI->getOperand(3).getReg(); 5041 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5042 DebugLoc dl = MI->getDebugLoc(); 5043 bool isThumb2 = Subtarget->isThumb2(); 5044 5045 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 5046 unsigned scratch = 5047 MRI.createVirtualRegister(isThumb2 ? ARM::rGPRRegisterClass 5048 : ARM::GPRRegisterClass); 5049 5050 if (isThumb2) { 5051 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass); 5052 MRI.constrainRegClass(oldval, ARM::rGPRRegisterClass); 5053 MRI.constrainRegClass(newval, ARM::rGPRRegisterClass); 5054 } 5055 5056 unsigned ldrOpc, strOpc; 5057 switch (Size) { 5058 default: llvm_unreachable("unsupported size for AtomicCmpSwap!"); 5059 case 1: 5060 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB; 5061 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB; 5062 break; 5063 case 2: 5064 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH; 5065 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH; 5066 break; 5067 case 4: 5068 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX; 5069 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX; 5070 break; 5071 } 5072 5073 MachineFunction *MF = BB->getParent(); 5074 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5075 MachineFunction::iterator It = BB; 5076 ++It; // insert the new blocks after the current block 5077 5078 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 5079 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 5080 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5081 MF->insert(It, loop1MBB); 5082 MF->insert(It, loop2MBB); 5083 MF->insert(It, exitMBB); 5084 5085 // Transfer the remainder of BB and its successor edges to exitMBB. 5086 exitMBB->splice(exitMBB->begin(), BB, 5087 llvm::next(MachineBasicBlock::iterator(MI)), 5088 BB->end()); 5089 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5090 5091 // thisMBB: 5092 // ... 5093 // fallthrough --> loop1MBB 5094 BB->addSuccessor(loop1MBB); 5095 5096 // loop1MBB: 5097 // ldrex dest, [ptr] 5098 // cmp dest, oldval 5099 // bne exitMBB 5100 BB = loop1MBB; 5101 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); 5102 if (ldrOpc == ARM::t2LDREX) 5103 MIB.addImm(0); 5104 AddDefaultPred(MIB); 5105 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 5106 .addReg(dest).addReg(oldval)); 5107 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5108 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5109 BB->addSuccessor(loop2MBB); 5110 BB->addSuccessor(exitMBB); 5111 5112 // loop2MBB: 5113 // strex scratch, newval, [ptr] 5114 // cmp scratch, #0 5115 // bne loop1MBB 5116 BB = loop2MBB; 5117 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval).addReg(ptr); 5118 if (strOpc == ARM::t2STREX) 5119 MIB.addImm(0); 5120 AddDefaultPred(MIB); 5121 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5122 .addReg(scratch).addImm(0)); 5123 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5124 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5125 BB->addSuccessor(loop1MBB); 5126 BB->addSuccessor(exitMBB); 5127 5128 // exitMBB: 5129 // ... 5130 BB = exitMBB; 5131 5132 MI->eraseFromParent(); // The instruction is gone now. 5133 5134 return BB; 5135} 5136 5137MachineBasicBlock * 5138ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 5139 unsigned Size, unsigned BinOpcode) const { 5140 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. 5141 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5142 5143 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5144 MachineFunction *MF = BB->getParent(); 5145 MachineFunction::iterator It = BB; 5146 ++It; 5147 5148 unsigned dest = MI->getOperand(0).getReg(); 5149 unsigned ptr = MI->getOperand(1).getReg(); 5150 unsigned incr = MI->getOperand(2).getReg(); 5151 DebugLoc dl = MI->getDebugLoc(); 5152 bool isThumb2 = Subtarget->isThumb2(); 5153 5154 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 5155 if (isThumb2) { 5156 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass); 5157 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass); 5158 } 5159 5160 unsigned ldrOpc, strOpc; 5161 switch (Size) { 5162 default: llvm_unreachable("unsupported size for AtomicCmpSwap!"); 5163 case 1: 5164 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB; 5165 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB; 5166 break; 5167 case 2: 5168 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH; 5169 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH; 5170 break; 5171 case 4: 5172 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX; 5173 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX; 5174 break; 5175 } 5176 5177 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5178 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5179 MF->insert(It, loopMBB); 5180 MF->insert(It, exitMBB); 5181 5182 // Transfer the remainder of BB and its successor edges to exitMBB. 5183 exitMBB->splice(exitMBB->begin(), BB, 5184 llvm::next(MachineBasicBlock::iterator(MI)), 5185 BB->end()); 5186 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5187 5188 TargetRegisterClass *TRC = 5189 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; 5190 unsigned scratch = MRI.createVirtualRegister(TRC); 5191 unsigned scratch2 = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC); 5192 5193 // thisMBB: 5194 // ... 5195 // fallthrough --> loopMBB 5196 BB->addSuccessor(loopMBB); 5197 5198 // loopMBB: 5199 // ldrex dest, ptr 5200 // <binop> scratch2, dest, incr 5201 // strex scratch, scratch2, ptr 5202 // cmp scratch, #0 5203 // bne- loopMBB 5204 // fallthrough --> exitMBB 5205 BB = loopMBB; 5206 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); 5207 if (ldrOpc == ARM::t2LDREX) 5208 MIB.addImm(0); 5209 AddDefaultPred(MIB); 5210 if (BinOpcode) { 5211 // operand order needs to go the other way for NAND 5212 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr) 5213 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2). 5214 addReg(incr).addReg(dest)).addReg(0); 5215 else 5216 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2). 5217 addReg(dest).addReg(incr)).addReg(0); 5218 } 5219 5220 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr); 5221 if (strOpc == ARM::t2STREX) 5222 MIB.addImm(0); 5223 AddDefaultPred(MIB); 5224 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5225 .addReg(scratch).addImm(0)); 5226 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5227 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5228 5229 BB->addSuccessor(loopMBB); 5230 BB->addSuccessor(exitMBB); 5231 5232 // exitMBB: 5233 // ... 5234 BB = exitMBB; 5235 5236 MI->eraseFromParent(); // The instruction is gone now. 5237 5238 return BB; 5239} 5240 5241MachineBasicBlock * 5242ARMTargetLowering::EmitAtomicBinaryMinMax(MachineInstr *MI, 5243 MachineBasicBlock *BB, 5244 unsigned Size, 5245 bool signExtend, 5246 ARMCC::CondCodes Cond) const { 5247 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5248 5249 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5250 MachineFunction *MF = BB->getParent(); 5251 MachineFunction::iterator It = BB; 5252 ++It; 5253 5254 unsigned dest = MI->getOperand(0).getReg(); 5255 unsigned ptr = MI->getOperand(1).getReg(); 5256 unsigned incr = MI->getOperand(2).getReg(); 5257 unsigned oldval = dest; 5258 DebugLoc dl = MI->getDebugLoc(); 5259 bool isThumb2 = Subtarget->isThumb2(); 5260 5261 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 5262 if (isThumb2) { 5263 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass); 5264 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass); 5265 } 5266 5267 unsigned ldrOpc, strOpc, extendOpc; 5268 switch (Size) { 5269 default: llvm_unreachable("unsupported size for AtomicCmpSwap!"); 5270 case 1: 5271 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB; 5272 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB; 5273 extendOpc = isThumb2 ? ARM::t2SXTB : ARM::SXTB; 5274 break; 5275 case 2: 5276 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH; 5277 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH; 5278 extendOpc = isThumb2 ? ARM::t2SXTH : ARM::SXTH; 5279 break; 5280 case 4: 5281 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX; 5282 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX; 5283 extendOpc = 0; 5284 break; 5285 } 5286 5287 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5288 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5289 MF->insert(It, loopMBB); 5290 MF->insert(It, exitMBB); 5291 5292 // Transfer the remainder of BB and its successor edges to exitMBB. 5293 exitMBB->splice(exitMBB->begin(), BB, 5294 llvm::next(MachineBasicBlock::iterator(MI)), 5295 BB->end()); 5296 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5297 5298 TargetRegisterClass *TRC = 5299 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; 5300 unsigned scratch = MRI.createVirtualRegister(TRC); 5301 unsigned scratch2 = MRI.createVirtualRegister(TRC); 5302 5303 // thisMBB: 5304 // ... 5305 // fallthrough --> loopMBB 5306 BB->addSuccessor(loopMBB); 5307 5308 // loopMBB: 5309 // ldrex dest, ptr 5310 // (sign extend dest, if required) 5311 // cmp dest, incr 5312 // cmov.cond scratch2, dest, incr 5313 // strex scratch, scratch2, ptr 5314 // cmp scratch, #0 5315 // bne- loopMBB 5316 // fallthrough --> exitMBB 5317 BB = loopMBB; 5318 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); 5319 if (ldrOpc == ARM::t2LDREX) 5320 MIB.addImm(0); 5321 AddDefaultPred(MIB); 5322 5323 // Sign extend the value, if necessary. 5324 if (signExtend && extendOpc) { 5325 oldval = MRI.createVirtualRegister(ARM::GPRRegisterClass); 5326 AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval) 5327 .addReg(dest) 5328 .addImm(0)); 5329 } 5330 5331 // Build compare and cmov instructions. 5332 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 5333 .addReg(oldval).addReg(incr)); 5334 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr), scratch2) 5335 .addReg(oldval).addReg(incr).addImm(Cond).addReg(ARM::CPSR); 5336 5337 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr); 5338 if (strOpc == ARM::t2STREX) 5339 MIB.addImm(0); 5340 AddDefaultPred(MIB); 5341 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5342 .addReg(scratch).addImm(0)); 5343 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5344 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5345 5346 BB->addSuccessor(loopMBB); 5347 BB->addSuccessor(exitMBB); 5348 5349 // exitMBB: 5350 // ... 5351 BB = exitMBB; 5352 5353 MI->eraseFromParent(); // The instruction is gone now. 5354 5355 return BB; 5356} 5357 5358MachineBasicBlock * 5359ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB, 5360 unsigned Op1, unsigned Op2, 5361 bool NeedsCarry, bool IsCmpxchg) const { 5362 // This also handles ATOMIC_SWAP, indicated by Op1==0. 5363 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5364 5365 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 5366 MachineFunction *MF = BB->getParent(); 5367 MachineFunction::iterator It = BB; 5368 ++It; 5369 5370 unsigned destlo = MI->getOperand(0).getReg(); 5371 unsigned desthi = MI->getOperand(1).getReg(); 5372 unsigned ptr = MI->getOperand(2).getReg(); 5373 unsigned vallo = MI->getOperand(3).getReg(); 5374 unsigned valhi = MI->getOperand(4).getReg(); 5375 DebugLoc dl = MI->getDebugLoc(); 5376 bool isThumb2 = Subtarget->isThumb2(); 5377 5378 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 5379 if (isThumb2) { 5380 MRI.constrainRegClass(destlo, ARM::rGPRRegisterClass); 5381 MRI.constrainRegClass(desthi, ARM::rGPRRegisterClass); 5382 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass); 5383 } 5384 5385 unsigned ldrOpc = isThumb2 ? ARM::t2LDREXD : ARM::LDREXD; 5386 unsigned strOpc = isThumb2 ? ARM::t2STREXD : ARM::STREXD; 5387 5388 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5389 MachineBasicBlock *contBB = 0, *cont2BB = 0; 5390 if (IsCmpxchg) { 5391 contBB = MF->CreateMachineBasicBlock(LLVM_BB); 5392 cont2BB = MF->CreateMachineBasicBlock(LLVM_BB); 5393 } 5394 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 5395 MF->insert(It, loopMBB); 5396 if (IsCmpxchg) { 5397 MF->insert(It, contBB); 5398 MF->insert(It, cont2BB); 5399 } 5400 MF->insert(It, exitMBB); 5401 5402 // Transfer the remainder of BB and its successor edges to exitMBB. 5403 exitMBB->splice(exitMBB->begin(), BB, 5404 llvm::next(MachineBasicBlock::iterator(MI)), 5405 BB->end()); 5406 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 5407 5408 TargetRegisterClass *TRC = 5409 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; 5410 unsigned storesuccess = MRI.createVirtualRegister(TRC); 5411 5412 // thisMBB: 5413 // ... 5414 // fallthrough --> loopMBB 5415 BB->addSuccessor(loopMBB); 5416 5417 // loopMBB: 5418 // ldrexd r2, r3, ptr 5419 // <binopa> r0, r2, incr 5420 // <binopb> r1, r3, incr 5421 // strexd storesuccess, r0, r1, ptr 5422 // cmp storesuccess, #0 5423 // bne- loopMBB 5424 // fallthrough --> exitMBB 5425 // 5426 // Note that the registers are explicitly specified because there is not any 5427 // way to force the register allocator to allocate a register pair. 5428 // 5429 // FIXME: The hardcoded registers are not necessary for Thumb2, but we 5430 // need to properly enforce the restriction that the two output registers 5431 // for ldrexd must be different. 5432 BB = loopMBB; 5433 // Load 5434 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc)) 5435 .addReg(ARM::R2, RegState::Define) 5436 .addReg(ARM::R3, RegState::Define).addReg(ptr)); 5437 // Copy r2/r3 into dest. (This copy will normally be coalesced.) 5438 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), destlo).addReg(ARM::R2); 5439 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), desthi).addReg(ARM::R3); 5440 5441 if (IsCmpxchg) { 5442 // Add early exit 5443 for (unsigned i = 0; i < 2; i++) { 5444 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : 5445 ARM::CMPrr)) 5446 .addReg(i == 0 ? destlo : desthi) 5447 .addReg(i == 0 ? vallo : valhi)); 5448 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5449 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5450 BB->addSuccessor(exitMBB); 5451 BB->addSuccessor(i == 0 ? contBB : cont2BB); 5452 BB = (i == 0 ? contBB : cont2BB); 5453 } 5454 5455 // Copy to physregs for strexd 5456 unsigned setlo = MI->getOperand(5).getReg(); 5457 unsigned sethi = MI->getOperand(6).getReg(); 5458 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(setlo); 5459 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(sethi); 5460 } else if (Op1) { 5461 // Perform binary operation 5462 AddDefaultPred(BuildMI(BB, dl, TII->get(Op1), ARM::R0) 5463 .addReg(destlo).addReg(vallo)) 5464 .addReg(NeedsCarry ? ARM::CPSR : 0, getDefRegState(NeedsCarry)); 5465 AddDefaultPred(BuildMI(BB, dl, TII->get(Op2), ARM::R1) 5466 .addReg(desthi).addReg(valhi)).addReg(0); 5467 } else { 5468 // Copy to physregs for strexd 5469 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(vallo); 5470 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(valhi); 5471 } 5472 5473 // Store 5474 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), storesuccess) 5475 .addReg(ARM::R0).addReg(ARM::R1).addReg(ptr)); 5476 // Cmp+jump 5477 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 5478 .addReg(storesuccess).addImm(0)); 5479 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 5480 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR); 5481 5482 BB->addSuccessor(loopMBB); 5483 BB->addSuccessor(exitMBB); 5484 5485 // exitMBB: 5486 // ... 5487 BB = exitMBB; 5488 5489 MI->eraseFromParent(); // The instruction is gone now. 5490 5491 return BB; 5492} 5493 5494/// EmitBasePointerRecalculation - For functions using a base pointer, we 5495/// rematerialize it (via the frame pointer). 5496void ARMTargetLowering:: 5497EmitBasePointerRecalculation(MachineInstr *MI, MachineBasicBlock *MBB, 5498 MachineBasicBlock *DispatchBB) const { 5499 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5500 const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII); 5501 MachineFunction &MF = *MI->getParent()->getParent(); 5502 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 5503 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo(); 5504 5505 if (!RI.hasBasePointer(MF)) return; 5506 5507 MachineBasicBlock::iterator MBBI = MI; 5508 5509 int32_t NumBytes = AFI->getFramePtrSpillOffset(); 5510 unsigned FramePtr = RI.getFrameRegister(MF); 5511 assert(MF.getTarget().getFrameLowering()->hasFP(MF) && 5512 "Base pointer without frame pointer?"); 5513 5514 if (AFI->isThumb2Function()) 5515 llvm::emitT2RegPlusImmediate(*MBB, MBBI, MI->getDebugLoc(), ARM::R6, 5516 FramePtr, -NumBytes, ARMCC::AL, 0, *AII); 5517 else if (AFI->isThumbFunction()) 5518 llvm::emitThumbRegPlusImmediate(*MBB, MBBI, MI->getDebugLoc(), ARM::R6, 5519 FramePtr, -NumBytes, *AII, RI); 5520 else 5521 llvm::emitARMRegPlusImmediate(*MBB, MBBI, MI->getDebugLoc(), ARM::R6, 5522 FramePtr, -NumBytes, ARMCC::AL, 0, *AII); 5523 5524 if (!RI.needsStackRealignment(MF)) return; 5525 5526 // If there's dynamic realignment, adjust for it. 5527 MachineFrameInfo *MFI = MF.getFrameInfo(); 5528 unsigned MaxAlign = MFI->getMaxAlignment(); 5529 assert(!AFI->isThumb1OnlyFunction()); 5530 5531 // Emit bic r6, r6, MaxAlign 5532 unsigned bicOpc = AFI->isThumbFunction() ? ARM::t2BICri : ARM::BICri; 5533 AddDefaultCC( 5534 AddDefaultPred( 5535 BuildMI(*MBB, MBBI, MI->getDebugLoc(), TII->get(bicOpc), ARM::R6) 5536 .addReg(ARM::R6, RegState::Kill) 5537 .addImm(MaxAlign - 1))); 5538} 5539 5540/// SetupEntryBlockForSjLj - Insert code into the entry block that creates and 5541/// registers the function context. 5542void ARMTargetLowering:: 5543SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB, 5544 MachineBasicBlock *DispatchBB, int FI) const { 5545 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5546 DebugLoc dl = MI->getDebugLoc(); 5547 MachineFunction *MF = MBB->getParent(); 5548 MachineRegisterInfo *MRI = &MF->getRegInfo(); 5549 MachineConstantPool *MCP = MF->getConstantPool(); 5550 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>(); 5551 const Function *F = MF->getFunction(); 5552 5553 bool isThumb = Subtarget->isThumb(); 5554 bool isThumb2 = Subtarget->isThumb2(); 5555 5556 unsigned PCLabelId = AFI->createPICLabelUId(); 5557 unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8; 5558 ARMConstantPoolValue *CPV = 5559 ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj); 5560 unsigned CPI = MCP->getConstantPoolIndex(CPV, 4); 5561 5562 const TargetRegisterClass *TRC = 5563 isThumb ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; 5564 5565 // Grab constant pool and fixed stack memory operands. 5566 MachineMemOperand *CPMMO = 5567 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(), 5568 MachineMemOperand::MOLoad, 4, 4); 5569 5570 MachineMemOperand *FIMMOSt = 5571 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 5572 MachineMemOperand::MOStore, 4, 4); 5573 5574 EmitBasePointerRecalculation(MI, MBB, DispatchBB); 5575 5576 // Load the address of the dispatch MBB into the jump buffer. 5577 if (isThumb2) { 5578 // Incoming value: jbuf 5579 // ldr.n r5, LCPI1_1 5580 // orr r5, r5, #1 5581 // add r5, pc 5582 // str r5, [$jbuf, #+4] ; &jbuf[1] 5583 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5584 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1) 5585 .addConstantPoolIndex(CPI) 5586 .addMemOperand(CPMMO)); 5587 // Set the low bit because of thumb mode. 5588 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5589 AddDefaultCC( 5590 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2) 5591 .addReg(NewVReg1, RegState::Kill) 5592 .addImm(0x01))); 5593 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 5594 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3) 5595 .addReg(NewVReg2, RegState::Kill) 5596 .addImm(PCLabelId); 5597 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12)) 5598 .addReg(NewVReg3, RegState::Kill) 5599 .addFrameIndex(FI) 5600 .addImm(36) // &jbuf[1] :: pc 5601 .addMemOperand(FIMMOSt)); 5602 } else if (isThumb) { 5603 // Incoming value: jbuf 5604 // ldr.n r1, LCPI1_4 5605 // add r1, pc 5606 // mov r2, #1 5607 // orrs r1, r2 5608 // add r2, $jbuf, #+4 ; &jbuf[1] 5609 // str r1, [r2] 5610 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5611 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1) 5612 .addConstantPoolIndex(CPI) 5613 .addMemOperand(CPMMO)); 5614 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5615 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2) 5616 .addReg(NewVReg1, RegState::Kill) 5617 .addImm(PCLabelId); 5618 // Set the low bit because of thumb mode. 5619 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 5620 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3) 5621 .addReg(ARM::CPSR, RegState::Define) 5622 .addImm(1)); 5623 unsigned NewVReg4 = MRI->createVirtualRegister(TRC); 5624 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4) 5625 .addReg(ARM::CPSR, RegState::Define) 5626 .addReg(NewVReg2, RegState::Kill) 5627 .addReg(NewVReg3, RegState::Kill)); 5628 unsigned NewVReg5 = MRI->createVirtualRegister(TRC); 5629 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tADDrSPi), NewVReg5) 5630 .addFrameIndex(FI) 5631 .addImm(36)); // &jbuf[1] :: pc 5632 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi)) 5633 .addReg(NewVReg4, RegState::Kill) 5634 .addReg(NewVReg5, RegState::Kill) 5635 .addImm(0) 5636 .addMemOperand(FIMMOSt)); 5637 } else { 5638 // Incoming value: jbuf 5639 // ldr r1, LCPI1_1 5640 // add r1, pc, r1 5641 // str r1, [$jbuf, #+4] ; &jbuf[1] 5642 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5643 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1) 5644 .addConstantPoolIndex(CPI) 5645 .addImm(0) 5646 .addMemOperand(CPMMO)); 5647 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5648 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2) 5649 .addReg(NewVReg1, RegState::Kill) 5650 .addImm(PCLabelId)); 5651 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12)) 5652 .addReg(NewVReg2, RegState::Kill) 5653 .addFrameIndex(FI) 5654 .addImm(36) // &jbuf[1] :: pc 5655 .addMemOperand(FIMMOSt)); 5656 } 5657} 5658 5659MachineBasicBlock *ARMTargetLowering:: 5660EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const { 5661 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5662 DebugLoc dl = MI->getDebugLoc(); 5663 MachineFunction *MF = MBB->getParent(); 5664 MachineRegisterInfo *MRI = &MF->getRegInfo(); 5665 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>(); 5666 MachineFrameInfo *MFI = MF->getFrameInfo(); 5667 int FI = MFI->getFunctionContextIndex(); 5668 5669 const TargetRegisterClass *TRC = 5670 Subtarget->isThumb() ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass; 5671 5672 // Get a mapping of the call site numbers to all of the landing pads they're 5673 // associated with. 5674 DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2> > CallSiteNumToLPad; 5675 unsigned MaxCSNum = 0; 5676 MachineModuleInfo &MMI = MF->getMMI(); 5677 for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E; ++BB) { 5678 if (!BB->isLandingPad()) continue; 5679 5680 // FIXME: We should assert that the EH_LABEL is the first MI in the landing 5681 // pad. 5682 for (MachineBasicBlock::iterator 5683 II = BB->begin(), IE = BB->end(); II != IE; ++II) { 5684 if (!II->isEHLabel()) continue; 5685 5686 MCSymbol *Sym = II->getOperand(0).getMCSymbol(); 5687 if (!MMI.hasCallSiteLandingPad(Sym)) continue; 5688 5689 SmallVectorImpl<unsigned> &CallSiteIdxs = MMI.getCallSiteLandingPad(Sym); 5690 for (SmallVectorImpl<unsigned>::iterator 5691 CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end(); 5692 CSI != CSE; ++CSI) { 5693 CallSiteNumToLPad[*CSI].push_back(BB); 5694 MaxCSNum = std::max(MaxCSNum, *CSI); 5695 } 5696 break; 5697 } 5698 } 5699 5700 // Get an ordered list of the machine basic blocks for the jump table. 5701 std::vector<MachineBasicBlock*> LPadList; 5702 LPadList.reserve(CallSiteNumToLPad.size()); 5703 for (unsigned I = 1; I <= MaxCSNum; ++I) { 5704 SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I]; 5705 for (SmallVectorImpl<MachineBasicBlock*>::iterator 5706 II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) 5707 LPadList.push_back(*II); 5708 } 5709 5710 assert(!LPadList.empty() && 5711 "No landing pad destinations for the dispatch jump table!"); 5712 5713 // Create the jump table and associated information. 5714 MachineJumpTableInfo *JTI = 5715 MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline); 5716 unsigned MJTI = JTI->createJumpTableIndex(LPadList); 5717 unsigned UId = AFI->createJumpTableUId(); 5718 5719 // Create the MBBs for the dispatch code. 5720 5721 // Shove the dispatch's address into the return slot in the function context. 5722 MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock(); 5723 DispatchBB->setIsLandingPad(); 5724 MBB->addSuccessor(DispatchBB); 5725 5726 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock(); 5727 BuildMI(TrapBB, dl, TII->get(Subtarget->isThumb() ? ARM::tTRAP : ARM::TRAP)); 5728 DispatchBB->addSuccessor(TrapBB); 5729 5730 MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock(); 5731 DispatchBB->addSuccessor(DispContBB); 5732 5733 // Insert and renumber MBBs. 5734 MachineBasicBlock *Last = &MF->back(); 5735 MF->insert(MF->end(), DispatchBB); 5736 MF->insert(MF->end(), DispContBB); 5737 MF->insert(MF->end(), TrapBB); 5738 MF->RenumberBlocks(Last); 5739 5740 // Insert code into the entry block that creates and registers the function 5741 // context. 5742 SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI); 5743 5744 MachineMemOperand *FIMMOLd = 5745 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 5746 MachineMemOperand::MOLoad | 5747 MachineMemOperand::MOVolatile, 4, 4); 5748 5749 if (Subtarget->isThumb2()) { 5750 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5751 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1) 5752 .addFrameIndex(FI) 5753 .addImm(4) 5754 .addMemOperand(FIMMOLd)); 5755 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri)) 5756 .addReg(NewVReg1) 5757 .addImm(LPadList.size())); 5758 BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc)) 5759 .addMBB(TrapBB) 5760 .addImm(ARMCC::HI) 5761 .addReg(ARM::CPSR); 5762 5763 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5764 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg2) 5765 .addJumpTableIndex(MJTI) 5766 .addImm(UId)); 5767 5768 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 5769 AddDefaultCC( 5770 AddDefaultPred( 5771 BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg3) 5772 .addReg(NewVReg2, RegState::Kill) 5773 .addReg(NewVReg1) 5774 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2)))); 5775 5776 BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT)) 5777 .addReg(NewVReg3, RegState::Kill) 5778 .addReg(NewVReg1) 5779 .addJumpTableIndex(MJTI) 5780 .addImm(UId); 5781 } else if (Subtarget->isThumb()) { 5782 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5783 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1) 5784 .addFrameIndex(FI) 5785 .addImm(1) 5786 .addMemOperand(FIMMOLd)); 5787 5788 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8)) 5789 .addReg(NewVReg1) 5790 .addImm(LPadList.size())); 5791 BuildMI(DispatchBB, dl, TII->get(ARM::tBcc)) 5792 .addMBB(TrapBB) 5793 .addImm(ARMCC::HI) 5794 .addReg(ARM::CPSR); 5795 5796 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5797 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2) 5798 .addReg(ARM::CPSR, RegState::Define) 5799 .addReg(NewVReg1) 5800 .addImm(2)); 5801 5802 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 5803 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3) 5804 .addJumpTableIndex(MJTI) 5805 .addImm(UId)); 5806 5807 unsigned NewVReg4 = MRI->createVirtualRegister(TRC); 5808 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4) 5809 .addReg(ARM::CPSR, RegState::Define) 5810 .addReg(NewVReg2, RegState::Kill) 5811 .addReg(NewVReg3)); 5812 5813 MachineMemOperand *JTMMOLd = 5814 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(), 5815 MachineMemOperand::MOLoad, 4, 4); 5816 5817 unsigned NewVReg5 = MRI->createVirtualRegister(TRC); 5818 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5) 5819 .addReg(NewVReg4, RegState::Kill) 5820 .addImm(0) 5821 .addMemOperand(JTMMOLd)); 5822 5823 unsigned NewVReg6 = MRI->createVirtualRegister(TRC); 5824 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6) 5825 .addReg(ARM::CPSR, RegState::Define) 5826 .addReg(NewVReg5, RegState::Kill) 5827 .addReg(NewVReg3)); 5828 5829 BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr)) 5830 .addReg(NewVReg6, RegState::Kill) 5831 .addJumpTableIndex(MJTI) 5832 .addImm(UId); 5833 } else { 5834 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); 5835 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1) 5836 .addFrameIndex(FI) 5837 .addImm(4) 5838 .addMemOperand(FIMMOLd)); 5839 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri)) 5840 .addReg(NewVReg1) 5841 .addImm(LPadList.size())); 5842 BuildMI(DispatchBB, dl, TII->get(ARM::Bcc)) 5843 .addMBB(TrapBB) 5844 .addImm(ARMCC::HI) 5845 .addReg(ARM::CPSR); 5846 5847 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); 5848 AddDefaultCC( 5849 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg2) 5850 .addReg(NewVReg1) 5851 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2)))); 5852 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); 5853 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg3) 5854 .addJumpTableIndex(MJTI) 5855 .addImm(UId)); 5856 5857 MachineMemOperand *JTMMOLd = 5858 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(), 5859 MachineMemOperand::MOLoad, 4, 4); 5860 unsigned NewVReg4 = MRI->createVirtualRegister(TRC); 5861 AddDefaultPred( 5862 BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg4) 5863 .addReg(NewVReg2, RegState::Kill) 5864 .addReg(NewVReg3) 5865 .addImm(0) 5866 .addMemOperand(JTMMOLd)); 5867 5868 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd)) 5869 .addReg(NewVReg4, RegState::Kill) 5870 .addReg(NewVReg3) 5871 .addJumpTableIndex(MJTI) 5872 .addImm(UId); 5873 } 5874 5875 // Add the jump table entries as successors to the MBB. 5876 for (std::vector<MachineBasicBlock*>::iterator 5877 I = LPadList.begin(), E = LPadList.end(); I != E; ++I) 5878 DispContBB->addSuccessor(*I); 5879 5880 // The instruction is gone now. 5881 MI->eraseFromParent(); 5882 5883 return MBB; 5884} 5885 5886static 5887MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) { 5888 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(), 5889 E = MBB->succ_end(); I != E; ++I) 5890 if (*I != Succ) 5891 return *I; 5892 llvm_unreachable("Expecting a BB with two successors!"); 5893} 5894 5895MachineBasicBlock * 5896ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 5897 MachineBasicBlock *BB) const { 5898 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 5899 DebugLoc dl = MI->getDebugLoc(); 5900 bool isThumb2 = Subtarget->isThumb2(); 5901 switch (MI->getOpcode()) { 5902 default: { 5903 MI->dump(); 5904 llvm_unreachable("Unexpected instr type to insert"); 5905 } 5906 // The Thumb2 pre-indexed stores have the same MI operands, they just 5907 // define them differently in the .td files from the isel patterns, so 5908 // they need pseudos. 5909 case ARM::t2STR_preidx: 5910 MI->setDesc(TII->get(ARM::t2STR_PRE)); 5911 return BB; 5912 case ARM::t2STRB_preidx: 5913 MI->setDesc(TII->get(ARM::t2STRB_PRE)); 5914 return BB; 5915 case ARM::t2STRH_preidx: 5916 MI->setDesc(TII->get(ARM::t2STRH_PRE)); 5917 return BB; 5918 5919 case ARM::STRi_preidx: 5920 case ARM::STRBi_preidx: { 5921 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ? 5922 ARM::STR_PRE_IMM : ARM::STRB_PRE_IMM; 5923 // Decode the offset. 5924 unsigned Offset = MI->getOperand(4).getImm(); 5925 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub; 5926 Offset = ARM_AM::getAM2Offset(Offset); 5927 if (isSub) 5928 Offset = -Offset; 5929 5930 MachineMemOperand *MMO = *MI->memoperands_begin(); 5931 BuildMI(*BB, MI, dl, TII->get(NewOpc)) 5932 .addOperand(MI->getOperand(0)) // Rn_wb 5933 .addOperand(MI->getOperand(1)) // Rt 5934 .addOperand(MI->getOperand(2)) // Rn 5935 .addImm(Offset) // offset (skip GPR==zero_reg) 5936 .addOperand(MI->getOperand(5)) // pred 5937 .addOperand(MI->getOperand(6)) 5938 .addMemOperand(MMO); 5939 MI->eraseFromParent(); 5940 return BB; 5941 } 5942 case ARM::STRr_preidx: 5943 case ARM::STRBr_preidx: 5944 case ARM::STRH_preidx: { 5945 unsigned NewOpc; 5946 switch (MI->getOpcode()) { 5947 default: llvm_unreachable("unexpected opcode!"); 5948 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break; 5949 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break; 5950 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break; 5951 } 5952 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc)); 5953 for (unsigned i = 0; i < MI->getNumOperands(); ++i) 5954 MIB.addOperand(MI->getOperand(i)); 5955 MI->eraseFromParent(); 5956 return BB; 5957 } 5958 case ARM::ATOMIC_LOAD_ADD_I8: 5959 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 5960 case ARM::ATOMIC_LOAD_ADD_I16: 5961 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 5962 case ARM::ATOMIC_LOAD_ADD_I32: 5963 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr); 5964 5965 case ARM::ATOMIC_LOAD_AND_I8: 5966 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 5967 case ARM::ATOMIC_LOAD_AND_I16: 5968 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 5969 case ARM::ATOMIC_LOAD_AND_I32: 5970 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 5971 5972 case ARM::ATOMIC_LOAD_OR_I8: 5973 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 5974 case ARM::ATOMIC_LOAD_OR_I16: 5975 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 5976 case ARM::ATOMIC_LOAD_OR_I32: 5977 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 5978 5979 case ARM::ATOMIC_LOAD_XOR_I8: 5980 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 5981 case ARM::ATOMIC_LOAD_XOR_I16: 5982 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 5983 case ARM::ATOMIC_LOAD_XOR_I32: 5984 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr); 5985 5986 case ARM::ATOMIC_LOAD_NAND_I8: 5987 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 5988 case ARM::ATOMIC_LOAD_NAND_I16: 5989 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 5990 case ARM::ATOMIC_LOAD_NAND_I32: 5991 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr); 5992 5993 case ARM::ATOMIC_LOAD_SUB_I8: 5994 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 5995 case ARM::ATOMIC_LOAD_SUB_I16: 5996 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 5997 case ARM::ATOMIC_LOAD_SUB_I32: 5998 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr); 5999 6000 case ARM::ATOMIC_LOAD_MIN_I8: 6001 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::LT); 6002 case ARM::ATOMIC_LOAD_MIN_I16: 6003 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::LT); 6004 case ARM::ATOMIC_LOAD_MIN_I32: 6005 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::LT); 6006 6007 case ARM::ATOMIC_LOAD_MAX_I8: 6008 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::GT); 6009 case ARM::ATOMIC_LOAD_MAX_I16: 6010 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::GT); 6011 case ARM::ATOMIC_LOAD_MAX_I32: 6012 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::GT); 6013 6014 case ARM::ATOMIC_LOAD_UMIN_I8: 6015 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::LO); 6016 case ARM::ATOMIC_LOAD_UMIN_I16: 6017 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::LO); 6018 case ARM::ATOMIC_LOAD_UMIN_I32: 6019 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::LO); 6020 6021 case ARM::ATOMIC_LOAD_UMAX_I8: 6022 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::HI); 6023 case ARM::ATOMIC_LOAD_UMAX_I16: 6024 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::HI); 6025 case ARM::ATOMIC_LOAD_UMAX_I32: 6026 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::HI); 6027 6028 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0); 6029 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0); 6030 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0); 6031 6032 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1); 6033 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2); 6034 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4); 6035 6036 6037 case ARM::ATOMADD6432: 6038 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr, 6039 isThumb2 ? ARM::t2ADCrr : ARM::ADCrr, 6040 /*NeedsCarry*/ true); 6041 case ARM::ATOMSUB6432: 6042 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr, 6043 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr, 6044 /*NeedsCarry*/ true); 6045 case ARM::ATOMOR6432: 6046 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr, 6047 isThumb2 ? ARM::t2ORRrr : ARM::ORRrr); 6048 case ARM::ATOMXOR6432: 6049 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2EORrr : ARM::EORrr, 6050 isThumb2 ? ARM::t2EORrr : ARM::EORrr); 6051 case ARM::ATOMAND6432: 6052 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr, 6053 isThumb2 ? ARM::t2ANDrr : ARM::ANDrr); 6054 case ARM::ATOMSWAP6432: 6055 return EmitAtomicBinary64(MI, BB, 0, 0, false); 6056 case ARM::ATOMCMPXCHG6432: 6057 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr, 6058 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr, 6059 /*NeedsCarry*/ false, /*IsCmpxchg*/true); 6060 6061 case ARM::tMOVCCr_pseudo: { 6062 // To "insert" a SELECT_CC instruction, we actually have to insert the 6063 // diamond control-flow pattern. The incoming instruction knows the 6064 // destination vreg to set, the condition code register to branch on, the 6065 // true/false values to select between, and a branch opcode to use. 6066 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 6067 MachineFunction::iterator It = BB; 6068 ++It; 6069 6070 // thisMBB: 6071 // ... 6072 // TrueVal = ... 6073 // cmpTY ccX, r1, r2 6074 // bCC copy1MBB 6075 // fallthrough --> copy0MBB 6076 MachineBasicBlock *thisMBB = BB; 6077 MachineFunction *F = BB->getParent(); 6078 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 6079 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 6080 F->insert(It, copy0MBB); 6081 F->insert(It, sinkMBB); 6082 6083 // Transfer the remainder of BB and its successor edges to sinkMBB. 6084 sinkMBB->splice(sinkMBB->begin(), BB, 6085 llvm::next(MachineBasicBlock::iterator(MI)), 6086 BB->end()); 6087 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 6088 6089 BB->addSuccessor(copy0MBB); 6090 BB->addSuccessor(sinkMBB); 6091 6092 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB) 6093 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg()); 6094 6095 // copy0MBB: 6096 // %FalseValue = ... 6097 // # fallthrough to sinkMBB 6098 BB = copy0MBB; 6099 6100 // Update machine-CFG edges 6101 BB->addSuccessor(sinkMBB); 6102 6103 // sinkMBB: 6104 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 6105 // ... 6106 BB = sinkMBB; 6107 BuildMI(*BB, BB->begin(), dl, 6108 TII->get(ARM::PHI), MI->getOperand(0).getReg()) 6109 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 6110 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 6111 6112 MI->eraseFromParent(); // The pseudo instruction is gone now. 6113 return BB; 6114 } 6115 6116 case ARM::BCCi64: 6117 case ARM::BCCZi64: { 6118 // If there is an unconditional branch to the other successor, remove it. 6119 BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end()); 6120 6121 // Compare both parts that make up the double comparison separately for 6122 // equality. 6123 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64; 6124 6125 unsigned LHS1 = MI->getOperand(1).getReg(); 6126 unsigned LHS2 = MI->getOperand(2).getReg(); 6127 if (RHSisZero) { 6128 AddDefaultPred(BuildMI(BB, dl, 6129 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 6130 .addReg(LHS1).addImm(0)); 6131 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri)) 6132 .addReg(LHS2).addImm(0) 6133 .addImm(ARMCC::EQ).addReg(ARM::CPSR); 6134 } else { 6135 unsigned RHS1 = MI->getOperand(3).getReg(); 6136 unsigned RHS2 = MI->getOperand(4).getReg(); 6137 AddDefaultPred(BuildMI(BB, dl, 6138 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 6139 .addReg(LHS1).addReg(RHS1)); 6140 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr)) 6141 .addReg(LHS2).addReg(RHS2) 6142 .addImm(ARMCC::EQ).addReg(ARM::CPSR); 6143 } 6144 6145 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB(); 6146 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB); 6147 if (MI->getOperand(0).getImm() == ARMCC::NE) 6148 std::swap(destMBB, exitMBB); 6149 6150 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)) 6151 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR); 6152 if (isThumb2) 6153 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB)); 6154 else 6155 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB); 6156 6157 MI->eraseFromParent(); // The pseudo instruction is gone now. 6158 return BB; 6159 } 6160 6161 case ARM::ABS: 6162 case ARM::t2ABS: { 6163 // To insert an ABS instruction, we have to insert the 6164 // diamond control-flow pattern. The incoming instruction knows the 6165 // source vreg to test against 0, the destination vreg to set, 6166 // the condition code register to branch on, the 6167 // true/false values to select between, and a branch opcode to use. 6168 // It transforms 6169 // V1 = ABS V0 6170 // into 6171 // V2 = MOVS V0 6172 // BCC (branch to SinkBB if V0 >= 0) 6173 // RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0) 6174 // SinkBB: V1 = PHI(V2, V3) 6175 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 6176 MachineFunction::iterator BBI = BB; 6177 ++BBI; 6178 MachineFunction *Fn = BB->getParent(); 6179 MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB); 6180 MachineBasicBlock *SinkBB = Fn->CreateMachineBasicBlock(LLVM_BB); 6181 Fn->insert(BBI, RSBBB); 6182 Fn->insert(BBI, SinkBB); 6183 6184 unsigned int ABSSrcReg = MI->getOperand(1).getReg(); 6185 unsigned int ABSDstReg = MI->getOperand(0).getReg(); 6186 bool isThumb2 = Subtarget->isThumb2(); 6187 MachineRegisterInfo &MRI = Fn->getRegInfo(); 6188 // In Thumb mode S must not be specified if source register is the SP or 6189 // PC and if destination register is the SP, so restrict register class 6190 unsigned NewMovDstReg = MRI.createVirtualRegister( 6191 isThumb2 ? ARM::rGPRRegisterClass : ARM::GPRRegisterClass); 6192 unsigned NewRsbDstReg = MRI.createVirtualRegister( 6193 isThumb2 ? ARM::rGPRRegisterClass : ARM::GPRRegisterClass); 6194 6195 // Transfer the remainder of BB and its successor edges to sinkMBB. 6196 SinkBB->splice(SinkBB->begin(), BB, 6197 llvm::next(MachineBasicBlock::iterator(MI)), 6198 BB->end()); 6199 SinkBB->transferSuccessorsAndUpdatePHIs(BB); 6200 6201 BB->addSuccessor(RSBBB); 6202 BB->addSuccessor(SinkBB); 6203 6204 // fall through to SinkMBB 6205 RSBBB->addSuccessor(SinkBB); 6206 6207 // insert a movs at the end of BB 6208 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVr : ARM::MOVr), 6209 NewMovDstReg) 6210 .addReg(ABSSrcReg, RegState::Kill) 6211 .addImm((unsigned)ARMCC::AL).addReg(0) 6212 .addReg(ARM::CPSR, RegState::Define); 6213 6214 // insert a bcc with opposite CC to ARMCC::MI at the end of BB 6215 BuildMI(BB, dl, 6216 TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB) 6217 .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR); 6218 6219 // insert rsbri in RSBBB 6220 // Note: BCC and rsbri will be converted into predicated rsbmi 6221 // by if-conversion pass 6222 BuildMI(*RSBBB, RSBBB->begin(), dl, 6223 TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg) 6224 .addReg(NewMovDstReg, RegState::Kill) 6225 .addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 6226 6227 // insert PHI in SinkBB, 6228 // reuse ABSDstReg to not change uses of ABS instruction 6229 BuildMI(*SinkBB, SinkBB->begin(), dl, 6230 TII->get(ARM::PHI), ABSDstReg) 6231 .addReg(NewRsbDstReg).addMBB(RSBBB) 6232 .addReg(NewMovDstReg).addMBB(BB); 6233 6234 // remove ABS instruction 6235 MI->eraseFromParent(); 6236 6237 // return last added BB 6238 return SinkBB; 6239 } 6240 } 6241} 6242 6243void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, 6244 SDNode *Node) const { 6245 const MCInstrDesc &MCID = MI->getDesc(); 6246 if (!MCID.hasPostISelHook()) { 6247 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) && 6248 "Pseudo flag-setting opcodes must be marked with 'hasPostISelHook'"); 6249 return; 6250 } 6251 6252 // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB, 6253 // RSC. Coming out of isel, they have an implicit CPSR def, but the optional 6254 // operand is still set to noreg. If needed, set the optional operand's 6255 // register to CPSR, and remove the redundant implicit def. 6256 // 6257 // e.g. ADCS (...opt:%noreg, CPSR<imp-def>) -> ADC (... opt:CPSR<def>). 6258 6259 // Rename pseudo opcodes. 6260 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode()); 6261 if (NewOpc) { 6262 const ARMBaseInstrInfo *TII = 6263 static_cast<const ARMBaseInstrInfo*>(getTargetMachine().getInstrInfo()); 6264 MI->setDesc(TII->get(NewOpc)); 6265 } 6266 unsigned ccOutIdx = MCID.getNumOperands() - 1; 6267 6268 // Any ARM instruction that sets the 's' bit should specify an optional 6269 // "cc_out" operand in the last operand position. 6270 if (!MCID.hasOptionalDef() || !MCID.OpInfo[ccOutIdx].isOptionalDef()) { 6271 assert(!NewOpc && "Optional cc_out operand required"); 6272 return; 6273 } 6274 // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it 6275 // since we already have an optional CPSR def. 6276 bool definesCPSR = false; 6277 bool deadCPSR = false; 6278 for (unsigned i = MCID.getNumOperands(), e = MI->getNumOperands(); 6279 i != e; ++i) { 6280 const MachineOperand &MO = MI->getOperand(i); 6281 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) { 6282 definesCPSR = true; 6283 if (MO.isDead()) 6284 deadCPSR = true; 6285 MI->RemoveOperand(i); 6286 break; 6287 } 6288 } 6289 if (!definesCPSR) { 6290 assert(!NewOpc && "Optional cc_out operand required"); 6291 return; 6292 } 6293 assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag"); 6294 if (deadCPSR) { 6295 assert(!MI->getOperand(ccOutIdx).getReg() && 6296 "expect uninitialized optional cc_out operand"); 6297 return; 6298 } 6299 6300 // If this instruction was defined with an optional CPSR def and its dag node 6301 // had a live implicit CPSR def, then activate the optional CPSR def. 6302 MachineOperand &MO = MI->getOperand(ccOutIdx); 6303 MO.setReg(ARM::CPSR); 6304 MO.setIsDef(true); 6305} 6306 6307//===----------------------------------------------------------------------===// 6308// ARM Optimization Hooks 6309//===----------------------------------------------------------------------===// 6310 6311static 6312SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, 6313 TargetLowering::DAGCombinerInfo &DCI) { 6314 SelectionDAG &DAG = DCI.DAG; 6315 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6316 EVT VT = N->getValueType(0); 6317 unsigned Opc = N->getOpcode(); 6318 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 6319 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 6320 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 6321 ISD::CondCode CC = ISD::SETCC_INVALID; 6322 6323 if (isSlctCC) { 6324 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 6325 } else { 6326 SDValue CCOp = Slct.getOperand(0); 6327 if (CCOp.getOpcode() == ISD::SETCC) 6328 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 6329 } 6330 6331 bool DoXform = false; 6332 bool InvCC = false; 6333 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 6334 "Bad input!"); 6335 6336 if (LHS.getOpcode() == ISD::Constant && 6337 cast<ConstantSDNode>(LHS)->isNullValue()) { 6338 DoXform = true; 6339 } else if (CC != ISD::SETCC_INVALID && 6340 RHS.getOpcode() == ISD::Constant && 6341 cast<ConstantSDNode>(RHS)->isNullValue()) { 6342 std::swap(LHS, RHS); 6343 SDValue Op0 = Slct.getOperand(0); 6344 EVT OpVT = isSlctCC ? Op0.getValueType() : 6345 Op0.getOperand(0).getValueType(); 6346 bool isInt = OpVT.isInteger(); 6347 CC = ISD::getSetCCInverse(CC, isInt); 6348 6349 if (!TLI.isCondCodeLegal(CC, OpVT)) 6350 return SDValue(); // Inverse operator isn't legal. 6351 6352 DoXform = true; 6353 InvCC = true; 6354 } 6355 6356 if (DoXform) { 6357 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS); 6358 if (isSlctCC) 6359 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result, 6360 Slct.getOperand(0), Slct.getOperand(1), CC); 6361 SDValue CCOp = Slct.getOperand(0); 6362 if (InvCC) 6363 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(), 6364 CCOp.getOperand(0), CCOp.getOperand(1), CC); 6365 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 6366 CCOp, OtherOp, Result); 6367 } 6368 return SDValue(); 6369} 6370 6371// AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction 6372// (only after legalization). 6373static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1, 6374 TargetLowering::DAGCombinerInfo &DCI, 6375 const ARMSubtarget *Subtarget) { 6376 6377 // Only perform optimization if after legalize, and if NEON is available. We 6378 // also expected both operands to be BUILD_VECTORs. 6379 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON() 6380 || N0.getOpcode() != ISD::BUILD_VECTOR 6381 || N1.getOpcode() != ISD::BUILD_VECTOR) 6382 return SDValue(); 6383 6384 // Check output type since VPADDL operand elements can only be 8, 16, or 32. 6385 EVT VT = N->getValueType(0); 6386 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64) 6387 return SDValue(); 6388 6389 // Check that the vector operands are of the right form. 6390 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR 6391 // operands, where N is the size of the formed vector. 6392 // Each EXTRACT_VECTOR should have the same input vector and odd or even 6393 // index such that we have a pair wise add pattern. 6394 6395 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing. 6396 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 6397 return SDValue(); 6398 SDValue Vec = N0->getOperand(0)->getOperand(0); 6399 SDNode *V = Vec.getNode(); 6400 unsigned nextIndex = 0; 6401 6402 // For each operands to the ADD which are BUILD_VECTORs, 6403 // check to see if each of their operands are an EXTRACT_VECTOR with 6404 // the same vector and appropriate index. 6405 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) { 6406 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT 6407 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) { 6408 6409 SDValue ExtVec0 = N0->getOperand(i); 6410 SDValue ExtVec1 = N1->getOperand(i); 6411 6412 // First operand is the vector, verify its the same. 6413 if (V != ExtVec0->getOperand(0).getNode() || 6414 V != ExtVec1->getOperand(0).getNode()) 6415 return SDValue(); 6416 6417 // Second is the constant, verify its correct. 6418 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1)); 6419 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1)); 6420 6421 // For the constant, we want to see all the even or all the odd. 6422 if (!C0 || !C1 || C0->getZExtValue() != nextIndex 6423 || C1->getZExtValue() != nextIndex+1) 6424 return SDValue(); 6425 6426 // Increment index. 6427 nextIndex+=2; 6428 } else 6429 return SDValue(); 6430 } 6431 6432 // Create VPADDL node. 6433 SelectionDAG &DAG = DCI.DAG; 6434 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6435 6436 // Build operand list. 6437 SmallVector<SDValue, 8> Ops; 6438 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls, 6439 TLI.getPointerTy())); 6440 6441 // Input is the vector. 6442 Ops.push_back(Vec); 6443 6444 // Get widened type and narrowed type. 6445 MVT widenType; 6446 unsigned numElem = VT.getVectorNumElements(); 6447 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) { 6448 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break; 6449 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break; 6450 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break; 6451 default: 6452 assert(0 && "Invalid vector element type for padd optimization."); 6453 } 6454 6455 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), 6456 widenType, &Ops[0], Ops.size()); 6457 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, tmp); 6458} 6459 6460/// PerformADDCombineWithOperands - Try DAG combinations for an ADD with 6461/// operands N0 and N1. This is a helper for PerformADDCombine that is 6462/// called with the default operands, and if that fails, with commuted 6463/// operands. 6464static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1, 6465 TargetLowering::DAGCombinerInfo &DCI, 6466 const ARMSubtarget *Subtarget){ 6467 6468 // Attempt to create vpaddl for this add. 6469 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget); 6470 if (Result.getNode()) 6471 return Result; 6472 6473 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 6474 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) { 6475 SDValue Result = combineSelectAndUse(N, N0, N1, DCI); 6476 if (Result.getNode()) return Result; 6477 } 6478 return SDValue(); 6479} 6480 6481/// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD. 6482/// 6483static SDValue PerformADDCombine(SDNode *N, 6484 TargetLowering::DAGCombinerInfo &DCI, 6485 const ARMSubtarget *Subtarget) { 6486 SDValue N0 = N->getOperand(0); 6487 SDValue N1 = N->getOperand(1); 6488 6489 // First try with the default operand order. 6490 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget); 6491 if (Result.getNode()) 6492 return Result; 6493 6494 // If that didn't work, try again with the operands commuted. 6495 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget); 6496} 6497 6498/// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB. 6499/// 6500static SDValue PerformSUBCombine(SDNode *N, 6501 TargetLowering::DAGCombinerInfo &DCI) { 6502 SDValue N0 = N->getOperand(0); 6503 SDValue N1 = N->getOperand(1); 6504 6505 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 6506 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 6507 SDValue Result = combineSelectAndUse(N, N1, N0, DCI); 6508 if (Result.getNode()) return Result; 6509 } 6510 6511 return SDValue(); 6512} 6513 6514/// PerformVMULCombine 6515/// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the 6516/// special multiplier accumulator forwarding. 6517/// vmul d3, d0, d2 6518/// vmla d3, d1, d2 6519/// is faster than 6520/// vadd d3, d0, d1 6521/// vmul d3, d3, d2 6522static SDValue PerformVMULCombine(SDNode *N, 6523 TargetLowering::DAGCombinerInfo &DCI, 6524 const ARMSubtarget *Subtarget) { 6525 if (!Subtarget->hasVMLxForwarding()) 6526 return SDValue(); 6527 6528 SelectionDAG &DAG = DCI.DAG; 6529 SDValue N0 = N->getOperand(0); 6530 SDValue N1 = N->getOperand(1); 6531 unsigned Opcode = N0.getOpcode(); 6532 if (Opcode != ISD::ADD && Opcode != ISD::SUB && 6533 Opcode != ISD::FADD && Opcode != ISD::FSUB) { 6534 Opcode = N1.getOpcode(); 6535 if (Opcode != ISD::ADD && Opcode != ISD::SUB && 6536 Opcode != ISD::FADD && Opcode != ISD::FSUB) 6537 return SDValue(); 6538 std::swap(N0, N1); 6539 } 6540 6541 EVT VT = N->getValueType(0); 6542 DebugLoc DL = N->getDebugLoc(); 6543 SDValue N00 = N0->getOperand(0); 6544 SDValue N01 = N0->getOperand(1); 6545 return DAG.getNode(Opcode, DL, VT, 6546 DAG.getNode(ISD::MUL, DL, VT, N00, N1), 6547 DAG.getNode(ISD::MUL, DL, VT, N01, N1)); 6548} 6549 6550static SDValue PerformMULCombine(SDNode *N, 6551 TargetLowering::DAGCombinerInfo &DCI, 6552 const ARMSubtarget *Subtarget) { 6553 SelectionDAG &DAG = DCI.DAG; 6554 6555 if (Subtarget->isThumb1Only()) 6556 return SDValue(); 6557 6558 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 6559 return SDValue(); 6560 6561 EVT VT = N->getValueType(0); 6562 if (VT.is64BitVector() || VT.is128BitVector()) 6563 return PerformVMULCombine(N, DCI, Subtarget); 6564 if (VT != MVT::i32) 6565 return SDValue(); 6566 6567 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6568 if (!C) 6569 return SDValue(); 6570 6571 uint64_t MulAmt = C->getZExtValue(); 6572 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt); 6573 ShiftAmt = ShiftAmt & (32 - 1); 6574 SDValue V = N->getOperand(0); 6575 DebugLoc DL = N->getDebugLoc(); 6576 6577 SDValue Res; 6578 MulAmt >>= ShiftAmt; 6579 if (isPowerOf2_32(MulAmt - 1)) { 6580 // (mul x, 2^N + 1) => (add (shl x, N), x) 6581 Res = DAG.getNode(ISD::ADD, DL, VT, 6582 V, DAG.getNode(ISD::SHL, DL, VT, 6583 V, DAG.getConstant(Log2_32(MulAmt-1), 6584 MVT::i32))); 6585 } else if (isPowerOf2_32(MulAmt + 1)) { 6586 // (mul x, 2^N - 1) => (sub (shl x, N), x) 6587 Res = DAG.getNode(ISD::SUB, DL, VT, 6588 DAG.getNode(ISD::SHL, DL, VT, 6589 V, DAG.getConstant(Log2_32(MulAmt+1), 6590 MVT::i32)), 6591 V); 6592 } else 6593 return SDValue(); 6594 6595 if (ShiftAmt != 0) 6596 Res = DAG.getNode(ISD::SHL, DL, VT, Res, 6597 DAG.getConstant(ShiftAmt, MVT::i32)); 6598 6599 // Do not add new nodes to DAG combiner worklist. 6600 DCI.CombineTo(N, Res, false); 6601 return SDValue(); 6602} 6603 6604static SDValue PerformANDCombine(SDNode *N, 6605 TargetLowering::DAGCombinerInfo &DCI) { 6606 6607 // Attempt to use immediate-form VBIC 6608 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1)); 6609 DebugLoc dl = N->getDebugLoc(); 6610 EVT VT = N->getValueType(0); 6611 SelectionDAG &DAG = DCI.DAG; 6612 6613 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 6614 return SDValue(); 6615 6616 APInt SplatBits, SplatUndef; 6617 unsigned SplatBitSize; 6618 bool HasAnyUndefs; 6619 if (BVN && 6620 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { 6621 if (SplatBitSize <= 64) { 6622 EVT VbicVT; 6623 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(), 6624 SplatUndef.getZExtValue(), SplatBitSize, 6625 DAG, VbicVT, VT.is128BitVector(), 6626 OtherModImm); 6627 if (Val.getNode()) { 6628 SDValue Input = 6629 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0)); 6630 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val); 6631 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic); 6632 } 6633 } 6634 } 6635 6636 return SDValue(); 6637} 6638 6639/// PerformORCombine - Target-specific dag combine xforms for ISD::OR 6640static SDValue PerformORCombine(SDNode *N, 6641 TargetLowering::DAGCombinerInfo &DCI, 6642 const ARMSubtarget *Subtarget) { 6643 // Attempt to use immediate-form VORR 6644 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1)); 6645 DebugLoc dl = N->getDebugLoc(); 6646 EVT VT = N->getValueType(0); 6647 SelectionDAG &DAG = DCI.DAG; 6648 6649 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 6650 return SDValue(); 6651 6652 APInt SplatBits, SplatUndef; 6653 unsigned SplatBitSize; 6654 bool HasAnyUndefs; 6655 if (BVN && Subtarget->hasNEON() && 6656 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) { 6657 if (SplatBitSize <= 64) { 6658 EVT VorrVT; 6659 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(), 6660 SplatUndef.getZExtValue(), SplatBitSize, 6661 DAG, VorrVT, VT.is128BitVector(), 6662 OtherModImm); 6663 if (Val.getNode()) { 6664 SDValue Input = 6665 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0)); 6666 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val); 6667 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr); 6668 } 6669 } 6670 } 6671 6672 SDValue N0 = N->getOperand(0); 6673 if (N0.getOpcode() != ISD::AND) 6674 return SDValue(); 6675 SDValue N1 = N->getOperand(1); 6676 6677 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant. 6678 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() && 6679 DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 6680 APInt SplatUndef; 6681 unsigned SplatBitSize; 6682 bool HasAnyUndefs; 6683 6684 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1)); 6685 APInt SplatBits0; 6686 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize, 6687 HasAnyUndefs) && !HasAnyUndefs) { 6688 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1)); 6689 APInt SplatBits1; 6690 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize, 6691 HasAnyUndefs) && !HasAnyUndefs && 6692 SplatBits0 == ~SplatBits1) { 6693 // Canonicalize the vector type to make instruction selection simpler. 6694 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32; 6695 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT, 6696 N0->getOperand(1), N0->getOperand(0), 6697 N1->getOperand(0)); 6698 return DAG.getNode(ISD::BITCAST, dl, VT, Result); 6699 } 6700 } 6701 } 6702 6703 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when 6704 // reasonable. 6705 6706 // BFI is only available on V6T2+ 6707 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops()) 6708 return SDValue(); 6709 6710 DebugLoc DL = N->getDebugLoc(); 6711 // 1) or (and A, mask), val => ARMbfi A, val, mask 6712 // iff (val & mask) == val 6713 // 6714 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask 6715 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2) 6716 // && mask == ~mask2 6717 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2) 6718 // && ~mask == mask2 6719 // (i.e., copy a bitfield value into another bitfield of the same width) 6720 6721 if (VT != MVT::i32) 6722 return SDValue(); 6723 6724 SDValue N00 = N0.getOperand(0); 6725 6726 // The value and the mask need to be constants so we can verify this is 6727 // actually a bitfield set. If the mask is 0xffff, we can do better 6728 // via a movt instruction, so don't use BFI in that case. 6729 SDValue MaskOp = N0.getOperand(1); 6730 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp); 6731 if (!MaskC) 6732 return SDValue(); 6733 unsigned Mask = MaskC->getZExtValue(); 6734 if (Mask == 0xffff) 6735 return SDValue(); 6736 SDValue Res; 6737 // Case (1): or (and A, mask), val => ARMbfi A, val, mask 6738 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 6739 if (N1C) { 6740 unsigned Val = N1C->getZExtValue(); 6741 if ((Val & ~Mask) != Val) 6742 return SDValue(); 6743 6744 if (ARM::isBitFieldInvertedMask(Mask)) { 6745 Val >>= CountTrailingZeros_32(~Mask); 6746 6747 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, 6748 DAG.getConstant(Val, MVT::i32), 6749 DAG.getConstant(Mask, MVT::i32)); 6750 6751 // Do not add new nodes to DAG combiner worklist. 6752 DCI.CombineTo(N, Res, false); 6753 return SDValue(); 6754 } 6755 } else if (N1.getOpcode() == ISD::AND) { 6756 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask 6757 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 6758 if (!N11C) 6759 return SDValue(); 6760 unsigned Mask2 = N11C->getZExtValue(); 6761 6762 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern 6763 // as is to match. 6764 if (ARM::isBitFieldInvertedMask(Mask) && 6765 (Mask == ~Mask2)) { 6766 // The pack halfword instruction works better for masks that fit it, 6767 // so use that when it's available. 6768 if (Subtarget->hasT2ExtractPack() && 6769 (Mask == 0xffff || Mask == 0xffff0000)) 6770 return SDValue(); 6771 // 2a 6772 unsigned amt = CountTrailingZeros_32(Mask2); 6773 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0), 6774 DAG.getConstant(amt, MVT::i32)); 6775 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res, 6776 DAG.getConstant(Mask, MVT::i32)); 6777 // Do not add new nodes to DAG combiner worklist. 6778 DCI.CombineTo(N, Res, false); 6779 return SDValue(); 6780 } else if (ARM::isBitFieldInvertedMask(~Mask) && 6781 (~Mask == Mask2)) { 6782 // The pack halfword instruction works better for masks that fit it, 6783 // so use that when it's available. 6784 if (Subtarget->hasT2ExtractPack() && 6785 (Mask2 == 0xffff || Mask2 == 0xffff0000)) 6786 return SDValue(); 6787 // 2b 6788 unsigned lsb = CountTrailingZeros_32(Mask); 6789 Res = DAG.getNode(ISD::SRL, DL, VT, N00, 6790 DAG.getConstant(lsb, MVT::i32)); 6791 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res, 6792 DAG.getConstant(Mask2, MVT::i32)); 6793 // Do not add new nodes to DAG combiner worklist. 6794 DCI.CombineTo(N, Res, false); 6795 return SDValue(); 6796 } 6797 } 6798 6799 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) && 6800 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) && 6801 ARM::isBitFieldInvertedMask(~Mask)) { 6802 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask 6803 // where lsb(mask) == #shamt and masked bits of B are known zero. 6804 SDValue ShAmt = N00.getOperand(1); 6805 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 6806 unsigned LSB = CountTrailingZeros_32(Mask); 6807 if (ShAmtC != LSB) 6808 return SDValue(); 6809 6810 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0), 6811 DAG.getConstant(~Mask, MVT::i32)); 6812 6813 // Do not add new nodes to DAG combiner worklist. 6814 DCI.CombineTo(N, Res, false); 6815 } 6816 6817 return SDValue(); 6818} 6819 6820/// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff 6821/// the bits being cleared by the AND are not demanded by the BFI. 6822static SDValue PerformBFICombine(SDNode *N, 6823 TargetLowering::DAGCombinerInfo &DCI) { 6824 SDValue N1 = N->getOperand(1); 6825 if (N1.getOpcode() == ISD::AND) { 6826 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 6827 if (!N11C) 6828 return SDValue(); 6829 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue(); 6830 unsigned LSB = CountTrailingZeros_32(~InvMask); 6831 unsigned Width = (32 - CountLeadingZeros_32(~InvMask)) - LSB; 6832 unsigned Mask = (1 << Width)-1; 6833 unsigned Mask2 = N11C->getZExtValue(); 6834 if ((Mask & (~Mask2)) == 0) 6835 return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0), 6836 N->getOperand(0), N1.getOperand(0), 6837 N->getOperand(2)); 6838 } 6839 return SDValue(); 6840} 6841 6842/// PerformVMOVRRDCombine - Target-specific dag combine xforms for 6843/// ARMISD::VMOVRRD. 6844static SDValue PerformVMOVRRDCombine(SDNode *N, 6845 TargetLowering::DAGCombinerInfo &DCI) { 6846 // vmovrrd(vmovdrr x, y) -> x,y 6847 SDValue InDouble = N->getOperand(0); 6848 if (InDouble.getOpcode() == ARMISD::VMOVDRR) 6849 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1)); 6850 6851 // vmovrrd(load f64) -> (load i32), (load i32) 6852 SDNode *InNode = InDouble.getNode(); 6853 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() && 6854 InNode->getValueType(0) == MVT::f64 && 6855 InNode->getOperand(1).getOpcode() == ISD::FrameIndex && 6856 !cast<LoadSDNode>(InNode)->isVolatile()) { 6857 // TODO: Should this be done for non-FrameIndex operands? 6858 LoadSDNode *LD = cast<LoadSDNode>(InNode); 6859 6860 SelectionDAG &DAG = DCI.DAG; 6861 DebugLoc DL = LD->getDebugLoc(); 6862 SDValue BasePtr = LD->getBasePtr(); 6863 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr, 6864 LD->getPointerInfo(), LD->isVolatile(), 6865 LD->isNonTemporal(), LD->getAlignment()); 6866 6867 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, 6868 DAG.getConstant(4, MVT::i32)); 6869 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr, 6870 LD->getPointerInfo(), LD->isVolatile(), 6871 LD->isNonTemporal(), 6872 std::min(4U, LD->getAlignment() / 2)); 6873 6874 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1)); 6875 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2); 6876 DCI.RemoveFromWorklist(LD); 6877 DAG.DeleteNode(LD); 6878 return Result; 6879 } 6880 6881 return SDValue(); 6882} 6883 6884/// PerformVMOVDRRCombine - Target-specific dag combine xforms for 6885/// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands. 6886static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) { 6887 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X) 6888 SDValue Op0 = N->getOperand(0); 6889 SDValue Op1 = N->getOperand(1); 6890 if (Op0.getOpcode() == ISD::BITCAST) 6891 Op0 = Op0.getOperand(0); 6892 if (Op1.getOpcode() == ISD::BITCAST) 6893 Op1 = Op1.getOperand(0); 6894 if (Op0.getOpcode() == ARMISD::VMOVRRD && 6895 Op0.getNode() == Op1.getNode() && 6896 Op0.getResNo() == 0 && Op1.getResNo() == 1) 6897 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6898 N->getValueType(0), Op0.getOperand(0)); 6899 return SDValue(); 6900} 6901 6902/// PerformSTORECombine - Target-specific dag combine xforms for 6903/// ISD::STORE. 6904static SDValue PerformSTORECombine(SDNode *N, 6905 TargetLowering::DAGCombinerInfo &DCI) { 6906 // Bitcast an i64 store extracted from a vector to f64. 6907 // Otherwise, the i64 value will be legalized to a pair of i32 values. 6908 StoreSDNode *St = cast<StoreSDNode>(N); 6909 SDValue StVal = St->getValue(); 6910 if (!ISD::isNormalStore(St) || St->isVolatile()) 6911 return SDValue(); 6912 6913 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR && 6914 StVal.getNode()->hasOneUse() && !St->isVolatile()) { 6915 SelectionDAG &DAG = DCI.DAG; 6916 DebugLoc DL = St->getDebugLoc(); 6917 SDValue BasePtr = St->getBasePtr(); 6918 SDValue NewST1 = DAG.getStore(St->getChain(), DL, 6919 StVal.getNode()->getOperand(0), BasePtr, 6920 St->getPointerInfo(), St->isVolatile(), 6921 St->isNonTemporal(), St->getAlignment()); 6922 6923 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, 6924 DAG.getConstant(4, MVT::i32)); 6925 return DAG.getStore(NewST1.getValue(0), DL, StVal.getNode()->getOperand(1), 6926 OffsetPtr, St->getPointerInfo(), St->isVolatile(), 6927 St->isNonTemporal(), 6928 std::min(4U, St->getAlignment() / 2)); 6929 } 6930 6931 if (StVal.getValueType() != MVT::i64 || 6932 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 6933 return SDValue(); 6934 6935 SelectionDAG &DAG = DCI.DAG; 6936 DebugLoc dl = StVal.getDebugLoc(); 6937 SDValue IntVec = StVal.getOperand(0); 6938 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, 6939 IntVec.getValueType().getVectorNumElements()); 6940 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec); 6941 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 6942 Vec, StVal.getOperand(1)); 6943 dl = N->getDebugLoc(); 6944 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt); 6945 // Make the DAGCombiner fold the bitcasts. 6946 DCI.AddToWorklist(Vec.getNode()); 6947 DCI.AddToWorklist(ExtElt.getNode()); 6948 DCI.AddToWorklist(V.getNode()); 6949 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(), 6950 St->getPointerInfo(), St->isVolatile(), 6951 St->isNonTemporal(), St->getAlignment(), 6952 St->getTBAAInfo()); 6953} 6954 6955/// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node 6956/// are normal, non-volatile loads. If so, it is profitable to bitcast an 6957/// i64 vector to have f64 elements, since the value can then be loaded 6958/// directly into a VFP register. 6959static bool hasNormalLoadOperand(SDNode *N) { 6960 unsigned NumElts = N->getValueType(0).getVectorNumElements(); 6961 for (unsigned i = 0; i < NumElts; ++i) { 6962 SDNode *Elt = N->getOperand(i).getNode(); 6963 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile()) 6964 return true; 6965 } 6966 return false; 6967} 6968 6969/// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for 6970/// ISD::BUILD_VECTOR. 6971static SDValue PerformBUILD_VECTORCombine(SDNode *N, 6972 TargetLowering::DAGCombinerInfo &DCI){ 6973 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X): 6974 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value 6975 // into a pair of GPRs, which is fine when the value is used as a scalar, 6976 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD. 6977 SelectionDAG &DAG = DCI.DAG; 6978 if (N->getNumOperands() == 2) { 6979 SDValue RV = PerformVMOVDRRCombine(N, DAG); 6980 if (RV.getNode()) 6981 return RV; 6982 } 6983 6984 // Load i64 elements as f64 values so that type legalization does not split 6985 // them up into i32 values. 6986 EVT VT = N->getValueType(0); 6987 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N)) 6988 return SDValue(); 6989 DebugLoc dl = N->getDebugLoc(); 6990 SmallVector<SDValue, 8> Ops; 6991 unsigned NumElts = VT.getVectorNumElements(); 6992 for (unsigned i = 0; i < NumElts; ++i) { 6993 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i)); 6994 Ops.push_back(V); 6995 // Make the DAGCombiner fold the bitcast. 6996 DCI.AddToWorklist(V.getNode()); 6997 } 6998 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts); 6999 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts); 7000 return DAG.getNode(ISD::BITCAST, dl, VT, BV); 7001} 7002 7003/// PerformInsertEltCombine - Target-specific dag combine xforms for 7004/// ISD::INSERT_VECTOR_ELT. 7005static SDValue PerformInsertEltCombine(SDNode *N, 7006 TargetLowering::DAGCombinerInfo &DCI) { 7007 // Bitcast an i64 load inserted into a vector to f64. 7008 // Otherwise, the i64 value will be legalized to a pair of i32 values. 7009 EVT VT = N->getValueType(0); 7010 SDNode *Elt = N->getOperand(1).getNode(); 7011 if (VT.getVectorElementType() != MVT::i64 || 7012 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile()) 7013 return SDValue(); 7014 7015 SelectionDAG &DAG = DCI.DAG; 7016 DebugLoc dl = N->getDebugLoc(); 7017 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, 7018 VT.getVectorNumElements()); 7019 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0)); 7020 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1)); 7021 // Make the DAGCombiner fold the bitcasts. 7022 DCI.AddToWorklist(Vec.getNode()); 7023 DCI.AddToWorklist(V.getNode()); 7024 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT, 7025 Vec, V, N->getOperand(2)); 7026 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt); 7027} 7028 7029/// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for 7030/// ISD::VECTOR_SHUFFLE. 7031static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) { 7032 // The LLVM shufflevector instruction does not require the shuffle mask 7033 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does 7034 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the 7035 // operands do not match the mask length, they are extended by concatenating 7036 // them with undef vectors. That is probably the right thing for other 7037 // targets, but for NEON it is better to concatenate two double-register 7038 // size vector operands into a single quad-register size vector. Do that 7039 // transformation here: 7040 // shuffle(concat(v1, undef), concat(v2, undef)) -> 7041 // shuffle(concat(v1, v2), undef) 7042 SDValue Op0 = N->getOperand(0); 7043 SDValue Op1 = N->getOperand(1); 7044 if (Op0.getOpcode() != ISD::CONCAT_VECTORS || 7045 Op1.getOpcode() != ISD::CONCAT_VECTORS || 7046 Op0.getNumOperands() != 2 || 7047 Op1.getNumOperands() != 2) 7048 return SDValue(); 7049 SDValue Concat0Op1 = Op0.getOperand(1); 7050 SDValue Concat1Op1 = Op1.getOperand(1); 7051 if (Concat0Op1.getOpcode() != ISD::UNDEF || 7052 Concat1Op1.getOpcode() != ISD::UNDEF) 7053 return SDValue(); 7054 // Skip the transformation if any of the types are illegal. 7055 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 7056 EVT VT = N->getValueType(0); 7057 if (!TLI.isTypeLegal(VT) || 7058 !TLI.isTypeLegal(Concat0Op1.getValueType()) || 7059 !TLI.isTypeLegal(Concat1Op1.getValueType())) 7060 return SDValue(); 7061 7062 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, 7063 Op0.getOperand(0), Op1.getOperand(0)); 7064 // Translate the shuffle mask. 7065 SmallVector<int, 16> NewMask; 7066 unsigned NumElts = VT.getVectorNumElements(); 7067 unsigned HalfElts = NumElts/2; 7068 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 7069 for (unsigned n = 0; n < NumElts; ++n) { 7070 int MaskElt = SVN->getMaskElt(n); 7071 int NewElt = -1; 7072 if (MaskElt < (int)HalfElts) 7073 NewElt = MaskElt; 7074 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts)) 7075 NewElt = HalfElts + MaskElt - NumElts; 7076 NewMask.push_back(NewElt); 7077 } 7078 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat, 7079 DAG.getUNDEF(VT), NewMask.data()); 7080} 7081 7082/// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and 7083/// NEON load/store intrinsics to merge base address updates. 7084static SDValue CombineBaseUpdate(SDNode *N, 7085 TargetLowering::DAGCombinerInfo &DCI) { 7086 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 7087 return SDValue(); 7088 7089 SelectionDAG &DAG = DCI.DAG; 7090 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID || 7091 N->getOpcode() == ISD::INTRINSIC_W_CHAIN); 7092 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1); 7093 SDValue Addr = N->getOperand(AddrOpIdx); 7094 7095 // Search for a use of the address operand that is an increment. 7096 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), 7097 UE = Addr.getNode()->use_end(); UI != UE; ++UI) { 7098 SDNode *User = *UI; 7099 if (User->getOpcode() != ISD::ADD || 7100 UI.getUse().getResNo() != Addr.getResNo()) 7101 continue; 7102 7103 // Check that the add is independent of the load/store. Otherwise, folding 7104 // it would create a cycle. 7105 if (User->isPredecessorOf(N) || N->isPredecessorOf(User)) 7106 continue; 7107 7108 // Find the new opcode for the updating load/store. 7109 bool isLoad = true; 7110 bool isLaneOp = false; 7111 unsigned NewOpc = 0; 7112 unsigned NumVecs = 0; 7113 if (isIntrinsic) { 7114 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 7115 switch (IntNo) { 7116 default: assert(0 && "unexpected intrinsic for Neon base update"); 7117 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD; 7118 NumVecs = 1; break; 7119 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD; 7120 NumVecs = 2; break; 7121 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD; 7122 NumVecs = 3; break; 7123 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD; 7124 NumVecs = 4; break; 7125 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD; 7126 NumVecs = 2; isLaneOp = true; break; 7127 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD; 7128 NumVecs = 3; isLaneOp = true; break; 7129 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD; 7130 NumVecs = 4; isLaneOp = true; break; 7131 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD; 7132 NumVecs = 1; isLoad = false; break; 7133 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD; 7134 NumVecs = 2; isLoad = false; break; 7135 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD; 7136 NumVecs = 3; isLoad = false; break; 7137 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD; 7138 NumVecs = 4; isLoad = false; break; 7139 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD; 7140 NumVecs = 2; isLoad = false; isLaneOp = true; break; 7141 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD; 7142 NumVecs = 3; isLoad = false; isLaneOp = true; break; 7143 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD; 7144 NumVecs = 4; isLoad = false; isLaneOp = true; break; 7145 } 7146 } else { 7147 isLaneOp = true; 7148 switch (N->getOpcode()) { 7149 default: assert(0 && "unexpected opcode for Neon base update"); 7150 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break; 7151 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break; 7152 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break; 7153 } 7154 } 7155 7156 // Find the size of memory referenced by the load/store. 7157 EVT VecTy; 7158 if (isLoad) 7159 VecTy = N->getValueType(0); 7160 else 7161 VecTy = N->getOperand(AddrOpIdx+1).getValueType(); 7162 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8; 7163 if (isLaneOp) 7164 NumBytes /= VecTy.getVectorNumElements(); 7165 7166 // If the increment is a constant, it must match the memory ref size. 7167 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0); 7168 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) { 7169 uint64_t IncVal = CInc->getZExtValue(); 7170 if (IncVal != NumBytes) 7171 continue; 7172 } else if (NumBytes >= 3 * 16) { 7173 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two 7174 // separate instructions that make it harder to use a non-constant update. 7175 continue; 7176 } 7177 7178 // Create the new updating load/store node. 7179 EVT Tys[6]; 7180 unsigned NumResultVecs = (isLoad ? NumVecs : 0); 7181 unsigned n; 7182 for (n = 0; n < NumResultVecs; ++n) 7183 Tys[n] = VecTy; 7184 Tys[n++] = MVT::i32; 7185 Tys[n] = MVT::Other; 7186 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs+2); 7187 SmallVector<SDValue, 8> Ops; 7188 Ops.push_back(N->getOperand(0)); // incoming chain 7189 Ops.push_back(N->getOperand(AddrOpIdx)); 7190 Ops.push_back(Inc); 7191 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) { 7192 Ops.push_back(N->getOperand(i)); 7193 } 7194 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N); 7195 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, N->getDebugLoc(), SDTys, 7196 Ops.data(), Ops.size(), 7197 MemInt->getMemoryVT(), 7198 MemInt->getMemOperand()); 7199 7200 // Update the uses. 7201 std::vector<SDValue> NewResults; 7202 for (unsigned i = 0; i < NumResultVecs; ++i) { 7203 NewResults.push_back(SDValue(UpdN.getNode(), i)); 7204 } 7205 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain 7206 DCI.CombineTo(N, NewResults); 7207 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs)); 7208 7209 break; 7210 } 7211 return SDValue(); 7212} 7213 7214/// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a 7215/// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic 7216/// are also VDUPLANEs. If so, combine them to a vldN-dup operation and 7217/// return true. 7218static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { 7219 SelectionDAG &DAG = DCI.DAG; 7220 EVT VT = N->getValueType(0); 7221 // vldN-dup instructions only support 64-bit vectors for N > 1. 7222 if (!VT.is64BitVector()) 7223 return false; 7224 7225 // Check if the VDUPLANE operand is a vldN-dup intrinsic. 7226 SDNode *VLD = N->getOperand(0).getNode(); 7227 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN) 7228 return false; 7229 unsigned NumVecs = 0; 7230 unsigned NewOpc = 0; 7231 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue(); 7232 if (IntNo == Intrinsic::arm_neon_vld2lane) { 7233 NumVecs = 2; 7234 NewOpc = ARMISD::VLD2DUP; 7235 } else if (IntNo == Intrinsic::arm_neon_vld3lane) { 7236 NumVecs = 3; 7237 NewOpc = ARMISD::VLD3DUP; 7238 } else if (IntNo == Intrinsic::arm_neon_vld4lane) { 7239 NumVecs = 4; 7240 NewOpc = ARMISD::VLD4DUP; 7241 } else { 7242 return false; 7243 } 7244 7245 // First check that all the vldN-lane uses are VDUPLANEs and that the lane 7246 // numbers match the load. 7247 unsigned VLDLaneNo = 7248 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue(); 7249 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); 7250 UI != UE; ++UI) { 7251 // Ignore uses of the chain result. 7252 if (UI.getUse().getResNo() == NumVecs) 7253 continue; 7254 SDNode *User = *UI; 7255 if (User->getOpcode() != ARMISD::VDUPLANE || 7256 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue()) 7257 return false; 7258 } 7259 7260 // Create the vldN-dup node. 7261 EVT Tys[5]; 7262 unsigned n; 7263 for (n = 0; n < NumVecs; ++n) 7264 Tys[n] = VT; 7265 Tys[n] = MVT::Other; 7266 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1); 7267 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) }; 7268 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD); 7269 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys, 7270 Ops, 2, VLDMemInt->getMemoryVT(), 7271 VLDMemInt->getMemOperand()); 7272 7273 // Update the uses. 7274 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end(); 7275 UI != UE; ++UI) { 7276 unsigned ResNo = UI.getUse().getResNo(); 7277 // Ignore uses of the chain result. 7278 if (ResNo == NumVecs) 7279 continue; 7280 SDNode *User = *UI; 7281 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo)); 7282 } 7283 7284 // Now the vldN-lane intrinsic is dead except for its chain result. 7285 // Update uses of the chain. 7286 std::vector<SDValue> VLDDupResults; 7287 for (unsigned n = 0; n < NumVecs; ++n) 7288 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n)); 7289 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs)); 7290 DCI.CombineTo(VLD, VLDDupResults); 7291 7292 return true; 7293} 7294 7295/// PerformVDUPLANECombine - Target-specific dag combine xforms for 7296/// ARMISD::VDUPLANE. 7297static SDValue PerformVDUPLANECombine(SDNode *N, 7298 TargetLowering::DAGCombinerInfo &DCI) { 7299 SDValue Op = N->getOperand(0); 7300 7301 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses 7302 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation. 7303 if (CombineVLDDUP(N, DCI)) 7304 return SDValue(N, 0); 7305 7306 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is 7307 // redundant. Ignore bit_converts for now; element sizes are checked below. 7308 while (Op.getOpcode() == ISD::BITCAST) 7309 Op = Op.getOperand(0); 7310 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM) 7311 return SDValue(); 7312 7313 // Make sure the VMOV element size is not bigger than the VDUPLANE elements. 7314 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits(); 7315 // The canonical VMOV for a zero vector uses a 32-bit element size. 7316 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 7317 unsigned EltBits; 7318 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0) 7319 EltSize = 8; 7320 EVT VT = N->getValueType(0); 7321 if (EltSize > VT.getVectorElementType().getSizeInBits()) 7322 return SDValue(); 7323 7324 return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 7325} 7326 7327// isConstVecPow2 - Return true if each vector element is a power of 2, all 7328// elements are the same constant, C, and Log2(C) ranges from 1 to 32. 7329static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C) 7330{ 7331 integerPart cN; 7332 integerPart c0 = 0; 7333 for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements(); 7334 I != E; I++) { 7335 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I)); 7336 if (!C) 7337 return false; 7338 7339 bool isExact; 7340 APFloat APF = C->getValueAPF(); 7341 if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact) 7342 != APFloat::opOK || !isExact) 7343 return false; 7344 7345 c0 = (I == 0) ? cN : c0; 7346 if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32) 7347 return false; 7348 } 7349 C = c0; 7350 return true; 7351} 7352 7353/// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD) 7354/// can replace combinations of VMUL and VCVT (floating-point to integer) 7355/// when the VMUL has a constant operand that is a power of 2. 7356/// 7357/// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): 7358/// vmul.f32 d16, d17, d16 7359/// vcvt.s32.f32 d16, d16 7360/// becomes: 7361/// vcvt.s32.f32 d16, d16, #3 7362static SDValue PerformVCVTCombine(SDNode *N, 7363 TargetLowering::DAGCombinerInfo &DCI, 7364 const ARMSubtarget *Subtarget) { 7365 SelectionDAG &DAG = DCI.DAG; 7366 SDValue Op = N->getOperand(0); 7367 7368 if (!Subtarget->hasNEON() || !Op.getValueType().isVector() || 7369 Op.getOpcode() != ISD::FMUL) 7370 return SDValue(); 7371 7372 uint64_t C; 7373 SDValue N0 = Op->getOperand(0); 7374 SDValue ConstVec = Op->getOperand(1); 7375 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT; 7376 7377 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR || 7378 !isConstVecPow2(ConstVec, isSigned, C)) 7379 return SDValue(); 7380 7381 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs : 7382 Intrinsic::arm_neon_vcvtfp2fxu; 7383 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), 7384 N->getValueType(0), 7385 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0, 7386 DAG.getConstant(Log2_64(C), MVT::i32)); 7387} 7388 7389/// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD) 7390/// can replace combinations of VCVT (integer to floating-point) and VDIV 7391/// when the VDIV has a constant operand that is a power of 2. 7392/// 7393/// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): 7394/// vcvt.f32.s32 d16, d16 7395/// vdiv.f32 d16, d17, d16 7396/// becomes: 7397/// vcvt.f32.s32 d16, d16, #3 7398static SDValue PerformVDIVCombine(SDNode *N, 7399 TargetLowering::DAGCombinerInfo &DCI, 7400 const ARMSubtarget *Subtarget) { 7401 SelectionDAG &DAG = DCI.DAG; 7402 SDValue Op = N->getOperand(0); 7403 unsigned OpOpcode = Op.getNode()->getOpcode(); 7404 7405 if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() || 7406 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP)) 7407 return SDValue(); 7408 7409 uint64_t C; 7410 SDValue ConstVec = N->getOperand(1); 7411 bool isSigned = OpOpcode == ISD::SINT_TO_FP; 7412 7413 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR || 7414 !isConstVecPow2(ConstVec, isSigned, C)) 7415 return SDValue(); 7416 7417 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp : 7418 Intrinsic::arm_neon_vcvtfxu2fp; 7419 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), 7420 Op.getValueType(), 7421 DAG.getConstant(IntrinsicOpcode, MVT::i32), 7422 Op.getOperand(0), DAG.getConstant(Log2_64(C), MVT::i32)); 7423} 7424 7425/// Getvshiftimm - Check if this is a valid build_vector for the immediate 7426/// operand of a vector shift operation, where all the elements of the 7427/// build_vector must have the same constant integer value. 7428static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) { 7429 // Ignore bit_converts. 7430 while (Op.getOpcode() == ISD::BITCAST) 7431 Op = Op.getOperand(0); 7432 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); 7433 APInt SplatBits, SplatUndef; 7434 unsigned SplatBitSize; 7435 bool HasAnyUndefs; 7436 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, 7437 HasAnyUndefs, ElementBits) || 7438 SplatBitSize > ElementBits) 7439 return false; 7440 Cnt = SplatBits.getSExtValue(); 7441 return true; 7442} 7443 7444/// isVShiftLImm - Check if this is a valid build_vector for the immediate 7445/// operand of a vector shift left operation. That value must be in the range: 7446/// 0 <= Value < ElementBits for a left shift; or 7447/// 0 <= Value <= ElementBits for a long left shift. 7448static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) { 7449 assert(VT.isVector() && "vector shift count is not a vector type"); 7450 unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); 7451 if (! getVShiftImm(Op, ElementBits, Cnt)) 7452 return false; 7453 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits); 7454} 7455 7456/// isVShiftRImm - Check if this is a valid build_vector for the immediate 7457/// operand of a vector shift right operation. For a shift opcode, the value 7458/// is positive, but for an intrinsic the value count must be negative. The 7459/// absolute value must be in the range: 7460/// 1 <= |Value| <= ElementBits for a right shift; or 7461/// 1 <= |Value| <= ElementBits/2 for a narrow right shift. 7462static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic, 7463 int64_t &Cnt) { 7464 assert(VT.isVector() && "vector shift count is not a vector type"); 7465 unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); 7466 if (! getVShiftImm(Op, ElementBits, Cnt)) 7467 return false; 7468 if (isIntrinsic) 7469 Cnt = -Cnt; 7470 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits)); 7471} 7472 7473/// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics. 7474static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { 7475 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); 7476 switch (IntNo) { 7477 default: 7478 // Don't do anything for most intrinsics. 7479 break; 7480 7481 // Vector shifts: check for immediate versions and lower them. 7482 // Note: This is done during DAG combining instead of DAG legalizing because 7483 // the build_vectors for 64-bit vector element shift counts are generally 7484 // not legal, and it is hard to see their values after they get legalized to 7485 // loads from a constant pool. 7486 case Intrinsic::arm_neon_vshifts: 7487 case Intrinsic::arm_neon_vshiftu: 7488 case Intrinsic::arm_neon_vshiftls: 7489 case Intrinsic::arm_neon_vshiftlu: 7490 case Intrinsic::arm_neon_vshiftn: 7491 case Intrinsic::arm_neon_vrshifts: 7492 case Intrinsic::arm_neon_vrshiftu: 7493 case Intrinsic::arm_neon_vrshiftn: 7494 case Intrinsic::arm_neon_vqshifts: 7495 case Intrinsic::arm_neon_vqshiftu: 7496 case Intrinsic::arm_neon_vqshiftsu: 7497 case Intrinsic::arm_neon_vqshiftns: 7498 case Intrinsic::arm_neon_vqshiftnu: 7499 case Intrinsic::arm_neon_vqshiftnsu: 7500 case Intrinsic::arm_neon_vqrshiftns: 7501 case Intrinsic::arm_neon_vqrshiftnu: 7502 case Intrinsic::arm_neon_vqrshiftnsu: { 7503 EVT VT = N->getOperand(1).getValueType(); 7504 int64_t Cnt; 7505 unsigned VShiftOpc = 0; 7506 7507 switch (IntNo) { 7508 case Intrinsic::arm_neon_vshifts: 7509 case Intrinsic::arm_neon_vshiftu: 7510 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) { 7511 VShiftOpc = ARMISD::VSHL; 7512 break; 7513 } 7514 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) { 7515 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ? 7516 ARMISD::VSHRs : ARMISD::VSHRu); 7517 break; 7518 } 7519 return SDValue(); 7520 7521 case Intrinsic::arm_neon_vshiftls: 7522 case Intrinsic::arm_neon_vshiftlu: 7523 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt)) 7524 break; 7525 llvm_unreachable("invalid shift count for vshll intrinsic"); 7526 7527 case Intrinsic::arm_neon_vrshifts: 7528 case Intrinsic::arm_neon_vrshiftu: 7529 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) 7530 break; 7531 return SDValue(); 7532 7533 case Intrinsic::arm_neon_vqshifts: 7534 case Intrinsic::arm_neon_vqshiftu: 7535 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) 7536 break; 7537 return SDValue(); 7538 7539 case Intrinsic::arm_neon_vqshiftsu: 7540 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) 7541 break; 7542 llvm_unreachable("invalid shift count for vqshlu intrinsic"); 7543 7544 case Intrinsic::arm_neon_vshiftn: 7545 case Intrinsic::arm_neon_vrshiftn: 7546 case Intrinsic::arm_neon_vqshiftns: 7547 case Intrinsic::arm_neon_vqshiftnu: 7548 case Intrinsic::arm_neon_vqshiftnsu: 7549 case Intrinsic::arm_neon_vqrshiftns: 7550 case Intrinsic::arm_neon_vqrshiftnu: 7551 case Intrinsic::arm_neon_vqrshiftnsu: 7552 // Narrowing shifts require an immediate right shift. 7553 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt)) 7554 break; 7555 llvm_unreachable("invalid shift count for narrowing vector shift " 7556 "intrinsic"); 7557 7558 default: 7559 llvm_unreachable("unhandled vector shift"); 7560 } 7561 7562 switch (IntNo) { 7563 case Intrinsic::arm_neon_vshifts: 7564 case Intrinsic::arm_neon_vshiftu: 7565 // Opcode already set above. 7566 break; 7567 case Intrinsic::arm_neon_vshiftls: 7568 case Intrinsic::arm_neon_vshiftlu: 7569 if (Cnt == VT.getVectorElementType().getSizeInBits()) 7570 VShiftOpc = ARMISD::VSHLLi; 7571 else 7572 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ? 7573 ARMISD::VSHLLs : ARMISD::VSHLLu); 7574 break; 7575 case Intrinsic::arm_neon_vshiftn: 7576 VShiftOpc = ARMISD::VSHRN; break; 7577 case Intrinsic::arm_neon_vrshifts: 7578 VShiftOpc = ARMISD::VRSHRs; break; 7579 case Intrinsic::arm_neon_vrshiftu: 7580 VShiftOpc = ARMISD::VRSHRu; break; 7581 case Intrinsic::arm_neon_vrshiftn: 7582 VShiftOpc = ARMISD::VRSHRN; break; 7583 case Intrinsic::arm_neon_vqshifts: 7584 VShiftOpc = ARMISD::VQSHLs; break; 7585 case Intrinsic::arm_neon_vqshiftu: 7586 VShiftOpc = ARMISD::VQSHLu; break; 7587 case Intrinsic::arm_neon_vqshiftsu: 7588 VShiftOpc = ARMISD::VQSHLsu; break; 7589 case Intrinsic::arm_neon_vqshiftns: 7590 VShiftOpc = ARMISD::VQSHRNs; break; 7591 case Intrinsic::arm_neon_vqshiftnu: 7592 VShiftOpc = ARMISD::VQSHRNu; break; 7593 case Intrinsic::arm_neon_vqshiftnsu: 7594 VShiftOpc = ARMISD::VQSHRNsu; break; 7595 case Intrinsic::arm_neon_vqrshiftns: 7596 VShiftOpc = ARMISD::VQRSHRNs; break; 7597 case Intrinsic::arm_neon_vqrshiftnu: 7598 VShiftOpc = ARMISD::VQRSHRNu; break; 7599 case Intrinsic::arm_neon_vqrshiftnsu: 7600 VShiftOpc = ARMISD::VQRSHRNsu; break; 7601 } 7602 7603 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), 7604 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32)); 7605 } 7606 7607 case Intrinsic::arm_neon_vshiftins: { 7608 EVT VT = N->getOperand(1).getValueType(); 7609 int64_t Cnt; 7610 unsigned VShiftOpc = 0; 7611 7612 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt)) 7613 VShiftOpc = ARMISD::VSLI; 7614 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt)) 7615 VShiftOpc = ARMISD::VSRI; 7616 else { 7617 llvm_unreachable("invalid shift count for vsli/vsri intrinsic"); 7618 } 7619 7620 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), 7621 N->getOperand(1), N->getOperand(2), 7622 DAG.getConstant(Cnt, MVT::i32)); 7623 } 7624 7625 case Intrinsic::arm_neon_vqrshifts: 7626 case Intrinsic::arm_neon_vqrshiftu: 7627 // No immediate versions of these to check for. 7628 break; 7629 } 7630 7631 return SDValue(); 7632} 7633 7634/// PerformShiftCombine - Checks for immediate versions of vector shifts and 7635/// lowers them. As with the vector shift intrinsics, this is done during DAG 7636/// combining instead of DAG legalizing because the build_vectors for 64-bit 7637/// vector element shift counts are generally not legal, and it is hard to see 7638/// their values after they get legalized to loads from a constant pool. 7639static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG, 7640 const ARMSubtarget *ST) { 7641 EVT VT = N->getValueType(0); 7642 7643 // Nothing to be done for scalar shifts. 7644 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 7645 if (!VT.isVector() || !TLI.isTypeLegal(VT)) 7646 return SDValue(); 7647 7648 assert(ST->hasNEON() && "unexpected vector shift"); 7649 int64_t Cnt; 7650 7651 switch (N->getOpcode()) { 7652 default: llvm_unreachable("unexpected shift opcode"); 7653 7654 case ISD::SHL: 7655 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt)) 7656 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0), 7657 DAG.getConstant(Cnt, MVT::i32)); 7658 break; 7659 7660 case ISD::SRA: 7661 case ISD::SRL: 7662 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) { 7663 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ? 7664 ARMISD::VSHRs : ARMISD::VSHRu); 7665 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0), 7666 DAG.getConstant(Cnt, MVT::i32)); 7667 } 7668 } 7669 return SDValue(); 7670} 7671 7672/// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND, 7673/// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND. 7674static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG, 7675 const ARMSubtarget *ST) { 7676 SDValue N0 = N->getOperand(0); 7677 7678 // Check for sign- and zero-extensions of vector extract operations of 8- 7679 // and 16-bit vector elements. NEON supports these directly. They are 7680 // handled during DAG combining because type legalization will promote them 7681 // to 32-bit types and it is messy to recognize the operations after that. 7682 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { 7683 SDValue Vec = N0.getOperand(0); 7684 SDValue Lane = N0.getOperand(1); 7685 EVT VT = N->getValueType(0); 7686 EVT EltVT = N0.getValueType(); 7687 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 7688 7689 if (VT == MVT::i32 && 7690 (EltVT == MVT::i8 || EltVT == MVT::i16) && 7691 TLI.isTypeLegal(Vec.getValueType()) && 7692 isa<ConstantSDNode>(Lane)) { 7693 7694 unsigned Opc = 0; 7695 switch (N->getOpcode()) { 7696 default: llvm_unreachable("unexpected opcode"); 7697 case ISD::SIGN_EXTEND: 7698 Opc = ARMISD::VGETLANEs; 7699 break; 7700 case ISD::ZERO_EXTEND: 7701 case ISD::ANY_EXTEND: 7702 Opc = ARMISD::VGETLANEu; 7703 break; 7704 } 7705 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane); 7706 } 7707 } 7708 7709 return SDValue(); 7710} 7711 7712/// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC 7713/// to match f32 max/min patterns to use NEON vmax/vmin instructions. 7714static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG, 7715 const ARMSubtarget *ST) { 7716 // If the target supports NEON, try to use vmax/vmin instructions for f32 7717 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set, 7718 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is 7719 // a NaN; only do the transformation when it matches that behavior. 7720 7721 // For now only do this when using NEON for FP operations; if using VFP, it 7722 // is not obvious that the benefit outweighs the cost of switching to the 7723 // NEON pipeline. 7724 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() || 7725 N->getValueType(0) != MVT::f32) 7726 return SDValue(); 7727 7728 SDValue CondLHS = N->getOperand(0); 7729 SDValue CondRHS = N->getOperand(1); 7730 SDValue LHS = N->getOperand(2); 7731 SDValue RHS = N->getOperand(3); 7732 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get(); 7733 7734 unsigned Opcode = 0; 7735 bool IsReversed; 7736 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) { 7737 IsReversed = false; // x CC y ? x : y 7738 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) { 7739 IsReversed = true ; // x CC y ? y : x 7740 } else { 7741 return SDValue(); 7742 } 7743 7744 bool IsUnordered; 7745 switch (CC) { 7746 default: break; 7747 case ISD::SETOLT: 7748 case ISD::SETOLE: 7749 case ISD::SETLT: 7750 case ISD::SETLE: 7751 case ISD::SETULT: 7752 case ISD::SETULE: 7753 // If LHS is NaN, an ordered comparison will be false and the result will 7754 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS 7755 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN. 7756 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE); 7757 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS)) 7758 break; 7759 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin 7760 // will return -0, so vmin can only be used for unsafe math or if one of 7761 // the operands is known to be nonzero. 7762 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) && 7763 !UnsafeFPMath && 7764 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 7765 break; 7766 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN; 7767 break; 7768 7769 case ISD::SETOGT: 7770 case ISD::SETOGE: 7771 case ISD::SETGT: 7772 case ISD::SETGE: 7773 case ISD::SETUGT: 7774 case ISD::SETUGE: 7775 // If LHS is NaN, an ordered comparison will be false and the result will 7776 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS 7777 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN. 7778 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE); 7779 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS)) 7780 break; 7781 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax 7782 // will return +0, so vmax can only be used for unsafe math or if one of 7783 // the operands is known to be nonzero. 7784 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) && 7785 !UnsafeFPMath && 7786 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 7787 break; 7788 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX; 7789 break; 7790 } 7791 7792 if (!Opcode) 7793 return SDValue(); 7794 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS); 7795} 7796 7797/// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV. 7798SDValue 7799ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const { 7800 SDValue Cmp = N->getOperand(4); 7801 if (Cmp.getOpcode() != ARMISD::CMPZ) 7802 // Only looking at EQ and NE cases. 7803 return SDValue(); 7804 7805 EVT VT = N->getValueType(0); 7806 DebugLoc dl = N->getDebugLoc(); 7807 SDValue LHS = Cmp.getOperand(0); 7808 SDValue RHS = Cmp.getOperand(1); 7809 SDValue FalseVal = N->getOperand(0); 7810 SDValue TrueVal = N->getOperand(1); 7811 SDValue ARMcc = N->getOperand(2); 7812 ARMCC::CondCodes CC = 7813 (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue(); 7814 7815 // Simplify 7816 // mov r1, r0 7817 // cmp r1, x 7818 // mov r0, y 7819 // moveq r0, x 7820 // to 7821 // cmp r0, x 7822 // movne r0, y 7823 // 7824 // mov r1, r0 7825 // cmp r1, x 7826 // mov r0, x 7827 // movne r0, y 7828 // to 7829 // cmp r0, x 7830 // movne r0, y 7831 /// FIXME: Turn this into a target neutral optimization? 7832 SDValue Res; 7833 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) { 7834 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc, 7835 N->getOperand(3), Cmp); 7836 } else if (CC == ARMCC::EQ && TrueVal == RHS) { 7837 SDValue ARMcc; 7838 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl); 7839 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc, 7840 N->getOperand(3), NewCmp); 7841 } 7842 7843 if (Res.getNode()) { 7844 APInt KnownZero, KnownOne; 7845 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 7846 DAG.ComputeMaskedBits(SDValue(N,0), Mask, KnownZero, KnownOne); 7847 // Capture demanded bits information that would be otherwise lost. 7848 if (KnownZero == 0xfffffffe) 7849 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, 7850 DAG.getValueType(MVT::i1)); 7851 else if (KnownZero == 0xffffff00) 7852 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, 7853 DAG.getValueType(MVT::i8)); 7854 else if (KnownZero == 0xffff0000) 7855 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, 7856 DAG.getValueType(MVT::i16)); 7857 } 7858 7859 return Res; 7860} 7861 7862SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N, 7863 DAGCombinerInfo &DCI) const { 7864 switch (N->getOpcode()) { 7865 default: break; 7866 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget); 7867 case ISD::SUB: return PerformSUBCombine(N, DCI); 7868 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget); 7869 case ISD::OR: return PerformORCombine(N, DCI, Subtarget); 7870 case ISD::AND: return PerformANDCombine(N, DCI); 7871 case ARMISD::BFI: return PerformBFICombine(N, DCI); 7872 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI); 7873 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG); 7874 case ISD::STORE: return PerformSTORECombine(N, DCI); 7875 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI); 7876 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI); 7877 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG); 7878 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI); 7879 case ISD::FP_TO_SINT: 7880 case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget); 7881 case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget); 7882 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG); 7883 case ISD::SHL: 7884 case ISD::SRA: 7885 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget); 7886 case ISD::SIGN_EXTEND: 7887 case ISD::ZERO_EXTEND: 7888 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget); 7889 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget); 7890 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG); 7891 case ARMISD::VLD2DUP: 7892 case ARMISD::VLD3DUP: 7893 case ARMISD::VLD4DUP: 7894 return CombineBaseUpdate(N, DCI); 7895 case ISD::INTRINSIC_VOID: 7896 case ISD::INTRINSIC_W_CHAIN: 7897 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) { 7898 case Intrinsic::arm_neon_vld1: 7899 case Intrinsic::arm_neon_vld2: 7900 case Intrinsic::arm_neon_vld3: 7901 case Intrinsic::arm_neon_vld4: 7902 case Intrinsic::arm_neon_vld2lane: 7903 case Intrinsic::arm_neon_vld3lane: 7904 case Intrinsic::arm_neon_vld4lane: 7905 case Intrinsic::arm_neon_vst1: 7906 case Intrinsic::arm_neon_vst2: 7907 case Intrinsic::arm_neon_vst3: 7908 case Intrinsic::arm_neon_vst4: 7909 case Intrinsic::arm_neon_vst2lane: 7910 case Intrinsic::arm_neon_vst3lane: 7911 case Intrinsic::arm_neon_vst4lane: 7912 return CombineBaseUpdate(N, DCI); 7913 default: break; 7914 } 7915 break; 7916 } 7917 return SDValue(); 7918} 7919 7920bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc, 7921 EVT VT) const { 7922 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE); 7923} 7924 7925bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { 7926 if (!Subtarget->allowsUnalignedMem()) 7927 return false; 7928 7929 switch (VT.getSimpleVT().SimpleTy) { 7930 default: 7931 return false; 7932 case MVT::i8: 7933 case MVT::i16: 7934 case MVT::i32: 7935 return true; 7936 // FIXME: VLD1 etc with standard alignment is legal. 7937 } 7938} 7939 7940static bool isLegalT1AddressImmediate(int64_t V, EVT VT) { 7941 if (V < 0) 7942 return false; 7943 7944 unsigned Scale = 1; 7945 switch (VT.getSimpleVT().SimpleTy) { 7946 default: return false; 7947 case MVT::i1: 7948 case MVT::i8: 7949 // Scale == 1; 7950 break; 7951 case MVT::i16: 7952 // Scale == 2; 7953 Scale = 2; 7954 break; 7955 case MVT::i32: 7956 // Scale == 4; 7957 Scale = 4; 7958 break; 7959 } 7960 7961 if ((V & (Scale - 1)) != 0) 7962 return false; 7963 V /= Scale; 7964 return V == (V & ((1LL << 5) - 1)); 7965} 7966 7967static bool isLegalT2AddressImmediate(int64_t V, EVT VT, 7968 const ARMSubtarget *Subtarget) { 7969 bool isNeg = false; 7970 if (V < 0) { 7971 isNeg = true; 7972 V = - V; 7973 } 7974 7975 switch (VT.getSimpleVT().SimpleTy) { 7976 default: return false; 7977 case MVT::i1: 7978 case MVT::i8: 7979 case MVT::i16: 7980 case MVT::i32: 7981 // + imm12 or - imm8 7982 if (isNeg) 7983 return V == (V & ((1LL << 8) - 1)); 7984 return V == (V & ((1LL << 12) - 1)); 7985 case MVT::f32: 7986 case MVT::f64: 7987 // Same as ARM mode. FIXME: NEON? 7988 if (!Subtarget->hasVFP2()) 7989 return false; 7990 if ((V & 3) != 0) 7991 return false; 7992 V >>= 2; 7993 return V == (V & ((1LL << 8) - 1)); 7994 } 7995} 7996 7997/// isLegalAddressImmediate - Return true if the integer value can be used 7998/// as the offset of the target addressing mode for load / store of the 7999/// given type. 8000static bool isLegalAddressImmediate(int64_t V, EVT VT, 8001 const ARMSubtarget *Subtarget) { 8002 if (V == 0) 8003 return true; 8004 8005 if (!VT.isSimple()) 8006 return false; 8007 8008 if (Subtarget->isThumb1Only()) 8009 return isLegalT1AddressImmediate(V, VT); 8010 else if (Subtarget->isThumb2()) 8011 return isLegalT2AddressImmediate(V, VT, Subtarget); 8012 8013 // ARM mode. 8014 if (V < 0) 8015 V = - V; 8016 switch (VT.getSimpleVT().SimpleTy) { 8017 default: return false; 8018 case MVT::i1: 8019 case MVT::i8: 8020 case MVT::i32: 8021 // +- imm12 8022 return V == (V & ((1LL << 12) - 1)); 8023 case MVT::i16: 8024 // +- imm8 8025 return V == (V & ((1LL << 8) - 1)); 8026 case MVT::f32: 8027 case MVT::f64: 8028 if (!Subtarget->hasVFP2()) // FIXME: NEON? 8029 return false; 8030 if ((V & 3) != 0) 8031 return false; 8032 V >>= 2; 8033 return V == (V & ((1LL << 8) - 1)); 8034 } 8035} 8036 8037bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM, 8038 EVT VT) const { 8039 int Scale = AM.Scale; 8040 if (Scale < 0) 8041 return false; 8042 8043 switch (VT.getSimpleVT().SimpleTy) { 8044 default: return false; 8045 case MVT::i1: 8046 case MVT::i8: 8047 case MVT::i16: 8048 case MVT::i32: 8049 if (Scale == 1) 8050 return true; 8051 // r + r << imm 8052 Scale = Scale & ~1; 8053 return Scale == 2 || Scale == 4 || Scale == 8; 8054 case MVT::i64: 8055 // r + r 8056 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 8057 return true; 8058 return false; 8059 case MVT::isVoid: 8060 // Note, we allow "void" uses (basically, uses that aren't loads or 8061 // stores), because arm allows folding a scale into many arithmetic 8062 // operations. This should be made more precise and revisited later. 8063 8064 // Allow r << imm, but the imm has to be a multiple of two. 8065 if (Scale & 1) return false; 8066 return isPowerOf2_32(Scale); 8067 } 8068} 8069 8070/// isLegalAddressingMode - Return true if the addressing mode represented 8071/// by AM is legal for this target, for a load/store of the specified type. 8072bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM, 8073 Type *Ty) const { 8074 EVT VT = getValueType(Ty, true); 8075 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget)) 8076 return false; 8077 8078 // Can never fold addr of global into load/store. 8079 if (AM.BaseGV) 8080 return false; 8081 8082 switch (AM.Scale) { 8083 case 0: // no scale reg, must be "r+i" or "r", or "i". 8084 break; 8085 case 1: 8086 if (Subtarget->isThumb1Only()) 8087 return false; 8088 // FALL THROUGH. 8089 default: 8090 // ARM doesn't support any R+R*scale+imm addr modes. 8091 if (AM.BaseOffs) 8092 return false; 8093 8094 if (!VT.isSimple()) 8095 return false; 8096 8097 if (Subtarget->isThumb2()) 8098 return isLegalT2ScaledAddressingMode(AM, VT); 8099 8100 int Scale = AM.Scale; 8101 switch (VT.getSimpleVT().SimpleTy) { 8102 default: return false; 8103 case MVT::i1: 8104 case MVT::i8: 8105 case MVT::i32: 8106 if (Scale < 0) Scale = -Scale; 8107 if (Scale == 1) 8108 return true; 8109 // r + r << imm 8110 return isPowerOf2_32(Scale & ~1); 8111 case MVT::i16: 8112 case MVT::i64: 8113 // r + r 8114 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 8115 return true; 8116 return false; 8117 8118 case MVT::isVoid: 8119 // Note, we allow "void" uses (basically, uses that aren't loads or 8120 // stores), because arm allows folding a scale into many arithmetic 8121 // operations. This should be made more precise and revisited later. 8122 8123 // Allow r << imm, but the imm has to be a multiple of two. 8124 if (Scale & 1) return false; 8125 return isPowerOf2_32(Scale); 8126 } 8127 break; 8128 } 8129 return true; 8130} 8131 8132/// isLegalICmpImmediate - Return true if the specified immediate is legal 8133/// icmp immediate, that is the target has icmp instructions which can compare 8134/// a register against the immediate without having to materialize the 8135/// immediate into a register. 8136bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const { 8137 if (!Subtarget->isThumb()) 8138 return ARM_AM::getSOImmVal(Imm) != -1; 8139 if (Subtarget->isThumb2()) 8140 return ARM_AM::getT2SOImmVal(Imm) != -1; 8141 return Imm >= 0 && Imm <= 255; 8142} 8143 8144/// isLegalAddImmediate - Return true if the specified immediate is legal 8145/// add immediate, that is the target has add instructions which can add 8146/// a register with the immediate without having to materialize the 8147/// immediate into a register. 8148bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const { 8149 return ARM_AM::getSOImmVal(Imm) != -1; 8150} 8151 8152static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT, 8153 bool isSEXTLoad, SDValue &Base, 8154 SDValue &Offset, bool &isInc, 8155 SelectionDAG &DAG) { 8156 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 8157 return false; 8158 8159 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { 8160 // AddressingMode 3 8161 Base = Ptr->getOperand(0); 8162 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 8163 int RHSC = (int)RHS->getZExtValue(); 8164 if (RHSC < 0 && RHSC > -256) { 8165 assert(Ptr->getOpcode() == ISD::ADD); 8166 isInc = false; 8167 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 8168 return true; 8169 } 8170 } 8171 isInc = (Ptr->getOpcode() == ISD::ADD); 8172 Offset = Ptr->getOperand(1); 8173 return true; 8174 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) { 8175 // AddressingMode 2 8176 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 8177 int RHSC = (int)RHS->getZExtValue(); 8178 if (RHSC < 0 && RHSC > -0x1000) { 8179 assert(Ptr->getOpcode() == ISD::ADD); 8180 isInc = false; 8181 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 8182 Base = Ptr->getOperand(0); 8183 return true; 8184 } 8185 } 8186 8187 if (Ptr->getOpcode() == ISD::ADD) { 8188 isInc = true; 8189 ARM_AM::ShiftOpc ShOpcVal= 8190 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode()); 8191 if (ShOpcVal != ARM_AM::no_shift) { 8192 Base = Ptr->getOperand(1); 8193 Offset = Ptr->getOperand(0); 8194 } else { 8195 Base = Ptr->getOperand(0); 8196 Offset = Ptr->getOperand(1); 8197 } 8198 return true; 8199 } 8200 8201 isInc = (Ptr->getOpcode() == ISD::ADD); 8202 Base = Ptr->getOperand(0); 8203 Offset = Ptr->getOperand(1); 8204 return true; 8205 } 8206 8207 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store. 8208 return false; 8209} 8210 8211static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT, 8212 bool isSEXTLoad, SDValue &Base, 8213 SDValue &Offset, bool &isInc, 8214 SelectionDAG &DAG) { 8215 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 8216 return false; 8217 8218 Base = Ptr->getOperand(0); 8219 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 8220 int RHSC = (int)RHS->getZExtValue(); 8221 if (RHSC < 0 && RHSC > -0x100) { // 8 bits. 8222 assert(Ptr->getOpcode() == ISD::ADD); 8223 isInc = false; 8224 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 8225 return true; 8226 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero. 8227 isInc = Ptr->getOpcode() == ISD::ADD; 8228 Offset = DAG.getConstant(RHSC, RHS->getValueType(0)); 8229 return true; 8230 } 8231 } 8232 8233 return false; 8234} 8235 8236/// getPreIndexedAddressParts - returns true by value, base pointer and 8237/// offset pointer and addressing mode by reference if the node's address 8238/// can be legally represented as pre-indexed load / store address. 8239bool 8240ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 8241 SDValue &Offset, 8242 ISD::MemIndexedMode &AM, 8243 SelectionDAG &DAG) const { 8244 if (Subtarget->isThumb1Only()) 8245 return false; 8246 8247 EVT VT; 8248 SDValue Ptr; 8249 bool isSEXTLoad = false; 8250 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 8251 Ptr = LD->getBasePtr(); 8252 VT = LD->getMemoryVT(); 8253 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 8254 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 8255 Ptr = ST->getBasePtr(); 8256 VT = ST->getMemoryVT(); 8257 } else 8258 return false; 8259 8260 bool isInc; 8261 bool isLegal = false; 8262 if (Subtarget->isThumb2()) 8263 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, 8264 Offset, isInc, DAG); 8265 else 8266 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, 8267 Offset, isInc, DAG); 8268 if (!isLegal) 8269 return false; 8270 8271 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC; 8272 return true; 8273} 8274 8275/// getPostIndexedAddressParts - returns true by value, base pointer and 8276/// offset pointer and addressing mode by reference if this node can be 8277/// combined with a load / store to form a post-indexed load / store. 8278bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 8279 SDValue &Base, 8280 SDValue &Offset, 8281 ISD::MemIndexedMode &AM, 8282 SelectionDAG &DAG) const { 8283 if (Subtarget->isThumb1Only()) 8284 return false; 8285 8286 EVT VT; 8287 SDValue Ptr; 8288 bool isSEXTLoad = false; 8289 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 8290 VT = LD->getMemoryVT(); 8291 Ptr = LD->getBasePtr(); 8292 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 8293 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 8294 VT = ST->getMemoryVT(); 8295 Ptr = ST->getBasePtr(); 8296 } else 8297 return false; 8298 8299 bool isInc; 8300 bool isLegal = false; 8301 if (Subtarget->isThumb2()) 8302 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 8303 isInc, DAG); 8304 else 8305 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 8306 isInc, DAG); 8307 if (!isLegal) 8308 return false; 8309 8310 if (Ptr != Base) { 8311 // Swap base ptr and offset to catch more post-index load / store when 8312 // it's legal. In Thumb2 mode, offset must be an immediate. 8313 if (Ptr == Offset && Op->getOpcode() == ISD::ADD && 8314 !Subtarget->isThumb2()) 8315 std::swap(Base, Offset); 8316 8317 // Post-indexed load / store update the base pointer. 8318 if (Ptr != Base) 8319 return false; 8320 } 8321 8322 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; 8323 return true; 8324} 8325 8326void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 8327 const APInt &Mask, 8328 APInt &KnownZero, 8329 APInt &KnownOne, 8330 const SelectionDAG &DAG, 8331 unsigned Depth) const { 8332 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 8333 switch (Op.getOpcode()) { 8334 default: break; 8335 case ARMISD::CMOV: { 8336 // Bits are known zero/one if known on the LHS and RHS. 8337 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 8338 if (KnownZero == 0 && KnownOne == 0) return; 8339 8340 APInt KnownZeroRHS, KnownOneRHS; 8341 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, 8342 KnownZeroRHS, KnownOneRHS, Depth+1); 8343 KnownZero &= KnownZeroRHS; 8344 KnownOne &= KnownOneRHS; 8345 return; 8346 } 8347 } 8348} 8349 8350//===----------------------------------------------------------------------===// 8351// ARM Inline Assembly Support 8352//===----------------------------------------------------------------------===// 8353 8354bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const { 8355 // Looking for "rev" which is V6+. 8356 if (!Subtarget->hasV6Ops()) 8357 return false; 8358 8359 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 8360 std::string AsmStr = IA->getAsmString(); 8361 SmallVector<StringRef, 4> AsmPieces; 8362 SplitString(AsmStr, AsmPieces, ";\n"); 8363 8364 switch (AsmPieces.size()) { 8365 default: return false; 8366 case 1: 8367 AsmStr = AsmPieces[0]; 8368 AsmPieces.clear(); 8369 SplitString(AsmStr, AsmPieces, " \t,"); 8370 8371 // rev $0, $1 8372 if (AsmPieces.size() == 3 && 8373 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" && 8374 IA->getConstraintString().compare(0, 4, "=l,l") == 0) { 8375 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 8376 if (Ty && Ty->getBitWidth() == 32) 8377 return IntrinsicLowering::LowerToByteSwap(CI); 8378 } 8379 break; 8380 } 8381 8382 return false; 8383} 8384 8385/// getConstraintType - Given a constraint letter, return the type of 8386/// constraint it is for this target. 8387ARMTargetLowering::ConstraintType 8388ARMTargetLowering::getConstraintType(const std::string &Constraint) const { 8389 if (Constraint.size() == 1) { 8390 switch (Constraint[0]) { 8391 default: break; 8392 case 'l': return C_RegisterClass; 8393 case 'w': return C_RegisterClass; 8394 case 'h': return C_RegisterClass; 8395 case 'x': return C_RegisterClass; 8396 case 't': return C_RegisterClass; 8397 case 'j': return C_Other; // Constant for movw. 8398 // An address with a single base register. Due to the way we 8399 // currently handle addresses it is the same as an 'r' memory constraint. 8400 case 'Q': return C_Memory; 8401 } 8402 } else if (Constraint.size() == 2) { 8403 switch (Constraint[0]) { 8404 default: break; 8405 // All 'U+' constraints are addresses. 8406 case 'U': return C_Memory; 8407 } 8408 } 8409 return TargetLowering::getConstraintType(Constraint); 8410} 8411 8412/// Examine constraint type and operand type and determine a weight value. 8413/// This object must already have been set up with the operand type 8414/// and the current alternative constraint selected. 8415TargetLowering::ConstraintWeight 8416ARMTargetLowering::getSingleConstraintMatchWeight( 8417 AsmOperandInfo &info, const char *constraint) const { 8418 ConstraintWeight weight = CW_Invalid; 8419 Value *CallOperandVal = info.CallOperandVal; 8420 // If we don't have a value, we can't do a match, 8421 // but allow it at the lowest weight. 8422 if (CallOperandVal == NULL) 8423 return CW_Default; 8424 Type *type = CallOperandVal->getType(); 8425 // Look at the constraint type. 8426 switch (*constraint) { 8427 default: 8428 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 8429 break; 8430 case 'l': 8431 if (type->isIntegerTy()) { 8432 if (Subtarget->isThumb()) 8433 weight = CW_SpecificReg; 8434 else 8435 weight = CW_Register; 8436 } 8437 break; 8438 case 'w': 8439 if (type->isFloatingPointTy()) 8440 weight = CW_Register; 8441 break; 8442 } 8443 return weight; 8444} 8445 8446typedef std::pair<unsigned, const TargetRegisterClass*> RCPair; 8447RCPair 8448ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 8449 EVT VT) const { 8450 if (Constraint.size() == 1) { 8451 // GCC ARM Constraint Letters 8452 switch (Constraint[0]) { 8453 case 'l': // Low regs or general regs. 8454 if (Subtarget->isThumb()) 8455 return RCPair(0U, ARM::tGPRRegisterClass); 8456 else 8457 return RCPair(0U, ARM::GPRRegisterClass); 8458 case 'h': // High regs or no regs. 8459 if (Subtarget->isThumb()) 8460 return RCPair(0U, ARM::hGPRRegisterClass); 8461 break; 8462 case 'r': 8463 return RCPair(0U, ARM::GPRRegisterClass); 8464 case 'w': 8465 if (VT == MVT::f32) 8466 return RCPair(0U, ARM::SPRRegisterClass); 8467 if (VT.getSizeInBits() == 64) 8468 return RCPair(0U, ARM::DPRRegisterClass); 8469 if (VT.getSizeInBits() == 128) 8470 return RCPair(0U, ARM::QPRRegisterClass); 8471 break; 8472 case 'x': 8473 if (VT == MVT::f32) 8474 return RCPair(0U, ARM::SPR_8RegisterClass); 8475 if (VT.getSizeInBits() == 64) 8476 return RCPair(0U, ARM::DPR_8RegisterClass); 8477 if (VT.getSizeInBits() == 128) 8478 return RCPair(0U, ARM::QPR_8RegisterClass); 8479 break; 8480 case 't': 8481 if (VT == MVT::f32) 8482 return RCPair(0U, ARM::SPRRegisterClass); 8483 break; 8484 } 8485 } 8486 if (StringRef("{cc}").equals_lower(Constraint)) 8487 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass); 8488 8489 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 8490} 8491 8492/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 8493/// vector. If it is invalid, don't add anything to Ops. 8494void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op, 8495 std::string &Constraint, 8496 std::vector<SDValue>&Ops, 8497 SelectionDAG &DAG) const { 8498 SDValue Result(0, 0); 8499 8500 // Currently only support length 1 constraints. 8501 if (Constraint.length() != 1) return; 8502 8503 char ConstraintLetter = Constraint[0]; 8504 switch (ConstraintLetter) { 8505 default: break; 8506 case 'j': 8507 case 'I': case 'J': case 'K': case 'L': 8508 case 'M': case 'N': case 'O': 8509 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op); 8510 if (!C) 8511 return; 8512 8513 int64_t CVal64 = C->getSExtValue(); 8514 int CVal = (int) CVal64; 8515 // None of these constraints allow values larger than 32 bits. Check 8516 // that the value fits in an int. 8517 if (CVal != CVal64) 8518 return; 8519 8520 switch (ConstraintLetter) { 8521 case 'j': 8522 // Constant suitable for movw, must be between 0 and 8523 // 65535. 8524 if (Subtarget->hasV6T2Ops()) 8525 if (CVal >= 0 && CVal <= 65535) 8526 break; 8527 return; 8528 case 'I': 8529 if (Subtarget->isThumb1Only()) { 8530 // This must be a constant between 0 and 255, for ADD 8531 // immediates. 8532 if (CVal >= 0 && CVal <= 255) 8533 break; 8534 } else if (Subtarget->isThumb2()) { 8535 // A constant that can be used as an immediate value in a 8536 // data-processing instruction. 8537 if (ARM_AM::getT2SOImmVal(CVal) != -1) 8538 break; 8539 } else { 8540 // A constant that can be used as an immediate value in a 8541 // data-processing instruction. 8542 if (ARM_AM::getSOImmVal(CVal) != -1) 8543 break; 8544 } 8545 return; 8546 8547 case 'J': 8548 if (Subtarget->isThumb()) { // FIXME thumb2 8549 // This must be a constant between -255 and -1, for negated ADD 8550 // immediates. This can be used in GCC with an "n" modifier that 8551 // prints the negated value, for use with SUB instructions. It is 8552 // not useful otherwise but is implemented for compatibility. 8553 if (CVal >= -255 && CVal <= -1) 8554 break; 8555 } else { 8556 // This must be a constant between -4095 and 4095. It is not clear 8557 // what this constraint is intended for. Implemented for 8558 // compatibility with GCC. 8559 if (CVal >= -4095 && CVal <= 4095) 8560 break; 8561 } 8562 return; 8563 8564 case 'K': 8565 if (Subtarget->isThumb1Only()) { 8566 // A 32-bit value where only one byte has a nonzero value. Exclude 8567 // zero to match GCC. This constraint is used by GCC internally for 8568 // constants that can be loaded with a move/shift combination. 8569 // It is not useful otherwise but is implemented for compatibility. 8570 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal)) 8571 break; 8572 } else if (Subtarget->isThumb2()) { 8573 // A constant whose bitwise inverse can be used as an immediate 8574 // value in a data-processing instruction. This can be used in GCC 8575 // with a "B" modifier that prints the inverted value, for use with 8576 // BIC and MVN instructions. It is not useful otherwise but is 8577 // implemented for compatibility. 8578 if (ARM_AM::getT2SOImmVal(~CVal) != -1) 8579 break; 8580 } else { 8581 // A constant whose bitwise inverse can be used as an immediate 8582 // value in a data-processing instruction. This can be used in GCC 8583 // with a "B" modifier that prints the inverted value, for use with 8584 // BIC and MVN instructions. It is not useful otherwise but is 8585 // implemented for compatibility. 8586 if (ARM_AM::getSOImmVal(~CVal) != -1) 8587 break; 8588 } 8589 return; 8590 8591 case 'L': 8592 if (Subtarget->isThumb1Only()) { 8593 // This must be a constant between -7 and 7, 8594 // for 3-operand ADD/SUB immediate instructions. 8595 if (CVal >= -7 && CVal < 7) 8596 break; 8597 } else if (Subtarget->isThumb2()) { 8598 // A constant whose negation can be used as an immediate value in a 8599 // data-processing instruction. This can be used in GCC with an "n" 8600 // modifier that prints the negated value, for use with SUB 8601 // instructions. It is not useful otherwise but is implemented for 8602 // compatibility. 8603 if (ARM_AM::getT2SOImmVal(-CVal) != -1) 8604 break; 8605 } else { 8606 // A constant whose negation can be used as an immediate value in a 8607 // data-processing instruction. This can be used in GCC with an "n" 8608 // modifier that prints the negated value, for use with SUB 8609 // instructions. It is not useful otherwise but is implemented for 8610 // compatibility. 8611 if (ARM_AM::getSOImmVal(-CVal) != -1) 8612 break; 8613 } 8614 return; 8615 8616 case 'M': 8617 if (Subtarget->isThumb()) { // FIXME thumb2 8618 // This must be a multiple of 4 between 0 and 1020, for 8619 // ADD sp + immediate. 8620 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0)) 8621 break; 8622 } else { 8623 // A power of two or a constant between 0 and 32. This is used in 8624 // GCC for the shift amount on shifted register operands, but it is 8625 // useful in general for any shift amounts. 8626 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0)) 8627 break; 8628 } 8629 return; 8630 8631 case 'N': 8632 if (Subtarget->isThumb()) { // FIXME thumb2 8633 // This must be a constant between 0 and 31, for shift amounts. 8634 if (CVal >= 0 && CVal <= 31) 8635 break; 8636 } 8637 return; 8638 8639 case 'O': 8640 if (Subtarget->isThumb()) { // FIXME thumb2 8641 // This must be a multiple of 4 between -508 and 508, for 8642 // ADD/SUB sp = sp + immediate. 8643 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0)) 8644 break; 8645 } 8646 return; 8647 } 8648 Result = DAG.getTargetConstant(CVal, Op.getValueType()); 8649 break; 8650 } 8651 8652 if (Result.getNode()) { 8653 Ops.push_back(Result); 8654 return; 8655 } 8656 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 8657} 8658 8659bool 8660ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 8661 // The ARM target isn't yet aware of offsets. 8662 return false; 8663} 8664 8665bool ARM::isBitFieldInvertedMask(unsigned v) { 8666 if (v == 0xffffffff) 8667 return 0; 8668 // there can be 1's on either or both "outsides", all the "inside" 8669 // bits must be 0's 8670 unsigned int lsb = 0, msb = 31; 8671 while (v & (1 << msb)) --msb; 8672 while (v & (1 << lsb)) ++lsb; 8673 for (unsigned int i = lsb; i <= msb; ++i) { 8674 if (v & (1 << i)) 8675 return 0; 8676 } 8677 return 1; 8678} 8679 8680/// isFPImmLegal - Returns true if the target can instruction select the 8681/// specified FP immediate natively. If false, the legalizer will 8682/// materialize the FP immediate as a load from a constant pool. 8683bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 8684 if (!Subtarget->hasVFP3()) 8685 return false; 8686 if (VT == MVT::f32) 8687 return ARM_AM::getFP32Imm(Imm) != -1; 8688 if (VT == MVT::f64) 8689 return ARM_AM::getFP64Imm(Imm) != -1; 8690 return false; 8691} 8692 8693/// getTgtMemIntrinsic - Represent NEON load and store intrinsics as 8694/// MemIntrinsicNodes. The associated MachineMemOperands record the alignment 8695/// specified in the intrinsic calls. 8696bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info, 8697 const CallInst &I, 8698 unsigned Intrinsic) const { 8699 switch (Intrinsic) { 8700 case Intrinsic::arm_neon_vld1: 8701 case Intrinsic::arm_neon_vld2: 8702 case Intrinsic::arm_neon_vld3: 8703 case Intrinsic::arm_neon_vld4: 8704 case Intrinsic::arm_neon_vld2lane: 8705 case Intrinsic::arm_neon_vld3lane: 8706 case Intrinsic::arm_neon_vld4lane: { 8707 Info.opc = ISD::INTRINSIC_W_CHAIN; 8708 // Conservatively set memVT to the entire set of vectors loaded. 8709 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8; 8710 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); 8711 Info.ptrVal = I.getArgOperand(0); 8712 Info.offset = 0; 8713 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1); 8714 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue(); 8715 Info.vol = false; // volatile loads with NEON intrinsics not supported 8716 Info.readMem = true; 8717 Info.writeMem = false; 8718 return true; 8719 } 8720 case Intrinsic::arm_neon_vst1: 8721 case Intrinsic::arm_neon_vst2: 8722 case Intrinsic::arm_neon_vst3: 8723 case Intrinsic::arm_neon_vst4: 8724 case Intrinsic::arm_neon_vst2lane: 8725 case Intrinsic::arm_neon_vst3lane: 8726 case Intrinsic::arm_neon_vst4lane: { 8727 Info.opc = ISD::INTRINSIC_VOID; 8728 // Conservatively set memVT to the entire set of vectors stored. 8729 unsigned NumElts = 0; 8730 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) { 8731 Type *ArgTy = I.getArgOperand(ArgI)->getType(); 8732 if (!ArgTy->isVectorTy()) 8733 break; 8734 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8; 8735 } 8736 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts); 8737 Info.ptrVal = I.getArgOperand(0); 8738 Info.offset = 0; 8739 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1); 8740 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue(); 8741 Info.vol = false; // volatile stores with NEON intrinsics not supported 8742 Info.readMem = false; 8743 Info.writeMem = true; 8744 return true; 8745 } 8746 case Intrinsic::arm_strexd: { 8747 Info.opc = ISD::INTRINSIC_W_CHAIN; 8748 Info.memVT = MVT::i64; 8749 Info.ptrVal = I.getArgOperand(2); 8750 Info.offset = 0; 8751 Info.align = 8; 8752 Info.vol = true; 8753 Info.readMem = false; 8754 Info.writeMem = true; 8755 return true; 8756 } 8757 case Intrinsic::arm_ldrexd: { 8758 Info.opc = ISD::INTRINSIC_W_CHAIN; 8759 Info.memVT = MVT::i64; 8760 Info.ptrVal = I.getArgOperand(0); 8761 Info.offset = 0; 8762 Info.align = 8; 8763 Info.vol = true; 8764 Info.readMem = true; 8765 Info.writeMem = false; 8766 return true; 8767 } 8768 default: 8769 break; 8770 } 8771 8772 return false; 8773} 8774