ARMISelLowering.cpp revision f96e4de403453e57aea75bcac1ed99af686d33c4
1//===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Evan Cheng and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "ARM.h" 16#include "ARMAddressingModes.h" 17#include "ARMConstantPoolValue.h" 18#include "ARMISelLowering.h" 19#include "ARMMachineFunctionInfo.h" 20#include "ARMRegisterInfo.h" 21#include "ARMSubtarget.h" 22#include "ARMTargetMachine.h" 23#include "llvm/CallingConv.h" 24#include "llvm/Constants.h" 25#include "llvm/Instruction.h" 26#include "llvm/CodeGen/MachineBasicBlock.h" 27#include "llvm/CodeGen/MachineFrameInfo.h" 28#include "llvm/CodeGen/MachineFunction.h" 29#include "llvm/CodeGen/MachineInstrBuilder.h" 30#include "llvm/CodeGen/SelectionDAG.h" 31#include "llvm/CodeGen/SSARegMap.h" 32#include "llvm/Target/TargetOptions.h" 33#include "llvm/ADT/VectorExtras.h" 34#include "llvm/Support/MathExtras.h" 35using namespace llvm; 36 37ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) 38 : TargetLowering(TM), ARMPCLabelIndex(0) { 39 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 40 41 if (Subtarget->isTargetDarwin()) { 42 // Don't have these. 43 setLibcallName(RTLIB::UINTTOFP_I64_F32, NULL); 44 setLibcallName(RTLIB::UINTTOFP_I64_F64, NULL); 45 46 // Uses VFP for Thumb libfuncs if available. 47 if (Subtarget->isThumb() && Subtarget->hasVFP2()) { 48 // Single-precision floating-point arithmetic. 49 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp"); 50 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp"); 51 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp"); 52 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp"); 53 54 // Double-precision floating-point arithmetic. 55 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp"); 56 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp"); 57 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp"); 58 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp"); 59 60 // Single-precision comparisons. 61 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp"); 62 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp"); 63 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp"); 64 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp"); 65 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp"); 66 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp"); 67 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp"); 68 setLibcallName(RTLIB::O_F32, "__unordsf2vfp"); 69 70 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 71 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE); 72 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 73 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 74 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 75 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 76 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 77 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 78 79 // Double-precision comparisons. 80 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp"); 81 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp"); 82 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp"); 83 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp"); 84 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp"); 85 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp"); 86 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp"); 87 setLibcallName(RTLIB::O_F64, "__unorddf2vfp"); 88 89 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 90 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE); 91 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 92 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 93 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 94 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 95 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 96 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 97 98 // Floating-point to integer conversions. 99 // i64 conversions are done via library routines even when generating VFP 100 // instructions, so use the same ones. 101 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp"); 102 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp"); 103 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp"); 104 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp"); 105 106 // Conversions between floating types. 107 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp"); 108 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp"); 109 110 // Integer to floating-point conversions. 111 // i64 conversions are done via library routines even when generating VFP 112 // instructions, so use the same ones. 113 // FIXME: There appears to be some naming inconsistency in ARM libgcc: e.g. 114 // __floatunsidf vs. __floatunssidfvfp. 115 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp"); 116 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp"); 117 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp"); 118 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp"); 119 } 120 } 121 122 addRegisterClass(MVT::i32, ARM::GPRRegisterClass); 123 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) { 124 addRegisterClass(MVT::f32, ARM::SPRRegisterClass); 125 addRegisterClass(MVT::f64, ARM::DPRRegisterClass); 126 } 127 computeRegisterProperties(); 128 129 // ARM does not have f32 extending load. 130 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); 131 132 // ARM supports all 4 flavors of integer indexed load / store. 133 for (unsigned im = (unsigned)ISD::PRE_INC; 134 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { 135 setIndexedLoadAction(im, MVT::i1, Legal); 136 setIndexedLoadAction(im, MVT::i8, Legal); 137 setIndexedLoadAction(im, MVT::i16, Legal); 138 setIndexedLoadAction(im, MVT::i32, Legal); 139 setIndexedStoreAction(im, MVT::i1, Legal); 140 setIndexedStoreAction(im, MVT::i8, Legal); 141 setIndexedStoreAction(im, MVT::i16, Legal); 142 setIndexedStoreAction(im, MVT::i32, Legal); 143 } 144 145 // i64 operation support. 146 if (Subtarget->isThumb()) { 147 setOperationAction(ISD::MUL, MVT::i64, Expand); 148 setOperationAction(ISD::MULHU, MVT::i32, Expand); 149 setOperationAction(ISD::MULHS, MVT::i32, Expand); 150 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 151 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 152 } else { 153 setOperationAction(ISD::MUL, MVT::i64, Expand); 154 setOperationAction(ISD::MULHU, MVT::i32, Expand); 155 if (!Subtarget->hasV6Ops()) 156 setOperationAction(ISD::MULHS, MVT::i32, Expand); 157 } 158 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 159 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 160 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 161 setOperationAction(ISD::SRL, MVT::i64, Custom); 162 setOperationAction(ISD::SRA, MVT::i64, Custom); 163 164 // ARM does not have ROTL. 165 setOperationAction(ISD::ROTL, MVT::i32, Expand); 166 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 167 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 168 if (!Subtarget->hasV5TOps() || Subtarget->isThumb()) 169 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 170 171 // Only ARMv6 has BSWAP. 172 if (!Subtarget->hasV6Ops()) 173 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 174 175 // These are expanded into libcalls. 176 setOperationAction(ISD::SDIV, MVT::i32, Expand); 177 setOperationAction(ISD::UDIV, MVT::i32, Expand); 178 setOperationAction(ISD::SREM, MVT::i32, Expand); 179 setOperationAction(ISD::UREM, MVT::i32, Expand); 180 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 181 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 182 183 // Support label based line numbers. 184 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 185 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 186 187 setOperationAction(ISD::RET, MVT::Other, Custom); 188 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 189 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 190 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom); 191 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 192 193 // Expand mem operations genericly. 194 setOperationAction(ISD::MEMSET , MVT::Other, Expand); 195 setOperationAction(ISD::MEMCPY , MVT::Other, Custom); 196 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand); 197 198 // Use the default implementation. 199 setOperationAction(ISD::VASTART , MVT::Other, Expand); 200 setOperationAction(ISD::VAARG , MVT::Other, Expand); 201 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 202 setOperationAction(ISD::VAEND , MVT::Other, Expand); 203 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 204 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 205 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand); 206 207 if (!Subtarget->hasV6Ops()) { 208 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 209 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 210 } 211 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 212 213 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) 214 // Turn f64->i64 into FMRRD iff target supports vfp2. 215 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom); 216 217 setOperationAction(ISD::SETCC , MVT::i32, Expand); 218 setOperationAction(ISD::SETCC , MVT::f32, Expand); 219 setOperationAction(ISD::SETCC , MVT::f64, Expand); 220 setOperationAction(ISD::SELECT , MVT::i32, Expand); 221 setOperationAction(ISD::SELECT , MVT::f32, Expand); 222 setOperationAction(ISD::SELECT , MVT::f64, Expand); 223 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 224 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 225 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 226 227 setOperationAction(ISD::BRCOND , MVT::Other, Expand); 228 setOperationAction(ISD::BR_CC , MVT::i32, Custom); 229 setOperationAction(ISD::BR_CC , MVT::f32, Custom); 230 setOperationAction(ISD::BR_CC , MVT::f64, Custom); 231 setOperationAction(ISD::BR_JT , MVT::Other, Custom); 232 233 setOperationAction(ISD::VASTART, MVT::Other, Custom); 234 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 235 setOperationAction(ISD::VAEND, MVT::Other, Expand); 236 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 237 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 238 239 // FP Constants can't be immediates. 240 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 241 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 242 243 // We don't support sin/cos/fmod/copysign/pow 244 setOperationAction(ISD::FSIN , MVT::f64, Expand); 245 setOperationAction(ISD::FSIN , MVT::f32, Expand); 246 setOperationAction(ISD::FCOS , MVT::f32, Expand); 247 setOperationAction(ISD::FCOS , MVT::f64, Expand); 248 setOperationAction(ISD::FREM , MVT::f64, Expand); 249 setOperationAction(ISD::FREM , MVT::f32, Expand); 250 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 251 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 252 setOperationAction(ISD::FPOW , MVT::f64, Expand); 253 setOperationAction(ISD::FPOW , MVT::f32, Expand); 254 255 // int <-> fp are custom expanded into bit_convert + ARMISD ops. 256 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 257 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 258 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 259 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 260 261 setStackPointerRegisterToSaveRestore(ARM::SP); 262 setSchedulingPreference(SchedulingForRegPressure); 263 setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10); 264 setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2); 265 266 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type 267} 268 269 270const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { 271 switch (Opcode) { 272 default: return 0; 273 case ARMISD::Wrapper: return "ARMISD::Wrapper"; 274 case ARMISD::WrapperJT: return "ARMISD::WrapperJT"; 275 case ARMISD::CALL: return "ARMISD::CALL"; 276 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED"; 277 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK"; 278 case ARMISD::tCALL: return "ARMISD::tCALL"; 279 case ARMISD::BRCOND: return "ARMISD::BRCOND"; 280 case ARMISD::BR_JT: return "ARMISD::BR_JT"; 281 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; 282 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD"; 283 case ARMISD::CMP: return "ARMISD::CMP"; 284 case ARMISD::CMPNZ: return "ARMISD::CMPNZ"; 285 case ARMISD::CMPFP: return "ARMISD::CMPFP"; 286 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0"; 287 case ARMISD::FMSTAT: return "ARMISD::FMSTAT"; 288 case ARMISD::CMOV: return "ARMISD::CMOV"; 289 case ARMISD::CNEG: return "ARMISD::CNEG"; 290 291 case ARMISD::FTOSI: return "ARMISD::FTOSI"; 292 case ARMISD::FTOUI: return "ARMISD::FTOUI"; 293 case ARMISD::SITOF: return "ARMISD::SITOF"; 294 case ARMISD::UITOF: return "ARMISD::UITOF"; 295 296 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG"; 297 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG"; 298 case ARMISD::RRX: return "ARMISD::RRX"; 299 300 case ARMISD::FMRRD: return "ARMISD::FMRRD"; 301 case ARMISD::FMDRR: return "ARMISD::FMDRR"; 302 303 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER"; 304 } 305} 306 307//===----------------------------------------------------------------------===// 308// Lowering Code 309//===----------------------------------------------------------------------===// 310 311 312/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC 313static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { 314 switch (CC) { 315 default: assert(0 && "Unknown condition code!"); 316 case ISD::SETNE: return ARMCC::NE; 317 case ISD::SETEQ: return ARMCC::EQ; 318 case ISD::SETGT: return ARMCC::GT; 319 case ISD::SETGE: return ARMCC::GE; 320 case ISD::SETLT: return ARMCC::LT; 321 case ISD::SETLE: return ARMCC::LE; 322 case ISD::SETUGT: return ARMCC::HI; 323 case ISD::SETUGE: return ARMCC::HS; 324 case ISD::SETULT: return ARMCC::LO; 325 case ISD::SETULE: return ARMCC::LS; 326 } 327} 328 329/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It 330/// returns true if the operands should be inverted to form the proper 331/// comparison. 332static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, 333 ARMCC::CondCodes &CondCode2) { 334 bool Invert = false; 335 CondCode2 = ARMCC::AL; 336 switch (CC) { 337 default: assert(0 && "Unknown FP condition!"); 338 case ISD::SETEQ: 339 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; 340 case ISD::SETGT: 341 case ISD::SETOGT: CondCode = ARMCC::GT; break; 342 case ISD::SETGE: 343 case ISD::SETOGE: CondCode = ARMCC::GE; break; 344 case ISD::SETOLT: CondCode = ARMCC::MI; break; 345 case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break; 346 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break; 347 case ISD::SETO: CondCode = ARMCC::VC; break; 348 case ISD::SETUO: CondCode = ARMCC::VS; break; 349 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break; 350 case ISD::SETUGT: CondCode = ARMCC::HI; break; 351 case ISD::SETUGE: CondCode = ARMCC::PL; break; 352 case ISD::SETLT: 353 case ISD::SETULT: CondCode = ARMCC::LT; break; 354 case ISD::SETLE: 355 case ISD::SETULE: CondCode = ARMCC::LE; break; 356 case ISD::SETNE: 357 case ISD::SETUNE: CondCode = ARMCC::NE; break; 358 } 359 return Invert; 360} 361 362static void 363HowToPassArgument(MVT::ValueType ObjectVT, unsigned NumGPRs, 364 unsigned StackOffset, unsigned &NeededGPRs, 365 unsigned &NeededStackSize, unsigned &GPRPad, 366 unsigned &StackPad, unsigned Flags) { 367 NeededStackSize = 0; 368 NeededGPRs = 0; 369 StackPad = 0; 370 GPRPad = 0; 371 unsigned align = (Flags >> ISD::ParamFlags::OrigAlignmentOffs); 372 GPRPad = NumGPRs % ((align + 3)/4); 373 StackPad = StackOffset % align; 374 unsigned firstGPR = NumGPRs + GPRPad; 375 switch (ObjectVT) { 376 default: assert(0 && "Unhandled argument type!"); 377 case MVT::i32: 378 case MVT::f32: 379 if (firstGPR < 4) 380 NeededGPRs = 1; 381 else 382 NeededStackSize = 4; 383 break; 384 case MVT::i64: 385 case MVT::f64: 386 if (firstGPR < 3) 387 NeededGPRs = 2; 388 else if (firstGPR == 3) { 389 NeededGPRs = 1; 390 NeededStackSize = 4; 391 } else 392 NeededStackSize = 8; 393 } 394} 395 396/// LowerCALL - Lowering a ISD::CALL node into a callseq_start <- 397/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter 398/// nodes. 399SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { 400 MVT::ValueType RetVT= Op.Val->getValueType(0); 401 SDOperand Chain = Op.getOperand(0); 402 unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 403 assert((CallConv == CallingConv::C || 404 CallConv == CallingConv::Fast) && "unknown calling convention"); 405 SDOperand Callee = Op.getOperand(4); 406 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 407 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 408 unsigned NumGPRs = 0; // GPRs used for parameter passing. 409 410 // Count how many bytes are to be pushed on the stack. 411 unsigned NumBytes = 0; 412 413 // Add up all the space actually used. 414 for (unsigned i = 0; i < NumOps; ++i) { 415 unsigned ObjSize; 416 unsigned ObjGPRs; 417 unsigned StackPad; 418 unsigned GPRPad; 419 MVT::ValueType ObjectVT = Op.getOperand(5+2*i).getValueType(); 420 unsigned Flags = Op.getConstantOperandVal(5+2*i+1); 421 HowToPassArgument(ObjectVT, NumGPRs, NumBytes, ObjGPRs, ObjSize, 422 GPRPad, StackPad, Flags); 423 NumBytes += ObjSize + StackPad; 424 NumGPRs += ObjGPRs + GPRPad; 425 } 426 427 // Adjust the stack pointer for the new arguments... 428 // These operations are automatically eliminated by the prolog/epilog pass 429 Chain = DAG.getCALLSEQ_START(Chain, 430 DAG.getConstant(NumBytes, MVT::i32)); 431 432 SDOperand StackPtr = DAG.getRegister(ARM::SP, MVT::i32); 433 434 static const unsigned GPRArgRegs[] = { 435 ARM::R0, ARM::R1, ARM::R2, ARM::R3 436 }; 437 438 NumGPRs = 0; 439 std::vector<std::pair<unsigned, SDOperand> > RegsToPass; 440 std::vector<SDOperand> MemOpChains; 441 for (unsigned i = 0; i != NumOps; ++i) { 442 SDOperand Arg = Op.getOperand(5+2*i); 443 unsigned Flags = Op.getConstantOperandVal(5+2*i+1); 444 MVT::ValueType ArgVT = Arg.getValueType(); 445 446 unsigned ObjSize; 447 unsigned ObjGPRs; 448 unsigned GPRPad; 449 unsigned StackPad; 450 HowToPassArgument(ArgVT, NumGPRs, ArgOffset, ObjGPRs, 451 ObjSize, GPRPad, StackPad, Flags); 452 NumGPRs += GPRPad; 453 ArgOffset += StackPad; 454 if (ObjGPRs > 0) { 455 switch (ArgVT) { 456 default: assert(0 && "Unexpected ValueType for argument!"); 457 case MVT::i32: 458 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Arg)); 459 break; 460 case MVT::f32: 461 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], 462 DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg))); 463 break; 464 case MVT::i64: { 465 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg, 466 DAG.getConstant(0, getPointerTy())); 467 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg, 468 DAG.getConstant(1, getPointerTy())); 469 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo)); 470 if (ObjGPRs == 2) 471 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi)); 472 else { 473 SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType()); 474 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 475 MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0)); 476 } 477 break; 478 } 479 case MVT::f64: { 480 SDOperand Cvt = DAG.getNode(ARMISD::FMRRD, 481 DAG.getVTList(MVT::i32, MVT::i32), 482 &Arg, 1); 483 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Cvt)); 484 if (ObjGPRs == 2) 485 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], 486 Cvt.getValue(1))); 487 else { 488 SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType()); 489 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 490 MemOpChains.push_back(DAG.getStore(Chain, Cvt.getValue(1), PtrOff, 491 NULL, 0)); 492 } 493 break; 494 } 495 } 496 } else { 497 assert(ObjSize != 0); 498 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 499 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 500 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 501 } 502 503 NumGPRs += ObjGPRs; 504 ArgOffset += ObjSize; 505 } 506 507 if (!MemOpChains.empty()) 508 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 509 &MemOpChains[0], MemOpChains.size()); 510 511 // Build a sequence of copy-to-reg nodes chained together with token chain 512 // and flag operands which copy the outgoing args into the appropriate regs. 513 SDOperand InFlag; 514 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 515 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 516 InFlag); 517 InFlag = Chain.getValue(1); 518 } 519 520 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 521 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 522 // node so that legalize doesn't hack it. 523 bool isDirect = false; 524 bool isARMFunc = false; 525 bool isLocalARMFunc = false; 526 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 527 GlobalValue *GV = G->getGlobal(); 528 isDirect = true; 529 bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() || 530 GV->hasLinkOnceLinkage()); 531 bool isStub = (isExt && Subtarget->isTargetDarwin()) && 532 getTargetMachine().getRelocationModel() != Reloc::Static; 533 isARMFunc = !Subtarget->isThumb() || isStub; 534 // ARM call to a local ARM function is predicable. 535 isLocalARMFunc = !Subtarget->isThumb() && !isExt; 536 // tBX takes a register source operand. 537 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) { 538 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex, 539 ARMCP::CPStub, 4); 540 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2); 541 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 542 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0); 543 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 544 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel); 545 } else 546 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy()); 547 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 548 isDirect = true; 549 bool isStub = Subtarget->isTargetDarwin() && 550 getTargetMachine().getRelocationModel() != Reloc::Static; 551 isARMFunc = !Subtarget->isThumb() || isStub; 552 // tBX takes a register source operand. 553 const char *Sym = S->getSymbol(); 554 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) { 555 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex, 556 ARMCP::CPStub, 4); 557 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2); 558 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 559 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0); 560 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 561 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel); 562 } else 563 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy()); 564 } 565 566 // FIXME: handle tail calls differently. 567 unsigned CallOpc; 568 if (Subtarget->isThumb()) { 569 if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc)) 570 CallOpc = ARMISD::CALL_NOLINK; 571 else 572 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL; 573 } else { 574 CallOpc = (isDirect || Subtarget->hasV5TOps()) 575 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL) 576 : ARMISD::CALL_NOLINK; 577 } 578 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) { 579 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK 580 Chain = DAG.getCopyToReg(Chain, ARM::LR, 581 DAG.getNode(ISD::UNDEF, MVT::i32), InFlag); 582 InFlag = Chain.getValue(1); 583 } 584 585 std::vector<MVT::ValueType> NodeTys; 586 NodeTys.push_back(MVT::Other); // Returns a chain 587 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 588 589 std::vector<SDOperand> Ops; 590 Ops.push_back(Chain); 591 Ops.push_back(Callee); 592 593 // Add argument registers to the end of the list so that they are known live 594 // into the call. 595 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 596 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 597 RegsToPass[i].second.getValueType())); 598 599 if (InFlag.Val) 600 Ops.push_back(InFlag); 601 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); 602 InFlag = Chain.getValue(1); 603 604 SDOperand CSOps[] = { Chain, DAG.getConstant(NumBytes, MVT::i32), InFlag }; 605 Chain = DAG.getNode(ISD::CALLSEQ_END, 606 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 607 ((RetVT != MVT::Other) ? 2 : 1), CSOps, 3); 608 if (RetVT != MVT::Other) 609 InFlag = Chain.getValue(1); 610 611 std::vector<SDOperand> ResultVals; 612 NodeTys.clear(); 613 614 // If the call has results, copy the values out of the ret val registers. 615 switch (RetVT) { 616 default: assert(0 && "Unexpected ret value!"); 617 case MVT::Other: 618 break; 619 case MVT::i32: 620 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1); 621 ResultVals.push_back(Chain.getValue(0)); 622 if (Op.Val->getValueType(1) == MVT::i32) { 623 // Returns a i64 value. 624 Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32, 625 Chain.getValue(2)).getValue(1); 626 ResultVals.push_back(Chain.getValue(0)); 627 NodeTys.push_back(MVT::i32); 628 } 629 NodeTys.push_back(MVT::i32); 630 break; 631 case MVT::f32: 632 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1); 633 ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f32, 634 Chain.getValue(0))); 635 NodeTys.push_back(MVT::f32); 636 break; 637 case MVT::f64: { 638 SDOperand Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag); 639 SDOperand Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2)); 640 ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi)); 641 NodeTys.push_back(MVT::f64); 642 break; 643 } 644 } 645 646 NodeTys.push_back(MVT::Other); 647 648 if (ResultVals.empty()) 649 return Chain; 650 651 ResultVals.push_back(Chain); 652 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, &ResultVals[0], 653 ResultVals.size()); 654 return Res.getValue(Op.ResNo); 655} 656 657static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { 658 SDOperand Copy; 659 SDOperand Chain = Op.getOperand(0); 660 switch(Op.getNumOperands()) { 661 default: 662 assert(0 && "Do not know how to return this many arguments!"); 663 abort(); 664 case 1: { 665 SDOperand LR = DAG.getRegister(ARM::LR, MVT::i32); 666 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain); 667 } 668 case 3: 669 Op = Op.getOperand(1); 670 if (Op.getValueType() == MVT::f32) { 671 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 672 } else if (Op.getValueType() == MVT::f64) { 673 // Recursively legalize f64 -> i64. 674 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Op); 675 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op, 676 DAG.getConstant(0, MVT::i32)); 677 } 678 Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDOperand()); 679 if (DAG.getMachineFunction().liveout_empty()) 680 DAG.getMachineFunction().addLiveOut(ARM::R0); 681 break; 682 case 5: 683 Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand()); 684 Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1)); 685 // If we haven't noted the R0+R1 are live out, do so now. 686 if (DAG.getMachineFunction().liveout_empty()) { 687 DAG.getMachineFunction().addLiveOut(ARM::R0); 688 DAG.getMachineFunction().addLiveOut(ARM::R1); 689 } 690 break; 691 } 692 693 //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag 694 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 695} 696 697// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 698// their target countpart wrapped in the ARMISD::Wrapper node. Suppose N is 699// one of the above mentioned nodes. It has to be wrapped because otherwise 700// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 701// be used to form addressing mode. These wrapped nodes will be selected 702// into MOVi. 703static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { 704 MVT::ValueType PtrVT = Op.getValueType(); 705 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 706 SDOperand Res; 707 if (CP->isMachineConstantPoolEntry()) 708 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, 709 CP->getAlignment()); 710 else 711 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, 712 CP->getAlignment()); 713 return DAG.getNode(ARMISD::Wrapper, MVT::i32, Res); 714} 715 716// Lower ISD::GlobalTLSAddress using the "general dynamic" model 717SDOperand 718ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 719 SelectionDAG &DAG) { 720 MVT::ValueType PtrVT = getPointerTy(); 721 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 722 ARMConstantPoolValue *CPV = 723 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue, 724 PCAdj, "tlsgd", true); 725 SDOperand Argument = DAG.getTargetConstantPool(CPV, PtrVT, 2); 726 Argument = DAG.getNode(ARMISD::Wrapper, MVT::i32, Argument); 727 Argument = DAG.getLoad(PtrVT, DAG.getEntryNode(), Argument, NULL, 0); 728 SDOperand Chain = Argument.getValue(1); 729 730 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 731 Argument = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Argument, PICLabel); 732 733 // call __tls_get_addr. 734 ArgListTy Args; 735 ArgListEntry Entry; 736 Entry.Node = Argument; 737 Entry.Ty = (const Type *) Type::Int32Ty; 738 Args.push_back(Entry); 739 std::pair<SDOperand, SDOperand> CallResult = 740 LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, 741 CallingConv::C, false, 742 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG); 743 return CallResult.first; 744} 745 746// Lower ISD::GlobalTLSAddress using the "initial exec" or 747// "local exec" model. 748SDOperand 749ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, 750 SelectionDAG &DAG) { 751 GlobalValue *GV = GA->getGlobal(); 752 SDOperand Offset; 753 SDOperand Chain = DAG.getEntryNode(); 754 MVT::ValueType PtrVT = getPointerTy(); 755 // Get the Thread Pointer 756 SDOperand ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, PtrVT); 757 758 if (GV->isDeclaration()){ 759 // initial exec model 760 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 761 ARMConstantPoolValue *CPV = 762 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue, 763 PCAdj, "gottpoff", true); 764 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2); 765 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset); 766 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); 767 Chain = Offset.getValue(1); 768 769 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 770 Offset = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Offset, PICLabel); 771 772 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); 773 } else { 774 // local exec model 775 ARMConstantPoolValue *CPV = 776 new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff"); 777 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2); 778 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset); 779 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); 780 } 781 782 // The address of the thread local variable is the add of the thread 783 // pointer with the offset of the variable. 784 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset); 785} 786 787SDOperand 788ARMTargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) { 789 // TODO: implement the "local dynamic" model 790 assert(Subtarget->isTargetELF() && 791 "TLS not implemented for non-ELF targets"); 792 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 793 // If the relocation model is PIC, use the "General Dynamic" TLS Model, 794 // otherwise use the "Local Exec" TLS Model 795 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) 796 return LowerToTLSGeneralDynamicModel(GA, DAG); 797 else 798 return LowerToTLSExecModels(GA, DAG); 799} 800 801SDOperand ARMTargetLowering::LowerGlobalAddressELF(SDOperand Op, 802 SelectionDAG &DAG) { 803 MVT::ValueType PtrVT = getPointerTy(); 804 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 805 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 806 if (RelocM == Reloc::PIC_) { 807 bool UseGOTOFF = GV->hasInternalLinkage() || GV->hasHiddenVisibility(); 808 ARMConstantPoolValue *CPV = 809 new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT"); 810 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); 811 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 812 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 813 SDOperand Chain = Result.getValue(1); 814 SDOperand GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT); 815 Result = DAG.getNode(ISD::ADD, PtrVT, Result, GOT); 816 if (!UseGOTOFF) 817 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0); 818 return Result; 819 } else { 820 SDOperand CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2); 821 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 822 return DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 823 } 824} 825 826/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol 827/// even in non-static mode. 828static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) { 829 return RelocM != Reloc::Static && 830 (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() || 831 (GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode())); 832} 833 834SDOperand ARMTargetLowering::LowerGlobalAddressDarwin(SDOperand Op, 835 SelectionDAG &DAG) { 836 MVT::ValueType PtrVT = getPointerTy(); 837 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 838 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 839 bool IsIndirect = GVIsIndirectSymbol(GV, RelocM); 840 SDOperand CPAddr; 841 if (RelocM == Reloc::Static) 842 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2); 843 else { 844 unsigned PCAdj = (RelocM != Reloc::PIC_) 845 ? 0 : (Subtarget->isThumb() ? 4 : 8); 846 ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr 847 : ARMCP::CPValue; 848 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex, 849 Kind, PCAdj); 850 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); 851 } 852 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 853 854 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 855 SDOperand Chain = Result.getValue(1); 856 857 if (RelocM == Reloc::PIC_) { 858 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 859 Result = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel); 860 } 861 if (IsIndirect) 862 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0); 863 864 return Result; 865} 866 867SDOperand ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDOperand Op, 868 SelectionDAG &DAG){ 869 assert(Subtarget->isTargetELF() && 870 "GLOBAL OFFSET TABLE not implemented for non-ELF targets"); 871 MVT::ValueType PtrVT = getPointerTy(); 872 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 873 ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_", 874 ARMPCLabelIndex, 875 ARMCP::CPValue, PCAdj); 876 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); 877 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 878 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 879 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 880 return DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel); 881} 882 883static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, 884 unsigned VarArgsFrameIndex) { 885 // vastart just stores the address of the VarArgsFrameIndex slot into the 886 // memory location argument. 887 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 888 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 889 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); 890 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(), 891 SV->getOffset()); 892} 893 894static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG, 895 unsigned *vRegs, unsigned ArgNo, 896 unsigned &NumGPRs, unsigned &ArgOffset) { 897 MachineFunction &MF = DAG.getMachineFunction(); 898 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); 899 SDOperand Root = Op.getOperand(0); 900 std::vector<SDOperand> ArgValues; 901 SSARegMap *RegMap = MF.getSSARegMap(); 902 903 static const unsigned GPRArgRegs[] = { 904 ARM::R0, ARM::R1, ARM::R2, ARM::R3 905 }; 906 907 unsigned ObjSize; 908 unsigned ObjGPRs; 909 unsigned GPRPad; 910 unsigned StackPad; 911 unsigned Flags = Op.getConstantOperandVal(ArgNo + 3); 912 HowToPassArgument(ObjectVT, NumGPRs, ArgOffset, ObjGPRs, 913 ObjSize, GPRPad, StackPad, Flags); 914 NumGPRs += GPRPad; 915 ArgOffset += StackPad; 916 917 SDOperand ArgValue; 918 if (ObjGPRs == 1) { 919 unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass); 920 MF.addLiveIn(GPRArgRegs[NumGPRs], VReg); 921 vRegs[NumGPRs] = VReg; 922 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); 923 if (ObjectVT == MVT::f32) 924 ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue); 925 } else if (ObjGPRs == 2) { 926 unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass); 927 MF.addLiveIn(GPRArgRegs[NumGPRs], VReg); 928 vRegs[NumGPRs] = VReg; 929 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); 930 931 VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass); 932 MF.addLiveIn(GPRArgRegs[NumGPRs+1], VReg); 933 vRegs[NumGPRs+1] = VReg; 934 SDOperand ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32); 935 936 if (ObjectVT == MVT::i64) 937 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2); 938 else 939 ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2); 940 } 941 NumGPRs += ObjGPRs; 942 943 if (ObjSize) { 944 // If the argument is actually used, emit a load from the right stack 945 // slot. 946 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) { 947 MachineFrameInfo *MFI = MF.getFrameInfo(); 948 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 949 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 950 if (ObjGPRs == 0) 951 ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); 952 else { 953 SDOperand ArgValue2 = 954 DAG.getLoad(MVT::i32, Root, FIN, NULL, 0); 955 if (ObjectVT == MVT::i64) 956 ArgValue= DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2); 957 else 958 ArgValue= DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2); 959 } 960 } else { 961 // Don't emit a dead load. 962 ArgValue = DAG.getNode(ISD::UNDEF, ObjectVT); 963 } 964 965 ArgOffset += ObjSize; // Move on to the next argument. 966 } 967 968 return ArgValue; 969} 970 971SDOperand 972ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { 973 std::vector<SDOperand> ArgValues; 974 SDOperand Root = Op.getOperand(0); 975 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 976 unsigned NumGPRs = 0; // GPRs used for parameter passing. 977 unsigned VRegs[4]; 978 979 unsigned NumArgs = Op.Val->getNumValues()-1; 980 for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo) 981 ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, VRegs, ArgNo, 982 NumGPRs, ArgOffset)); 983 984 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 985 if (isVarArg) { 986 static const unsigned GPRArgRegs[] = { 987 ARM::R0, ARM::R1, ARM::R2, ARM::R3 988 }; 989 990 MachineFunction &MF = DAG.getMachineFunction(); 991 SSARegMap *RegMap = MF.getSSARegMap(); 992 MachineFrameInfo *MFI = MF.getFrameInfo(); 993 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 994 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 995 unsigned VARegSize = (4 - NumGPRs) * 4; 996 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1); 997 if (VARegSaveSize) { 998 // If this function is vararg, store any remaining integer argument regs 999 // to their spots on the stack so that they may be loaded by deferencing 1000 // the result of va_next. 1001 AFI->setVarArgsRegSaveSize(VARegSaveSize); 1002 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset + 1003 VARegSaveSize - VARegSize); 1004 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 1005 1006 SmallVector<SDOperand, 4> MemOps; 1007 for (; NumGPRs < 4; ++NumGPRs) { 1008 unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass); 1009 MF.addLiveIn(GPRArgRegs[NumGPRs], VReg); 1010 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32); 1011 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1012 MemOps.push_back(Store); 1013 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 1014 DAG.getConstant(4, getPointerTy())); 1015 } 1016 if (!MemOps.empty()) 1017 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 1018 &MemOps[0], MemOps.size()); 1019 } else 1020 // This will point to the next argument passed via stack. 1021 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset); 1022 } 1023 1024 ArgValues.push_back(Root); 1025 1026 // Return the new list of results. 1027 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(), 1028 Op.Val->value_end()); 1029 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); 1030} 1031 1032/// isFloatingPointZero - Return true if this is +0.0. 1033static bool isFloatingPointZero(SDOperand Op) { 1034 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 1035 return CFP->getValueAPF().isPosZero(); 1036 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) { 1037 // Maybe this has already been legalized into the constant pool? 1038 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) { 1039 SDOperand WrapperOp = Op.getOperand(1).getOperand(0); 1040 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp)) 1041 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 1042 return CFP->getValueAPF().isPosZero(); 1043 } 1044 } 1045 return false; 1046} 1047 1048static bool isLegalCmpImmediate(unsigned C, bool isThumb) { 1049 return ( isThumb && (C & ~255U) == 0) || 1050 (!isThumb && ARM_AM::getSOImmVal(C) != -1); 1051} 1052 1053/// Returns appropriate ARM CMP (cmp) and corresponding condition code for 1054/// the given operands. 1055static SDOperand getARMCmp(SDOperand LHS, SDOperand RHS, ISD::CondCode CC, 1056 SDOperand &ARMCC, SelectionDAG &DAG, bool isThumb) { 1057 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.Val)) { 1058 unsigned C = RHSC->getValue(); 1059 if (!isLegalCmpImmediate(C, isThumb)) { 1060 // Constant does not fit, try adjusting it by one? 1061 switch (CC) { 1062 default: break; 1063 case ISD::SETLT: 1064 case ISD::SETGE: 1065 if (isLegalCmpImmediate(C-1, isThumb)) { 1066 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 1067 RHS = DAG.getConstant(C-1, MVT::i32); 1068 } 1069 break; 1070 case ISD::SETULT: 1071 case ISD::SETUGE: 1072 if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) { 1073 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 1074 RHS = DAG.getConstant(C-1, MVT::i32); 1075 } 1076 break; 1077 case ISD::SETLE: 1078 case ISD::SETGT: 1079 if (isLegalCmpImmediate(C+1, isThumb)) { 1080 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; 1081 RHS = DAG.getConstant(C+1, MVT::i32); 1082 } 1083 break; 1084 case ISD::SETULE: 1085 case ISD::SETUGT: 1086 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb)) { 1087 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 1088 RHS = DAG.getConstant(C+1, MVT::i32); 1089 } 1090 break; 1091 } 1092 } 1093 } 1094 1095 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 1096 ARMISD::NodeType CompareType; 1097 switch (CondCode) { 1098 default: 1099 CompareType = ARMISD::CMP; 1100 break; 1101 case ARMCC::EQ: 1102 case ARMCC::NE: 1103 case ARMCC::MI: 1104 case ARMCC::PL: 1105 // Uses only N and Z Flags 1106 CompareType = ARMISD::CMPNZ; 1107 break; 1108 } 1109 ARMCC = DAG.getConstant(CondCode, MVT::i32); 1110 return DAG.getNode(CompareType, MVT::Flag, LHS, RHS); 1111} 1112 1113/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands. 1114static SDOperand getVFPCmp(SDOperand LHS, SDOperand RHS, SelectionDAG &DAG) { 1115 SDOperand Cmp; 1116 if (!isFloatingPointZero(RHS)) 1117 Cmp = DAG.getNode(ARMISD::CMPFP, MVT::Flag, LHS, RHS); 1118 else 1119 Cmp = DAG.getNode(ARMISD::CMPFPw0, MVT::Flag, LHS); 1120 return DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp); 1121} 1122 1123static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG, 1124 const ARMSubtarget *ST) { 1125 MVT::ValueType VT = Op.getValueType(); 1126 SDOperand LHS = Op.getOperand(0); 1127 SDOperand RHS = Op.getOperand(1); 1128 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 1129 SDOperand TrueVal = Op.getOperand(2); 1130 SDOperand FalseVal = Op.getOperand(3); 1131 1132 if (LHS.getValueType() == MVT::i32) { 1133 SDOperand ARMCC; 1134 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1135 SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb()); 1136 return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, CCR, Cmp); 1137 } 1138 1139 ARMCC::CondCodes CondCode, CondCode2; 1140 if (FPCCToARMCC(CC, CondCode, CondCode2)) 1141 std::swap(TrueVal, FalseVal); 1142 1143 SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32); 1144 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1145 SDOperand Cmp = getVFPCmp(LHS, RHS, DAG); 1146 SDOperand Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, 1147 ARMCC, CCR, Cmp); 1148 if (CondCode2 != ARMCC::AL) { 1149 SDOperand ARMCC2 = DAG.getConstant(CondCode2, MVT::i32); 1150 // FIXME: Needs another CMP because flag can have but one use. 1151 SDOperand Cmp2 = getVFPCmp(LHS, RHS, DAG); 1152 Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, CCR, Cmp2); 1153 } 1154 return Result; 1155} 1156 1157static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG, 1158 const ARMSubtarget *ST) { 1159 SDOperand Chain = Op.getOperand(0); 1160 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 1161 SDOperand LHS = Op.getOperand(2); 1162 SDOperand RHS = Op.getOperand(3); 1163 SDOperand Dest = Op.getOperand(4); 1164 1165 if (LHS.getValueType() == MVT::i32) { 1166 SDOperand ARMCC; 1167 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1168 SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb()); 1169 return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, CCR,Cmp); 1170 } 1171 1172 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); 1173 ARMCC::CondCodes CondCode, CondCode2; 1174 if (FPCCToARMCC(CC, CondCode, CondCode2)) 1175 // Swap the LHS/RHS of the comparison if needed. 1176 std::swap(LHS, RHS); 1177 1178 SDOperand Cmp = getVFPCmp(LHS, RHS, DAG); 1179 SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32); 1180 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1181 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag); 1182 SDOperand Ops[] = { Chain, Dest, ARMCC, CCR, Cmp }; 1183 SDOperand Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5); 1184 if (CondCode2 != ARMCC::AL) { 1185 ARMCC = DAG.getConstant(CondCode2, MVT::i32); 1186 SDOperand Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) }; 1187 Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5); 1188 } 1189 return Res; 1190} 1191 1192SDOperand ARMTargetLowering::LowerBR_JT(SDOperand Op, SelectionDAG &DAG) { 1193 SDOperand Chain = Op.getOperand(0); 1194 SDOperand Table = Op.getOperand(1); 1195 SDOperand Index = Op.getOperand(2); 1196 1197 MVT::ValueType PTy = getPointerTy(); 1198 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); 1199 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>(); 1200 SDOperand UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); 1201 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); 1202 Table = DAG.getNode(ARMISD::WrapperJT, MVT::i32, JTI, UId); 1203 Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy)); 1204 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1205 bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1206 Addr = DAG.getLoad(isPIC ? (MVT::ValueType)MVT::i32 : PTy, 1207 Chain, Addr, NULL, 0); 1208 Chain = Addr.getValue(1); 1209 if (isPIC) 1210 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Table); 1211 return DAG.getNode(ARMISD::BR_JT, MVT::Other, Chain, Addr, JTI, UId); 1212} 1213 1214static SDOperand LowerFP_TO_INT(SDOperand Op, SelectionDAG &DAG) { 1215 unsigned Opc = 1216 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI; 1217 Op = DAG.getNode(Opc, MVT::f32, Op.getOperand(0)); 1218 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 1219} 1220 1221static SDOperand LowerINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { 1222 MVT::ValueType VT = Op.getValueType(); 1223 unsigned Opc = 1224 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF; 1225 1226 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 1227 return DAG.getNode(Opc, VT, Op); 1228} 1229 1230static SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) { 1231 // Implement fcopysign with a fabs and a conditional fneg. 1232 SDOperand Tmp0 = Op.getOperand(0); 1233 SDOperand Tmp1 = Op.getOperand(1); 1234 MVT::ValueType VT = Op.getValueType(); 1235 MVT::ValueType SrcVT = Tmp1.getValueType(); 1236 SDOperand AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0); 1237 SDOperand Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG); 1238 SDOperand ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32); 1239 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1240 return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp); 1241} 1242 1243static SDOperand LowerBIT_CONVERT(SDOperand Op, SelectionDAG &DAG) { 1244 // Turn f64->i64 into FMRRD. 1245 assert(Op.getValueType() == MVT::i64 && 1246 Op.getOperand(0).getValueType() == MVT::f64); 1247 1248 Op = Op.getOperand(0); 1249 SDOperand Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), 1250 &Op, 1); 1251 1252 // Merge the pieces into a single i64 value. 1253 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1)); 1254} 1255 1256static SDOperand LowerSRx(SDOperand Op, SelectionDAG &DAG, 1257 const ARMSubtarget *ST) { 1258 assert(Op.getValueType() == MVT::i64 && 1259 (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) && 1260 "Unknown shift to lower!"); 1261 1262 // We only lower SRA, SRL of 1 here, all others use generic lowering. 1263 if (!isa<ConstantSDNode>(Op.getOperand(1)) || 1264 cast<ConstantSDNode>(Op.getOperand(1))->getValue() != 1) 1265 return SDOperand(); 1266 1267 // If we are in thumb mode, we don't have RRX. 1268 if (ST->isThumb()) return SDOperand(); 1269 1270 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr. 1271 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 1272 DAG.getConstant(0, MVT::i32)); 1273 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 1274 DAG.getConstant(1, MVT::i32)); 1275 1276 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and 1277 // captures the result into a carry flag. 1278 unsigned Opc = Op.getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG; 1279 Hi = DAG.getNode(Opc, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1); 1280 1281 // The low part is an ARMISD::RRX operand, which shifts the carry in. 1282 Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1)); 1283 1284 // Merge the pieces into a single i64 value. 1285 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 1286} 1287 1288SDOperand ARMTargetLowering::LowerMEMCPY(SDOperand Op, SelectionDAG &DAG) { 1289 SDOperand Chain = Op.getOperand(0); 1290 SDOperand Dest = Op.getOperand(1); 1291 SDOperand Src = Op.getOperand(2); 1292 SDOperand Count = Op.getOperand(3); 1293 unsigned Align = 1294 (unsigned)cast<ConstantSDNode>(Op.getOperand(4))->getValue(); 1295 if (Align == 0) Align = 1; 1296 1297 ConstantSDNode *I = dyn_cast<ConstantSDNode>(Count); 1298 // Just call memcpy if: 1299 // not 4-byte aligned 1300 // size is unknown 1301 // size is >= the threshold. 1302 if ((Align & 3) != 0 || 1303 !I || 1304 I->getValue() >= 64 || 1305 (I->getValue() & 3) != 0) { 1306 MVT::ValueType IntPtr = getPointerTy(); 1307 TargetLowering::ArgListTy Args; 1308 TargetLowering::ArgListEntry Entry; 1309 Entry.Ty = getTargetData()->getIntPtrType(); 1310 Entry.Node = Op.getOperand(1); Args.push_back(Entry); 1311 Entry.Node = Op.getOperand(2); Args.push_back(Entry); 1312 Entry.Node = Op.getOperand(3); Args.push_back(Entry); 1313 std::pair<SDOperand,SDOperand> CallResult = 1314 LowerCallTo(Chain, Type::VoidTy, false, false, CallingConv::C, false, 1315 DAG.getExternalSymbol("memcpy", IntPtr), Args, DAG); 1316 return CallResult.second; 1317 } 1318 1319 // Otherwise do repeated 4-byte loads and stores. To be improved. 1320 assert((I->getValue() & 3) == 0); 1321 assert((Align & 3) == 0); 1322 unsigned NumMemOps = I->getValue() >> 2; 1323 unsigned EmittedNumMemOps = 0; 1324 unsigned SrcOff = 0, DstOff = 0; 1325 MVT::ValueType VT = MVT::i32; 1326 unsigned VTSize = 4; 1327 const unsigned MAX_LOADS_IN_LDM = 6; 1328 SDOperand LoadChains[MAX_LOADS_IN_LDM]; 1329 SDOperand Loads[MAX_LOADS_IN_LDM]; 1330 1331 // Emit up to 4 loads, then a TokenFactor barrier, then the same 1332 // number of stores. The loads and stores will get combined into 1333 // ldm/stm later on. 1334 while(EmittedNumMemOps < NumMemOps) { 1335 unsigned i; 1336 for (i=0; i<MAX_LOADS_IN_LDM && EmittedNumMemOps+i < NumMemOps; i++) { 1337 Loads[i] = DAG.getLoad(VT, Chain, 1338 DAG.getNode(ISD::ADD, VT, Src, 1339 DAG.getConstant(SrcOff, VT)), 1340 NULL, 0); 1341 LoadChains[i] = Loads[i].getValue(1); 1342 SrcOff += VTSize; 1343 } 1344 1345 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &LoadChains[0], i); 1346 1347 for (i=0; i<MAX_LOADS_IN_LDM && EmittedNumMemOps+i < NumMemOps; i++) { 1348 Chain = DAG.getStore(Chain, Loads[i], 1349 DAG.getNode(ISD::ADD, VT, Dest, 1350 DAG.getConstant(DstOff, VT)), 1351 NULL, 0); 1352 DstOff += VTSize; 1353 } 1354 EmittedNumMemOps += i; 1355 } 1356 1357 return Chain; 1358} 1359 1360SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 1361 switch (Op.getOpcode()) { 1362 default: assert(0 && "Don't know how to custom lower this!"); abort(); 1363 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 1364 case ISD::GlobalAddress: 1365 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) : 1366 LowerGlobalAddressELF(Op, DAG); 1367 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 1368 case ISD::CALL: return LowerCALL(Op, DAG); 1369 case ISD::RET: return LowerRET(Op, DAG); 1370 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget); 1371 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget); 1372 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 1373 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex); 1374 case ISD::SINT_TO_FP: 1375 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); 1376 case ISD::FP_TO_SINT: 1377 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG); 1378 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 1379 case ISD::BIT_CONVERT: return LowerBIT_CONVERT(Op, DAG); 1380 case ISD::SRL: 1381 case ISD::SRA: return LowerSRx(Op, DAG, Subtarget); 1382 case ISD::FORMAL_ARGUMENTS: 1383 return LowerFORMAL_ARGUMENTS(Op, DAG); 1384 case ISD::RETURNADDR: break; 1385 case ISD::FRAMEADDR: break; 1386 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG); 1387 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG); 1388 } 1389 return SDOperand(); 1390} 1391 1392//===----------------------------------------------------------------------===// 1393// ARM Scheduler Hooks 1394//===----------------------------------------------------------------------===// 1395 1396MachineBasicBlock * 1397ARMTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 1398 MachineBasicBlock *BB) { 1399 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1400 switch (MI->getOpcode()) { 1401 default: assert(false && "Unexpected instr type to insert"); 1402 case ARM::tMOVCCr: { 1403 // To "insert" a SELECT_CC instruction, we actually have to insert the 1404 // diamond control-flow pattern. The incoming instruction knows the 1405 // destination vreg to set, the condition code register to branch on, the 1406 // true/false values to select between, and a branch opcode to use. 1407 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1408 ilist<MachineBasicBlock>::iterator It = BB; 1409 ++It; 1410 1411 // thisMBB: 1412 // ... 1413 // TrueVal = ... 1414 // cmpTY ccX, r1, r2 1415 // bCC copy1MBB 1416 // fallthrough --> copy0MBB 1417 MachineBasicBlock *thisMBB = BB; 1418 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 1419 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 1420 BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB) 1421 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg()); 1422 MachineFunction *F = BB->getParent(); 1423 F->getBasicBlockList().insert(It, copy0MBB); 1424 F->getBasicBlockList().insert(It, sinkMBB); 1425 // Update machine-CFG edges by first adding all successors of the current 1426 // block to the new block which will contain the Phi node for the select. 1427 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 1428 e = BB->succ_end(); i != e; ++i) 1429 sinkMBB->addSuccessor(*i); 1430 // Next, remove all successors of the current block, and add the true 1431 // and fallthrough blocks as its successors. 1432 while(!BB->succ_empty()) 1433 BB->removeSuccessor(BB->succ_begin()); 1434 BB->addSuccessor(copy0MBB); 1435 BB->addSuccessor(sinkMBB); 1436 1437 // copy0MBB: 1438 // %FalseValue = ... 1439 // # fallthrough to sinkMBB 1440 BB = copy0MBB; 1441 1442 // Update machine-CFG edges 1443 BB->addSuccessor(sinkMBB); 1444 1445 // sinkMBB: 1446 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1447 // ... 1448 BB = sinkMBB; 1449 BuildMI(BB, TII->get(ARM::PHI), MI->getOperand(0).getReg()) 1450 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 1451 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 1452 1453 delete MI; // The pseudo instruction is gone now. 1454 return BB; 1455 } 1456 } 1457} 1458 1459//===----------------------------------------------------------------------===// 1460// ARM Optimization Hooks 1461//===----------------------------------------------------------------------===// 1462 1463/// isLegalAddressImmediate - Return true if the integer value can be used 1464/// as the offset of the target addressing mode for load / store of the 1465/// given type. 1466static bool isLegalAddressImmediate(int64_t V, MVT::ValueType VT, 1467 const ARMSubtarget *Subtarget) { 1468 if (V == 0) 1469 return true; 1470 1471 if (Subtarget->isThumb()) { 1472 if (V < 0) 1473 return false; 1474 1475 unsigned Scale = 1; 1476 switch (VT) { 1477 default: return false; 1478 case MVT::i1: 1479 case MVT::i8: 1480 // Scale == 1; 1481 break; 1482 case MVT::i16: 1483 // Scale == 2; 1484 Scale = 2; 1485 break; 1486 case MVT::i32: 1487 // Scale == 4; 1488 Scale = 4; 1489 break; 1490 } 1491 1492 if ((V & (Scale - 1)) != 0) 1493 return false; 1494 V /= Scale; 1495 return V == V & ((1LL << 5) - 1); 1496 } 1497 1498 if (V < 0) 1499 V = - V; 1500 switch (VT) { 1501 default: return false; 1502 case MVT::i1: 1503 case MVT::i8: 1504 case MVT::i32: 1505 // +- imm12 1506 return V == V & ((1LL << 12) - 1); 1507 case MVT::i16: 1508 // +- imm8 1509 return V == V & ((1LL << 8) - 1); 1510 case MVT::f32: 1511 case MVT::f64: 1512 if (!Subtarget->hasVFP2()) 1513 return false; 1514 if ((V & 3) != 0) 1515 return false; 1516 V >>= 2; 1517 return V == V & ((1LL << 8) - 1); 1518 } 1519} 1520 1521/// isLegalAddressingMode - Return true if the addressing mode represented 1522/// by AM is legal for this target, for a load/store of the specified type. 1523bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM, 1524 const Type *Ty) const { 1525 if (!isLegalAddressImmediate(AM.BaseOffs, getValueType(Ty), Subtarget)) 1526 return false; 1527 1528 // Can never fold addr of global into load/store. 1529 if (AM.BaseGV) 1530 return false; 1531 1532 switch (AM.Scale) { 1533 case 0: // no scale reg, must be "r+i" or "r", or "i". 1534 break; 1535 case 1: 1536 if (Subtarget->isThumb()) 1537 return false; 1538 // FALL THROUGH. 1539 default: 1540 // ARM doesn't support any R+R*scale+imm addr modes. 1541 if (AM.BaseOffs) 1542 return false; 1543 1544 int Scale = AM.Scale; 1545 switch (getValueType(Ty)) { 1546 default: return false; 1547 case MVT::i1: 1548 case MVT::i8: 1549 case MVT::i32: 1550 case MVT::i64: 1551 // This assumes i64 is legalized to a pair of i32. If not (i.e. 1552 // ldrd / strd are used, then its address mode is same as i16. 1553 // r + r 1554 if (Scale < 0) Scale = -Scale; 1555 if (Scale == 1) 1556 return true; 1557 // r + r << imm 1558 return isPowerOf2_32(Scale & ~1); 1559 case MVT::i16: 1560 // r + r 1561 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 1562 return true; 1563 return false; 1564 1565 case MVT::isVoid: 1566 // Note, we allow "void" uses (basically, uses that aren't loads or 1567 // stores), because arm allows folding a scale into many arithmetic 1568 // operations. This should be made more precise and revisited later. 1569 1570 // Allow r << imm, but the imm has to be a multiple of two. 1571 if (AM.Scale & 1) return false; 1572 return isPowerOf2_32(AM.Scale); 1573 } 1574 break; 1575 } 1576 return true; 1577} 1578 1579 1580static bool getIndexedAddressParts(SDNode *Ptr, MVT::ValueType VT, 1581 bool isSEXTLoad, SDOperand &Base, 1582 SDOperand &Offset, bool &isInc, 1583 SelectionDAG &DAG) { 1584 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 1585 return false; 1586 1587 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { 1588 // AddressingMode 3 1589 Base = Ptr->getOperand(0); 1590 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 1591 int RHSC = (int)RHS->getValue(); 1592 if (RHSC < 0 && RHSC > -256) { 1593 isInc = false; 1594 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 1595 return true; 1596 } 1597 } 1598 isInc = (Ptr->getOpcode() == ISD::ADD); 1599 Offset = Ptr->getOperand(1); 1600 return true; 1601 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) { 1602 // AddressingMode 2 1603 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 1604 int RHSC = (int)RHS->getValue(); 1605 if (RHSC < 0 && RHSC > -0x1000) { 1606 isInc = false; 1607 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 1608 Base = Ptr->getOperand(0); 1609 return true; 1610 } 1611 } 1612 1613 if (Ptr->getOpcode() == ISD::ADD) { 1614 isInc = true; 1615 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0)); 1616 if (ShOpcVal != ARM_AM::no_shift) { 1617 Base = Ptr->getOperand(1); 1618 Offset = Ptr->getOperand(0); 1619 } else { 1620 Base = Ptr->getOperand(0); 1621 Offset = Ptr->getOperand(1); 1622 } 1623 return true; 1624 } 1625 1626 isInc = (Ptr->getOpcode() == ISD::ADD); 1627 Base = Ptr->getOperand(0); 1628 Offset = Ptr->getOperand(1); 1629 return true; 1630 } 1631 1632 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store. 1633 return false; 1634} 1635 1636/// getPreIndexedAddressParts - returns true by value, base pointer and 1637/// offset pointer and addressing mode by reference if the node's address 1638/// can be legally represented as pre-indexed load / store address. 1639bool 1640ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base, 1641 SDOperand &Offset, 1642 ISD::MemIndexedMode &AM, 1643 SelectionDAG &DAG) { 1644 if (Subtarget->isThumb()) 1645 return false; 1646 1647 MVT::ValueType VT; 1648 SDOperand Ptr; 1649 bool isSEXTLoad = false; 1650 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1651 Ptr = LD->getBasePtr(); 1652 VT = LD->getLoadedVT(); 1653 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 1654 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1655 Ptr = ST->getBasePtr(); 1656 VT = ST->getStoredVT(); 1657 } else 1658 return false; 1659 1660 bool isInc; 1661 bool isLegal = getIndexedAddressParts(Ptr.Val, VT, isSEXTLoad, Base, Offset, 1662 isInc, DAG); 1663 if (isLegal) { 1664 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC; 1665 return true; 1666 } 1667 return false; 1668} 1669 1670/// getPostIndexedAddressParts - returns true by value, base pointer and 1671/// offset pointer and addressing mode by reference if this node can be 1672/// combined with a load / store to form a post-indexed load / store. 1673bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 1674 SDOperand &Base, 1675 SDOperand &Offset, 1676 ISD::MemIndexedMode &AM, 1677 SelectionDAG &DAG) { 1678 if (Subtarget->isThumb()) 1679 return false; 1680 1681 MVT::ValueType VT; 1682 SDOperand Ptr; 1683 bool isSEXTLoad = false; 1684 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1685 VT = LD->getLoadedVT(); 1686 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 1687 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1688 VT = ST->getStoredVT(); 1689 } else 1690 return false; 1691 1692 bool isInc; 1693 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 1694 isInc, DAG); 1695 if (isLegal) { 1696 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; 1697 return true; 1698 } 1699 return false; 1700} 1701 1702void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 1703 uint64_t Mask, 1704 uint64_t &KnownZero, 1705 uint64_t &KnownOne, 1706 const SelectionDAG &DAG, 1707 unsigned Depth) const { 1708 KnownZero = 0; 1709 KnownOne = 0; 1710 switch (Op.getOpcode()) { 1711 default: break; 1712 case ARMISD::CMOV: { 1713 // Bits are known zero/one if known on the LHS and RHS. 1714 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 1715 if (KnownZero == 0 && KnownOne == 0) return; 1716 1717 uint64_t KnownZeroRHS, KnownOneRHS; 1718 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, 1719 KnownZeroRHS, KnownOneRHS, Depth+1); 1720 KnownZero &= KnownZeroRHS; 1721 KnownOne &= KnownOneRHS; 1722 return; 1723 } 1724 } 1725} 1726 1727//===----------------------------------------------------------------------===// 1728// ARM Inline Assembly Support 1729//===----------------------------------------------------------------------===// 1730 1731/// getConstraintType - Given a constraint letter, return the type of 1732/// constraint it is for this target. 1733ARMTargetLowering::ConstraintType 1734ARMTargetLowering::getConstraintType(const std::string &Constraint) const { 1735 if (Constraint.size() == 1) { 1736 switch (Constraint[0]) { 1737 default: break; 1738 case 'l': return C_RegisterClass; 1739 case 'w': return C_RegisterClass; 1740 } 1741 } 1742 return TargetLowering::getConstraintType(Constraint); 1743} 1744 1745std::pair<unsigned, const TargetRegisterClass*> 1746ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 1747 MVT::ValueType VT) const { 1748 if (Constraint.size() == 1) { 1749 // GCC RS6000 Constraint Letters 1750 switch (Constraint[0]) { 1751 case 'l': 1752 // FIXME: in thumb mode, 'l' is only low-regs. 1753 // FALL THROUGH. 1754 case 'r': 1755 return std::make_pair(0U, ARM::GPRRegisterClass); 1756 case 'w': 1757 if (VT == MVT::f32) 1758 return std::make_pair(0U, ARM::SPRRegisterClass); 1759 if (VT == MVT::f64) 1760 return std::make_pair(0U, ARM::DPRRegisterClass); 1761 break; 1762 } 1763 } 1764 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 1765} 1766 1767std::vector<unsigned> ARMTargetLowering:: 1768getRegClassForInlineAsmConstraint(const std::string &Constraint, 1769 MVT::ValueType VT) const { 1770 if (Constraint.size() != 1) 1771 return std::vector<unsigned>(); 1772 1773 switch (Constraint[0]) { // GCC ARM Constraint Letters 1774 default: break; 1775 case 'l': 1776 case 'r': 1777 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1778 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1779 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1780 ARM::R12, ARM::LR, 0); 1781 case 'w': 1782 if (VT == MVT::f32) 1783 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1784 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1785 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1786 ARM::S12,ARM::S13,ARM::S14,ARM::S15, 1787 ARM::S16,ARM::S17,ARM::S18,ARM::S19, 1788 ARM::S20,ARM::S21,ARM::S22,ARM::S23, 1789 ARM::S24,ARM::S25,ARM::S26,ARM::S27, 1790 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0); 1791 if (VT == MVT::f64) 1792 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1793 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1794 ARM::D8, ARM::D9, ARM::D10,ARM::D11, 1795 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0); 1796 break; 1797 } 1798 1799 return std::vector<unsigned>(); 1800} 1801