ARMJITInfo.cpp revision 108c838093704650378b194fe9afc5ebb9e91455
1//===-- ARMJITInfo.cpp - Implement the JIT interfaces for the ARM target --===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the JIT interfaces for the ARM target. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "jit" 15#include "ARMJITInfo.h" 16#include "ARMInstrInfo.h" 17#include "ARMConstantPoolValue.h" 18#include "ARMRelocations.h" 19#include "ARMSubtarget.h" 20#include "llvm/Function.h" 21#include "llvm/CodeGen/JITCodeEmitter.h" 22#include "llvm/Support/Debug.h" 23#include "llvm/Support/ErrorHandling.h" 24#include "llvm/Support/raw_ostream.h" 25#include "llvm/System/Memory.h" 26#include <cstdlib> 27using namespace llvm; 28 29void ARMJITInfo::replaceMachineCodeForFunction(void *Old, void *New) { 30 llvm_report_error("ARMJITInfo::replaceMachineCodeForFunction"); 31} 32 33/// JITCompilerFunction - This contains the address of the JIT function used to 34/// compile a function lazily. 35static TargetJITInfo::JITCompilerFn JITCompilerFunction; 36 37// Get the ASMPREFIX for the current host. This is often '_'. 38#ifndef __USER_LABEL_PREFIX__ 39#define __USER_LABEL_PREFIX__ 40#endif 41#define GETASMPREFIX2(X) #X 42#define GETASMPREFIX(X) GETASMPREFIX2(X) 43#define ASMPREFIX GETASMPREFIX(__USER_LABEL_PREFIX__) 44 45// CompilationCallback stub - We can't use a C function with inline assembly in 46// it, because we the prolog/epilog inserted by GCC won't work for us (we need 47// to preserve more context and manipulate the stack directly). Instead, 48// write our own wrapper, which does things our way, so we have complete 49// control over register saving and restoring. 50extern "C" { 51#if defined(__arm__) 52 void ARMCompilationCallback(); 53 asm( 54 ".text\n" 55 ".align 2\n" 56 ".globl " ASMPREFIX "ARMCompilationCallback\n" 57 ASMPREFIX "ARMCompilationCallback:\n" 58 // Save caller saved registers since they may contain stuff 59 // for the real target function right now. We have to act as if this 60 // whole compilation callback doesn't exist as far as the caller is 61 // concerned, so we can't just preserve the callee saved regs. 62 "stmdb sp!, {r0, r1, r2, r3, lr}\n" 63#ifndef __SOFTFP__ 64 "fstmfdd sp!, {d0, d1, d2, d3, d4, d5, d6, d7}\n" 65#endif 66 // The LR contains the address of the stub function on entry. 67 // pass it as the argument to the C part of the callback 68 "mov r0, lr\n" 69 "sub sp, sp, #4\n" 70 // Call the C portion of the callback 71 "bl " ASMPREFIX "ARMCompilationCallbackC\n" 72 "add sp, sp, #4\n" 73 // Restoring the LR to the return address of the function that invoked 74 // the stub and de-allocating the stack space for it requires us to 75 // swap the two saved LR values on the stack, as they're backwards 76 // for what we need since the pop instruction has a pre-determined 77 // order for the registers. 78 // +--------+ 79 // 0 | LR | Original return address 80 // +--------+ 81 // 1 | LR | Stub address (start of stub) 82 // 2-5 | R3..R0 | Saved registers (we need to preserve all regs) 83 // 6-20 | D0..D7 | Saved VFP registers 84 // +--------+ 85 // 86#ifndef __SOFTFP__ 87 // Restore VFP caller-saved registers. 88 "fldmfdd sp!, {d0, d1, d2, d3, d4, d5, d6, d7}\n" 89#endif 90 // 91 // We need to exchange the values in slots 0 and 1 so we can 92 // return to the address in slot 1 with the address in slot 0 93 // restored to the LR. 94 "ldr r0, [sp,#20]\n" 95 "ldr r1, [sp,#16]\n" 96 "str r1, [sp,#20]\n" 97 "str r0, [sp,#16]\n" 98 // Return to the (newly modified) stub to invoke the real function. 99 // The above twiddling of the saved return addresses allows us to 100 // deallocate everything, including the LR the stub saved, all in one 101 // pop instruction. 102 "ldmia sp!, {r0, r1, r2, r3, lr, pc}\n" 103 ); 104#else // Not an ARM host 105 void ARMCompilationCallback() { 106 llvm_unreachable("Cannot call ARMCompilationCallback() on a non-ARM arch!"); 107 } 108#endif 109} 110 111/// ARMCompilationCallbackC - This is the target-specific function invoked 112/// by the function stub when we did not know the real target of a call. 113/// This function must locate the start of the stub or call site and pass 114/// it into the JIT compiler function. 115extern "C" void ARMCompilationCallbackC(intptr_t StubAddr) { 116 // Get the address of the compiled code for this function. 117 intptr_t NewVal = (intptr_t)JITCompilerFunction((void*)StubAddr); 118 119 // Rewrite the call target... so that we don't end up here every time we 120 // execute the call. We're replacing the first two instructions of the 121 // stub with: 122 // ldr pc, [pc,#-4] 123 // <addr> 124 if (!sys::Memory::setRangeWritable((void*)StubAddr, 8)) { 125 llvm_unreachable("ERROR: Unable to mark stub writable"); 126 } 127 *(intptr_t *)StubAddr = 0xe51ff004; // ldr pc, [pc, #-4] 128 *(intptr_t *)(StubAddr+4) = NewVal; 129 if (!sys::Memory::setRangeExecutable((void*)StubAddr, 8)) { 130 llvm_unreachable("ERROR: Unable to mark stub executable"); 131 } 132} 133 134TargetJITInfo::LazyResolverFn 135ARMJITInfo::getLazyResolverFunction(JITCompilerFn F) { 136 JITCompilerFunction = F; 137 return ARMCompilationCallback; 138} 139 140void *ARMJITInfo::emitGlobalValueIndirectSym(const GlobalValue *GV, void *Ptr, 141 JITCodeEmitter &JCE) { 142 MachineCodeEmitter::BufferState BS; 143 JCE.startGVStub(BS, GV, 4, 4); 144 intptr_t Addr = (intptr_t)JCE.getCurrentPCValue(); 145 if (!sys::Memory::setRangeWritable((void*)Addr, 4)) { 146 llvm_unreachable("ERROR: Unable to mark indirect symbol writable"); 147 } 148 JCE.emitWordLE((intptr_t)Ptr); 149 if (!sys::Memory::setRangeExecutable((void*)Addr, 4)) { 150 llvm_unreachable("ERROR: Unable to mark indirect symbol executable"); 151 } 152 void *PtrAddr = JCE.finishGVStub(BS); 153 addIndirectSymAddr(Ptr, (intptr_t)PtrAddr); 154 return PtrAddr; 155} 156 157TargetJITInfo::StubLayout ARMJITInfo::getStubLayout() { 158 // The stub contains up to 3 4-byte instructions, aligned at 4 bytes, and a 159 // 4-byte address. See emitFunctionStub for details. 160 StubLayout Result = {16, 4}; 161 return Result; 162} 163 164void *ARMJITInfo::emitFunctionStub(const Function* F, void *Fn, 165 JITCodeEmitter &JCE) { 166 void *Addr; 167 // If this is just a call to an external function, emit a branch instead of a 168 // call. The code is the same except for one bit of the last instruction. 169 if (Fn != (void*)(intptr_t)ARMCompilationCallback) { 170 // Branch to the corresponding function addr. 171 if (IsPIC) { 172 // The stub is 16-byte size and 4-aligned. 173 intptr_t LazyPtr = getIndirectSymAddr(Fn); 174 if (!LazyPtr) { 175 // In PIC mode, the function stub is loading a lazy-ptr. 176 LazyPtr= (intptr_t)emitGlobalValueIndirectSym((GlobalValue*)F, Fn, JCE); 177 DEBUG(if (F) 178 errs() << "JIT: Indirect symbol emitted at [" << LazyPtr 179 << "] for GV '" << F->getName() << "'\n"; 180 else 181 errs() << "JIT: Stub emitted at [" << LazyPtr 182 << "] for external function at '" << Fn << "'\n"); 183 } 184 JCE.emitAlignment(4); 185 Addr = (void*)JCE.getCurrentPCValue(); 186 if (!sys::Memory::setRangeWritable(Addr, 16)) { 187 llvm_unreachable("ERROR: Unable to mark stub writable"); 188 } 189 JCE.emitWordLE(0xe59fc004); // ldr ip, [pc, #+4] 190 JCE.emitWordLE(0xe08fc00c); // L_func$scv: add ip, pc, ip 191 JCE.emitWordLE(0xe59cf000); // ldr pc, [ip] 192 JCE.emitWordLE(LazyPtr - (intptr_t(Addr)+4+8)); // func - (L_func$scv+8) 193 sys::Memory::InvalidateInstructionCache(Addr, 16); 194 if (!sys::Memory::setRangeExecutable(Addr, 16)) { 195 llvm_unreachable("ERROR: Unable to mark stub executable"); 196 } 197 } else { 198 // The stub is 8-byte size and 4-aligned. 199 JCE.emitAlignment(4); 200 Addr = (void*)JCE.getCurrentPCValue(); 201 if (!sys::Memory::setRangeWritable(Addr, 8)) { 202 llvm_unreachable("ERROR: Unable to mark stub writable"); 203 } 204 JCE.emitWordLE(0xe51ff004); // ldr pc, [pc, #-4] 205 JCE.emitWordLE((intptr_t)Fn); // addr of function 206 sys::Memory::InvalidateInstructionCache(Addr, 8); 207 if (!sys::Memory::setRangeExecutable(Addr, 8)) { 208 llvm_unreachable("ERROR: Unable to mark stub executable"); 209 } 210 } 211 } else { 212 // The compilation callback will overwrite the first two words of this 213 // stub with indirect branch instructions targeting the compiled code. 214 // This stub sets the return address to restart the stub, so that 215 // the new branch will be invoked when we come back. 216 // 217 // Branch and link to the compilation callback. 218 // The stub is 16-byte size and 4-byte aligned. 219 JCE.emitAlignment(4); 220 Addr = (void*)JCE.getCurrentPCValue(); 221 if (!sys::Memory::setRangeWritable(Addr, 16)) { 222 llvm_unreachable("ERROR: Unable to mark stub writable"); 223 } 224 // Save LR so the callback can determine which stub called it. 225 // The compilation callback is responsible for popping this prior 226 // to returning. 227 JCE.emitWordLE(0xe92d4000); // push {lr} 228 // Set the return address to go back to the start of this stub. 229 JCE.emitWordLE(0xe24fe00c); // sub lr, pc, #12 230 // Invoke the compilation callback. 231 JCE.emitWordLE(0xe51ff004); // ldr pc, [pc, #-4] 232 // The address of the compilation callback. 233 JCE.emitWordLE((intptr_t)ARMCompilationCallback); 234 sys::Memory::InvalidateInstructionCache(Addr, 16); 235 if (!sys::Memory::setRangeExecutable(Addr, 16)) { 236 llvm_unreachable("ERROR: Unable to mark stub executable"); 237 } 238 } 239 240 return Addr; 241} 242 243intptr_t ARMJITInfo::resolveRelocDestAddr(MachineRelocation *MR) const { 244 ARM::RelocationType RT = (ARM::RelocationType)MR->getRelocationType(); 245 switch (RT) { 246 default: 247 return (intptr_t)(MR->getResultPointer()); 248 case ARM::reloc_arm_pic_jt: 249 // Destination address - jump table base. 250 return (intptr_t)(MR->getResultPointer()) - MR->getConstantVal(); 251 case ARM::reloc_arm_jt_base: 252 // Jump table base address. 253 return getJumpTableBaseAddr(MR->getJumpTableIndex()); 254 case ARM::reloc_arm_cp_entry: 255 case ARM::reloc_arm_vfp_cp_entry: 256 // Constant pool entry address. 257 return getConstantPoolEntryAddr(MR->getConstantPoolIndex()); 258 case ARM::reloc_arm_machine_cp_entry: { 259 ARMConstantPoolValue *ACPV = (ARMConstantPoolValue*)MR->getConstantVal(); 260 assert((!ACPV->hasModifier() && !ACPV->mustAddCurrentAddress()) && 261 "Can't handle this machine constant pool entry yet!"); 262 intptr_t Addr = (intptr_t)(MR->getResultPointer()); 263 Addr -= getPCLabelAddr(ACPV->getLabelId()) + ACPV->getPCAdjustment(); 264 return Addr; 265 } 266 } 267} 268 269/// relocate - Before the JIT can run a block of code that has been emitted, 270/// it must rewrite the code to contain the actual addresses of any 271/// referenced global symbols. 272void ARMJITInfo::relocate(void *Function, MachineRelocation *MR, 273 unsigned NumRelocs, unsigned char* GOTBase) { 274 for (unsigned i = 0; i != NumRelocs; ++i, ++MR) { 275 void *RelocPos = (char*)Function + MR->getMachineCodeOffset(); 276 intptr_t ResultPtr = resolveRelocDestAddr(MR); 277 switch ((ARM::RelocationType)MR->getRelocationType()) { 278 case ARM::reloc_arm_cp_entry: 279 case ARM::reloc_arm_vfp_cp_entry: 280 case ARM::reloc_arm_relative: { 281 // It is necessary to calculate the correct PC relative value. We 282 // subtract the base addr from the target addr to form a byte offset. 283 ResultPtr = ResultPtr - (intptr_t)RelocPos - 8; 284 // If the result is positive, set bit U(23) to 1. 285 if (ResultPtr >= 0) 286 *((intptr_t*)RelocPos) |= 1 << ARMII::U_BitShift; 287 else { 288 // Otherwise, obtain the absolute value and set bit U(23) to 0. 289 *((intptr_t*)RelocPos) &= ~(1 << ARMII::U_BitShift); 290 ResultPtr = - ResultPtr; 291 } 292 // Set the immed value calculated. 293 // VFP immediate offset is multiplied by 4. 294 if (MR->getRelocationType() == ARM::reloc_arm_vfp_cp_entry) 295 ResultPtr = ResultPtr >> 2; 296 *((intptr_t*)RelocPos) |= ResultPtr; 297 // Set register Rn to PC. 298 *((intptr_t*)RelocPos) |= 299 ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift; 300 break; 301 } 302 case ARM::reloc_arm_pic_jt: 303 case ARM::reloc_arm_machine_cp_entry: 304 case ARM::reloc_arm_absolute: { 305 // These addresses have already been resolved. 306 *((intptr_t*)RelocPos) |= (intptr_t)ResultPtr; 307 break; 308 } 309 case ARM::reloc_arm_branch: { 310 // It is necessary to calculate the correct value of signed_immed_24 311 // field. We subtract the base addr from the target addr to form a 312 // byte offset, which must be inside the range -33554432 and +33554428. 313 // Then, we set the signed_immed_24 field of the instruction to bits 314 // [25:2] of the byte offset. More details ARM-ARM p. A4-11. 315 ResultPtr = ResultPtr - (intptr_t)RelocPos - 8; 316 ResultPtr = (ResultPtr & 0x03FFFFFC) >> 2; 317 assert(ResultPtr >= -33554432 && ResultPtr <= 33554428); 318 *((intptr_t*)RelocPos) |= ResultPtr; 319 break; 320 } 321 case ARM::reloc_arm_jt_base: { 322 // JT base - (instruction addr + 8) 323 ResultPtr = ResultPtr - (intptr_t)RelocPos - 8; 324 *((intptr_t*)RelocPos) |= ResultPtr; 325 break; 326 } 327 } 328 } 329} 330