ARMAsmParser.cpp revision 251bf25e7ee9702fed2a66deeb404ce473f7bac1
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#include "MCTargetDesc/ARMBaseInfo.h" 11#include "MCTargetDesc/ARMAddressingModes.h" 12#include "MCTargetDesc/ARMMCExpr.h" 13#include "llvm/MC/MCParser/MCAsmLexer.h" 14#include "llvm/MC/MCParser/MCAsmParser.h" 15#include "llvm/MC/MCParser/MCParsedAsmOperand.h" 16#include "llvm/MC/MCAsmInfo.h" 17#include "llvm/MC/MCContext.h" 18#include "llvm/MC/MCStreamer.h" 19#include "llvm/MC/MCExpr.h" 20#include "llvm/MC/MCInst.h" 21#include "llvm/MC/MCRegisterInfo.h" 22#include "llvm/MC/MCSubtargetInfo.h" 23#include "llvm/MC/MCTargetAsmParser.h" 24#include "llvm/Target/TargetRegistry.h" 25#include "llvm/Support/SourceMgr.h" 26#include "llvm/Support/raw_ostream.h" 27#include "llvm/ADT/OwningPtr.h" 28#include "llvm/ADT/STLExtras.h" 29#include "llvm/ADT/SmallVector.h" 30#include "llvm/ADT/StringExtras.h" 31#include "llvm/ADT/StringSwitch.h" 32#include "llvm/ADT/Twine.h" 33 34using namespace llvm; 35 36namespace { 37 38class ARMOperand; 39 40class ARMAsmParser : public MCTargetAsmParser { 41 MCSubtargetInfo &STI; 42 MCAsmParser &Parser; 43 44 MCAsmParser &getParser() const { return Parser; } 45 MCAsmLexer &getLexer() const { return Parser.getLexer(); } 46 47 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); } 48 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); } 49 50 int tryParseRegister(); 51 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &); 52 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &); 53 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &); 54 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &); 55 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic); 56 bool parsePrefix(ARMMCExpr::VariantKind &RefKind); 57 const MCExpr *applyPrefixToExpr(const MCExpr *E, 58 MCSymbolRefExpr::VariantKind Variant); 59 60 61 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, 62 unsigned &ShiftAmount); 63 bool parseDirectiveWord(unsigned Size, SMLoc L); 64 bool parseDirectiveThumb(SMLoc L); 65 bool parseDirectiveThumbFunc(SMLoc L); 66 bool parseDirectiveCode(SMLoc L); 67 bool parseDirectiveSyntax(SMLoc L); 68 69 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, 70 bool &CarrySetting, unsigned &ProcessorIMod); 71 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 72 bool &CanAcceptPredicationCode); 73 74 bool isThumb() const { 75 // FIXME: Can tablegen auto-generate this? 76 return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 77 } 78 bool isThumbOne() const { 79 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0; 80 } 81 void SwitchMode() { 82 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); 83 setAvailableFeatures(FB); 84 } 85 86 /// @name Auto-generated Match Functions 87 /// { 88 89#define GET_ASSEMBLER_HEADER 90#include "ARMGenAsmMatcher.inc" 91 92 /// } 93 94 OperandMatchResultTy parseCoprocNumOperand( 95 SmallVectorImpl<MCParsedAsmOperand*>&); 96 OperandMatchResultTy parseCoprocRegOperand( 97 SmallVectorImpl<MCParsedAsmOperand*>&); 98 OperandMatchResultTy parseMemBarrierOptOperand( 99 SmallVectorImpl<MCParsedAsmOperand*>&); 100 OperandMatchResultTy parseProcIFlagsOperand( 101 SmallVectorImpl<MCParsedAsmOperand*>&); 102 OperandMatchResultTy parseMSRMaskOperand( 103 SmallVectorImpl<MCParsedAsmOperand*>&); 104 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O, 105 StringRef Op, int Low, int High); 106 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 107 return parsePKHImm(O, "lsl", 0, 31); 108 } 109 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 110 return parsePKHImm(O, "asr", 1, 32); 111 } 112 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&); 113 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&); 114 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&); 115 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&); 116 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&); 117 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&); 118 119 // Asm Match Converter Methods 120 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 121 const SmallVectorImpl<MCParsedAsmOperand*> &); 122 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 123 const SmallVectorImpl<MCParsedAsmOperand*> &); 124 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 125 const SmallVectorImpl<MCParsedAsmOperand*> &); 126 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 127 const SmallVectorImpl<MCParsedAsmOperand*> &); 128 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 129 const SmallVectorImpl<MCParsedAsmOperand*> &); 130 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 131 const SmallVectorImpl<MCParsedAsmOperand*> &); 132 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode, 133 const SmallVectorImpl<MCParsedAsmOperand*> &); 134 135 bool validateInstruction(MCInst &Inst, 136 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 137 138public: 139 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser) 140 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) { 141 MCAsmParserExtension::Initialize(_Parser); 142 143 // Initialize the set of available features. 144 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 145 } 146 147 // Implementation of the MCTargetAsmParser interface: 148 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); 149 bool ParseInstruction(StringRef Name, SMLoc NameLoc, 150 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 151 bool ParseDirective(AsmToken DirectiveID); 152 153 bool MatchAndEmitInstruction(SMLoc IDLoc, 154 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 155 MCStreamer &Out); 156}; 157} // end anonymous namespace 158 159namespace { 160 161/// ARMOperand - Instances of this class represent a parsed ARM machine 162/// instruction. 163class ARMOperand : public MCParsedAsmOperand { 164 enum KindTy { 165 CondCode, 166 CCOut, 167 CoprocNum, 168 CoprocReg, 169 Immediate, 170 MemBarrierOpt, 171 Memory, 172 PostIndexRegister, 173 MSRMask, 174 ProcIFlags, 175 Register, 176 RegisterList, 177 DPRRegisterList, 178 SPRRegisterList, 179 ShiftedRegister, 180 ShiftedImmediate, 181 ShifterImmediate, 182 RotateImmediate, 183 BitfieldDescriptor, 184 Token 185 } Kind; 186 187 SMLoc StartLoc, EndLoc; 188 SmallVector<unsigned, 8> Registers; 189 190 union { 191 struct { 192 ARMCC::CondCodes Val; 193 } CC; 194 195 struct { 196 ARM_MB::MemBOpt Val; 197 } MBOpt; 198 199 struct { 200 unsigned Val; 201 } Cop; 202 203 struct { 204 ARM_PROC::IFlags Val; 205 } IFlags; 206 207 struct { 208 unsigned Val; 209 } MMask; 210 211 struct { 212 const char *Data; 213 unsigned Length; 214 } Tok; 215 216 struct { 217 unsigned RegNum; 218 } Reg; 219 220 struct { 221 const MCExpr *Val; 222 } Imm; 223 224 /// Combined record for all forms of ARM address expressions. 225 struct { 226 unsigned BaseRegNum; 227 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset 228 // was specified. 229 const MCConstantExpr *OffsetImm; // Offset immediate value 230 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL 231 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg 232 unsigned ShiftImm; // shift for OffsetReg. 233 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit) 234 } Mem; 235 236 struct { 237 unsigned RegNum; 238 bool isAdd; 239 ARM_AM::ShiftOpc ShiftTy; 240 unsigned ShiftImm; 241 } PostIdxReg; 242 243 struct { 244 bool isASR; 245 unsigned Imm; 246 } ShifterImm; 247 struct { 248 ARM_AM::ShiftOpc ShiftTy; 249 unsigned SrcReg; 250 unsigned ShiftReg; 251 unsigned ShiftImm; 252 } RegShiftedReg; 253 struct { 254 ARM_AM::ShiftOpc ShiftTy; 255 unsigned SrcReg; 256 unsigned ShiftImm; 257 } RegShiftedImm; 258 struct { 259 unsigned Imm; 260 } RotImm; 261 struct { 262 unsigned LSB; 263 unsigned Width; 264 } Bitfield; 265 }; 266 267 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 268public: 269 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() { 270 Kind = o.Kind; 271 StartLoc = o.StartLoc; 272 EndLoc = o.EndLoc; 273 switch (Kind) { 274 case CondCode: 275 CC = o.CC; 276 break; 277 case Token: 278 Tok = o.Tok; 279 break; 280 case CCOut: 281 case Register: 282 Reg = o.Reg; 283 break; 284 case RegisterList: 285 case DPRRegisterList: 286 case SPRRegisterList: 287 Registers = o.Registers; 288 break; 289 case CoprocNum: 290 case CoprocReg: 291 Cop = o.Cop; 292 break; 293 case Immediate: 294 Imm = o.Imm; 295 break; 296 case MemBarrierOpt: 297 MBOpt = o.MBOpt; 298 break; 299 case Memory: 300 Mem = o.Mem; 301 break; 302 case PostIndexRegister: 303 PostIdxReg = o.PostIdxReg; 304 break; 305 case MSRMask: 306 MMask = o.MMask; 307 break; 308 case ProcIFlags: 309 IFlags = o.IFlags; 310 break; 311 case ShifterImmediate: 312 ShifterImm = o.ShifterImm; 313 break; 314 case ShiftedRegister: 315 RegShiftedReg = o.RegShiftedReg; 316 break; 317 case ShiftedImmediate: 318 RegShiftedImm = o.RegShiftedImm; 319 break; 320 case RotateImmediate: 321 RotImm = o.RotImm; 322 break; 323 case BitfieldDescriptor: 324 Bitfield = o.Bitfield; 325 break; 326 } 327 } 328 329 /// getStartLoc - Get the location of the first token of this operand. 330 SMLoc getStartLoc() const { return StartLoc; } 331 /// getEndLoc - Get the location of the last token of this operand. 332 SMLoc getEndLoc() const { return EndLoc; } 333 334 ARMCC::CondCodes getCondCode() const { 335 assert(Kind == CondCode && "Invalid access!"); 336 return CC.Val; 337 } 338 339 unsigned getCoproc() const { 340 assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!"); 341 return Cop.Val; 342 } 343 344 StringRef getToken() const { 345 assert(Kind == Token && "Invalid access!"); 346 return StringRef(Tok.Data, Tok.Length); 347 } 348 349 unsigned getReg() const { 350 assert((Kind == Register || Kind == CCOut) && "Invalid access!"); 351 return Reg.RegNum; 352 } 353 354 const SmallVectorImpl<unsigned> &getRegList() const { 355 assert((Kind == RegisterList || Kind == DPRRegisterList || 356 Kind == SPRRegisterList) && "Invalid access!"); 357 return Registers; 358 } 359 360 const MCExpr *getImm() const { 361 assert(Kind == Immediate && "Invalid access!"); 362 return Imm.Val; 363 } 364 365 ARM_MB::MemBOpt getMemBarrierOpt() const { 366 assert(Kind == MemBarrierOpt && "Invalid access!"); 367 return MBOpt.Val; 368 } 369 370 ARM_PROC::IFlags getProcIFlags() const { 371 assert(Kind == ProcIFlags && "Invalid access!"); 372 return IFlags.Val; 373 } 374 375 unsigned getMSRMask() const { 376 assert(Kind == MSRMask && "Invalid access!"); 377 return MMask.Val; 378 } 379 380 bool isCoprocNum() const { return Kind == CoprocNum; } 381 bool isCoprocReg() const { return Kind == CoprocReg; } 382 bool isCondCode() const { return Kind == CondCode; } 383 bool isCCOut() const { return Kind == CCOut; } 384 bool isImm() const { return Kind == Immediate; } 385 bool isImm0_255() const { 386 if (Kind != Immediate) 387 return false; 388 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 389 if (!CE) return false; 390 int64_t Value = CE->getValue(); 391 return Value >= 0 && Value < 256; 392 } 393 bool isImm0_7() const { 394 if (Kind != Immediate) 395 return false; 396 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 397 if (!CE) return false; 398 int64_t Value = CE->getValue(); 399 return Value >= 0 && Value < 8; 400 } 401 bool isImm0_15() const { 402 if (Kind != Immediate) 403 return false; 404 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 405 if (!CE) return false; 406 int64_t Value = CE->getValue(); 407 return Value >= 0 && Value < 16; 408 } 409 bool isImm0_31() const { 410 if (Kind != Immediate) 411 return false; 412 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 413 if (!CE) return false; 414 int64_t Value = CE->getValue(); 415 return Value >= 0 && Value < 32; 416 } 417 bool isImm1_16() const { 418 if (Kind != Immediate) 419 return false; 420 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 421 if (!CE) return false; 422 int64_t Value = CE->getValue(); 423 return Value > 0 && Value < 17; 424 } 425 bool isImm1_32() const { 426 if (Kind != Immediate) 427 return false; 428 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 429 if (!CE) return false; 430 int64_t Value = CE->getValue(); 431 return Value > 0 && Value < 33; 432 } 433 bool isImm0_65535() const { 434 if (Kind != Immediate) 435 return false; 436 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 437 if (!CE) return false; 438 int64_t Value = CE->getValue(); 439 return Value >= 0 && Value < 65536; 440 } 441 bool isImm0_65535Expr() const { 442 if (Kind != Immediate) 443 return false; 444 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 445 // If it's not a constant expression, it'll generate a fixup and be 446 // handled later. 447 if (!CE) return true; 448 int64_t Value = CE->getValue(); 449 return Value >= 0 && Value < 65536; 450 } 451 bool isImm24bit() const { 452 if (Kind != Immediate) 453 return false; 454 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 455 if (!CE) return false; 456 int64_t Value = CE->getValue(); 457 return Value >= 0 && Value <= 0xffffff; 458 } 459 bool isPKHLSLImm() const { 460 if (Kind != Immediate) 461 return false; 462 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 463 if (!CE) return false; 464 int64_t Value = CE->getValue(); 465 return Value >= 0 && Value < 32; 466 } 467 bool isPKHASRImm() const { 468 if (Kind != Immediate) 469 return false; 470 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 471 if (!CE) return false; 472 int64_t Value = CE->getValue(); 473 return Value > 0 && Value <= 32; 474 } 475 bool isARMSOImm() const { 476 if (Kind != Immediate) 477 return false; 478 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 479 if (!CE) return false; 480 int64_t Value = CE->getValue(); 481 return ARM_AM::getSOImmVal(Value) != -1; 482 } 483 bool isT2SOImm() const { 484 if (Kind != Immediate) 485 return false; 486 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 487 if (!CE) return false; 488 int64_t Value = CE->getValue(); 489 return ARM_AM::getT2SOImmVal(Value) != -1; 490 } 491 bool isSetEndImm() const { 492 if (Kind != Immediate) 493 return false; 494 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 495 if (!CE) return false; 496 int64_t Value = CE->getValue(); 497 return Value == 1 || Value == 0; 498 } 499 bool isReg() const { return Kind == Register; } 500 bool isRegList() const { return Kind == RegisterList; } 501 bool isDPRRegList() const { return Kind == DPRRegisterList; } 502 bool isSPRRegList() const { return Kind == SPRRegisterList; } 503 bool isToken() const { return Kind == Token; } 504 bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; } 505 bool isMemory() const { return Kind == Memory; } 506 bool isShifterImm() const { return Kind == ShifterImmediate; } 507 bool isRegShiftedReg() const { return Kind == ShiftedRegister; } 508 bool isRegShiftedImm() const { return Kind == ShiftedImmediate; } 509 bool isRotImm() const { return Kind == RotateImmediate; } 510 bool isBitfield() const { return Kind == BitfieldDescriptor; } 511 bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; } 512 bool isPostIdxReg() const { 513 return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift; 514 } 515 bool isMemNoOffset() const { 516 if (Kind != Memory) 517 return false; 518 // No offset of any kind. 519 return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0; 520 } 521 bool isAddrMode2() const { 522 if (Kind != Memory) 523 return false; 524 // Check for register offset. 525 if (Mem.OffsetRegNum) return true; 526 // Immediate offset in range [-4095, 4095]. 527 if (!Mem.OffsetImm) return true; 528 int64_t Val = Mem.OffsetImm->getValue(); 529 return Val > -4096 && Val < 4096; 530 } 531 bool isAM2OffsetImm() const { 532 if (Kind != Immediate) 533 return false; 534 // Immediate offset in range [-4095, 4095]. 535 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 536 if (!CE) return false; 537 int64_t Val = CE->getValue(); 538 return Val > -4096 && Val < 4096; 539 } 540 bool isAddrMode3() const { 541 if (Kind != Memory) 542 return false; 543 // No shifts are legal for AM3. 544 if (Mem.ShiftType != ARM_AM::no_shift) return false; 545 // Check for register offset. 546 if (Mem.OffsetRegNum) return true; 547 // Immediate offset in range [-255, 255]. 548 if (!Mem.OffsetImm) return true; 549 int64_t Val = Mem.OffsetImm->getValue(); 550 return Val > -256 && Val < 256; 551 } 552 bool isAM3Offset() const { 553 if (Kind != Immediate && Kind != PostIndexRegister) 554 return false; 555 if (Kind == PostIndexRegister) 556 return PostIdxReg.ShiftTy == ARM_AM::no_shift; 557 // Immediate offset in range [-255, 255]. 558 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 559 if (!CE) return false; 560 int64_t Val = CE->getValue(); 561 // Special case, #-0 is INT32_MIN. 562 return (Val > -256 && Val < 256) || Val == INT32_MIN; 563 } 564 bool isAddrMode5() const { 565 if (Kind != Memory) 566 return false; 567 // Check for register offset. 568 if (Mem.OffsetRegNum) return false; 569 // Immediate offset in range [-1020, 1020] and a multiple of 4. 570 if (!Mem.OffsetImm) return true; 571 int64_t Val = Mem.OffsetImm->getValue(); 572 return Val >= -1020 && Val <= 1020 && ((Val & 3) == 0); 573 } 574 bool isMemRegOffset() const { 575 if (Kind != Memory || !Mem.OffsetRegNum) 576 return false; 577 return true; 578 } 579 bool isMemThumbRR() const { 580 // Thumb reg+reg addressing is simple. Just two registers, a base and 581 // an offset. No shifts, negations or any other complicating factors. 582 if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative || 583 Mem.ShiftType != ARM_AM::no_shift) 584 return false; 585 return true; 586 } 587 bool isMemImm8Offset() const { 588 if (Kind != Memory || Mem.OffsetRegNum != 0) 589 return false; 590 // Immediate offset in range [-255, 255]. 591 if (!Mem.OffsetImm) return true; 592 int64_t Val = Mem.OffsetImm->getValue(); 593 return Val > -256 && Val < 256; 594 } 595 bool isMemImm12Offset() const { 596 // If we have an immediate that's not a constant, treat it as a label 597 // reference needing a fixup. If it is a constant, it's something else 598 // and we reject it. 599 if (Kind == Immediate && !isa<MCConstantExpr>(getImm())) 600 return true; 601 602 if (Kind != Memory || Mem.OffsetRegNum != 0) 603 return false; 604 // Immediate offset in range [-4095, 4095]. 605 if (!Mem.OffsetImm) return true; 606 int64_t Val = Mem.OffsetImm->getValue(); 607 return Val > -4096 && Val < 4096; 608 } 609 bool isPostIdxImm8() const { 610 if (Kind != Immediate) 611 return false; 612 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 613 if (!CE) return false; 614 int64_t Val = CE->getValue(); 615 return Val > -256 && Val < 256; 616 } 617 618 bool isMSRMask() const { return Kind == MSRMask; } 619 bool isProcIFlags() const { return Kind == ProcIFlags; } 620 621 void addExpr(MCInst &Inst, const MCExpr *Expr) const { 622 // Add as immediates when possible. Null MCExpr = 0. 623 if (Expr == 0) 624 Inst.addOperand(MCOperand::CreateImm(0)); 625 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) 626 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 627 else 628 Inst.addOperand(MCOperand::CreateExpr(Expr)); 629 } 630 631 void addCondCodeOperands(MCInst &Inst, unsigned N) const { 632 assert(N == 2 && "Invalid number of operands!"); 633 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 634 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; 635 Inst.addOperand(MCOperand::CreateReg(RegNum)); 636 } 637 638 void addCoprocNumOperands(MCInst &Inst, unsigned N) const { 639 assert(N == 1 && "Invalid number of operands!"); 640 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 641 } 642 643 void addCoprocRegOperands(MCInst &Inst, unsigned N) const { 644 assert(N == 1 && "Invalid number of operands!"); 645 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 646 } 647 648 void addCCOutOperands(MCInst &Inst, unsigned N) const { 649 assert(N == 1 && "Invalid number of operands!"); 650 Inst.addOperand(MCOperand::CreateReg(getReg())); 651 } 652 653 void addRegOperands(MCInst &Inst, unsigned N) const { 654 assert(N == 1 && "Invalid number of operands!"); 655 Inst.addOperand(MCOperand::CreateReg(getReg())); 656 } 657 658 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { 659 assert(N == 3 && "Invalid number of operands!"); 660 assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!"); 661 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); 662 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); 663 Inst.addOperand(MCOperand::CreateImm( 664 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); 665 } 666 667 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { 668 assert(N == 2 && "Invalid number of operands!"); 669 assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!"); 670 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); 671 Inst.addOperand(MCOperand::CreateImm( 672 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm))); 673 } 674 675 676 void addShifterImmOperands(MCInst &Inst, unsigned N) const { 677 assert(N == 1 && "Invalid number of operands!"); 678 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) | 679 ShifterImm.Imm)); 680 } 681 682 void addRegListOperands(MCInst &Inst, unsigned N) const { 683 assert(N == 1 && "Invalid number of operands!"); 684 const SmallVectorImpl<unsigned> &RegList = getRegList(); 685 for (SmallVectorImpl<unsigned>::const_iterator 686 I = RegList.begin(), E = RegList.end(); I != E; ++I) 687 Inst.addOperand(MCOperand::CreateReg(*I)); 688 } 689 690 void addDPRRegListOperands(MCInst &Inst, unsigned N) const { 691 addRegListOperands(Inst, N); 692 } 693 694 void addSPRRegListOperands(MCInst &Inst, unsigned N) const { 695 addRegListOperands(Inst, N); 696 } 697 698 void addRotImmOperands(MCInst &Inst, unsigned N) const { 699 assert(N == 1 && "Invalid number of operands!"); 700 // Encoded as val>>3. The printer handles display as 8, 16, 24. 701 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3)); 702 } 703 704 void addBitfieldOperands(MCInst &Inst, unsigned N) const { 705 assert(N == 1 && "Invalid number of operands!"); 706 // Munge the lsb/width into a bitfield mask. 707 unsigned lsb = Bitfield.LSB; 708 unsigned width = Bitfield.Width; 709 // Make a 32-bit mask w/ the referenced bits clear and all other bits set. 710 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> 711 (32 - (lsb + width))); 712 Inst.addOperand(MCOperand::CreateImm(Mask)); 713 } 714 715 void addImmOperands(MCInst &Inst, unsigned N) const { 716 assert(N == 1 && "Invalid number of operands!"); 717 addExpr(Inst, getImm()); 718 } 719 720 void addImm0_255Operands(MCInst &Inst, unsigned N) const { 721 assert(N == 1 && "Invalid number of operands!"); 722 addExpr(Inst, getImm()); 723 } 724 725 void addImm0_7Operands(MCInst &Inst, unsigned N) const { 726 assert(N == 1 && "Invalid number of operands!"); 727 addExpr(Inst, getImm()); 728 } 729 730 void addImm0_15Operands(MCInst &Inst, unsigned N) const { 731 assert(N == 1 && "Invalid number of operands!"); 732 addExpr(Inst, getImm()); 733 } 734 735 void addImm0_31Operands(MCInst &Inst, unsigned N) const { 736 assert(N == 1 && "Invalid number of operands!"); 737 addExpr(Inst, getImm()); 738 } 739 740 void addImm1_16Operands(MCInst &Inst, unsigned N) const { 741 assert(N == 1 && "Invalid number of operands!"); 742 // The constant encodes as the immediate-1, and we store in the instruction 743 // the bits as encoded, so subtract off one here. 744 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 745 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 746 } 747 748 void addImm1_32Operands(MCInst &Inst, unsigned N) const { 749 assert(N == 1 && "Invalid number of operands!"); 750 // The constant encodes as the immediate-1, and we store in the instruction 751 // the bits as encoded, so subtract off one here. 752 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 753 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 754 } 755 756 void addImm0_65535Operands(MCInst &Inst, unsigned N) const { 757 assert(N == 1 && "Invalid number of operands!"); 758 addExpr(Inst, getImm()); 759 } 760 761 void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const { 762 assert(N == 1 && "Invalid number of operands!"); 763 addExpr(Inst, getImm()); 764 } 765 766 void addImm24bitOperands(MCInst &Inst, unsigned N) const { 767 assert(N == 1 && "Invalid number of operands!"); 768 addExpr(Inst, getImm()); 769 } 770 771 void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const { 772 assert(N == 1 && "Invalid number of operands!"); 773 addExpr(Inst, getImm()); 774 } 775 776 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { 777 assert(N == 1 && "Invalid number of operands!"); 778 // An ASR value of 32 encodes as 0, so that's how we want to add it to 779 // the instruction as well. 780 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 781 int Val = CE->getValue(); 782 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val)); 783 } 784 785 void addARMSOImmOperands(MCInst &Inst, unsigned N) const { 786 assert(N == 1 && "Invalid number of operands!"); 787 addExpr(Inst, getImm()); 788 } 789 790 void addT2SOImmOperands(MCInst &Inst, unsigned N) const { 791 assert(N == 1 && "Invalid number of operands!"); 792 addExpr(Inst, getImm()); 793 } 794 795 void addSetEndImmOperands(MCInst &Inst, unsigned N) const { 796 assert(N == 1 && "Invalid number of operands!"); 797 addExpr(Inst, getImm()); 798 } 799 800 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { 801 assert(N == 1 && "Invalid number of operands!"); 802 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt()))); 803 } 804 805 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { 806 assert(N == 1 && "Invalid number of operands!"); 807 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 808 } 809 810 void addAddrMode2Operands(MCInst &Inst, unsigned N) const { 811 assert(N == 3 && "Invalid number of operands!"); 812 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0; 813 if (!Mem.OffsetRegNum) { 814 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 815 // Special case for #-0 816 if (Val == INT32_MIN) Val = 0; 817 if (Val < 0) Val = -Val; 818 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 819 } else { 820 // For register offset, we encode the shift type and negation flag 821 // here. 822 Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 823 0, Mem.ShiftType); 824 } 825 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 826 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum)); 827 Inst.addOperand(MCOperand::CreateImm(Val)); 828 } 829 830 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { 831 assert(N == 2 && "Invalid number of operands!"); 832 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 833 assert(CE && "non-constant AM2OffsetImm operand!"); 834 int32_t Val = CE->getValue(); 835 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 836 // Special case for #-0 837 if (Val == INT32_MIN) Val = 0; 838 if (Val < 0) Val = -Val; 839 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 840 Inst.addOperand(MCOperand::CreateReg(0)); 841 Inst.addOperand(MCOperand::CreateImm(Val)); 842 } 843 844 void addAddrMode3Operands(MCInst &Inst, unsigned N) const { 845 assert(N == 3 && "Invalid number of operands!"); 846 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0; 847 if (!Mem.OffsetRegNum) { 848 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 849 // Special case for #-0 850 if (Val == INT32_MIN) Val = 0; 851 if (Val < 0) Val = -Val; 852 Val = ARM_AM::getAM3Opc(AddSub, Val); 853 } else { 854 // For register offset, we encode the shift type and negation flag 855 // here. 856 Val = ARM_AM::getAM3Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 0); 857 } 858 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 859 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum)); 860 Inst.addOperand(MCOperand::CreateImm(Val)); 861 } 862 863 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { 864 assert(N == 2 && "Invalid number of operands!"); 865 if (Kind == PostIndexRegister) { 866 int32_t Val = 867 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); 868 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 869 Inst.addOperand(MCOperand::CreateImm(Val)); 870 return; 871 } 872 873 // Constant offset. 874 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm()); 875 int32_t Val = CE->getValue(); 876 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 877 // Special case for #-0 878 if (Val == INT32_MIN) Val = 0; 879 if (Val < 0) Val = -Val; 880 Val = ARM_AM::getAM3Opc(AddSub, Val); 881 Inst.addOperand(MCOperand::CreateReg(0)); 882 Inst.addOperand(MCOperand::CreateImm(Val)); 883 } 884 885 void addAddrMode5Operands(MCInst &Inst, unsigned N) const { 886 assert(N == 2 && "Invalid number of operands!"); 887 // The lower two bits are always zero and as such are not encoded. 888 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0; 889 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 890 // Special case for #-0 891 if (Val == INT32_MIN) Val = 0; 892 if (Val < 0) Val = -Val; 893 Val = ARM_AM::getAM5Opc(AddSub, Val); 894 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 895 Inst.addOperand(MCOperand::CreateImm(Val)); 896 } 897 898 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const { 899 assert(N == 2 && "Invalid number of operands!"); 900 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0; 901 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 902 Inst.addOperand(MCOperand::CreateImm(Val)); 903 } 904 905 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { 906 assert(N == 2 && "Invalid number of operands!"); 907 // If this is an immediate, it's a label reference. 908 if (Kind == Immediate) { 909 addExpr(Inst, getImm()); 910 Inst.addOperand(MCOperand::CreateImm(0)); 911 return; 912 } 913 914 // Otherwise, it's a normal memory reg+offset. 915 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0; 916 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 917 Inst.addOperand(MCOperand::CreateImm(Val)); 918 } 919 920 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { 921 assert(N == 3 && "Invalid number of operands!"); 922 unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 923 Mem.ShiftImm, Mem.ShiftType); 924 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 925 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum)); 926 Inst.addOperand(MCOperand::CreateImm(Val)); 927 } 928 929 void addMemThumbRROperands(MCInst &Inst, unsigned N) const { 930 assert(N == 2 && "Invalid number of operands!"); 931 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 932 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum)); 933 } 934 935 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { 936 assert(N == 1 && "Invalid number of operands!"); 937 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 938 assert(CE && "non-constant post-idx-imm8 operand!"); 939 int Imm = CE->getValue(); 940 bool isAdd = Imm >= 0; 941 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; 942 Inst.addOperand(MCOperand::CreateImm(Imm)); 943 } 944 945 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { 946 assert(N == 2 && "Invalid number of operands!"); 947 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 948 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd)); 949 } 950 951 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { 952 assert(N == 2 && "Invalid number of operands!"); 953 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 954 // The sign, shift type, and shift amount are encoded in a single operand 955 // using the AM2 encoding helpers. 956 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; 957 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, 958 PostIdxReg.ShiftTy); 959 Inst.addOperand(MCOperand::CreateImm(Imm)); 960 } 961 962 void addMSRMaskOperands(MCInst &Inst, unsigned N) const { 963 assert(N == 1 && "Invalid number of operands!"); 964 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask()))); 965 } 966 967 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { 968 assert(N == 1 && "Invalid number of operands!"); 969 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags()))); 970 } 971 972 virtual void print(raw_ostream &OS) const; 973 974 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) { 975 ARMOperand *Op = new ARMOperand(CondCode); 976 Op->CC.Val = CC; 977 Op->StartLoc = S; 978 Op->EndLoc = S; 979 return Op; 980 } 981 982 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) { 983 ARMOperand *Op = new ARMOperand(CoprocNum); 984 Op->Cop.Val = CopVal; 985 Op->StartLoc = S; 986 Op->EndLoc = S; 987 return Op; 988 } 989 990 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) { 991 ARMOperand *Op = new ARMOperand(CoprocReg); 992 Op->Cop.Val = CopVal; 993 Op->StartLoc = S; 994 Op->EndLoc = S; 995 return Op; 996 } 997 998 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) { 999 ARMOperand *Op = new ARMOperand(CCOut); 1000 Op->Reg.RegNum = RegNum; 1001 Op->StartLoc = S; 1002 Op->EndLoc = S; 1003 return Op; 1004 } 1005 1006 static ARMOperand *CreateToken(StringRef Str, SMLoc S) { 1007 ARMOperand *Op = new ARMOperand(Token); 1008 Op->Tok.Data = Str.data(); 1009 Op->Tok.Length = Str.size(); 1010 Op->StartLoc = S; 1011 Op->EndLoc = S; 1012 return Op; 1013 } 1014 1015 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { 1016 ARMOperand *Op = new ARMOperand(Register); 1017 Op->Reg.RegNum = RegNum; 1018 Op->StartLoc = S; 1019 Op->EndLoc = E; 1020 return Op; 1021 } 1022 1023 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, 1024 unsigned SrcReg, 1025 unsigned ShiftReg, 1026 unsigned ShiftImm, 1027 SMLoc S, SMLoc E) { 1028 ARMOperand *Op = new ARMOperand(ShiftedRegister); 1029 Op->RegShiftedReg.ShiftTy = ShTy; 1030 Op->RegShiftedReg.SrcReg = SrcReg; 1031 Op->RegShiftedReg.ShiftReg = ShiftReg; 1032 Op->RegShiftedReg.ShiftImm = ShiftImm; 1033 Op->StartLoc = S; 1034 Op->EndLoc = E; 1035 return Op; 1036 } 1037 1038 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, 1039 unsigned SrcReg, 1040 unsigned ShiftImm, 1041 SMLoc S, SMLoc E) { 1042 ARMOperand *Op = new ARMOperand(ShiftedImmediate); 1043 Op->RegShiftedImm.ShiftTy = ShTy; 1044 Op->RegShiftedImm.SrcReg = SrcReg; 1045 Op->RegShiftedImm.ShiftImm = ShiftImm; 1046 Op->StartLoc = S; 1047 Op->EndLoc = E; 1048 return Op; 1049 } 1050 1051 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm, 1052 SMLoc S, SMLoc E) { 1053 ARMOperand *Op = new ARMOperand(ShifterImmediate); 1054 Op->ShifterImm.isASR = isASR; 1055 Op->ShifterImm.Imm = Imm; 1056 Op->StartLoc = S; 1057 Op->EndLoc = E; 1058 return Op; 1059 } 1060 1061 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) { 1062 ARMOperand *Op = new ARMOperand(RotateImmediate); 1063 Op->RotImm.Imm = Imm; 1064 Op->StartLoc = S; 1065 Op->EndLoc = E; 1066 return Op; 1067 } 1068 1069 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width, 1070 SMLoc S, SMLoc E) { 1071 ARMOperand *Op = new ARMOperand(BitfieldDescriptor); 1072 Op->Bitfield.LSB = LSB; 1073 Op->Bitfield.Width = Width; 1074 Op->StartLoc = S; 1075 Op->EndLoc = E; 1076 return Op; 1077 } 1078 1079 static ARMOperand * 1080 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs, 1081 SMLoc StartLoc, SMLoc EndLoc) { 1082 KindTy Kind = RegisterList; 1083 1084 if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID]. 1085 contains(Regs.front().first)) 1086 Kind = DPRRegisterList; 1087 else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID]. 1088 contains(Regs.front().first)) 1089 Kind = SPRRegisterList; 1090 1091 ARMOperand *Op = new ARMOperand(Kind); 1092 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator 1093 I = Regs.begin(), E = Regs.end(); I != E; ++I) 1094 Op->Registers.push_back(I->first); 1095 array_pod_sort(Op->Registers.begin(), Op->Registers.end()); 1096 Op->StartLoc = StartLoc; 1097 Op->EndLoc = EndLoc; 1098 return Op; 1099 } 1100 1101 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { 1102 ARMOperand *Op = new ARMOperand(Immediate); 1103 Op->Imm.Val = Val; 1104 Op->StartLoc = S; 1105 Op->EndLoc = E; 1106 return Op; 1107 } 1108 1109 static ARMOperand *CreateMem(unsigned BaseRegNum, 1110 const MCConstantExpr *OffsetImm, 1111 unsigned OffsetRegNum, 1112 ARM_AM::ShiftOpc ShiftType, 1113 unsigned ShiftImm, 1114 bool isNegative, 1115 SMLoc S, SMLoc E) { 1116 ARMOperand *Op = new ARMOperand(Memory); 1117 Op->Mem.BaseRegNum = BaseRegNum; 1118 Op->Mem.OffsetImm = OffsetImm; 1119 Op->Mem.OffsetRegNum = OffsetRegNum; 1120 Op->Mem.ShiftType = ShiftType; 1121 Op->Mem.ShiftImm = ShiftImm; 1122 Op->Mem.isNegative = isNegative; 1123 Op->StartLoc = S; 1124 Op->EndLoc = E; 1125 return Op; 1126 } 1127 1128 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd, 1129 ARM_AM::ShiftOpc ShiftTy, 1130 unsigned ShiftImm, 1131 SMLoc S, SMLoc E) { 1132 ARMOperand *Op = new ARMOperand(PostIndexRegister); 1133 Op->PostIdxReg.RegNum = RegNum; 1134 Op->PostIdxReg.isAdd = isAdd; 1135 Op->PostIdxReg.ShiftTy = ShiftTy; 1136 Op->PostIdxReg.ShiftImm = ShiftImm; 1137 Op->StartLoc = S; 1138 Op->EndLoc = E; 1139 return Op; 1140 } 1141 1142 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) { 1143 ARMOperand *Op = new ARMOperand(MemBarrierOpt); 1144 Op->MBOpt.Val = Opt; 1145 Op->StartLoc = S; 1146 Op->EndLoc = S; 1147 return Op; 1148 } 1149 1150 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) { 1151 ARMOperand *Op = new ARMOperand(ProcIFlags); 1152 Op->IFlags.Val = IFlags; 1153 Op->StartLoc = S; 1154 Op->EndLoc = S; 1155 return Op; 1156 } 1157 1158 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) { 1159 ARMOperand *Op = new ARMOperand(MSRMask); 1160 Op->MMask.Val = MMask; 1161 Op->StartLoc = S; 1162 Op->EndLoc = S; 1163 return Op; 1164 } 1165}; 1166 1167} // end anonymous namespace. 1168 1169void ARMOperand::print(raw_ostream &OS) const { 1170 switch (Kind) { 1171 case CondCode: 1172 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; 1173 break; 1174 case CCOut: 1175 OS << "<ccout " << getReg() << ">"; 1176 break; 1177 case CoprocNum: 1178 OS << "<coprocessor number: " << getCoproc() << ">"; 1179 break; 1180 case CoprocReg: 1181 OS << "<coprocessor register: " << getCoproc() << ">"; 1182 break; 1183 case MSRMask: 1184 OS << "<mask: " << getMSRMask() << ">"; 1185 break; 1186 case Immediate: 1187 getImm()->print(OS); 1188 break; 1189 case MemBarrierOpt: 1190 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">"; 1191 break; 1192 case Memory: 1193 OS << "<memory " 1194 << " base:" << Mem.BaseRegNum; 1195 OS << ">"; 1196 break; 1197 case PostIndexRegister: 1198 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") 1199 << PostIdxReg.RegNum; 1200 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) 1201 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " 1202 << PostIdxReg.ShiftImm; 1203 OS << ">"; 1204 break; 1205 case ProcIFlags: { 1206 OS << "<ARM_PROC::"; 1207 unsigned IFlags = getProcIFlags(); 1208 for (int i=2; i >= 0; --i) 1209 if (IFlags & (1 << i)) 1210 OS << ARM_PROC::IFlagsToString(1 << i); 1211 OS << ">"; 1212 break; 1213 } 1214 case Register: 1215 OS << "<register " << getReg() << ">"; 1216 break; 1217 case ShifterImmediate: 1218 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl") 1219 << " #" << ShifterImm.Imm << ">"; 1220 break; 1221 case ShiftedRegister: 1222 OS << "<so_reg_reg " 1223 << RegShiftedReg.SrcReg 1224 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm)) 1225 << ", " << RegShiftedReg.ShiftReg << ", " 1226 << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm) 1227 << ">"; 1228 break; 1229 case ShiftedImmediate: 1230 OS << "<so_reg_imm " 1231 << RegShiftedImm.SrcReg 1232 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm)) 1233 << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm) 1234 << ">"; 1235 break; 1236 case RotateImmediate: 1237 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">"; 1238 break; 1239 case BitfieldDescriptor: 1240 OS << "<bitfield " << "lsb: " << Bitfield.LSB 1241 << ", width: " << Bitfield.Width << ">"; 1242 break; 1243 case RegisterList: 1244 case DPRRegisterList: 1245 case SPRRegisterList: { 1246 OS << "<register_list "; 1247 1248 const SmallVectorImpl<unsigned> &RegList = getRegList(); 1249 for (SmallVectorImpl<unsigned>::const_iterator 1250 I = RegList.begin(), E = RegList.end(); I != E; ) { 1251 OS << *I; 1252 if (++I < E) OS << ", "; 1253 } 1254 1255 OS << ">"; 1256 break; 1257 } 1258 case Token: 1259 OS << "'" << getToken() << "'"; 1260 break; 1261 } 1262} 1263 1264/// @name Auto-generated Match Functions 1265/// { 1266 1267static unsigned MatchRegisterName(StringRef Name); 1268 1269/// } 1270 1271bool ARMAsmParser::ParseRegister(unsigned &RegNo, 1272 SMLoc &StartLoc, SMLoc &EndLoc) { 1273 RegNo = tryParseRegister(); 1274 1275 return (RegNo == (unsigned)-1); 1276} 1277 1278/// Try to parse a register name. The token must be an Identifier when called, 1279/// and if it is a register name the token is eaten and the register number is 1280/// returned. Otherwise return -1. 1281/// 1282int ARMAsmParser::tryParseRegister() { 1283 const AsmToken &Tok = Parser.getTok(); 1284 if (Tok.isNot(AsmToken::Identifier)) return -1; 1285 1286 // FIXME: Validate register for the current architecture; we have to do 1287 // validation later, so maybe there is no need for this here. 1288 std::string upperCase = Tok.getString().str(); 1289 std::string lowerCase = LowercaseString(upperCase); 1290 unsigned RegNum = MatchRegisterName(lowerCase); 1291 if (!RegNum) { 1292 RegNum = StringSwitch<unsigned>(lowerCase) 1293 .Case("r13", ARM::SP) 1294 .Case("r14", ARM::LR) 1295 .Case("r15", ARM::PC) 1296 .Case("ip", ARM::R12) 1297 .Default(0); 1298 } 1299 if (!RegNum) return -1; 1300 1301 Parser.Lex(); // Eat identifier token. 1302 return RegNum; 1303} 1304 1305// Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. 1306// If a recoverable error occurs, return 1. If an irrecoverable error 1307// occurs, return -1. An irrecoverable error is one where tokens have been 1308// consumed in the process of trying to parse the shifter (i.e., when it is 1309// indeed a shifter operand, but malformed). 1310int ARMAsmParser::tryParseShiftRegister( 1311 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1312 SMLoc S = Parser.getTok().getLoc(); 1313 const AsmToken &Tok = Parser.getTok(); 1314 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1315 1316 std::string upperCase = Tok.getString().str(); 1317 std::string lowerCase = LowercaseString(upperCase); 1318 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) 1319 .Case("lsl", ARM_AM::lsl) 1320 .Case("lsr", ARM_AM::lsr) 1321 .Case("asr", ARM_AM::asr) 1322 .Case("ror", ARM_AM::ror) 1323 .Case("rrx", ARM_AM::rrx) 1324 .Default(ARM_AM::no_shift); 1325 1326 if (ShiftTy == ARM_AM::no_shift) 1327 return 1; 1328 1329 Parser.Lex(); // Eat the operator. 1330 1331 // The source register for the shift has already been added to the 1332 // operand list, so we need to pop it off and combine it into the shifted 1333 // register operand instead. 1334 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val()); 1335 if (!PrevOp->isReg()) 1336 return Error(PrevOp->getStartLoc(), "shift must be of a register"); 1337 int SrcReg = PrevOp->getReg(); 1338 int64_t Imm = 0; 1339 int ShiftReg = 0; 1340 if (ShiftTy == ARM_AM::rrx) { 1341 // RRX Doesn't have an explicit shift amount. The encoder expects 1342 // the shift register to be the same as the source register. Seems odd, 1343 // but OK. 1344 ShiftReg = SrcReg; 1345 } else { 1346 // Figure out if this is shifted by a constant or a register (for non-RRX). 1347 if (Parser.getTok().is(AsmToken::Hash)) { 1348 Parser.Lex(); // Eat hash. 1349 SMLoc ImmLoc = Parser.getTok().getLoc(); 1350 const MCExpr *ShiftExpr = 0; 1351 if (getParser().ParseExpression(ShiftExpr)) { 1352 Error(ImmLoc, "invalid immediate shift value"); 1353 return -1; 1354 } 1355 // The expression must be evaluatable as an immediate. 1356 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr); 1357 if (!CE) { 1358 Error(ImmLoc, "invalid immediate shift value"); 1359 return -1; 1360 } 1361 // Range check the immediate. 1362 // lsl, ror: 0 <= imm <= 31 1363 // lsr, asr: 0 <= imm <= 32 1364 Imm = CE->getValue(); 1365 if (Imm < 0 || 1366 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || 1367 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { 1368 Error(ImmLoc, "immediate shift value out of range"); 1369 return -1; 1370 } 1371 } else if (Parser.getTok().is(AsmToken::Identifier)) { 1372 ShiftReg = tryParseRegister(); 1373 SMLoc L = Parser.getTok().getLoc(); 1374 if (ShiftReg == -1) { 1375 Error (L, "expected immediate or register in shift operand"); 1376 return -1; 1377 } 1378 } else { 1379 Error (Parser.getTok().getLoc(), 1380 "expected immediate or register in shift operand"); 1381 return -1; 1382 } 1383 } 1384 1385 if (ShiftReg && ShiftTy != ARM_AM::rrx) 1386 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, 1387 ShiftReg, Imm, 1388 S, Parser.getTok().getLoc())); 1389 else 1390 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, 1391 S, Parser.getTok().getLoc())); 1392 1393 return 0; 1394} 1395 1396 1397/// Try to parse a register name. The token must be an Identifier when called. 1398/// If it's a register, an AsmOperand is created. Another AsmOperand is created 1399/// if there is a "writeback". 'true' if it's not a register. 1400/// 1401/// TODO this is likely to change to allow different register types and or to 1402/// parse for a specific register type. 1403bool ARMAsmParser:: 1404tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1405 SMLoc S = Parser.getTok().getLoc(); 1406 int RegNo = tryParseRegister(); 1407 if (RegNo == -1) 1408 return true; 1409 1410 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc())); 1411 1412 const AsmToken &ExclaimTok = Parser.getTok(); 1413 if (ExclaimTok.is(AsmToken::Exclaim)) { 1414 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), 1415 ExclaimTok.getLoc())); 1416 Parser.Lex(); // Eat exclaim token 1417 } 1418 1419 return false; 1420} 1421 1422/// MatchCoprocessorOperandName - Try to parse an coprocessor related 1423/// instruction with a symbolic operand name. Example: "p1", "p7", "c3", 1424/// "c5", ... 1425static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { 1426 // Use the same layout as the tablegen'erated register name matcher. Ugly, 1427 // but efficient. 1428 switch (Name.size()) { 1429 default: break; 1430 case 2: 1431 if (Name[0] != CoprocOp) 1432 return -1; 1433 switch (Name[1]) { 1434 default: return -1; 1435 case '0': return 0; 1436 case '1': return 1; 1437 case '2': return 2; 1438 case '3': return 3; 1439 case '4': return 4; 1440 case '5': return 5; 1441 case '6': return 6; 1442 case '7': return 7; 1443 case '8': return 8; 1444 case '9': return 9; 1445 } 1446 break; 1447 case 3: 1448 if (Name[0] != CoprocOp || Name[1] != '1') 1449 return -1; 1450 switch (Name[2]) { 1451 default: return -1; 1452 case '0': return 10; 1453 case '1': return 11; 1454 case '2': return 12; 1455 case '3': return 13; 1456 case '4': return 14; 1457 case '5': return 15; 1458 } 1459 break; 1460 } 1461 1462 return -1; 1463} 1464 1465/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The 1466/// token must be an Identifier when called, and if it is a coprocessor 1467/// number, the token is eaten and the operand is added to the operand list. 1468ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1469parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1470 SMLoc S = Parser.getTok().getLoc(); 1471 const AsmToken &Tok = Parser.getTok(); 1472 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1473 1474 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p'); 1475 if (Num == -1) 1476 return MatchOperand_NoMatch; 1477 1478 Parser.Lex(); // Eat identifier token. 1479 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); 1480 return MatchOperand_Success; 1481} 1482 1483/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The 1484/// token must be an Identifier when called, and if it is a coprocessor 1485/// number, the token is eaten and the operand is added to the operand list. 1486ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1487parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1488 SMLoc S = Parser.getTok().getLoc(); 1489 const AsmToken &Tok = Parser.getTok(); 1490 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1491 1492 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); 1493 if (Reg == -1) 1494 return MatchOperand_NoMatch; 1495 1496 Parser.Lex(); // Eat identifier token. 1497 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); 1498 return MatchOperand_Success; 1499} 1500 1501/// Parse a register list, return it if successful else return null. The first 1502/// token must be a '{' when called. 1503bool ARMAsmParser:: 1504parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1505 assert(Parser.getTok().is(AsmToken::LCurly) && 1506 "Token is not a Left Curly Brace"); 1507 SMLoc S = Parser.getTok().getLoc(); 1508 1509 // Read the rest of the registers in the list. 1510 unsigned PrevRegNum = 0; 1511 SmallVector<std::pair<unsigned, SMLoc>, 32> Registers; 1512 1513 do { 1514 bool IsRange = Parser.getTok().is(AsmToken::Minus); 1515 Parser.Lex(); // Eat non-identifier token. 1516 1517 const AsmToken &RegTok = Parser.getTok(); 1518 SMLoc RegLoc = RegTok.getLoc(); 1519 if (RegTok.isNot(AsmToken::Identifier)) { 1520 Error(RegLoc, "register expected"); 1521 return true; 1522 } 1523 1524 int RegNum = tryParseRegister(); 1525 if (RegNum == -1) { 1526 Error(RegLoc, "register expected"); 1527 return true; 1528 } 1529 1530 if (IsRange) { 1531 int Reg = PrevRegNum; 1532 do { 1533 ++Reg; 1534 Registers.push_back(std::make_pair(Reg, RegLoc)); 1535 } while (Reg != RegNum); 1536 } else { 1537 Registers.push_back(std::make_pair(RegNum, RegLoc)); 1538 } 1539 1540 PrevRegNum = RegNum; 1541 } while (Parser.getTok().is(AsmToken::Comma) || 1542 Parser.getTok().is(AsmToken::Minus)); 1543 1544 // Process the right curly brace of the list. 1545 const AsmToken &RCurlyTok = Parser.getTok(); 1546 if (RCurlyTok.isNot(AsmToken::RCurly)) { 1547 Error(RCurlyTok.getLoc(), "'}' expected"); 1548 return true; 1549 } 1550 1551 SMLoc E = RCurlyTok.getLoc(); 1552 Parser.Lex(); // Eat right curly brace token. 1553 1554 // Verify the register list. 1555 SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator 1556 RI = Registers.begin(), RE = Registers.end(); 1557 1558 unsigned HighRegNum = getARMRegisterNumbering(RI->first); 1559 bool EmittedWarning = false; 1560 1561 DenseMap<unsigned, bool> RegMap; 1562 RegMap[HighRegNum] = true; 1563 1564 for (++RI; RI != RE; ++RI) { 1565 const std::pair<unsigned, SMLoc> &RegInfo = *RI; 1566 unsigned Reg = getARMRegisterNumbering(RegInfo.first); 1567 1568 if (RegMap[Reg]) { 1569 Error(RegInfo.second, "register duplicated in register list"); 1570 return true; 1571 } 1572 1573 if (!EmittedWarning && Reg < HighRegNum) 1574 Warning(RegInfo.second, 1575 "register not in ascending order in register list"); 1576 1577 RegMap[Reg] = true; 1578 HighRegNum = std::max(Reg, HighRegNum); 1579 } 1580 1581 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); 1582 return false; 1583} 1584 1585/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. 1586ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1587parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1588 SMLoc S = Parser.getTok().getLoc(); 1589 const AsmToken &Tok = Parser.getTok(); 1590 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1591 StringRef OptStr = Tok.getString(); 1592 1593 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size())) 1594 .Case("sy", ARM_MB::SY) 1595 .Case("st", ARM_MB::ST) 1596 .Case("sh", ARM_MB::ISH) 1597 .Case("ish", ARM_MB::ISH) 1598 .Case("shst", ARM_MB::ISHST) 1599 .Case("ishst", ARM_MB::ISHST) 1600 .Case("nsh", ARM_MB::NSH) 1601 .Case("un", ARM_MB::NSH) 1602 .Case("nshst", ARM_MB::NSHST) 1603 .Case("unst", ARM_MB::NSHST) 1604 .Case("osh", ARM_MB::OSH) 1605 .Case("oshst", ARM_MB::OSHST) 1606 .Default(~0U); 1607 1608 if (Opt == ~0U) 1609 return MatchOperand_NoMatch; 1610 1611 Parser.Lex(); // Eat identifier token. 1612 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); 1613 return MatchOperand_Success; 1614} 1615 1616/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. 1617ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1618parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1619 SMLoc S = Parser.getTok().getLoc(); 1620 const AsmToken &Tok = Parser.getTok(); 1621 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1622 StringRef IFlagsStr = Tok.getString(); 1623 1624 unsigned IFlags = 0; 1625 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { 1626 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1)) 1627 .Case("a", ARM_PROC::A) 1628 .Case("i", ARM_PROC::I) 1629 .Case("f", ARM_PROC::F) 1630 .Default(~0U); 1631 1632 // If some specific iflag is already set, it means that some letter is 1633 // present more than once, this is not acceptable. 1634 if (Flag == ~0U || (IFlags & Flag)) 1635 return MatchOperand_NoMatch; 1636 1637 IFlags |= Flag; 1638 } 1639 1640 Parser.Lex(); // Eat identifier token. 1641 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); 1642 return MatchOperand_Success; 1643} 1644 1645/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. 1646ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1647parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1648 SMLoc S = Parser.getTok().getLoc(); 1649 const AsmToken &Tok = Parser.getTok(); 1650 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1651 StringRef Mask = Tok.getString(); 1652 1653 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" 1654 size_t Start = 0, Next = Mask.find('_'); 1655 StringRef Flags = ""; 1656 std::string SpecReg = LowercaseString(Mask.slice(Start, Next)); 1657 if (Next != StringRef::npos) 1658 Flags = Mask.slice(Next+1, Mask.size()); 1659 1660 // FlagsVal contains the complete mask: 1661 // 3-0: Mask 1662 // 4: Special Reg (cpsr, apsr => 0; spsr => 1) 1663 unsigned FlagsVal = 0; 1664 1665 if (SpecReg == "apsr") { 1666 FlagsVal = StringSwitch<unsigned>(Flags) 1667 .Case("nzcvq", 0x8) // same as CPSR_f 1668 .Case("g", 0x4) // same as CPSR_s 1669 .Case("nzcvqg", 0xc) // same as CPSR_fs 1670 .Default(~0U); 1671 1672 if (FlagsVal == ~0U) { 1673 if (!Flags.empty()) 1674 return MatchOperand_NoMatch; 1675 else 1676 FlagsVal = 0; // No flag 1677 } 1678 } else if (SpecReg == "cpsr" || SpecReg == "spsr") { 1679 if (Flags == "all") // cpsr_all is an alias for cpsr_fc 1680 Flags = "fc"; 1681 for (int i = 0, e = Flags.size(); i != e; ++i) { 1682 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1)) 1683 .Case("c", 1) 1684 .Case("x", 2) 1685 .Case("s", 4) 1686 .Case("f", 8) 1687 .Default(~0U); 1688 1689 // If some specific flag is already set, it means that some letter is 1690 // present more than once, this is not acceptable. 1691 if (FlagsVal == ~0U || (FlagsVal & Flag)) 1692 return MatchOperand_NoMatch; 1693 FlagsVal |= Flag; 1694 } 1695 } else // No match for special register. 1696 return MatchOperand_NoMatch; 1697 1698 // Special register without flags are equivalent to "fc" flags. 1699 if (!FlagsVal) 1700 FlagsVal = 0x9; 1701 1702 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) 1703 if (SpecReg == "spsr") 1704 FlagsVal |= 16; 1705 1706 Parser.Lex(); // Eat identifier token. 1707 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 1708 return MatchOperand_Success; 1709} 1710 1711ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1712parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op, 1713 int Low, int High) { 1714 const AsmToken &Tok = Parser.getTok(); 1715 if (Tok.isNot(AsmToken::Identifier)) { 1716 Error(Parser.getTok().getLoc(), Op + " operand expected."); 1717 return MatchOperand_ParseFail; 1718 } 1719 StringRef ShiftName = Tok.getString(); 1720 std::string LowerOp = LowercaseString(Op); 1721 std::string UpperOp = UppercaseString(Op); 1722 if (ShiftName != LowerOp && ShiftName != UpperOp) { 1723 Error(Parser.getTok().getLoc(), Op + " operand expected."); 1724 return MatchOperand_ParseFail; 1725 } 1726 Parser.Lex(); // Eat shift type token. 1727 1728 // There must be a '#' and a shift amount. 1729 if (Parser.getTok().isNot(AsmToken::Hash)) { 1730 Error(Parser.getTok().getLoc(), "'#' expected"); 1731 return MatchOperand_ParseFail; 1732 } 1733 Parser.Lex(); // Eat hash token. 1734 1735 const MCExpr *ShiftAmount; 1736 SMLoc Loc = Parser.getTok().getLoc(); 1737 if (getParser().ParseExpression(ShiftAmount)) { 1738 Error(Loc, "illegal expression"); 1739 return MatchOperand_ParseFail; 1740 } 1741 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 1742 if (!CE) { 1743 Error(Loc, "constant expression expected"); 1744 return MatchOperand_ParseFail; 1745 } 1746 int Val = CE->getValue(); 1747 if (Val < Low || Val > High) { 1748 Error(Loc, "immediate value out of range"); 1749 return MatchOperand_ParseFail; 1750 } 1751 1752 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc())); 1753 1754 return MatchOperand_Success; 1755} 1756 1757ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1758parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1759 const AsmToken &Tok = Parser.getTok(); 1760 SMLoc S = Tok.getLoc(); 1761 if (Tok.isNot(AsmToken::Identifier)) { 1762 Error(Tok.getLoc(), "'be' or 'le' operand expected"); 1763 return MatchOperand_ParseFail; 1764 } 1765 int Val = StringSwitch<int>(Tok.getString()) 1766 .Case("be", 1) 1767 .Case("le", 0) 1768 .Default(-1); 1769 Parser.Lex(); // Eat the token. 1770 1771 if (Val == -1) { 1772 Error(Tok.getLoc(), "'be' or 'le' operand expected"); 1773 return MatchOperand_ParseFail; 1774 } 1775 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val, 1776 getContext()), 1777 S, Parser.getTok().getLoc())); 1778 return MatchOperand_Success; 1779} 1780 1781/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT 1782/// instructions. Legal values are: 1783/// lsl #n 'n' in [0,31] 1784/// asr #n 'n' in [1,32] 1785/// n == 32 encoded as n == 0. 1786ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1787parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1788 const AsmToken &Tok = Parser.getTok(); 1789 SMLoc S = Tok.getLoc(); 1790 if (Tok.isNot(AsmToken::Identifier)) { 1791 Error(S, "shift operator 'asr' or 'lsl' expected"); 1792 return MatchOperand_ParseFail; 1793 } 1794 StringRef ShiftName = Tok.getString(); 1795 bool isASR; 1796 if (ShiftName == "lsl" || ShiftName == "LSL") 1797 isASR = false; 1798 else if (ShiftName == "asr" || ShiftName == "ASR") 1799 isASR = true; 1800 else { 1801 Error(S, "shift operator 'asr' or 'lsl' expected"); 1802 return MatchOperand_ParseFail; 1803 } 1804 Parser.Lex(); // Eat the operator. 1805 1806 // A '#' and a shift amount. 1807 if (Parser.getTok().isNot(AsmToken::Hash)) { 1808 Error(Parser.getTok().getLoc(), "'#' expected"); 1809 return MatchOperand_ParseFail; 1810 } 1811 Parser.Lex(); // Eat hash token. 1812 1813 const MCExpr *ShiftAmount; 1814 SMLoc E = Parser.getTok().getLoc(); 1815 if (getParser().ParseExpression(ShiftAmount)) { 1816 Error(E, "malformed shift expression"); 1817 return MatchOperand_ParseFail; 1818 } 1819 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 1820 if (!CE) { 1821 Error(E, "shift amount must be an immediate"); 1822 return MatchOperand_ParseFail; 1823 } 1824 1825 int64_t Val = CE->getValue(); 1826 if (isASR) { 1827 // Shift amount must be in [1,32] 1828 if (Val < 1 || Val > 32) { 1829 Error(E, "'asr' shift amount must be in range [1,32]"); 1830 return MatchOperand_ParseFail; 1831 } 1832 // asr #32 encoded as asr #0. 1833 if (Val == 32) Val = 0; 1834 } else { 1835 // Shift amount must be in [1,32] 1836 if (Val < 0 || Val > 31) { 1837 Error(E, "'lsr' shift amount must be in range [0,31]"); 1838 return MatchOperand_ParseFail; 1839 } 1840 } 1841 1842 E = Parser.getTok().getLoc(); 1843 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E)); 1844 1845 return MatchOperand_Success; 1846} 1847 1848/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family 1849/// of instructions. Legal values are: 1850/// ror #n 'n' in {0, 8, 16, 24} 1851ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1852parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1853 const AsmToken &Tok = Parser.getTok(); 1854 SMLoc S = Tok.getLoc(); 1855 if (Tok.isNot(AsmToken::Identifier)) { 1856 Error(S, "rotate operator 'ror' expected"); 1857 return MatchOperand_ParseFail; 1858 } 1859 StringRef ShiftName = Tok.getString(); 1860 if (ShiftName != "ror" && ShiftName != "ROR") { 1861 Error(S, "rotate operator 'ror' expected"); 1862 return MatchOperand_ParseFail; 1863 } 1864 Parser.Lex(); // Eat the operator. 1865 1866 // A '#' and a rotate amount. 1867 if (Parser.getTok().isNot(AsmToken::Hash)) { 1868 Error(Parser.getTok().getLoc(), "'#' expected"); 1869 return MatchOperand_ParseFail; 1870 } 1871 Parser.Lex(); // Eat hash token. 1872 1873 const MCExpr *ShiftAmount; 1874 SMLoc E = Parser.getTok().getLoc(); 1875 if (getParser().ParseExpression(ShiftAmount)) { 1876 Error(E, "malformed rotate expression"); 1877 return MatchOperand_ParseFail; 1878 } 1879 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 1880 if (!CE) { 1881 Error(E, "rotate amount must be an immediate"); 1882 return MatchOperand_ParseFail; 1883 } 1884 1885 int64_t Val = CE->getValue(); 1886 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) 1887 // normally, zero is represented in asm by omitting the rotate operand 1888 // entirely. 1889 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { 1890 Error(E, "'ror' rotate amount must be 8, 16, or 24"); 1891 return MatchOperand_ParseFail; 1892 } 1893 1894 E = Parser.getTok().getLoc(); 1895 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E)); 1896 1897 return MatchOperand_Success; 1898} 1899 1900ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1901parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1902 SMLoc S = Parser.getTok().getLoc(); 1903 // The bitfield descriptor is really two operands, the LSB and the width. 1904 if (Parser.getTok().isNot(AsmToken::Hash)) { 1905 Error(Parser.getTok().getLoc(), "'#' expected"); 1906 return MatchOperand_ParseFail; 1907 } 1908 Parser.Lex(); // Eat hash token. 1909 1910 const MCExpr *LSBExpr; 1911 SMLoc E = Parser.getTok().getLoc(); 1912 if (getParser().ParseExpression(LSBExpr)) { 1913 Error(E, "malformed immediate expression"); 1914 return MatchOperand_ParseFail; 1915 } 1916 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr); 1917 if (!CE) { 1918 Error(E, "'lsb' operand must be an immediate"); 1919 return MatchOperand_ParseFail; 1920 } 1921 1922 int64_t LSB = CE->getValue(); 1923 // The LSB must be in the range [0,31] 1924 if (LSB < 0 || LSB > 31) { 1925 Error(E, "'lsb' operand must be in the range [0,31]"); 1926 return MatchOperand_ParseFail; 1927 } 1928 E = Parser.getTok().getLoc(); 1929 1930 // Expect another immediate operand. 1931 if (Parser.getTok().isNot(AsmToken::Comma)) { 1932 Error(Parser.getTok().getLoc(), "too few operands"); 1933 return MatchOperand_ParseFail; 1934 } 1935 Parser.Lex(); // Eat hash token. 1936 if (Parser.getTok().isNot(AsmToken::Hash)) { 1937 Error(Parser.getTok().getLoc(), "'#' expected"); 1938 return MatchOperand_ParseFail; 1939 } 1940 Parser.Lex(); // Eat hash token. 1941 1942 const MCExpr *WidthExpr; 1943 if (getParser().ParseExpression(WidthExpr)) { 1944 Error(E, "malformed immediate expression"); 1945 return MatchOperand_ParseFail; 1946 } 1947 CE = dyn_cast<MCConstantExpr>(WidthExpr); 1948 if (!CE) { 1949 Error(E, "'width' operand must be an immediate"); 1950 return MatchOperand_ParseFail; 1951 } 1952 1953 int64_t Width = CE->getValue(); 1954 // The LSB must be in the range [1,32-lsb] 1955 if (Width < 1 || Width > 32 - LSB) { 1956 Error(E, "'width' operand must be in the range [1,32-lsb]"); 1957 return MatchOperand_ParseFail; 1958 } 1959 E = Parser.getTok().getLoc(); 1960 1961 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E)); 1962 1963 return MatchOperand_Success; 1964} 1965 1966ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1967parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1968 // Check for a post-index addressing register operand. Specifically: 1969 // postidx_reg := '+' register {, shift} 1970 // | '-' register {, shift} 1971 // | register {, shift} 1972 1973 // This method must return MatchOperand_NoMatch without consuming any tokens 1974 // in the case where there is no match, as other alternatives take other 1975 // parse methods. 1976 AsmToken Tok = Parser.getTok(); 1977 SMLoc S = Tok.getLoc(); 1978 bool haveEaten = false; 1979 bool isAdd = true; 1980 int Reg = -1; 1981 if (Tok.is(AsmToken::Plus)) { 1982 Parser.Lex(); // Eat the '+' token. 1983 haveEaten = true; 1984 } else if (Tok.is(AsmToken::Minus)) { 1985 Parser.Lex(); // Eat the '-' token. 1986 isAdd = false; 1987 haveEaten = true; 1988 } 1989 if (Parser.getTok().is(AsmToken::Identifier)) 1990 Reg = tryParseRegister(); 1991 if (Reg == -1) { 1992 if (!haveEaten) 1993 return MatchOperand_NoMatch; 1994 Error(Parser.getTok().getLoc(), "register expected"); 1995 return MatchOperand_ParseFail; 1996 } 1997 SMLoc E = Parser.getTok().getLoc(); 1998 1999 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; 2000 unsigned ShiftImm = 0; 2001 if (Parser.getTok().is(AsmToken::Comma)) { 2002 Parser.Lex(); // Eat the ','. 2003 if (parseMemRegOffsetShift(ShiftTy, ShiftImm)) 2004 return MatchOperand_ParseFail; 2005 } 2006 2007 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, 2008 ShiftImm, S, E)); 2009 2010 return MatchOperand_Success; 2011} 2012 2013ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2014parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2015 // Check for a post-index addressing register operand. Specifically: 2016 // am3offset := '+' register 2017 // | '-' register 2018 // | register 2019 // | # imm 2020 // | # + imm 2021 // | # - imm 2022 2023 // This method must return MatchOperand_NoMatch without consuming any tokens 2024 // in the case where there is no match, as other alternatives take other 2025 // parse methods. 2026 AsmToken Tok = Parser.getTok(); 2027 SMLoc S = Tok.getLoc(); 2028 2029 // Do immediates first, as we always parse those if we have a '#'. 2030 if (Parser.getTok().is(AsmToken::Hash)) { 2031 Parser.Lex(); // Eat the '#'. 2032 // Explicitly look for a '-', as we need to encode negative zero 2033 // differently. 2034 bool isNegative = Parser.getTok().is(AsmToken::Minus); 2035 const MCExpr *Offset; 2036 if (getParser().ParseExpression(Offset)) 2037 return MatchOperand_ParseFail; 2038 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 2039 if (!CE) { 2040 Error(S, "constant expression expected"); 2041 return MatchOperand_ParseFail; 2042 } 2043 SMLoc E = Tok.getLoc(); 2044 // Negative zero is encoded as the flag value INT32_MIN. 2045 int32_t Val = CE->getValue(); 2046 if (isNegative && Val == 0) 2047 Val = INT32_MIN; 2048 2049 Operands.push_back( 2050 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E)); 2051 2052 return MatchOperand_Success; 2053 } 2054 2055 2056 bool haveEaten = false; 2057 bool isAdd = true; 2058 int Reg = -1; 2059 if (Tok.is(AsmToken::Plus)) { 2060 Parser.Lex(); // Eat the '+' token. 2061 haveEaten = true; 2062 } else if (Tok.is(AsmToken::Minus)) { 2063 Parser.Lex(); // Eat the '-' token. 2064 isAdd = false; 2065 haveEaten = true; 2066 } 2067 if (Parser.getTok().is(AsmToken::Identifier)) 2068 Reg = tryParseRegister(); 2069 if (Reg == -1) { 2070 if (!haveEaten) 2071 return MatchOperand_NoMatch; 2072 Error(Parser.getTok().getLoc(), "register expected"); 2073 return MatchOperand_ParseFail; 2074 } 2075 SMLoc E = Parser.getTok().getLoc(); 2076 2077 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, 2078 0, S, E)); 2079 2080 return MatchOperand_Success; 2081} 2082 2083/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 2084/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2085/// when they refer multiple MIOperands inside a single one. 2086bool ARMAsmParser:: 2087cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 2088 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2089 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2090 2091 // Create a writeback register dummy placeholder. 2092 Inst.addOperand(MCOperand::CreateImm(0)); 2093 2094 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 2095 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2096 return true; 2097} 2098 2099/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 2100/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2101/// when they refer multiple MIOperands inside a single one. 2102bool ARMAsmParser:: 2103cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 2104 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2105 // Create a writeback register dummy placeholder. 2106 Inst.addOperand(MCOperand::CreateImm(0)); 2107 assert(0 && "cvtStWriteBackRegAddrMode2 not implemented yet!"); 2108 return true; 2109} 2110 2111/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst. 2112/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2113/// when they refer multiple MIOperands inside a single one. 2114bool ARMAsmParser:: 2115cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 2116 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2117 // Rt 2118 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2119 // Create a writeback register dummy placeholder. 2120 Inst.addOperand(MCOperand::CreateImm(0)); 2121 // addr 2122 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 2123 // offset 2124 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 2125 // pred 2126 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2127 return true; 2128} 2129 2130/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst. 2131/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2132/// when they refer multiple MIOperands inside a single one. 2133bool ARMAsmParser:: 2134cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 2135 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2136 // Rt 2137 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2138 // Create a writeback register dummy placeholder. 2139 Inst.addOperand(MCOperand::CreateImm(0)); 2140 // addr 2141 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 2142 // offset 2143 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 2144 // pred 2145 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2146 return true; 2147} 2148 2149/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst. 2150/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2151/// when they refer multiple MIOperands inside a single one. 2152bool ARMAsmParser:: 2153cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 2154 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2155 // Create a writeback register dummy placeholder. 2156 Inst.addOperand(MCOperand::CreateImm(0)); 2157 // Rt 2158 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2159 // addr 2160 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 2161 // offset 2162 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 2163 // pred 2164 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2165 return true; 2166} 2167 2168/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst. 2169/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2170/// when they refer multiple MIOperands inside a single one. 2171bool ARMAsmParser:: 2172cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 2173 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2174 // Create a writeback register dummy placeholder. 2175 Inst.addOperand(MCOperand::CreateImm(0)); 2176 // Rt 2177 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2178 // addr 2179 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 2180 // offset 2181 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 2182 // pred 2183 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2184 return true; 2185} 2186 2187/// cvtLdrdPre - Convert parsed operands to MCInst. 2188/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2189/// when they refer multiple MIOperands inside a single one. 2190bool ARMAsmParser:: 2191cvtLdrdPre(MCInst &Inst, unsigned Opcode, 2192 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2193 // Rt, Rt2 2194 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2195 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 2196 // Create a writeback register dummy placeholder. 2197 Inst.addOperand(MCOperand::CreateImm(0)); 2198 // addr 2199 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 2200 // pred 2201 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2202 return true; 2203} 2204 2205/// Parse an ARM memory expression, return false if successful else return true 2206/// or an error. The first token must be a '[' when called. 2207bool ARMAsmParser:: 2208parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2209 SMLoc S, E; 2210 assert(Parser.getTok().is(AsmToken::LBrac) && 2211 "Token is not a Left Bracket"); 2212 S = Parser.getTok().getLoc(); 2213 Parser.Lex(); // Eat left bracket token. 2214 2215 const AsmToken &BaseRegTok = Parser.getTok(); 2216 int BaseRegNum = tryParseRegister(); 2217 if (BaseRegNum == -1) 2218 return Error(BaseRegTok.getLoc(), "register expected"); 2219 2220 // The next token must either be a comma or a closing bracket. 2221 const AsmToken &Tok = Parser.getTok(); 2222 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac)) 2223 return Error(Tok.getLoc(), "malformed memory operand"); 2224 2225 if (Tok.is(AsmToken::RBrac)) { 2226 E = Tok.getLoc(); 2227 Parser.Lex(); // Eat right bracket token. 2228 2229 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift, 2230 0, false, S, E)); 2231 2232 return false; 2233 } 2234 2235 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!"); 2236 Parser.Lex(); // Eat the comma. 2237 2238 // If we have a '#' it's an immediate offset, else assume it's a register 2239 // offset. 2240 if (Parser.getTok().is(AsmToken::Hash)) { 2241 Parser.Lex(); // Eat the '#'. 2242 E = Parser.getTok().getLoc(); 2243 2244 // FIXME: Special case #-0 so we can correctly set the U bit. 2245 2246 const MCExpr *Offset; 2247 if (getParser().ParseExpression(Offset)) 2248 return true; 2249 2250 // The expression has to be a constant. Memory references with relocations 2251 // don't come through here, as they use the <label> forms of the relevant 2252 // instructions. 2253 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 2254 if (!CE) 2255 return Error (E, "constant expression expected"); 2256 2257 // Now we should have the closing ']' 2258 E = Parser.getTok().getLoc(); 2259 if (Parser.getTok().isNot(AsmToken::RBrac)) 2260 return Error(E, "']' expected"); 2261 Parser.Lex(); // Eat right bracket token. 2262 2263 // Don't worry about range checking the value here. That's handled by 2264 // the is*() predicates. 2265 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0, 2266 ARM_AM::no_shift, 0, false, S,E)); 2267 2268 // If there's a pre-indexing writeback marker, '!', just add it as a token 2269 // operand. 2270 if (Parser.getTok().is(AsmToken::Exclaim)) { 2271 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 2272 Parser.Lex(); // Eat the '!'. 2273 } 2274 2275 return false; 2276 } 2277 2278 // The register offset is optionally preceded by a '+' or '-' 2279 bool isNegative = false; 2280 if (Parser.getTok().is(AsmToken::Minus)) { 2281 isNegative = true; 2282 Parser.Lex(); // Eat the '-'. 2283 } else if (Parser.getTok().is(AsmToken::Plus)) { 2284 // Nothing to do. 2285 Parser.Lex(); // Eat the '+'. 2286 } 2287 2288 E = Parser.getTok().getLoc(); 2289 int OffsetRegNum = tryParseRegister(); 2290 if (OffsetRegNum == -1) 2291 return Error(E, "register expected"); 2292 2293 // If there's a shift operator, handle it. 2294 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift; 2295 unsigned ShiftImm = 0; 2296 if (Parser.getTok().is(AsmToken::Comma)) { 2297 Parser.Lex(); // Eat the ','. 2298 if (parseMemRegOffsetShift(ShiftType, ShiftImm)) 2299 return true; 2300 } 2301 2302 // Now we should have the closing ']' 2303 E = Parser.getTok().getLoc(); 2304 if (Parser.getTok().isNot(AsmToken::RBrac)) 2305 return Error(E, "']' expected"); 2306 Parser.Lex(); // Eat right bracket token. 2307 2308 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum, 2309 ShiftType, ShiftImm, isNegative, 2310 S, E)); 2311 2312 // If there's a pre-indexing writeback marker, '!', just add it as a token 2313 // operand. 2314 if (Parser.getTok().is(AsmToken::Exclaim)) { 2315 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 2316 Parser.Lex(); // Eat the '!'. 2317 } 2318 2319 return false; 2320} 2321 2322/// parseMemRegOffsetShift - one of these two: 2323/// ( lsl | lsr | asr | ror ) , # shift_amount 2324/// rrx 2325/// return true if it parses a shift otherwise it returns false. 2326bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St, 2327 unsigned &Amount) { 2328 SMLoc Loc = Parser.getTok().getLoc(); 2329 const AsmToken &Tok = Parser.getTok(); 2330 if (Tok.isNot(AsmToken::Identifier)) 2331 return true; 2332 StringRef ShiftName = Tok.getString(); 2333 if (ShiftName == "lsl" || ShiftName == "LSL") 2334 St = ARM_AM::lsl; 2335 else if (ShiftName == "lsr" || ShiftName == "LSR") 2336 St = ARM_AM::lsr; 2337 else if (ShiftName == "asr" || ShiftName == "ASR") 2338 St = ARM_AM::asr; 2339 else if (ShiftName == "ror" || ShiftName == "ROR") 2340 St = ARM_AM::ror; 2341 else if (ShiftName == "rrx" || ShiftName == "RRX") 2342 St = ARM_AM::rrx; 2343 else 2344 return Error(Loc, "illegal shift operator"); 2345 Parser.Lex(); // Eat shift type token. 2346 2347 // rrx stands alone. 2348 Amount = 0; 2349 if (St != ARM_AM::rrx) { 2350 Loc = Parser.getTok().getLoc(); 2351 // A '#' and a shift amount. 2352 const AsmToken &HashTok = Parser.getTok(); 2353 if (HashTok.isNot(AsmToken::Hash)) 2354 return Error(HashTok.getLoc(), "'#' expected"); 2355 Parser.Lex(); // Eat hash token. 2356 2357 const MCExpr *Expr; 2358 if (getParser().ParseExpression(Expr)) 2359 return true; 2360 // Range check the immediate. 2361 // lsl, ror: 0 <= imm <= 31 2362 // lsr, asr: 0 <= imm <= 32 2363 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 2364 if (!CE) 2365 return Error(Loc, "shift amount must be an immediate"); 2366 int64_t Imm = CE->getValue(); 2367 if (Imm < 0 || 2368 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) || 2369 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32)) 2370 return Error(Loc, "immediate shift value out of range"); 2371 Amount = Imm; 2372 } 2373 2374 return false; 2375} 2376 2377/// Parse a arm instruction operand. For now this parses the operand regardless 2378/// of the mnemonic. 2379bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 2380 StringRef Mnemonic) { 2381 SMLoc S, E; 2382 2383 // Check if the current operand has a custom associated parser, if so, try to 2384 // custom parse the operand, or fallback to the general approach. 2385 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 2386 if (ResTy == MatchOperand_Success) 2387 return false; 2388 // If there wasn't a custom match, try the generic matcher below. Otherwise, 2389 // there was a match, but an error occurred, in which case, just return that 2390 // the operand parsing failed. 2391 if (ResTy == MatchOperand_ParseFail) 2392 return true; 2393 2394 switch (getLexer().getKind()) { 2395 default: 2396 Error(Parser.getTok().getLoc(), "unexpected token in operand"); 2397 return true; 2398 case AsmToken::Identifier: { 2399 if (!tryParseRegisterWithWriteBack(Operands)) 2400 return false; 2401 int Res = tryParseShiftRegister(Operands); 2402 if (Res == 0) // success 2403 return false; 2404 else if (Res == -1) // irrecoverable error 2405 return true; 2406 2407 // Fall though for the Identifier case that is not a register or a 2408 // special name. 2409 } 2410 case AsmToken::Integer: // things like 1f and 2b as a branch targets 2411 case AsmToken::Dot: { // . as a branch target 2412 // This was not a register so parse other operands that start with an 2413 // identifier (like labels) as expressions and create them as immediates. 2414 const MCExpr *IdVal; 2415 S = Parser.getTok().getLoc(); 2416 if (getParser().ParseExpression(IdVal)) 2417 return true; 2418 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 2419 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); 2420 return false; 2421 } 2422 case AsmToken::LBrac: 2423 return parseMemory(Operands); 2424 case AsmToken::LCurly: 2425 return parseRegisterList(Operands); 2426 case AsmToken::Hash: 2427 // #42 -> immediate. 2428 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate 2429 S = Parser.getTok().getLoc(); 2430 Parser.Lex(); 2431 const MCExpr *ImmVal; 2432 if (getParser().ParseExpression(ImmVal)) 2433 return true; 2434 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 2435 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); 2436 return false; 2437 case AsmToken::Colon: { 2438 // ":lower16:" and ":upper16:" expression prefixes 2439 // FIXME: Check it's an expression prefix, 2440 // e.g. (FOO - :lower16:BAR) isn't legal. 2441 ARMMCExpr::VariantKind RefKind; 2442 if (parsePrefix(RefKind)) 2443 return true; 2444 2445 const MCExpr *SubExprVal; 2446 if (getParser().ParseExpression(SubExprVal)) 2447 return true; 2448 2449 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal, 2450 getContext()); 2451 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 2452 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); 2453 return false; 2454 } 2455 } 2456} 2457 2458// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. 2459// :lower16: and :upper16:. 2460bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) { 2461 RefKind = ARMMCExpr::VK_ARM_None; 2462 2463 // :lower16: and :upper16: modifiers 2464 assert(getLexer().is(AsmToken::Colon) && "expected a :"); 2465 Parser.Lex(); // Eat ':' 2466 2467 if (getLexer().isNot(AsmToken::Identifier)) { 2468 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); 2469 return true; 2470 } 2471 2472 StringRef IDVal = Parser.getTok().getIdentifier(); 2473 if (IDVal == "lower16") { 2474 RefKind = ARMMCExpr::VK_ARM_LO16; 2475 } else if (IDVal == "upper16") { 2476 RefKind = ARMMCExpr::VK_ARM_HI16; 2477 } else { 2478 Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); 2479 return true; 2480 } 2481 Parser.Lex(); 2482 2483 if (getLexer().isNot(AsmToken::Colon)) { 2484 Error(Parser.getTok().getLoc(), "unexpected token after prefix"); 2485 return true; 2486 } 2487 Parser.Lex(); // Eat the last ':' 2488 return false; 2489} 2490 2491const MCExpr * 2492ARMAsmParser::applyPrefixToExpr(const MCExpr *E, 2493 MCSymbolRefExpr::VariantKind Variant) { 2494 // Recurse over the given expression, rebuilding it to apply the given variant 2495 // to the leftmost symbol. 2496 if (Variant == MCSymbolRefExpr::VK_None) 2497 return E; 2498 2499 switch (E->getKind()) { 2500 case MCExpr::Target: 2501 llvm_unreachable("Can't handle target expr yet"); 2502 case MCExpr::Constant: 2503 llvm_unreachable("Can't handle lower16/upper16 of constant yet"); 2504 2505 case MCExpr::SymbolRef: { 2506 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 2507 2508 if (SRE->getKind() != MCSymbolRefExpr::VK_None) 2509 return 0; 2510 2511 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext()); 2512 } 2513 2514 case MCExpr::Unary: 2515 llvm_unreachable("Can't handle unary expressions yet"); 2516 2517 case MCExpr::Binary: { 2518 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 2519 const MCExpr *LHS = applyPrefixToExpr(BE->getLHS(), Variant); 2520 const MCExpr *RHS = BE->getRHS(); 2521 if (!LHS) 2522 return 0; 2523 2524 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext()); 2525 } 2526 } 2527 2528 assert(0 && "Invalid expression kind!"); 2529 return 0; 2530} 2531 2532/// \brief Given a mnemonic, split out possible predication code and carry 2533/// setting letters to form a canonical mnemonic and flags. 2534// 2535// FIXME: Would be nice to autogen this. 2536StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, 2537 unsigned &PredicationCode, 2538 bool &CarrySetting, 2539 unsigned &ProcessorIMod) { 2540 PredicationCode = ARMCC::AL; 2541 CarrySetting = false; 2542 ProcessorIMod = 0; 2543 2544 // Ignore some mnemonics we know aren't predicated forms. 2545 // 2546 // FIXME: Would be nice to autogen this. 2547 if ((Mnemonic == "movs" && isThumb()) || 2548 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" || 2549 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || 2550 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" || 2551 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" || 2552 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" || 2553 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || 2554 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal") 2555 return Mnemonic; 2556 2557 // First, split out any predication code. Ignore mnemonics we know aren't 2558 // predicated but do have a carry-set and so weren't caught above. 2559 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && 2560 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" && 2561 Mnemonic != "umlals" && Mnemonic != "umulls") { 2562 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2)) 2563 .Case("eq", ARMCC::EQ) 2564 .Case("ne", ARMCC::NE) 2565 .Case("hs", ARMCC::HS) 2566 .Case("cs", ARMCC::HS) 2567 .Case("lo", ARMCC::LO) 2568 .Case("cc", ARMCC::LO) 2569 .Case("mi", ARMCC::MI) 2570 .Case("pl", ARMCC::PL) 2571 .Case("vs", ARMCC::VS) 2572 .Case("vc", ARMCC::VC) 2573 .Case("hi", ARMCC::HI) 2574 .Case("ls", ARMCC::LS) 2575 .Case("ge", ARMCC::GE) 2576 .Case("lt", ARMCC::LT) 2577 .Case("gt", ARMCC::GT) 2578 .Case("le", ARMCC::LE) 2579 .Case("al", ARMCC::AL) 2580 .Default(~0U); 2581 if (CC != ~0U) { 2582 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); 2583 PredicationCode = CC; 2584 } 2585 } 2586 2587 // Next, determine if we have a carry setting bit. We explicitly ignore all 2588 // the instructions we know end in 's'. 2589 if (Mnemonic.endswith("s") && 2590 !(Mnemonic == "asrs" || Mnemonic == "cps" || Mnemonic == "mls" || 2591 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" || 2592 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" || 2593 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" || 2594 Mnemonic == "vrsqrts" || Mnemonic == "srs" || 2595 (Mnemonic == "movs" && isThumb()))) { 2596 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); 2597 CarrySetting = true; 2598 } 2599 2600 // The "cps" instruction can have a interrupt mode operand which is glued into 2601 // the mnemonic. Check if this is the case, split it and parse the imod op 2602 if (Mnemonic.startswith("cps")) { 2603 // Split out any imod code. 2604 unsigned IMod = 2605 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2)) 2606 .Case("ie", ARM_PROC::IE) 2607 .Case("id", ARM_PROC::ID) 2608 .Default(~0U); 2609 if (IMod != ~0U) { 2610 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2); 2611 ProcessorIMod = IMod; 2612 } 2613 } 2614 2615 return Mnemonic; 2616} 2617 2618/// \brief Given a canonical mnemonic, determine if the instruction ever allows 2619/// inclusion of carry set or predication code operands. 2620// 2621// FIXME: It would be nice to autogen this. 2622void ARMAsmParser:: 2623getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 2624 bool &CanAcceptPredicationCode) { 2625 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || 2626 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || 2627 Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" || 2628 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" || 2629 Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" || 2630 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || 2631 Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" || 2632 Mnemonic == "eor" || Mnemonic == "smlal" || 2633 (Mnemonic == "mov" && !isThumbOne())) { 2634 CanAcceptCarrySet = true; 2635 } else { 2636 CanAcceptCarrySet = false; 2637 } 2638 2639 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" || 2640 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" || 2641 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" || 2642 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" || 2643 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" || 2644 Mnemonic == "setend" || 2645 ((Mnemonic == "pld" || Mnemonic == "pli") && !isThumb()) || 2646 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) 2647 && !isThumb()) || 2648 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) { 2649 CanAcceptPredicationCode = false; 2650 } else { 2651 CanAcceptPredicationCode = true; 2652 } 2653 2654 if (isThumb()) 2655 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" || 2656 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp") 2657 CanAcceptPredicationCode = false; 2658} 2659 2660/// Parse an arm instruction mnemonic followed by its operands. 2661bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc, 2662 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2663 // Create the leading tokens for the mnemonic, split by '.' characters. 2664 size_t Start = 0, Next = Name.find('.'); 2665 StringRef Mnemonic = Name.slice(Start, Next); 2666 2667 // Split out the predication code and carry setting flag from the mnemonic. 2668 unsigned PredicationCode; 2669 unsigned ProcessorIMod; 2670 bool CarrySetting; 2671 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting, 2672 ProcessorIMod); 2673 2674 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); 2675 2676 // FIXME: This is all a pretty gross hack. We should automatically handle 2677 // optional operands like this via tblgen. 2678 2679 // Next, add the CCOut and ConditionCode operands, if needed. 2680 // 2681 // For mnemonics which can ever incorporate a carry setting bit or predication 2682 // code, our matching model involves us always generating CCOut and 2683 // ConditionCode operands to match the mnemonic "as written" and then we let 2684 // the matcher deal with finding the right instruction or generating an 2685 // appropriate error. 2686 bool CanAcceptCarrySet, CanAcceptPredicationCode; 2687 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode); 2688 2689 // If we had a carry-set on an instruction that can't do that, issue an 2690 // error. 2691 if (!CanAcceptCarrySet && CarrySetting) { 2692 Parser.EatToEndOfStatement(); 2693 return Error(NameLoc, "instruction '" + Mnemonic + 2694 "' can not set flags, but 's' suffix specified"); 2695 } 2696 // If we had a predication code on an instruction that can't do that, issue an 2697 // error. 2698 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) { 2699 Parser.EatToEndOfStatement(); 2700 return Error(NameLoc, "instruction '" + Mnemonic + 2701 "' is not predicable, but condition code specified"); 2702 } 2703 2704 // Add the carry setting operand, if necessary. 2705 // 2706 // FIXME: It would be awesome if we could somehow invent a location such that 2707 // match errors on this operand would print a nice diagnostic about how the 2708 // 's' character in the mnemonic resulted in a CCOut operand. 2709 if (CanAcceptCarrySet) 2710 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, 2711 NameLoc)); 2712 2713 // Add the predication code operand, if necessary. 2714 if (CanAcceptPredicationCode) { 2715 Operands.push_back(ARMOperand::CreateCondCode( 2716 ARMCC::CondCodes(PredicationCode), NameLoc)); 2717 } 2718 2719 // Add the processor imod operand, if necessary. 2720 if (ProcessorIMod) { 2721 Operands.push_back(ARMOperand::CreateImm( 2722 MCConstantExpr::Create(ProcessorIMod, getContext()), 2723 NameLoc, NameLoc)); 2724 } else { 2725 // This mnemonic can't ever accept a imod, but the user wrote 2726 // one (or misspelled another mnemonic). 2727 2728 // FIXME: Issue a nice error. 2729 } 2730 2731 // Add the remaining tokens in the mnemonic. 2732 while (Next != StringRef::npos) { 2733 Start = Next; 2734 Next = Name.find('.', Start + 1); 2735 StringRef ExtraToken = Name.slice(Start, Next); 2736 2737 Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc)); 2738 } 2739 2740 // Read the remaining operands. 2741 if (getLexer().isNot(AsmToken::EndOfStatement)) { 2742 // Read the first operand. 2743 if (parseOperand(Operands, Mnemonic)) { 2744 Parser.EatToEndOfStatement(); 2745 return true; 2746 } 2747 2748 while (getLexer().is(AsmToken::Comma)) { 2749 Parser.Lex(); // Eat the comma. 2750 2751 // Parse and remember the operand. 2752 if (parseOperand(Operands, Mnemonic)) { 2753 Parser.EatToEndOfStatement(); 2754 return true; 2755 } 2756 } 2757 } 2758 2759 if (getLexer().isNot(AsmToken::EndOfStatement)) { 2760 Parser.EatToEndOfStatement(); 2761 return TokError("unexpected token in argument list"); 2762 } 2763 2764 Parser.Lex(); // Consume the EndOfStatement 2765 2766 2767 // The 'mov' mnemonic is special. One variant has a cc_out operand, while 2768 // another does not. Specifically, the MOVW instruction does not. So we 2769 // special case it here and remove the defaulted (non-setting) cc_out 2770 // operand if that's the instruction we're trying to match. 2771 // 2772 // We do this post-processing of the explicit operands rather than just 2773 // conditionally adding the cc_out in the first place because we need 2774 // to check the type of the parsed immediate operand. 2775 if (Mnemonic == "mov" && Operands.size() > 4 && 2776 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() && 2777 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() && 2778 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) { 2779 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 2780 Operands.erase(Operands.begin() + 1); 2781 delete Op; 2782 } 2783 2784 // ARM mode 'blx' need special handling, as the register operand version 2785 // is predicable, but the label operand version is not. So, we can't rely 2786 // on the Mnemonic based checking to correctly figure out when to put 2787 // a CondCode operand in the list. If we're trying to match the label 2788 // version, remove the CondCode operand here. 2789 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && 2790 static_cast<ARMOperand*>(Operands[2])->isImm()) { 2791 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 2792 Operands.erase(Operands.begin() + 1); 2793 delete Op; 2794 } 2795 return false; 2796} 2797 2798// Validate context-sensitive operand constraints. 2799// FIXME: We would really like to be able to tablegen'erate this. 2800bool ARMAsmParser:: 2801validateInstruction(MCInst &Inst, 2802 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2803 switch (Inst.getOpcode()) { 2804 case ARM::LDRD: 2805 case ARM::LDRD_PRE: 2806 case ARM::LDRD_POST: 2807 case ARM::LDREXD: { 2808 // Rt2 must be Rt + 1. 2809 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg()); 2810 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 2811 if (Rt2 != Rt + 1) 2812 return Error(Operands[3]->getStartLoc(), 2813 "destination operands must be sequential"); 2814 return false; 2815 } 2816 case ARM::STRD: 2817 case ARM::STRD_PRE: 2818 case ARM::STRD_POST: 2819 case ARM::STREXD: { 2820 // Rt2 must be Rt + 1. 2821 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 2822 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg()); 2823 if (Rt2 != Rt + 1) 2824 return Error(Operands[4]->getStartLoc(), 2825 "source operands must be sequential"); 2826 return false; 2827 } 2828 case ARM::SBFX: 2829 case ARM::UBFX: { 2830 // width must be in range [1, 32-lsb] 2831 unsigned lsb = Inst.getOperand(2).getImm(); 2832 unsigned widthm1 = Inst.getOperand(3).getImm(); 2833 if (widthm1 >= 32 - lsb) 2834 return Error(Operands[5]->getStartLoc(), 2835 "bitfield width must be in range [1,32-lsb]"); 2836 } 2837 } 2838 2839 return false; 2840} 2841 2842bool ARMAsmParser:: 2843MatchAndEmitInstruction(SMLoc IDLoc, 2844 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 2845 MCStreamer &Out) { 2846 MCInst Inst; 2847 unsigned ErrorInfo; 2848 MatchResultTy MatchResult; 2849 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo); 2850 switch (MatchResult) { 2851 case Match_Success: 2852 // Context sensitive operand constraints aren't handled by the matcher, 2853 // so check them here. 2854 if (validateInstruction(Inst, Operands)) 2855 return true; 2856 2857 Out.EmitInstruction(Inst); 2858 return false; 2859 case Match_MissingFeature: 2860 Error(IDLoc, "instruction requires a CPU feature not currently enabled"); 2861 return true; 2862 case Match_InvalidOperand: { 2863 SMLoc ErrorLoc = IDLoc; 2864 if (ErrorInfo != ~0U) { 2865 if (ErrorInfo >= Operands.size()) 2866 return Error(IDLoc, "too few operands for instruction"); 2867 2868 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 2869 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 2870 } 2871 2872 return Error(ErrorLoc, "invalid operand for instruction"); 2873 } 2874 case Match_MnemonicFail: 2875 return Error(IDLoc, "unrecognized instruction mnemonic"); 2876 case Match_ConversionFail: 2877 return Error(IDLoc, "unable to convert operands to instruction"); 2878 } 2879 2880 llvm_unreachable("Implement any new match types added!"); 2881 return true; 2882} 2883 2884/// parseDirective parses the arm specific directives 2885bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { 2886 StringRef IDVal = DirectiveID.getIdentifier(); 2887 if (IDVal == ".word") 2888 return parseDirectiveWord(4, DirectiveID.getLoc()); 2889 else if (IDVal == ".thumb") 2890 return parseDirectiveThumb(DirectiveID.getLoc()); 2891 else if (IDVal == ".thumb_func") 2892 return parseDirectiveThumbFunc(DirectiveID.getLoc()); 2893 else if (IDVal == ".code") 2894 return parseDirectiveCode(DirectiveID.getLoc()); 2895 else if (IDVal == ".syntax") 2896 return parseDirectiveSyntax(DirectiveID.getLoc()); 2897 return true; 2898} 2899 2900/// parseDirectiveWord 2901/// ::= .word [ expression (, expression)* ] 2902bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) { 2903 if (getLexer().isNot(AsmToken::EndOfStatement)) { 2904 for (;;) { 2905 const MCExpr *Value; 2906 if (getParser().ParseExpression(Value)) 2907 return true; 2908 2909 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/); 2910 2911 if (getLexer().is(AsmToken::EndOfStatement)) 2912 break; 2913 2914 // FIXME: Improve diagnostic. 2915 if (getLexer().isNot(AsmToken::Comma)) 2916 return Error(L, "unexpected token in directive"); 2917 Parser.Lex(); 2918 } 2919 } 2920 2921 Parser.Lex(); 2922 return false; 2923} 2924 2925/// parseDirectiveThumb 2926/// ::= .thumb 2927bool ARMAsmParser::parseDirectiveThumb(SMLoc L) { 2928 if (getLexer().isNot(AsmToken::EndOfStatement)) 2929 return Error(L, "unexpected token in directive"); 2930 Parser.Lex(); 2931 2932 // TODO: set thumb mode 2933 // TODO: tell the MC streamer the mode 2934 // getParser().getStreamer().Emit???(); 2935 return false; 2936} 2937 2938/// parseDirectiveThumbFunc 2939/// ::= .thumbfunc symbol_name 2940bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) { 2941 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo(); 2942 bool isMachO = MAI.hasSubsectionsViaSymbols(); 2943 StringRef Name; 2944 2945 // Darwin asm has function name after .thumb_func direction 2946 // ELF doesn't 2947 if (isMachO) { 2948 const AsmToken &Tok = Parser.getTok(); 2949 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) 2950 return Error(L, "unexpected token in .thumb_func directive"); 2951 Name = Tok.getString(); 2952 Parser.Lex(); // Consume the identifier token. 2953 } 2954 2955 if (getLexer().isNot(AsmToken::EndOfStatement)) 2956 return Error(L, "unexpected token in directive"); 2957 Parser.Lex(); 2958 2959 // FIXME: assuming function name will be the line following .thumb_func 2960 if (!isMachO) { 2961 Name = Parser.getTok().getString(); 2962 } 2963 2964 // Mark symbol as a thumb symbol. 2965 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name); 2966 getParser().getStreamer().EmitThumbFunc(Func); 2967 return false; 2968} 2969 2970/// parseDirectiveSyntax 2971/// ::= .syntax unified | divided 2972bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) { 2973 const AsmToken &Tok = Parser.getTok(); 2974 if (Tok.isNot(AsmToken::Identifier)) 2975 return Error(L, "unexpected token in .syntax directive"); 2976 StringRef Mode = Tok.getString(); 2977 if (Mode == "unified" || Mode == "UNIFIED") 2978 Parser.Lex(); 2979 else if (Mode == "divided" || Mode == "DIVIDED") 2980 return Error(L, "'.syntax divided' arm asssembly not supported"); 2981 else 2982 return Error(L, "unrecognized syntax mode in .syntax directive"); 2983 2984 if (getLexer().isNot(AsmToken::EndOfStatement)) 2985 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 2986 Parser.Lex(); 2987 2988 // TODO tell the MC streamer the mode 2989 // getParser().getStreamer().Emit???(); 2990 return false; 2991} 2992 2993/// parseDirectiveCode 2994/// ::= .code 16 | 32 2995bool ARMAsmParser::parseDirectiveCode(SMLoc L) { 2996 const AsmToken &Tok = Parser.getTok(); 2997 if (Tok.isNot(AsmToken::Integer)) 2998 return Error(L, "unexpected token in .code directive"); 2999 int64_t Val = Parser.getTok().getIntVal(); 3000 if (Val == 16) 3001 Parser.Lex(); 3002 else if (Val == 32) 3003 Parser.Lex(); 3004 else 3005 return Error(L, "invalid operand to .code directive"); 3006 3007 if (getLexer().isNot(AsmToken::EndOfStatement)) 3008 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 3009 Parser.Lex(); 3010 3011 if (Val == 16) { 3012 if (!isThumb()) { 3013 SwitchMode(); 3014 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 3015 } 3016 } else { 3017 if (isThumb()) { 3018 SwitchMode(); 3019 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 3020 } 3021 } 3022 3023 return false; 3024} 3025 3026extern "C" void LLVMInitializeARMAsmLexer(); 3027 3028/// Force static initialization. 3029extern "C" void LLVMInitializeARMAsmParser() { 3030 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget); 3031 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget); 3032 LLVMInitializeARMAsmLexer(); 3033} 3034 3035#define GET_REGISTER_MATCHER 3036#define GET_MATCHER_IMPLEMENTATION 3037#include "ARMGenAsmMatcher.inc" 3038