ARMAsmParser.cpp revision 326efe58918d3f0a431d07938054870fcd0e240f
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#include "MCTargetDesc/ARMBaseInfo.h" 11#include "MCTargetDesc/ARMAddressingModes.h" 12#include "MCTargetDesc/ARMMCExpr.h" 13#include "llvm/MC/MCParser/MCAsmLexer.h" 14#include "llvm/MC/MCParser/MCAsmParser.h" 15#include "llvm/MC/MCParser/MCParsedAsmOperand.h" 16#include "llvm/MC/MCAsmInfo.h" 17#include "llvm/MC/MCContext.h" 18#include "llvm/MC/MCStreamer.h" 19#include "llvm/MC/MCExpr.h" 20#include "llvm/MC/MCInst.h" 21#include "llvm/MC/MCInstrDesc.h" 22#include "llvm/MC/MCRegisterInfo.h" 23#include "llvm/MC/MCSubtargetInfo.h" 24#include "llvm/MC/MCTargetAsmParser.h" 25#include "llvm/Support/MathExtras.h" 26#include "llvm/Support/SourceMgr.h" 27#include "llvm/Support/TargetRegistry.h" 28#include "llvm/Support/raw_ostream.h" 29#include "llvm/ADT/BitVector.h" 30#include "llvm/ADT/OwningPtr.h" 31#include "llvm/ADT/STLExtras.h" 32#include "llvm/ADT/SmallVector.h" 33#include "llvm/ADT/StringExtras.h" 34#include "llvm/ADT/StringSwitch.h" 35#include "llvm/ADT/Twine.h" 36 37using namespace llvm; 38 39namespace { 40 41class ARMOperand; 42 43class ARMAsmParser : public MCTargetAsmParser { 44 MCSubtargetInfo &STI; 45 MCAsmParser &Parser; 46 47 struct { 48 ARMCC::CondCodes Cond; // Condition for IT block. 49 unsigned Mask:4; // Condition mask for instructions. 50 // Starting at first 1 (from lsb). 51 // '1' condition as indicated in IT. 52 // '0' inverse of condition (else). 53 // Count of instructions in IT block is 54 // 4 - trailingzeroes(mask) 55 56 bool FirstCond; // Explicit flag for when we're parsing the 57 // First instruction in the IT block. It's 58 // implied in the mask, so needs special 59 // handling. 60 61 unsigned CurPosition; // Current position in parsing of IT 62 // block. In range [0,3]. Initialized 63 // according to count of instructions in block. 64 // ~0U if no active IT block. 65 } ITState; 66 bool inITBlock() { return ITState.CurPosition != ~0U;} 67 void forwardITPosition() { 68 if (!inITBlock()) return; 69 // Move to the next instruction in the IT block, if there is one. If not, 70 // mark the block as done. 71 unsigned TZ = CountTrailingZeros_32(ITState.Mask); 72 if (++ITState.CurPosition == 5 - TZ) 73 ITState.CurPosition = ~0U; // Done with the IT block after this. 74 } 75 76 77 MCAsmParser &getParser() const { return Parser; } 78 MCAsmLexer &getLexer() const { return Parser.getLexer(); } 79 80 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); } 81 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); } 82 83 int tryParseRegister(); 84 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &); 85 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &); 86 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &); 87 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &); 88 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic); 89 bool parsePrefix(ARMMCExpr::VariantKind &RefKind); 90 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, 91 unsigned &ShiftAmount); 92 bool parseDirectiveWord(unsigned Size, SMLoc L); 93 bool parseDirectiveThumb(SMLoc L); 94 bool parseDirectiveThumbFunc(SMLoc L); 95 bool parseDirectiveCode(SMLoc L); 96 bool parseDirectiveSyntax(SMLoc L); 97 98 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, 99 bool &CarrySetting, unsigned &ProcessorIMod, 100 StringRef &ITMask); 101 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 102 bool &CanAcceptPredicationCode); 103 104 bool isThumb() const { 105 // FIXME: Can tablegen auto-generate this? 106 return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 107 } 108 bool isThumbOne() const { 109 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0; 110 } 111 bool isThumbTwo() const { 112 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2); 113 } 114 bool hasV6Ops() const { 115 return STI.getFeatureBits() & ARM::HasV6Ops; 116 } 117 void SwitchMode() { 118 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); 119 setAvailableFeatures(FB); 120 } 121 122 /// @name Auto-generated Match Functions 123 /// { 124 125#define GET_ASSEMBLER_HEADER 126#include "ARMGenAsmMatcher.inc" 127 128 /// } 129 130 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&); 131 OperandMatchResultTy parseCoprocNumOperand( 132 SmallVectorImpl<MCParsedAsmOperand*>&); 133 OperandMatchResultTy parseCoprocRegOperand( 134 SmallVectorImpl<MCParsedAsmOperand*>&); 135 OperandMatchResultTy parseMemBarrierOptOperand( 136 SmallVectorImpl<MCParsedAsmOperand*>&); 137 OperandMatchResultTy parseProcIFlagsOperand( 138 SmallVectorImpl<MCParsedAsmOperand*>&); 139 OperandMatchResultTy parseMSRMaskOperand( 140 SmallVectorImpl<MCParsedAsmOperand*>&); 141 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O, 142 StringRef Op, int Low, int High); 143 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 144 return parsePKHImm(O, "lsl", 0, 31); 145 } 146 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 147 return parsePKHImm(O, "asr", 1, 32); 148 } 149 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&); 150 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&); 151 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&); 152 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&); 153 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&); 154 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&); 155 156 // Asm Match Converter Methods 157 bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode, 158 const SmallVectorImpl<MCParsedAsmOperand*> &); 159 bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode, 160 const SmallVectorImpl<MCParsedAsmOperand*> &); 161 bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 162 const SmallVectorImpl<MCParsedAsmOperand*> &); 163 bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 164 const SmallVectorImpl<MCParsedAsmOperand*> &); 165 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 166 const SmallVectorImpl<MCParsedAsmOperand*> &); 167 bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 168 const SmallVectorImpl<MCParsedAsmOperand*> &); 169 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 170 const SmallVectorImpl<MCParsedAsmOperand*> &); 171 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 172 const SmallVectorImpl<MCParsedAsmOperand*> &); 173 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 174 const SmallVectorImpl<MCParsedAsmOperand*> &); 175 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 176 const SmallVectorImpl<MCParsedAsmOperand*> &); 177 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 178 const SmallVectorImpl<MCParsedAsmOperand*> &); 179 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 180 const SmallVectorImpl<MCParsedAsmOperand*> &); 181 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 182 const SmallVectorImpl<MCParsedAsmOperand*> &); 183 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode, 184 const SmallVectorImpl<MCParsedAsmOperand*> &); 185 bool cvtStrdPre(MCInst &Inst, unsigned Opcode, 186 const SmallVectorImpl<MCParsedAsmOperand*> &); 187 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 188 const SmallVectorImpl<MCParsedAsmOperand*> &); 189 bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode, 190 const SmallVectorImpl<MCParsedAsmOperand*> &); 191 192 bool validateInstruction(MCInst &Inst, 193 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 194 void processInstruction(MCInst &Inst, 195 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 196 bool shouldOmitCCOutOperand(StringRef Mnemonic, 197 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 198 199public: 200 enum ARMMatchResultTy { 201 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY, 202 Match_RequiresNotITBlock, 203 Match_RequiresV6, 204 Match_RequiresThumb2 205 }; 206 207 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser) 208 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) { 209 MCAsmParserExtension::Initialize(_Parser); 210 211 // Initialize the set of available features. 212 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 213 214 // Not in an ITBlock to start with. 215 ITState.CurPosition = ~0U; 216 } 217 218 // Implementation of the MCTargetAsmParser interface: 219 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); 220 bool ParseInstruction(StringRef Name, SMLoc NameLoc, 221 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 222 bool ParseDirective(AsmToken DirectiveID); 223 224 unsigned checkTargetMatchPredicate(MCInst &Inst); 225 226 bool MatchAndEmitInstruction(SMLoc IDLoc, 227 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 228 MCStreamer &Out); 229}; 230} // end anonymous namespace 231 232namespace { 233 234/// ARMOperand - Instances of this class represent a parsed ARM machine 235/// instruction. 236class ARMOperand : public MCParsedAsmOperand { 237 enum KindTy { 238 CondCode, 239 CCOut, 240 ITCondMask, 241 CoprocNum, 242 CoprocReg, 243 Immediate, 244 MemBarrierOpt, 245 Memory, 246 PostIndexRegister, 247 MSRMask, 248 ProcIFlags, 249 Register, 250 RegisterList, 251 DPRRegisterList, 252 SPRRegisterList, 253 ShiftedRegister, 254 ShiftedImmediate, 255 ShifterImmediate, 256 RotateImmediate, 257 BitfieldDescriptor, 258 Token 259 } Kind; 260 261 SMLoc StartLoc, EndLoc; 262 SmallVector<unsigned, 8> Registers; 263 264 union { 265 struct { 266 ARMCC::CondCodes Val; 267 } CC; 268 269 struct { 270 unsigned Val; 271 } Cop; 272 273 struct { 274 unsigned Mask:4; 275 } ITMask; 276 277 struct { 278 ARM_MB::MemBOpt Val; 279 } MBOpt; 280 281 struct { 282 ARM_PROC::IFlags Val; 283 } IFlags; 284 285 struct { 286 unsigned Val; 287 } MMask; 288 289 struct { 290 const char *Data; 291 unsigned Length; 292 } Tok; 293 294 struct { 295 unsigned RegNum; 296 } Reg; 297 298 struct { 299 const MCExpr *Val; 300 } Imm; 301 302 /// Combined record for all forms of ARM address expressions. 303 struct { 304 unsigned BaseRegNum; 305 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset 306 // was specified. 307 const MCConstantExpr *OffsetImm; // Offset immediate value 308 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL 309 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg 310 unsigned ShiftImm; // shift for OffsetReg. 311 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit) 312 } Mem; 313 314 struct { 315 unsigned RegNum; 316 bool isAdd; 317 ARM_AM::ShiftOpc ShiftTy; 318 unsigned ShiftImm; 319 } PostIdxReg; 320 321 struct { 322 bool isASR; 323 unsigned Imm; 324 } ShifterImm; 325 struct { 326 ARM_AM::ShiftOpc ShiftTy; 327 unsigned SrcReg; 328 unsigned ShiftReg; 329 unsigned ShiftImm; 330 } RegShiftedReg; 331 struct { 332 ARM_AM::ShiftOpc ShiftTy; 333 unsigned SrcReg; 334 unsigned ShiftImm; 335 } RegShiftedImm; 336 struct { 337 unsigned Imm; 338 } RotImm; 339 struct { 340 unsigned LSB; 341 unsigned Width; 342 } Bitfield; 343 }; 344 345 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 346public: 347 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() { 348 Kind = o.Kind; 349 StartLoc = o.StartLoc; 350 EndLoc = o.EndLoc; 351 switch (Kind) { 352 case CondCode: 353 CC = o.CC; 354 break; 355 case ITCondMask: 356 ITMask = o.ITMask; 357 break; 358 case Token: 359 Tok = o.Tok; 360 break; 361 case CCOut: 362 case Register: 363 Reg = o.Reg; 364 break; 365 case RegisterList: 366 case DPRRegisterList: 367 case SPRRegisterList: 368 Registers = o.Registers; 369 break; 370 case CoprocNum: 371 case CoprocReg: 372 Cop = o.Cop; 373 break; 374 case Immediate: 375 Imm = o.Imm; 376 break; 377 case MemBarrierOpt: 378 MBOpt = o.MBOpt; 379 break; 380 case Memory: 381 Mem = o.Mem; 382 break; 383 case PostIndexRegister: 384 PostIdxReg = o.PostIdxReg; 385 break; 386 case MSRMask: 387 MMask = o.MMask; 388 break; 389 case ProcIFlags: 390 IFlags = o.IFlags; 391 break; 392 case ShifterImmediate: 393 ShifterImm = o.ShifterImm; 394 break; 395 case ShiftedRegister: 396 RegShiftedReg = o.RegShiftedReg; 397 break; 398 case ShiftedImmediate: 399 RegShiftedImm = o.RegShiftedImm; 400 break; 401 case RotateImmediate: 402 RotImm = o.RotImm; 403 break; 404 case BitfieldDescriptor: 405 Bitfield = o.Bitfield; 406 break; 407 } 408 } 409 410 /// getStartLoc - Get the location of the first token of this operand. 411 SMLoc getStartLoc() const { return StartLoc; } 412 /// getEndLoc - Get the location of the last token of this operand. 413 SMLoc getEndLoc() const { return EndLoc; } 414 415 ARMCC::CondCodes getCondCode() const { 416 assert(Kind == CondCode && "Invalid access!"); 417 return CC.Val; 418 } 419 420 unsigned getCoproc() const { 421 assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!"); 422 return Cop.Val; 423 } 424 425 StringRef getToken() const { 426 assert(Kind == Token && "Invalid access!"); 427 return StringRef(Tok.Data, Tok.Length); 428 } 429 430 unsigned getReg() const { 431 assert((Kind == Register || Kind == CCOut) && "Invalid access!"); 432 return Reg.RegNum; 433 } 434 435 const SmallVectorImpl<unsigned> &getRegList() const { 436 assert((Kind == RegisterList || Kind == DPRRegisterList || 437 Kind == SPRRegisterList) && "Invalid access!"); 438 return Registers; 439 } 440 441 const MCExpr *getImm() const { 442 assert(Kind == Immediate && "Invalid access!"); 443 return Imm.Val; 444 } 445 446 ARM_MB::MemBOpt getMemBarrierOpt() const { 447 assert(Kind == MemBarrierOpt && "Invalid access!"); 448 return MBOpt.Val; 449 } 450 451 ARM_PROC::IFlags getProcIFlags() const { 452 assert(Kind == ProcIFlags && "Invalid access!"); 453 return IFlags.Val; 454 } 455 456 unsigned getMSRMask() const { 457 assert(Kind == MSRMask && "Invalid access!"); 458 return MMask.Val; 459 } 460 461 bool isCoprocNum() const { return Kind == CoprocNum; } 462 bool isCoprocReg() const { return Kind == CoprocReg; } 463 bool isCondCode() const { return Kind == CondCode; } 464 bool isCCOut() const { return Kind == CCOut; } 465 bool isITMask() const { return Kind == ITCondMask; } 466 bool isITCondCode() const { return Kind == CondCode; } 467 bool isImm() const { return Kind == Immediate; } 468 bool isImm8s4() const { 469 if (Kind != Immediate) 470 return false; 471 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 472 if (!CE) return false; 473 int64_t Value = CE->getValue(); 474 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020; 475 } 476 bool isImm0_1020s4() const { 477 if (Kind != Immediate) 478 return false; 479 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 480 if (!CE) return false; 481 int64_t Value = CE->getValue(); 482 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020; 483 } 484 bool isImm0_508s4() const { 485 if (Kind != Immediate) 486 return false; 487 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 488 if (!CE) return false; 489 int64_t Value = CE->getValue(); 490 return ((Value & 3) == 0) && Value >= 0 && Value <= 508; 491 } 492 bool isImm0_255() const { 493 if (Kind != Immediate) 494 return false; 495 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 496 if (!CE) return false; 497 int64_t Value = CE->getValue(); 498 return Value >= 0 && Value < 256; 499 } 500 bool isImm0_7() const { 501 if (Kind != Immediate) 502 return false; 503 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 504 if (!CE) return false; 505 int64_t Value = CE->getValue(); 506 return Value >= 0 && Value < 8; 507 } 508 bool isImm0_15() const { 509 if (Kind != Immediate) 510 return false; 511 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 512 if (!CE) return false; 513 int64_t Value = CE->getValue(); 514 return Value >= 0 && Value < 16; 515 } 516 bool isImm0_31() const { 517 if (Kind != Immediate) 518 return false; 519 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 520 if (!CE) return false; 521 int64_t Value = CE->getValue(); 522 return Value >= 0 && Value < 32; 523 } 524 bool isImm1_16() const { 525 if (Kind != Immediate) 526 return false; 527 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 528 if (!CE) return false; 529 int64_t Value = CE->getValue(); 530 return Value > 0 && Value < 17; 531 } 532 bool isImm1_32() const { 533 if (Kind != Immediate) 534 return false; 535 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 536 if (!CE) return false; 537 int64_t Value = CE->getValue(); 538 return Value > 0 && Value < 33; 539 } 540 bool isImm0_65535() const { 541 if (Kind != Immediate) 542 return false; 543 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 544 if (!CE) return false; 545 int64_t Value = CE->getValue(); 546 return Value >= 0 && Value < 65536; 547 } 548 bool isImm0_65535Expr() const { 549 if (Kind != Immediate) 550 return false; 551 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 552 // If it's not a constant expression, it'll generate a fixup and be 553 // handled later. 554 if (!CE) return true; 555 int64_t Value = CE->getValue(); 556 return Value >= 0 && Value < 65536; 557 } 558 bool isImm24bit() const { 559 if (Kind != Immediate) 560 return false; 561 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 562 if (!CE) return false; 563 int64_t Value = CE->getValue(); 564 return Value >= 0 && Value <= 0xffffff; 565 } 566 bool isImmThumbSR() const { 567 if (Kind != Immediate) 568 return false; 569 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 570 if (!CE) return false; 571 int64_t Value = CE->getValue(); 572 return Value > 0 && Value < 33; 573 } 574 bool isPKHLSLImm() const { 575 if (Kind != Immediate) 576 return false; 577 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 578 if (!CE) return false; 579 int64_t Value = CE->getValue(); 580 return Value >= 0 && Value < 32; 581 } 582 bool isPKHASRImm() const { 583 if (Kind != Immediate) 584 return false; 585 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 586 if (!CE) return false; 587 int64_t Value = CE->getValue(); 588 return Value > 0 && Value <= 32; 589 } 590 bool isARMSOImm() const { 591 if (Kind != Immediate) 592 return false; 593 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 594 if (!CE) return false; 595 int64_t Value = CE->getValue(); 596 return ARM_AM::getSOImmVal(Value) != -1; 597 } 598 bool isT2SOImm() const { 599 if (Kind != Immediate) 600 return false; 601 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 602 if (!CE) return false; 603 int64_t Value = CE->getValue(); 604 return ARM_AM::getT2SOImmVal(Value) != -1; 605 } 606 bool isSetEndImm() const { 607 if (Kind != Immediate) 608 return false; 609 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 610 if (!CE) return false; 611 int64_t Value = CE->getValue(); 612 return Value == 1 || Value == 0; 613 } 614 bool isReg() const { return Kind == Register; } 615 bool isRegList() const { return Kind == RegisterList; } 616 bool isDPRRegList() const { return Kind == DPRRegisterList; } 617 bool isSPRRegList() const { return Kind == SPRRegisterList; } 618 bool isToken() const { return Kind == Token; } 619 bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; } 620 bool isMemory() const { return Kind == Memory; } 621 bool isShifterImm() const { return Kind == ShifterImmediate; } 622 bool isRegShiftedReg() const { return Kind == ShiftedRegister; } 623 bool isRegShiftedImm() const { return Kind == ShiftedImmediate; } 624 bool isRotImm() const { return Kind == RotateImmediate; } 625 bool isBitfield() const { return Kind == BitfieldDescriptor; } 626 bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; } 627 bool isPostIdxReg() const { 628 return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift; 629 } 630 bool isMemNoOffset() const { 631 if (Kind != Memory) 632 return false; 633 // No offset of any kind. 634 return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0; 635 } 636 bool isAddrMode2() const { 637 if (Kind != Memory) 638 return false; 639 // Check for register offset. 640 if (Mem.OffsetRegNum) return true; 641 // Immediate offset in range [-4095, 4095]. 642 if (!Mem.OffsetImm) return true; 643 int64_t Val = Mem.OffsetImm->getValue(); 644 return Val > -4096 && Val < 4096; 645 } 646 bool isAM2OffsetImm() const { 647 if (Kind != Immediate) 648 return false; 649 // Immediate offset in range [-4095, 4095]. 650 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 651 if (!CE) return false; 652 int64_t Val = CE->getValue(); 653 return Val > -4096 && Val < 4096; 654 } 655 bool isAddrMode3() const { 656 if (Kind != Memory) 657 return false; 658 // No shifts are legal for AM3. 659 if (Mem.ShiftType != ARM_AM::no_shift) return false; 660 // Check for register offset. 661 if (Mem.OffsetRegNum) return true; 662 // Immediate offset in range [-255, 255]. 663 if (!Mem.OffsetImm) return true; 664 int64_t Val = Mem.OffsetImm->getValue(); 665 return Val > -256 && Val < 256; 666 } 667 bool isAM3Offset() const { 668 if (Kind != Immediate && Kind != PostIndexRegister) 669 return false; 670 if (Kind == PostIndexRegister) 671 return PostIdxReg.ShiftTy == ARM_AM::no_shift; 672 // Immediate offset in range [-255, 255]. 673 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 674 if (!CE) return false; 675 int64_t Val = CE->getValue(); 676 // Special case, #-0 is INT32_MIN. 677 return (Val > -256 && Val < 256) || Val == INT32_MIN; 678 } 679 bool isAddrMode5() const { 680 if (Kind != Memory) 681 return false; 682 // Check for register offset. 683 if (Mem.OffsetRegNum) return false; 684 // Immediate offset in range [-1020, 1020] and a multiple of 4. 685 if (!Mem.OffsetImm) return true; 686 int64_t Val = Mem.OffsetImm->getValue(); 687 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) || 688 Val == INT32_MIN; 689 } 690 bool isMemRegOffset() const { 691 if (Kind != Memory || !Mem.OffsetRegNum) 692 return false; 693 return true; 694 } 695 bool isT2MemRegOffset() const { 696 if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative) 697 return false; 698 // Only lsl #{0, 1, 2, 3} allowed. 699 if (Mem.ShiftType == ARM_AM::no_shift) 700 return true; 701 if (Mem.ShiftType != ARM_AM::lsl || Mem.ShiftImm > 3) 702 return false; 703 return true; 704 } 705 bool isMemThumbRR() const { 706 // Thumb reg+reg addressing is simple. Just two registers, a base and 707 // an offset. No shifts, negations or any other complicating factors. 708 if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative || 709 Mem.ShiftType != ARM_AM::no_shift) 710 return false; 711 return isARMLowRegister(Mem.BaseRegNum) && 712 (!Mem.OffsetRegNum || isARMLowRegister(Mem.OffsetRegNum)); 713 } 714 bool isMemThumbRIs4() const { 715 if (Kind != Memory || Mem.OffsetRegNum != 0 || 716 !isARMLowRegister(Mem.BaseRegNum)) 717 return false; 718 // Immediate offset, multiple of 4 in range [0, 124]. 719 if (!Mem.OffsetImm) return true; 720 int64_t Val = Mem.OffsetImm->getValue(); 721 return Val >= 0 && Val <= 124 && (Val % 4) == 0; 722 } 723 bool isMemThumbRIs2() const { 724 if (Kind != Memory || Mem.OffsetRegNum != 0 || 725 !isARMLowRegister(Mem.BaseRegNum)) 726 return false; 727 // Immediate offset, multiple of 4 in range [0, 62]. 728 if (!Mem.OffsetImm) return true; 729 int64_t Val = Mem.OffsetImm->getValue(); 730 return Val >= 0 && Val <= 62 && (Val % 2) == 0; 731 } 732 bool isMemThumbRIs1() const { 733 if (Kind != Memory || Mem.OffsetRegNum != 0 || 734 !isARMLowRegister(Mem.BaseRegNum)) 735 return false; 736 // Immediate offset in range [0, 31]. 737 if (!Mem.OffsetImm) return true; 738 int64_t Val = Mem.OffsetImm->getValue(); 739 return Val >= 0 && Val <= 31; 740 } 741 bool isMemThumbSPI() const { 742 if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP) 743 return false; 744 // Immediate offset, multiple of 4 in range [0, 1020]. 745 if (!Mem.OffsetImm) return true; 746 int64_t Val = Mem.OffsetImm->getValue(); 747 return Val >= 0 && Val <= 1020 && (Val % 4) == 0; 748 } 749 bool isMemImm8s4Offset() const { 750 if (Kind != Memory || Mem.OffsetRegNum != 0) 751 return false; 752 // Immediate offset a multiple of 4 in range [-1020, 1020]. 753 if (!Mem.OffsetImm) return true; 754 int64_t Val = Mem.OffsetImm->getValue(); 755 return Val >= -1020 && Val <= 1020 && (Val & 3) == 0; 756 } 757 bool isMemImm0_1020s4Offset() const { 758 if (Kind != Memory || Mem.OffsetRegNum != 0) 759 return false; 760 // Immediate offset a multiple of 4 in range [0, 1020]. 761 if (!Mem.OffsetImm) return true; 762 int64_t Val = Mem.OffsetImm->getValue(); 763 return Val >= 0 && Val <= 1020 && (Val & 3) == 0; 764 } 765 bool isMemImm8Offset() const { 766 if (Kind != Memory || Mem.OffsetRegNum != 0) 767 return false; 768 // Immediate offset in range [-255, 255]. 769 if (!Mem.OffsetImm) return true; 770 int64_t Val = Mem.OffsetImm->getValue(); 771 return Val > -256 && Val < 256; 772 } 773 bool isMemPosImm8Offset() const { 774 if (Kind != Memory || Mem.OffsetRegNum != 0) 775 return false; 776 // Immediate offset in range [0, 255]. 777 if (!Mem.OffsetImm) return true; 778 int64_t Val = Mem.OffsetImm->getValue(); 779 return Val >= 0 && Val < 256; 780 } 781 bool isMemNegImm8Offset() const { 782 if (Kind != Memory || Mem.OffsetRegNum != 0) 783 return false; 784 // Immediate offset in range [-255, -1]. 785 if (!Mem.OffsetImm) return true; 786 int64_t Val = Mem.OffsetImm->getValue(); 787 return Val > -256 && Val < 0; 788 } 789 bool isMemUImm12Offset() const { 790 // If we have an immediate that's not a constant, treat it as a label 791 // reference needing a fixup. If it is a constant, it's something else 792 // and we reject it. 793 if (Kind == Immediate && !isa<MCConstantExpr>(getImm())) 794 return true; 795 796 if (Kind != Memory || Mem.OffsetRegNum != 0) 797 return false; 798 // Immediate offset in range [0, 4095]. 799 if (!Mem.OffsetImm) return true; 800 int64_t Val = Mem.OffsetImm->getValue(); 801 return (Val >= 0 && Val < 4096); 802 } 803 bool isMemImm12Offset() const { 804 // If we have an immediate that's not a constant, treat it as a label 805 // reference needing a fixup. If it is a constant, it's something else 806 // and we reject it. 807 if (Kind == Immediate && !isa<MCConstantExpr>(getImm())) 808 return true; 809 810 if (Kind != Memory || Mem.OffsetRegNum != 0) 811 return false; 812 // Immediate offset in range [-4095, 4095]. 813 if (!Mem.OffsetImm) return true; 814 int64_t Val = Mem.OffsetImm->getValue(); 815 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 816 } 817 bool isPostIdxImm8() const { 818 if (Kind != Immediate) 819 return false; 820 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 821 if (!CE) return false; 822 int64_t Val = CE->getValue(); 823 return (Val > -256 && Val < 256) || (Val == INT32_MIN); 824 } 825 826 bool isMSRMask() const { return Kind == MSRMask; } 827 bool isProcIFlags() const { return Kind == ProcIFlags; } 828 829 void addExpr(MCInst &Inst, const MCExpr *Expr) const { 830 // Add as immediates when possible. Null MCExpr = 0. 831 if (Expr == 0) 832 Inst.addOperand(MCOperand::CreateImm(0)); 833 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) 834 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 835 else 836 Inst.addOperand(MCOperand::CreateExpr(Expr)); 837 } 838 839 void addCondCodeOperands(MCInst &Inst, unsigned N) const { 840 assert(N == 2 && "Invalid number of operands!"); 841 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 842 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; 843 Inst.addOperand(MCOperand::CreateReg(RegNum)); 844 } 845 846 void addCoprocNumOperands(MCInst &Inst, unsigned N) const { 847 assert(N == 1 && "Invalid number of operands!"); 848 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 849 } 850 851 void addITMaskOperands(MCInst &Inst, unsigned N) const { 852 assert(N == 1 && "Invalid number of operands!"); 853 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask)); 854 } 855 856 void addITCondCodeOperands(MCInst &Inst, unsigned N) const { 857 assert(N == 1 && "Invalid number of operands!"); 858 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 859 } 860 861 void addCoprocRegOperands(MCInst &Inst, unsigned N) const { 862 assert(N == 1 && "Invalid number of operands!"); 863 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 864 } 865 866 void addCCOutOperands(MCInst &Inst, unsigned N) const { 867 assert(N == 1 && "Invalid number of operands!"); 868 Inst.addOperand(MCOperand::CreateReg(getReg())); 869 } 870 871 void addRegOperands(MCInst &Inst, unsigned N) const { 872 assert(N == 1 && "Invalid number of operands!"); 873 Inst.addOperand(MCOperand::CreateReg(getReg())); 874 } 875 876 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { 877 assert(N == 3 && "Invalid number of operands!"); 878 assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!"); 879 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); 880 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); 881 Inst.addOperand(MCOperand::CreateImm( 882 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); 883 } 884 885 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { 886 assert(N == 2 && "Invalid number of operands!"); 887 assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!"); 888 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); 889 Inst.addOperand(MCOperand::CreateImm( 890 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm))); 891 } 892 893 void addShifterImmOperands(MCInst &Inst, unsigned N) const { 894 assert(N == 1 && "Invalid number of operands!"); 895 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) | 896 ShifterImm.Imm)); 897 } 898 899 void addRegListOperands(MCInst &Inst, unsigned N) const { 900 assert(N == 1 && "Invalid number of operands!"); 901 const SmallVectorImpl<unsigned> &RegList = getRegList(); 902 for (SmallVectorImpl<unsigned>::const_iterator 903 I = RegList.begin(), E = RegList.end(); I != E; ++I) 904 Inst.addOperand(MCOperand::CreateReg(*I)); 905 } 906 907 void addDPRRegListOperands(MCInst &Inst, unsigned N) const { 908 addRegListOperands(Inst, N); 909 } 910 911 void addSPRRegListOperands(MCInst &Inst, unsigned N) const { 912 addRegListOperands(Inst, N); 913 } 914 915 void addRotImmOperands(MCInst &Inst, unsigned N) const { 916 assert(N == 1 && "Invalid number of operands!"); 917 // Encoded as val>>3. The printer handles display as 8, 16, 24. 918 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3)); 919 } 920 921 void addBitfieldOperands(MCInst &Inst, unsigned N) const { 922 assert(N == 1 && "Invalid number of operands!"); 923 // Munge the lsb/width into a bitfield mask. 924 unsigned lsb = Bitfield.LSB; 925 unsigned width = Bitfield.Width; 926 // Make a 32-bit mask w/ the referenced bits clear and all other bits set. 927 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> 928 (32 - (lsb + width))); 929 Inst.addOperand(MCOperand::CreateImm(Mask)); 930 } 931 932 void addImmOperands(MCInst &Inst, unsigned N) const { 933 assert(N == 1 && "Invalid number of operands!"); 934 addExpr(Inst, getImm()); 935 } 936 937 void addImm8s4Operands(MCInst &Inst, unsigned N) const { 938 assert(N == 1 && "Invalid number of operands!"); 939 // FIXME: We really want to scale the value here, but the LDRD/STRD 940 // instruction don't encode operands that way yet. 941 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 942 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 943 } 944 945 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { 946 assert(N == 1 && "Invalid number of operands!"); 947 // The immediate is scaled by four in the encoding and is stored 948 // in the MCInst as such. Lop off the low two bits here. 949 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 950 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 951 } 952 953 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { 954 assert(N == 1 && "Invalid number of operands!"); 955 // The immediate is scaled by four in the encoding and is stored 956 // in the MCInst as such. Lop off the low two bits here. 957 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 958 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 959 } 960 961 void addImm0_255Operands(MCInst &Inst, unsigned N) const { 962 assert(N == 1 && "Invalid number of operands!"); 963 addExpr(Inst, getImm()); 964 } 965 966 void addImm0_7Operands(MCInst &Inst, unsigned N) const { 967 assert(N == 1 && "Invalid number of operands!"); 968 addExpr(Inst, getImm()); 969 } 970 971 void addImm0_15Operands(MCInst &Inst, unsigned N) const { 972 assert(N == 1 && "Invalid number of operands!"); 973 addExpr(Inst, getImm()); 974 } 975 976 void addImm0_31Operands(MCInst &Inst, unsigned N) const { 977 assert(N == 1 && "Invalid number of operands!"); 978 addExpr(Inst, getImm()); 979 } 980 981 void addImm1_16Operands(MCInst &Inst, unsigned N) const { 982 assert(N == 1 && "Invalid number of operands!"); 983 // The constant encodes as the immediate-1, and we store in the instruction 984 // the bits as encoded, so subtract off one here. 985 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 986 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 987 } 988 989 void addImm1_32Operands(MCInst &Inst, unsigned N) const { 990 assert(N == 1 && "Invalid number of operands!"); 991 // The constant encodes as the immediate-1, and we store in the instruction 992 // the bits as encoded, so subtract off one here. 993 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 994 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 995 } 996 997 void addImm0_65535Operands(MCInst &Inst, unsigned N) const { 998 assert(N == 1 && "Invalid number of operands!"); 999 addExpr(Inst, getImm()); 1000 } 1001 1002 void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const { 1003 assert(N == 1 && "Invalid number of operands!"); 1004 addExpr(Inst, getImm()); 1005 } 1006 1007 void addImm24bitOperands(MCInst &Inst, unsigned N) const { 1008 assert(N == 1 && "Invalid number of operands!"); 1009 addExpr(Inst, getImm()); 1010 } 1011 1012 void addImmThumbSROperands(MCInst &Inst, unsigned N) const { 1013 assert(N == 1 && "Invalid number of operands!"); 1014 // The constant encodes as the immediate, except for 32, which encodes as 1015 // zero. 1016 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1017 unsigned Imm = CE->getValue(); 1018 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm))); 1019 } 1020 1021 void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const { 1022 assert(N == 1 && "Invalid number of operands!"); 1023 addExpr(Inst, getImm()); 1024 } 1025 1026 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { 1027 assert(N == 1 && "Invalid number of operands!"); 1028 // An ASR value of 32 encodes as 0, so that's how we want to add it to 1029 // the instruction as well. 1030 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1031 int Val = CE->getValue(); 1032 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val)); 1033 } 1034 1035 void addARMSOImmOperands(MCInst &Inst, unsigned N) const { 1036 assert(N == 1 && "Invalid number of operands!"); 1037 addExpr(Inst, getImm()); 1038 } 1039 1040 void addT2SOImmOperands(MCInst &Inst, unsigned N) const { 1041 assert(N == 1 && "Invalid number of operands!"); 1042 addExpr(Inst, getImm()); 1043 } 1044 1045 void addSetEndImmOperands(MCInst &Inst, unsigned N) const { 1046 assert(N == 1 && "Invalid number of operands!"); 1047 addExpr(Inst, getImm()); 1048 } 1049 1050 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { 1051 assert(N == 1 && "Invalid number of operands!"); 1052 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt()))); 1053 } 1054 1055 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { 1056 assert(N == 1 && "Invalid number of operands!"); 1057 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1058 } 1059 1060 void addAddrMode2Operands(MCInst &Inst, unsigned N) const { 1061 assert(N == 3 && "Invalid number of operands!"); 1062 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0; 1063 if (!Mem.OffsetRegNum) { 1064 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1065 // Special case for #-0 1066 if (Val == INT32_MIN) Val = 0; 1067 if (Val < 0) Val = -Val; 1068 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1069 } else { 1070 // For register offset, we encode the shift type and negation flag 1071 // here. 1072 Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 1073 Mem.ShiftImm, Mem.ShiftType); 1074 } 1075 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1076 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum)); 1077 Inst.addOperand(MCOperand::CreateImm(Val)); 1078 } 1079 1080 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { 1081 assert(N == 2 && "Invalid number of operands!"); 1082 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1083 assert(CE && "non-constant AM2OffsetImm operand!"); 1084 int32_t Val = CE->getValue(); 1085 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1086 // Special case for #-0 1087 if (Val == INT32_MIN) Val = 0; 1088 if (Val < 0) Val = -Val; 1089 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1090 Inst.addOperand(MCOperand::CreateReg(0)); 1091 Inst.addOperand(MCOperand::CreateImm(Val)); 1092 } 1093 1094 void addAddrMode3Operands(MCInst &Inst, unsigned N) const { 1095 assert(N == 3 && "Invalid number of operands!"); 1096 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0; 1097 if (!Mem.OffsetRegNum) { 1098 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1099 // Special case for #-0 1100 if (Val == INT32_MIN) Val = 0; 1101 if (Val < 0) Val = -Val; 1102 Val = ARM_AM::getAM3Opc(AddSub, Val); 1103 } else { 1104 // For register offset, we encode the shift type and negation flag 1105 // here. 1106 Val = ARM_AM::getAM3Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 0); 1107 } 1108 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1109 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum)); 1110 Inst.addOperand(MCOperand::CreateImm(Val)); 1111 } 1112 1113 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { 1114 assert(N == 2 && "Invalid number of operands!"); 1115 if (Kind == PostIndexRegister) { 1116 int32_t Val = 1117 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); 1118 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1119 Inst.addOperand(MCOperand::CreateImm(Val)); 1120 return; 1121 } 1122 1123 // Constant offset. 1124 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm()); 1125 int32_t Val = CE->getValue(); 1126 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1127 // Special case for #-0 1128 if (Val == INT32_MIN) Val = 0; 1129 if (Val < 0) Val = -Val; 1130 Val = ARM_AM::getAM3Opc(AddSub, Val); 1131 Inst.addOperand(MCOperand::CreateReg(0)); 1132 Inst.addOperand(MCOperand::CreateImm(Val)); 1133 } 1134 1135 void addAddrMode5Operands(MCInst &Inst, unsigned N) const { 1136 assert(N == 2 && "Invalid number of operands!"); 1137 // The lower two bits are always zero and as such are not encoded. 1138 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0; 1139 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1140 // Special case for #-0 1141 if (Val == INT32_MIN) Val = 0; 1142 if (Val < 0) Val = -Val; 1143 Val = ARM_AM::getAM5Opc(AddSub, Val); 1144 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1145 Inst.addOperand(MCOperand::CreateImm(Val)); 1146 } 1147 1148 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const { 1149 assert(N == 2 && "Invalid number of operands!"); 1150 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0; 1151 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1152 Inst.addOperand(MCOperand::CreateImm(Val)); 1153 } 1154 1155 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const { 1156 assert(N == 2 && "Invalid number of operands!"); 1157 // The lower two bits are always zero and as such are not encoded. 1158 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0; 1159 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1160 Inst.addOperand(MCOperand::CreateImm(Val)); 1161 } 1162 1163 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1164 assert(N == 2 && "Invalid number of operands!"); 1165 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0; 1166 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1167 Inst.addOperand(MCOperand::CreateImm(Val)); 1168 } 1169 1170 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1171 addMemImm8OffsetOperands(Inst, N); 1172 } 1173 1174 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1175 addMemImm8OffsetOperands(Inst, N); 1176 } 1177 1178 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { 1179 assert(N == 2 && "Invalid number of operands!"); 1180 // If this is an immediate, it's a label reference. 1181 if (Kind == Immediate) { 1182 addExpr(Inst, getImm()); 1183 Inst.addOperand(MCOperand::CreateImm(0)); 1184 return; 1185 } 1186 1187 // Otherwise, it's a normal memory reg+offset. 1188 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0; 1189 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1190 Inst.addOperand(MCOperand::CreateImm(Val)); 1191 } 1192 1193 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { 1194 assert(N == 2 && "Invalid number of operands!"); 1195 // If this is an immediate, it's a label reference. 1196 if (Kind == Immediate) { 1197 addExpr(Inst, getImm()); 1198 Inst.addOperand(MCOperand::CreateImm(0)); 1199 return; 1200 } 1201 1202 // Otherwise, it's a normal memory reg+offset. 1203 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0; 1204 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1205 Inst.addOperand(MCOperand::CreateImm(Val)); 1206 } 1207 1208 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { 1209 assert(N == 3 && "Invalid number of operands!"); 1210 unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 1211 Mem.ShiftImm, Mem.ShiftType); 1212 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1213 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum)); 1214 Inst.addOperand(MCOperand::CreateImm(Val)); 1215 } 1216 1217 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { 1218 assert(N == 3 && "Invalid number of operands!"); 1219 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1220 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum)); 1221 Inst.addOperand(MCOperand::CreateImm(Mem.ShiftImm)); 1222 } 1223 1224 void addMemThumbRROperands(MCInst &Inst, unsigned N) const { 1225 assert(N == 2 && "Invalid number of operands!"); 1226 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1227 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum)); 1228 } 1229 1230 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const { 1231 assert(N == 2 && "Invalid number of operands!"); 1232 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0; 1233 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1234 Inst.addOperand(MCOperand::CreateImm(Val)); 1235 } 1236 1237 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const { 1238 assert(N == 2 && "Invalid number of operands!"); 1239 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 2) : 0; 1240 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1241 Inst.addOperand(MCOperand::CreateImm(Val)); 1242 } 1243 1244 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { 1245 assert(N == 2 && "Invalid number of operands!"); 1246 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0; 1247 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1248 Inst.addOperand(MCOperand::CreateImm(Val)); 1249 } 1250 1251 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { 1252 assert(N == 2 && "Invalid number of operands!"); 1253 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0; 1254 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum)); 1255 Inst.addOperand(MCOperand::CreateImm(Val)); 1256 } 1257 1258 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { 1259 assert(N == 1 && "Invalid number of operands!"); 1260 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1261 assert(CE && "non-constant post-idx-imm8 operand!"); 1262 int Imm = CE->getValue(); 1263 bool isAdd = Imm >= 0; 1264 if (Imm == INT32_MIN) Imm = 0; 1265 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; 1266 Inst.addOperand(MCOperand::CreateImm(Imm)); 1267 } 1268 1269 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { 1270 assert(N == 2 && "Invalid number of operands!"); 1271 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1272 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd)); 1273 } 1274 1275 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { 1276 assert(N == 2 && "Invalid number of operands!"); 1277 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1278 // The sign, shift type, and shift amount are encoded in a single operand 1279 // using the AM2 encoding helpers. 1280 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; 1281 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, 1282 PostIdxReg.ShiftTy); 1283 Inst.addOperand(MCOperand::CreateImm(Imm)); 1284 } 1285 1286 void addMSRMaskOperands(MCInst &Inst, unsigned N) const { 1287 assert(N == 1 && "Invalid number of operands!"); 1288 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask()))); 1289 } 1290 1291 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { 1292 assert(N == 1 && "Invalid number of operands!"); 1293 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags()))); 1294 } 1295 1296 virtual void print(raw_ostream &OS) const; 1297 1298 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) { 1299 ARMOperand *Op = new ARMOperand(ITCondMask); 1300 Op->ITMask.Mask = Mask; 1301 Op->StartLoc = S; 1302 Op->EndLoc = S; 1303 return Op; 1304 } 1305 1306 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) { 1307 ARMOperand *Op = new ARMOperand(CondCode); 1308 Op->CC.Val = CC; 1309 Op->StartLoc = S; 1310 Op->EndLoc = S; 1311 return Op; 1312 } 1313 1314 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) { 1315 ARMOperand *Op = new ARMOperand(CoprocNum); 1316 Op->Cop.Val = CopVal; 1317 Op->StartLoc = S; 1318 Op->EndLoc = S; 1319 return Op; 1320 } 1321 1322 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) { 1323 ARMOperand *Op = new ARMOperand(CoprocReg); 1324 Op->Cop.Val = CopVal; 1325 Op->StartLoc = S; 1326 Op->EndLoc = S; 1327 return Op; 1328 } 1329 1330 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) { 1331 ARMOperand *Op = new ARMOperand(CCOut); 1332 Op->Reg.RegNum = RegNum; 1333 Op->StartLoc = S; 1334 Op->EndLoc = S; 1335 return Op; 1336 } 1337 1338 static ARMOperand *CreateToken(StringRef Str, SMLoc S) { 1339 ARMOperand *Op = new ARMOperand(Token); 1340 Op->Tok.Data = Str.data(); 1341 Op->Tok.Length = Str.size(); 1342 Op->StartLoc = S; 1343 Op->EndLoc = S; 1344 return Op; 1345 } 1346 1347 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { 1348 ARMOperand *Op = new ARMOperand(Register); 1349 Op->Reg.RegNum = RegNum; 1350 Op->StartLoc = S; 1351 Op->EndLoc = E; 1352 return Op; 1353 } 1354 1355 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, 1356 unsigned SrcReg, 1357 unsigned ShiftReg, 1358 unsigned ShiftImm, 1359 SMLoc S, SMLoc E) { 1360 ARMOperand *Op = new ARMOperand(ShiftedRegister); 1361 Op->RegShiftedReg.ShiftTy = ShTy; 1362 Op->RegShiftedReg.SrcReg = SrcReg; 1363 Op->RegShiftedReg.ShiftReg = ShiftReg; 1364 Op->RegShiftedReg.ShiftImm = ShiftImm; 1365 Op->StartLoc = S; 1366 Op->EndLoc = E; 1367 return Op; 1368 } 1369 1370 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, 1371 unsigned SrcReg, 1372 unsigned ShiftImm, 1373 SMLoc S, SMLoc E) { 1374 ARMOperand *Op = new ARMOperand(ShiftedImmediate); 1375 Op->RegShiftedImm.ShiftTy = ShTy; 1376 Op->RegShiftedImm.SrcReg = SrcReg; 1377 Op->RegShiftedImm.ShiftImm = ShiftImm; 1378 Op->StartLoc = S; 1379 Op->EndLoc = E; 1380 return Op; 1381 } 1382 1383 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm, 1384 SMLoc S, SMLoc E) { 1385 ARMOperand *Op = new ARMOperand(ShifterImmediate); 1386 Op->ShifterImm.isASR = isASR; 1387 Op->ShifterImm.Imm = Imm; 1388 Op->StartLoc = S; 1389 Op->EndLoc = E; 1390 return Op; 1391 } 1392 1393 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) { 1394 ARMOperand *Op = new ARMOperand(RotateImmediate); 1395 Op->RotImm.Imm = Imm; 1396 Op->StartLoc = S; 1397 Op->EndLoc = E; 1398 return Op; 1399 } 1400 1401 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width, 1402 SMLoc S, SMLoc E) { 1403 ARMOperand *Op = new ARMOperand(BitfieldDescriptor); 1404 Op->Bitfield.LSB = LSB; 1405 Op->Bitfield.Width = Width; 1406 Op->StartLoc = S; 1407 Op->EndLoc = E; 1408 return Op; 1409 } 1410 1411 static ARMOperand * 1412 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs, 1413 SMLoc StartLoc, SMLoc EndLoc) { 1414 KindTy Kind = RegisterList; 1415 1416 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first)) 1417 Kind = DPRRegisterList; 1418 else if (ARMMCRegisterClasses[ARM::SPRRegClassID]. 1419 contains(Regs.front().first)) 1420 Kind = SPRRegisterList; 1421 1422 ARMOperand *Op = new ARMOperand(Kind); 1423 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator 1424 I = Regs.begin(), E = Regs.end(); I != E; ++I) 1425 Op->Registers.push_back(I->first); 1426 array_pod_sort(Op->Registers.begin(), Op->Registers.end()); 1427 Op->StartLoc = StartLoc; 1428 Op->EndLoc = EndLoc; 1429 return Op; 1430 } 1431 1432 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { 1433 ARMOperand *Op = new ARMOperand(Immediate); 1434 Op->Imm.Val = Val; 1435 Op->StartLoc = S; 1436 Op->EndLoc = E; 1437 return Op; 1438 } 1439 1440 static ARMOperand *CreateMem(unsigned BaseRegNum, 1441 const MCConstantExpr *OffsetImm, 1442 unsigned OffsetRegNum, 1443 ARM_AM::ShiftOpc ShiftType, 1444 unsigned ShiftImm, 1445 bool isNegative, 1446 SMLoc S, SMLoc E) { 1447 ARMOperand *Op = new ARMOperand(Memory); 1448 Op->Mem.BaseRegNum = BaseRegNum; 1449 Op->Mem.OffsetImm = OffsetImm; 1450 Op->Mem.OffsetRegNum = OffsetRegNum; 1451 Op->Mem.ShiftType = ShiftType; 1452 Op->Mem.ShiftImm = ShiftImm; 1453 Op->Mem.isNegative = isNegative; 1454 Op->StartLoc = S; 1455 Op->EndLoc = E; 1456 return Op; 1457 } 1458 1459 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd, 1460 ARM_AM::ShiftOpc ShiftTy, 1461 unsigned ShiftImm, 1462 SMLoc S, SMLoc E) { 1463 ARMOperand *Op = new ARMOperand(PostIndexRegister); 1464 Op->PostIdxReg.RegNum = RegNum; 1465 Op->PostIdxReg.isAdd = isAdd; 1466 Op->PostIdxReg.ShiftTy = ShiftTy; 1467 Op->PostIdxReg.ShiftImm = ShiftImm; 1468 Op->StartLoc = S; 1469 Op->EndLoc = E; 1470 return Op; 1471 } 1472 1473 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) { 1474 ARMOperand *Op = new ARMOperand(MemBarrierOpt); 1475 Op->MBOpt.Val = Opt; 1476 Op->StartLoc = S; 1477 Op->EndLoc = S; 1478 return Op; 1479 } 1480 1481 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) { 1482 ARMOperand *Op = new ARMOperand(ProcIFlags); 1483 Op->IFlags.Val = IFlags; 1484 Op->StartLoc = S; 1485 Op->EndLoc = S; 1486 return Op; 1487 } 1488 1489 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) { 1490 ARMOperand *Op = new ARMOperand(MSRMask); 1491 Op->MMask.Val = MMask; 1492 Op->StartLoc = S; 1493 Op->EndLoc = S; 1494 return Op; 1495 } 1496}; 1497 1498} // end anonymous namespace. 1499 1500void ARMOperand::print(raw_ostream &OS) const { 1501 switch (Kind) { 1502 case CondCode: 1503 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; 1504 break; 1505 case CCOut: 1506 OS << "<ccout " << getReg() << ">"; 1507 break; 1508 case ITCondMask: { 1509 static char MaskStr[][6] = { "()", "(t)", "(e)", "(tt)", "(et)", "(te)", 1510 "(ee)", "(ttt)", "(ett)", "(tet)", "(eet)", "(tte)", "(ete)", 1511 "(tee)", "(eee)" }; 1512 assert((ITMask.Mask & 0xf) == ITMask.Mask); 1513 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">"; 1514 break; 1515 } 1516 case CoprocNum: 1517 OS << "<coprocessor number: " << getCoproc() << ">"; 1518 break; 1519 case CoprocReg: 1520 OS << "<coprocessor register: " << getCoproc() << ">"; 1521 break; 1522 case MSRMask: 1523 OS << "<mask: " << getMSRMask() << ">"; 1524 break; 1525 case Immediate: 1526 getImm()->print(OS); 1527 break; 1528 case MemBarrierOpt: 1529 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">"; 1530 break; 1531 case Memory: 1532 OS << "<memory " 1533 << " base:" << Mem.BaseRegNum; 1534 OS << ">"; 1535 break; 1536 case PostIndexRegister: 1537 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") 1538 << PostIdxReg.RegNum; 1539 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) 1540 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " 1541 << PostIdxReg.ShiftImm; 1542 OS << ">"; 1543 break; 1544 case ProcIFlags: { 1545 OS << "<ARM_PROC::"; 1546 unsigned IFlags = getProcIFlags(); 1547 for (int i=2; i >= 0; --i) 1548 if (IFlags & (1 << i)) 1549 OS << ARM_PROC::IFlagsToString(1 << i); 1550 OS << ">"; 1551 break; 1552 } 1553 case Register: 1554 OS << "<register " << getReg() << ">"; 1555 break; 1556 case ShifterImmediate: 1557 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl") 1558 << " #" << ShifterImm.Imm << ">"; 1559 break; 1560 case ShiftedRegister: 1561 OS << "<so_reg_reg " 1562 << RegShiftedReg.SrcReg 1563 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm)) 1564 << ", " << RegShiftedReg.ShiftReg << ", " 1565 << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm) 1566 << ">"; 1567 break; 1568 case ShiftedImmediate: 1569 OS << "<so_reg_imm " 1570 << RegShiftedImm.SrcReg 1571 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm)) 1572 << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm) 1573 << ">"; 1574 break; 1575 case RotateImmediate: 1576 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">"; 1577 break; 1578 case BitfieldDescriptor: 1579 OS << "<bitfield " << "lsb: " << Bitfield.LSB 1580 << ", width: " << Bitfield.Width << ">"; 1581 break; 1582 case RegisterList: 1583 case DPRRegisterList: 1584 case SPRRegisterList: { 1585 OS << "<register_list "; 1586 1587 const SmallVectorImpl<unsigned> &RegList = getRegList(); 1588 for (SmallVectorImpl<unsigned>::const_iterator 1589 I = RegList.begin(), E = RegList.end(); I != E; ) { 1590 OS << *I; 1591 if (++I < E) OS << ", "; 1592 } 1593 1594 OS << ">"; 1595 break; 1596 } 1597 case Token: 1598 OS << "'" << getToken() << "'"; 1599 break; 1600 } 1601} 1602 1603/// @name Auto-generated Match Functions 1604/// { 1605 1606static unsigned MatchRegisterName(StringRef Name); 1607 1608/// } 1609 1610bool ARMAsmParser::ParseRegister(unsigned &RegNo, 1611 SMLoc &StartLoc, SMLoc &EndLoc) { 1612 RegNo = tryParseRegister(); 1613 1614 return (RegNo == (unsigned)-1); 1615} 1616 1617/// Try to parse a register name. The token must be an Identifier when called, 1618/// and if it is a register name the token is eaten and the register number is 1619/// returned. Otherwise return -1. 1620/// 1621int ARMAsmParser::tryParseRegister() { 1622 const AsmToken &Tok = Parser.getTok(); 1623 if (Tok.isNot(AsmToken::Identifier)) return -1; 1624 1625 // FIXME: Validate register for the current architecture; we have to do 1626 // validation later, so maybe there is no need for this here. 1627 std::string upperCase = Tok.getString().str(); 1628 std::string lowerCase = LowercaseString(upperCase); 1629 unsigned RegNum = MatchRegisterName(lowerCase); 1630 if (!RegNum) { 1631 RegNum = StringSwitch<unsigned>(lowerCase) 1632 .Case("r13", ARM::SP) 1633 .Case("r14", ARM::LR) 1634 .Case("r15", ARM::PC) 1635 .Case("ip", ARM::R12) 1636 .Default(0); 1637 } 1638 if (!RegNum) return -1; 1639 1640 Parser.Lex(); // Eat identifier token. 1641 return RegNum; 1642} 1643 1644// Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. 1645// If a recoverable error occurs, return 1. If an irrecoverable error 1646// occurs, return -1. An irrecoverable error is one where tokens have been 1647// consumed in the process of trying to parse the shifter (i.e., when it is 1648// indeed a shifter operand, but malformed). 1649int ARMAsmParser::tryParseShiftRegister( 1650 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1651 SMLoc S = Parser.getTok().getLoc(); 1652 const AsmToken &Tok = Parser.getTok(); 1653 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1654 1655 std::string upperCase = Tok.getString().str(); 1656 std::string lowerCase = LowercaseString(upperCase); 1657 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) 1658 .Case("lsl", ARM_AM::lsl) 1659 .Case("lsr", ARM_AM::lsr) 1660 .Case("asr", ARM_AM::asr) 1661 .Case("ror", ARM_AM::ror) 1662 .Case("rrx", ARM_AM::rrx) 1663 .Default(ARM_AM::no_shift); 1664 1665 if (ShiftTy == ARM_AM::no_shift) 1666 return 1; 1667 1668 Parser.Lex(); // Eat the operator. 1669 1670 // The source register for the shift has already been added to the 1671 // operand list, so we need to pop it off and combine it into the shifted 1672 // register operand instead. 1673 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val()); 1674 if (!PrevOp->isReg()) 1675 return Error(PrevOp->getStartLoc(), "shift must be of a register"); 1676 int SrcReg = PrevOp->getReg(); 1677 int64_t Imm = 0; 1678 int ShiftReg = 0; 1679 if (ShiftTy == ARM_AM::rrx) { 1680 // RRX Doesn't have an explicit shift amount. The encoder expects 1681 // the shift register to be the same as the source register. Seems odd, 1682 // but OK. 1683 ShiftReg = SrcReg; 1684 } else { 1685 // Figure out if this is shifted by a constant or a register (for non-RRX). 1686 if (Parser.getTok().is(AsmToken::Hash)) { 1687 Parser.Lex(); // Eat hash. 1688 SMLoc ImmLoc = Parser.getTok().getLoc(); 1689 const MCExpr *ShiftExpr = 0; 1690 if (getParser().ParseExpression(ShiftExpr)) { 1691 Error(ImmLoc, "invalid immediate shift value"); 1692 return -1; 1693 } 1694 // The expression must be evaluatable as an immediate. 1695 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr); 1696 if (!CE) { 1697 Error(ImmLoc, "invalid immediate shift value"); 1698 return -1; 1699 } 1700 // Range check the immediate. 1701 // lsl, ror: 0 <= imm <= 31 1702 // lsr, asr: 0 <= imm <= 32 1703 Imm = CE->getValue(); 1704 if (Imm < 0 || 1705 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || 1706 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { 1707 Error(ImmLoc, "immediate shift value out of range"); 1708 return -1; 1709 } 1710 } else if (Parser.getTok().is(AsmToken::Identifier)) { 1711 ShiftReg = tryParseRegister(); 1712 SMLoc L = Parser.getTok().getLoc(); 1713 if (ShiftReg == -1) { 1714 Error (L, "expected immediate or register in shift operand"); 1715 return -1; 1716 } 1717 } else { 1718 Error (Parser.getTok().getLoc(), 1719 "expected immediate or register in shift operand"); 1720 return -1; 1721 } 1722 } 1723 1724 if (ShiftReg && ShiftTy != ARM_AM::rrx) 1725 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, 1726 ShiftReg, Imm, 1727 S, Parser.getTok().getLoc())); 1728 else 1729 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, 1730 S, Parser.getTok().getLoc())); 1731 1732 return 0; 1733} 1734 1735 1736/// Try to parse a register name. The token must be an Identifier when called. 1737/// If it's a register, an AsmOperand is created. Another AsmOperand is created 1738/// if there is a "writeback". 'true' if it's not a register. 1739/// 1740/// TODO this is likely to change to allow different register types and or to 1741/// parse for a specific register type. 1742bool ARMAsmParser:: 1743tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1744 SMLoc S = Parser.getTok().getLoc(); 1745 int RegNo = tryParseRegister(); 1746 if (RegNo == -1) 1747 return true; 1748 1749 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc())); 1750 1751 const AsmToken &ExclaimTok = Parser.getTok(); 1752 if (ExclaimTok.is(AsmToken::Exclaim)) { 1753 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), 1754 ExclaimTok.getLoc())); 1755 Parser.Lex(); // Eat exclaim token 1756 } 1757 1758 return false; 1759} 1760 1761/// MatchCoprocessorOperandName - Try to parse an coprocessor related 1762/// instruction with a symbolic operand name. Example: "p1", "p7", "c3", 1763/// "c5", ... 1764static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { 1765 // Use the same layout as the tablegen'erated register name matcher. Ugly, 1766 // but efficient. 1767 switch (Name.size()) { 1768 default: break; 1769 case 2: 1770 if (Name[0] != CoprocOp) 1771 return -1; 1772 switch (Name[1]) { 1773 default: return -1; 1774 case '0': return 0; 1775 case '1': return 1; 1776 case '2': return 2; 1777 case '3': return 3; 1778 case '4': return 4; 1779 case '5': return 5; 1780 case '6': return 6; 1781 case '7': return 7; 1782 case '8': return 8; 1783 case '9': return 9; 1784 } 1785 break; 1786 case 3: 1787 if (Name[0] != CoprocOp || Name[1] != '1') 1788 return -1; 1789 switch (Name[2]) { 1790 default: return -1; 1791 case '0': return 10; 1792 case '1': return 11; 1793 case '2': return 12; 1794 case '3': return 13; 1795 case '4': return 14; 1796 case '5': return 15; 1797 } 1798 break; 1799 } 1800 1801 return -1; 1802} 1803 1804/// parseITCondCode - Try to parse a condition code for an IT instruction. 1805ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1806parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1807 SMLoc S = Parser.getTok().getLoc(); 1808 const AsmToken &Tok = Parser.getTok(); 1809 if (!Tok.is(AsmToken::Identifier)) 1810 return MatchOperand_NoMatch; 1811 unsigned CC = StringSwitch<unsigned>(Tok.getString()) 1812 .Case("eq", ARMCC::EQ) 1813 .Case("ne", ARMCC::NE) 1814 .Case("hs", ARMCC::HS) 1815 .Case("cs", ARMCC::HS) 1816 .Case("lo", ARMCC::LO) 1817 .Case("cc", ARMCC::LO) 1818 .Case("mi", ARMCC::MI) 1819 .Case("pl", ARMCC::PL) 1820 .Case("vs", ARMCC::VS) 1821 .Case("vc", ARMCC::VC) 1822 .Case("hi", ARMCC::HI) 1823 .Case("ls", ARMCC::LS) 1824 .Case("ge", ARMCC::GE) 1825 .Case("lt", ARMCC::LT) 1826 .Case("gt", ARMCC::GT) 1827 .Case("le", ARMCC::LE) 1828 .Case("al", ARMCC::AL) 1829 .Default(~0U); 1830 if (CC == ~0U) 1831 return MatchOperand_NoMatch; 1832 Parser.Lex(); // Eat the token. 1833 1834 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); 1835 1836 return MatchOperand_Success; 1837} 1838 1839/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The 1840/// token must be an Identifier when called, and if it is a coprocessor 1841/// number, the token is eaten and the operand is added to the operand list. 1842ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1843parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1844 SMLoc S = Parser.getTok().getLoc(); 1845 const AsmToken &Tok = Parser.getTok(); 1846 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1847 1848 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p'); 1849 if (Num == -1) 1850 return MatchOperand_NoMatch; 1851 1852 Parser.Lex(); // Eat identifier token. 1853 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); 1854 return MatchOperand_Success; 1855} 1856 1857/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The 1858/// token must be an Identifier when called, and if it is a coprocessor 1859/// number, the token is eaten and the operand is added to the operand list. 1860ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1861parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1862 SMLoc S = Parser.getTok().getLoc(); 1863 const AsmToken &Tok = Parser.getTok(); 1864 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1865 1866 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); 1867 if (Reg == -1) 1868 return MatchOperand_NoMatch; 1869 1870 Parser.Lex(); // Eat identifier token. 1871 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); 1872 return MatchOperand_Success; 1873} 1874 1875// For register list parsing, we need to map from raw GPR register numbering 1876// to the enumeration values. The enumeration values aren't sorted by 1877// register number due to our using "sp", "lr" and "pc" as canonical names. 1878static unsigned getNextRegister(unsigned Reg) { 1879 // If this is a GPR, we need to do it manually, otherwise we can rely 1880 // on the sort ordering of the enumeration since the other reg-classes 1881 // are sane. 1882 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 1883 return Reg + 1; 1884 switch(Reg) { 1885 default: assert(0 && "Invalid GPR number!"); 1886 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; 1887 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; 1888 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; 1889 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; 1890 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; 1891 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; 1892 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; 1893 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; 1894 } 1895} 1896 1897/// Parse a register list. 1898bool ARMAsmParser:: 1899parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1900 assert(Parser.getTok().is(AsmToken::LCurly) && 1901 "Token is not a Left Curly Brace"); 1902 SMLoc S = Parser.getTok().getLoc(); 1903 Parser.Lex(); // Eat '{' token. 1904 SMLoc RegLoc = Parser.getTok().getLoc(); 1905 1906 // Check the first register in the list to see what register class 1907 // this is a list of. 1908 int Reg = tryParseRegister(); 1909 if (Reg == -1) 1910 return Error(RegLoc, "register expected"); 1911 1912 MCRegisterClass *RC; 1913 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 1914 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; 1915 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) 1916 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; 1917 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) 1918 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; 1919 else 1920 return Error(RegLoc, "invalid register in register list"); 1921 1922 // The reglist instructions have at most 16 registers, so reserve 1923 // space for that many. 1924 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers; 1925 // Store the first register. 1926 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 1927 1928 // This starts immediately after the first register token in the list, 1929 // so we can see either a comma or a minus (range separator) as a legal 1930 // next token. 1931 while (Parser.getTok().is(AsmToken::Comma) || 1932 Parser.getTok().is(AsmToken::Minus)) { 1933 if (Parser.getTok().is(AsmToken::Minus)) { 1934 Parser.Lex(); // Eat the comma. 1935 SMLoc EndLoc = Parser.getTok().getLoc(); 1936 int EndReg = tryParseRegister(); 1937 if (EndReg == -1) 1938 return Error(EndLoc, "register expected"); 1939 // If the register is the same as the start reg, there's nothing 1940 // more to do. 1941 if (Reg == EndReg) 1942 continue; 1943 // The register must be in the same register class as the first. 1944 if (!RC->contains(EndReg)) 1945 return Error(EndLoc, "invalid register in register list"); 1946 // Ranges must go from low to high. 1947 if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg)) 1948 return Error(EndLoc, "bad range in register list"); 1949 1950 // Add all the registers in the range to the register list. 1951 while (Reg != EndReg) { 1952 Reg = getNextRegister(Reg); 1953 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 1954 } 1955 continue; 1956 } 1957 Parser.Lex(); // Eat the comma. 1958 RegLoc = Parser.getTok().getLoc(); 1959 int OldReg = Reg; 1960 Reg = tryParseRegister(); 1961 if (Reg == -1) 1962 return Error(RegLoc, "register expected"); 1963 // The register must be in the same register class as the first. 1964 if (!RC->contains(Reg)) 1965 return Error(RegLoc, "invalid register in register list"); 1966 // List must be monotonically increasing. 1967 if (getARMRegisterNumbering(Reg) <= getARMRegisterNumbering(OldReg)) 1968 return Error(RegLoc, "register list not in ascending order"); 1969 // VFP register lists must also be contiguous. 1970 // It's OK to use the enumeration values directly here rather, as the 1971 // VFP register classes have the enum sorted properly. 1972 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && 1973 Reg != OldReg + 1) 1974 return Error(RegLoc, "non-contiguous register range"); 1975 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 1976 } 1977 1978 SMLoc E = Parser.getTok().getLoc(); 1979 if (Parser.getTok().isNot(AsmToken::RCurly)) 1980 return Error(E, "'}' expected"); 1981 Parser.Lex(); // Eat '}' token. 1982 1983 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); 1984 return false; 1985} 1986 1987/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. 1988ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1989parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1990 SMLoc S = Parser.getTok().getLoc(); 1991 const AsmToken &Tok = Parser.getTok(); 1992 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1993 StringRef OptStr = Tok.getString(); 1994 1995 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size())) 1996 .Case("sy", ARM_MB::SY) 1997 .Case("st", ARM_MB::ST) 1998 .Case("sh", ARM_MB::ISH) 1999 .Case("ish", ARM_MB::ISH) 2000 .Case("shst", ARM_MB::ISHST) 2001 .Case("ishst", ARM_MB::ISHST) 2002 .Case("nsh", ARM_MB::NSH) 2003 .Case("un", ARM_MB::NSH) 2004 .Case("nshst", ARM_MB::NSHST) 2005 .Case("unst", ARM_MB::NSHST) 2006 .Case("osh", ARM_MB::OSH) 2007 .Case("oshst", ARM_MB::OSHST) 2008 .Default(~0U); 2009 2010 if (Opt == ~0U) 2011 return MatchOperand_NoMatch; 2012 2013 Parser.Lex(); // Eat identifier token. 2014 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); 2015 return MatchOperand_Success; 2016} 2017 2018/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. 2019ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2020parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2021 SMLoc S = Parser.getTok().getLoc(); 2022 const AsmToken &Tok = Parser.getTok(); 2023 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 2024 StringRef IFlagsStr = Tok.getString(); 2025 2026 unsigned IFlags = 0; 2027 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { 2028 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1)) 2029 .Case("a", ARM_PROC::A) 2030 .Case("i", ARM_PROC::I) 2031 .Case("f", ARM_PROC::F) 2032 .Default(~0U); 2033 2034 // If some specific iflag is already set, it means that some letter is 2035 // present more than once, this is not acceptable. 2036 if (Flag == ~0U || (IFlags & Flag)) 2037 return MatchOperand_NoMatch; 2038 2039 IFlags |= Flag; 2040 } 2041 2042 Parser.Lex(); // Eat identifier token. 2043 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); 2044 return MatchOperand_Success; 2045} 2046 2047/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. 2048ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2049parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2050 SMLoc S = Parser.getTok().getLoc(); 2051 const AsmToken &Tok = Parser.getTok(); 2052 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 2053 StringRef Mask = Tok.getString(); 2054 2055 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" 2056 size_t Start = 0, Next = Mask.find('_'); 2057 StringRef Flags = ""; 2058 std::string SpecReg = LowercaseString(Mask.slice(Start, Next)); 2059 if (Next != StringRef::npos) 2060 Flags = Mask.slice(Next+1, Mask.size()); 2061 2062 // FlagsVal contains the complete mask: 2063 // 3-0: Mask 2064 // 4: Special Reg (cpsr, apsr => 0; spsr => 1) 2065 unsigned FlagsVal = 0; 2066 2067 if (SpecReg == "apsr") { 2068 FlagsVal = StringSwitch<unsigned>(Flags) 2069 .Case("nzcvq", 0x8) // same as CPSR_f 2070 .Case("g", 0x4) // same as CPSR_s 2071 .Case("nzcvqg", 0xc) // same as CPSR_fs 2072 .Default(~0U); 2073 2074 if (FlagsVal == ~0U) { 2075 if (!Flags.empty()) 2076 return MatchOperand_NoMatch; 2077 else 2078 FlagsVal = 8; // No flag 2079 } 2080 } else if (SpecReg == "cpsr" || SpecReg == "spsr") { 2081 if (Flags == "all") // cpsr_all is an alias for cpsr_fc 2082 Flags = "fc"; 2083 for (int i = 0, e = Flags.size(); i != e; ++i) { 2084 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1)) 2085 .Case("c", 1) 2086 .Case("x", 2) 2087 .Case("s", 4) 2088 .Case("f", 8) 2089 .Default(~0U); 2090 2091 // If some specific flag is already set, it means that some letter is 2092 // present more than once, this is not acceptable. 2093 if (FlagsVal == ~0U || (FlagsVal & Flag)) 2094 return MatchOperand_NoMatch; 2095 FlagsVal |= Flag; 2096 } 2097 } else // No match for special register. 2098 return MatchOperand_NoMatch; 2099 2100 // Special register without flags are equivalent to "fc" flags. 2101 if (!FlagsVal) 2102 FlagsVal = 0x9; 2103 2104 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) 2105 if (SpecReg == "spsr") 2106 FlagsVal |= 16; 2107 2108 Parser.Lex(); // Eat identifier token. 2109 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 2110 return MatchOperand_Success; 2111} 2112 2113ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2114parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op, 2115 int Low, int High) { 2116 const AsmToken &Tok = Parser.getTok(); 2117 if (Tok.isNot(AsmToken::Identifier)) { 2118 Error(Parser.getTok().getLoc(), Op + " operand expected."); 2119 return MatchOperand_ParseFail; 2120 } 2121 StringRef ShiftName = Tok.getString(); 2122 std::string LowerOp = LowercaseString(Op); 2123 std::string UpperOp = UppercaseString(Op); 2124 if (ShiftName != LowerOp && ShiftName != UpperOp) { 2125 Error(Parser.getTok().getLoc(), Op + " operand expected."); 2126 return MatchOperand_ParseFail; 2127 } 2128 Parser.Lex(); // Eat shift type token. 2129 2130 // There must be a '#' and a shift amount. 2131 if (Parser.getTok().isNot(AsmToken::Hash)) { 2132 Error(Parser.getTok().getLoc(), "'#' expected"); 2133 return MatchOperand_ParseFail; 2134 } 2135 Parser.Lex(); // Eat hash token. 2136 2137 const MCExpr *ShiftAmount; 2138 SMLoc Loc = Parser.getTok().getLoc(); 2139 if (getParser().ParseExpression(ShiftAmount)) { 2140 Error(Loc, "illegal expression"); 2141 return MatchOperand_ParseFail; 2142 } 2143 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 2144 if (!CE) { 2145 Error(Loc, "constant expression expected"); 2146 return MatchOperand_ParseFail; 2147 } 2148 int Val = CE->getValue(); 2149 if (Val < Low || Val > High) { 2150 Error(Loc, "immediate value out of range"); 2151 return MatchOperand_ParseFail; 2152 } 2153 2154 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc())); 2155 2156 return MatchOperand_Success; 2157} 2158 2159ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2160parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2161 const AsmToken &Tok = Parser.getTok(); 2162 SMLoc S = Tok.getLoc(); 2163 if (Tok.isNot(AsmToken::Identifier)) { 2164 Error(Tok.getLoc(), "'be' or 'le' operand expected"); 2165 return MatchOperand_ParseFail; 2166 } 2167 int Val = StringSwitch<int>(Tok.getString()) 2168 .Case("be", 1) 2169 .Case("le", 0) 2170 .Default(-1); 2171 Parser.Lex(); // Eat the token. 2172 2173 if (Val == -1) { 2174 Error(Tok.getLoc(), "'be' or 'le' operand expected"); 2175 return MatchOperand_ParseFail; 2176 } 2177 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val, 2178 getContext()), 2179 S, Parser.getTok().getLoc())); 2180 return MatchOperand_Success; 2181} 2182 2183/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT 2184/// instructions. Legal values are: 2185/// lsl #n 'n' in [0,31] 2186/// asr #n 'n' in [1,32] 2187/// n == 32 encoded as n == 0. 2188ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2189parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2190 const AsmToken &Tok = Parser.getTok(); 2191 SMLoc S = Tok.getLoc(); 2192 if (Tok.isNot(AsmToken::Identifier)) { 2193 Error(S, "shift operator 'asr' or 'lsl' expected"); 2194 return MatchOperand_ParseFail; 2195 } 2196 StringRef ShiftName = Tok.getString(); 2197 bool isASR; 2198 if (ShiftName == "lsl" || ShiftName == "LSL") 2199 isASR = false; 2200 else if (ShiftName == "asr" || ShiftName == "ASR") 2201 isASR = true; 2202 else { 2203 Error(S, "shift operator 'asr' or 'lsl' expected"); 2204 return MatchOperand_ParseFail; 2205 } 2206 Parser.Lex(); // Eat the operator. 2207 2208 // A '#' and a shift amount. 2209 if (Parser.getTok().isNot(AsmToken::Hash)) { 2210 Error(Parser.getTok().getLoc(), "'#' expected"); 2211 return MatchOperand_ParseFail; 2212 } 2213 Parser.Lex(); // Eat hash token. 2214 2215 const MCExpr *ShiftAmount; 2216 SMLoc E = Parser.getTok().getLoc(); 2217 if (getParser().ParseExpression(ShiftAmount)) { 2218 Error(E, "malformed shift expression"); 2219 return MatchOperand_ParseFail; 2220 } 2221 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 2222 if (!CE) { 2223 Error(E, "shift amount must be an immediate"); 2224 return MatchOperand_ParseFail; 2225 } 2226 2227 int64_t Val = CE->getValue(); 2228 if (isASR) { 2229 // Shift amount must be in [1,32] 2230 if (Val < 1 || Val > 32) { 2231 Error(E, "'asr' shift amount must be in range [1,32]"); 2232 return MatchOperand_ParseFail; 2233 } 2234 // asr #32 encoded as asr #0. 2235 if (Val == 32) Val = 0; 2236 } else { 2237 // Shift amount must be in [1,32] 2238 if (Val < 0 || Val > 31) { 2239 Error(E, "'lsr' shift amount must be in range [0,31]"); 2240 return MatchOperand_ParseFail; 2241 } 2242 } 2243 2244 E = Parser.getTok().getLoc(); 2245 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E)); 2246 2247 return MatchOperand_Success; 2248} 2249 2250/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family 2251/// of instructions. Legal values are: 2252/// ror #n 'n' in {0, 8, 16, 24} 2253ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2254parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2255 const AsmToken &Tok = Parser.getTok(); 2256 SMLoc S = Tok.getLoc(); 2257 if (Tok.isNot(AsmToken::Identifier)) 2258 return MatchOperand_NoMatch; 2259 StringRef ShiftName = Tok.getString(); 2260 if (ShiftName != "ror" && ShiftName != "ROR") 2261 return MatchOperand_NoMatch; 2262 Parser.Lex(); // Eat the operator. 2263 2264 // A '#' and a rotate amount. 2265 if (Parser.getTok().isNot(AsmToken::Hash)) { 2266 Error(Parser.getTok().getLoc(), "'#' expected"); 2267 return MatchOperand_ParseFail; 2268 } 2269 Parser.Lex(); // Eat hash token. 2270 2271 const MCExpr *ShiftAmount; 2272 SMLoc E = Parser.getTok().getLoc(); 2273 if (getParser().ParseExpression(ShiftAmount)) { 2274 Error(E, "malformed rotate expression"); 2275 return MatchOperand_ParseFail; 2276 } 2277 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 2278 if (!CE) { 2279 Error(E, "rotate amount must be an immediate"); 2280 return MatchOperand_ParseFail; 2281 } 2282 2283 int64_t Val = CE->getValue(); 2284 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) 2285 // normally, zero is represented in asm by omitting the rotate operand 2286 // entirely. 2287 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { 2288 Error(E, "'ror' rotate amount must be 8, 16, or 24"); 2289 return MatchOperand_ParseFail; 2290 } 2291 2292 E = Parser.getTok().getLoc(); 2293 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E)); 2294 2295 return MatchOperand_Success; 2296} 2297 2298ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2299parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2300 SMLoc S = Parser.getTok().getLoc(); 2301 // The bitfield descriptor is really two operands, the LSB and the width. 2302 if (Parser.getTok().isNot(AsmToken::Hash)) { 2303 Error(Parser.getTok().getLoc(), "'#' expected"); 2304 return MatchOperand_ParseFail; 2305 } 2306 Parser.Lex(); // Eat hash token. 2307 2308 const MCExpr *LSBExpr; 2309 SMLoc E = Parser.getTok().getLoc(); 2310 if (getParser().ParseExpression(LSBExpr)) { 2311 Error(E, "malformed immediate expression"); 2312 return MatchOperand_ParseFail; 2313 } 2314 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr); 2315 if (!CE) { 2316 Error(E, "'lsb' operand must be an immediate"); 2317 return MatchOperand_ParseFail; 2318 } 2319 2320 int64_t LSB = CE->getValue(); 2321 // The LSB must be in the range [0,31] 2322 if (LSB < 0 || LSB > 31) { 2323 Error(E, "'lsb' operand must be in the range [0,31]"); 2324 return MatchOperand_ParseFail; 2325 } 2326 E = Parser.getTok().getLoc(); 2327 2328 // Expect another immediate operand. 2329 if (Parser.getTok().isNot(AsmToken::Comma)) { 2330 Error(Parser.getTok().getLoc(), "too few operands"); 2331 return MatchOperand_ParseFail; 2332 } 2333 Parser.Lex(); // Eat hash token. 2334 if (Parser.getTok().isNot(AsmToken::Hash)) { 2335 Error(Parser.getTok().getLoc(), "'#' expected"); 2336 return MatchOperand_ParseFail; 2337 } 2338 Parser.Lex(); // Eat hash token. 2339 2340 const MCExpr *WidthExpr; 2341 if (getParser().ParseExpression(WidthExpr)) { 2342 Error(E, "malformed immediate expression"); 2343 return MatchOperand_ParseFail; 2344 } 2345 CE = dyn_cast<MCConstantExpr>(WidthExpr); 2346 if (!CE) { 2347 Error(E, "'width' operand must be an immediate"); 2348 return MatchOperand_ParseFail; 2349 } 2350 2351 int64_t Width = CE->getValue(); 2352 // The LSB must be in the range [1,32-lsb] 2353 if (Width < 1 || Width > 32 - LSB) { 2354 Error(E, "'width' operand must be in the range [1,32-lsb]"); 2355 return MatchOperand_ParseFail; 2356 } 2357 E = Parser.getTok().getLoc(); 2358 2359 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E)); 2360 2361 return MatchOperand_Success; 2362} 2363 2364ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2365parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2366 // Check for a post-index addressing register operand. Specifically: 2367 // postidx_reg := '+' register {, shift} 2368 // | '-' register {, shift} 2369 // | register {, shift} 2370 2371 // This method must return MatchOperand_NoMatch without consuming any tokens 2372 // in the case where there is no match, as other alternatives take other 2373 // parse methods. 2374 AsmToken Tok = Parser.getTok(); 2375 SMLoc S = Tok.getLoc(); 2376 bool haveEaten = false; 2377 bool isAdd = true; 2378 int Reg = -1; 2379 if (Tok.is(AsmToken::Plus)) { 2380 Parser.Lex(); // Eat the '+' token. 2381 haveEaten = true; 2382 } else if (Tok.is(AsmToken::Minus)) { 2383 Parser.Lex(); // Eat the '-' token. 2384 isAdd = false; 2385 haveEaten = true; 2386 } 2387 if (Parser.getTok().is(AsmToken::Identifier)) 2388 Reg = tryParseRegister(); 2389 if (Reg == -1) { 2390 if (!haveEaten) 2391 return MatchOperand_NoMatch; 2392 Error(Parser.getTok().getLoc(), "register expected"); 2393 return MatchOperand_ParseFail; 2394 } 2395 SMLoc E = Parser.getTok().getLoc(); 2396 2397 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; 2398 unsigned ShiftImm = 0; 2399 if (Parser.getTok().is(AsmToken::Comma)) { 2400 Parser.Lex(); // Eat the ','. 2401 if (parseMemRegOffsetShift(ShiftTy, ShiftImm)) 2402 return MatchOperand_ParseFail; 2403 } 2404 2405 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, 2406 ShiftImm, S, E)); 2407 2408 return MatchOperand_Success; 2409} 2410 2411ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2412parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2413 // Check for a post-index addressing register operand. Specifically: 2414 // am3offset := '+' register 2415 // | '-' register 2416 // | register 2417 // | # imm 2418 // | # + imm 2419 // | # - imm 2420 2421 // This method must return MatchOperand_NoMatch without consuming any tokens 2422 // in the case where there is no match, as other alternatives take other 2423 // parse methods. 2424 AsmToken Tok = Parser.getTok(); 2425 SMLoc S = Tok.getLoc(); 2426 2427 // Do immediates first, as we always parse those if we have a '#'. 2428 if (Parser.getTok().is(AsmToken::Hash)) { 2429 Parser.Lex(); // Eat the '#'. 2430 // Explicitly look for a '-', as we need to encode negative zero 2431 // differently. 2432 bool isNegative = Parser.getTok().is(AsmToken::Minus); 2433 const MCExpr *Offset; 2434 if (getParser().ParseExpression(Offset)) 2435 return MatchOperand_ParseFail; 2436 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 2437 if (!CE) { 2438 Error(S, "constant expression expected"); 2439 return MatchOperand_ParseFail; 2440 } 2441 SMLoc E = Tok.getLoc(); 2442 // Negative zero is encoded as the flag value INT32_MIN. 2443 int32_t Val = CE->getValue(); 2444 if (isNegative && Val == 0) 2445 Val = INT32_MIN; 2446 2447 Operands.push_back( 2448 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E)); 2449 2450 return MatchOperand_Success; 2451 } 2452 2453 2454 bool haveEaten = false; 2455 bool isAdd = true; 2456 int Reg = -1; 2457 if (Tok.is(AsmToken::Plus)) { 2458 Parser.Lex(); // Eat the '+' token. 2459 haveEaten = true; 2460 } else if (Tok.is(AsmToken::Minus)) { 2461 Parser.Lex(); // Eat the '-' token. 2462 isAdd = false; 2463 haveEaten = true; 2464 } 2465 if (Parser.getTok().is(AsmToken::Identifier)) 2466 Reg = tryParseRegister(); 2467 if (Reg == -1) { 2468 if (!haveEaten) 2469 return MatchOperand_NoMatch; 2470 Error(Parser.getTok().getLoc(), "register expected"); 2471 return MatchOperand_ParseFail; 2472 } 2473 SMLoc E = Parser.getTok().getLoc(); 2474 2475 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, 2476 0, S, E)); 2477 2478 return MatchOperand_Success; 2479} 2480 2481/// cvtT2LdrdPre - Convert parsed operands to MCInst. 2482/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2483/// when they refer multiple MIOperands inside a single one. 2484bool ARMAsmParser:: 2485cvtT2LdrdPre(MCInst &Inst, unsigned Opcode, 2486 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2487 // Rt, Rt2 2488 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2489 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 2490 // Create a writeback register dummy placeholder. 2491 Inst.addOperand(MCOperand::CreateReg(0)); 2492 // addr 2493 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); 2494 // pred 2495 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2496 return true; 2497} 2498 2499/// cvtT2StrdPre - Convert parsed operands to MCInst. 2500/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2501/// when they refer multiple MIOperands inside a single one. 2502bool ARMAsmParser:: 2503cvtT2StrdPre(MCInst &Inst, unsigned Opcode, 2504 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2505 // Create a writeback register dummy placeholder. 2506 Inst.addOperand(MCOperand::CreateReg(0)); 2507 // Rt, Rt2 2508 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2509 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 2510 // addr 2511 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); 2512 // pred 2513 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2514 return true; 2515} 2516 2517/// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst. 2518/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2519/// when they refer multiple MIOperands inside a single one. 2520bool ARMAsmParser:: 2521cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 2522 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2523 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2524 2525 // Create a writeback register dummy placeholder. 2526 Inst.addOperand(MCOperand::CreateImm(0)); 2527 2528 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2); 2529 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2530 return true; 2531} 2532 2533/// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst. 2534/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2535/// when they refer multiple MIOperands inside a single one. 2536bool ARMAsmParser:: 2537cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 2538 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2539 // Create a writeback register dummy placeholder. 2540 Inst.addOperand(MCOperand::CreateImm(0)); 2541 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2542 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2); 2543 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2544 return true; 2545} 2546 2547/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 2548/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2549/// when they refer multiple MIOperands inside a single one. 2550bool ARMAsmParser:: 2551cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 2552 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2553 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2554 2555 // Create a writeback register dummy placeholder. 2556 Inst.addOperand(MCOperand::CreateImm(0)); 2557 2558 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 2559 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2560 return true; 2561} 2562 2563/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. 2564/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2565/// when they refer multiple MIOperands inside a single one. 2566bool ARMAsmParser:: 2567cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 2568 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2569 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2570 2571 // Create a writeback register dummy placeholder. 2572 Inst.addOperand(MCOperand::CreateImm(0)); 2573 2574 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); 2575 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2576 return true; 2577} 2578 2579 2580/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. 2581/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2582/// when they refer multiple MIOperands inside a single one. 2583bool ARMAsmParser:: 2584cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 2585 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2586 // Create a writeback register dummy placeholder. 2587 Inst.addOperand(MCOperand::CreateImm(0)); 2588 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2589 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); 2590 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2591 return true; 2592} 2593 2594/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 2595/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2596/// when they refer multiple MIOperands inside a single one. 2597bool ARMAsmParser:: 2598cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 2599 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2600 // Create a writeback register dummy placeholder. 2601 Inst.addOperand(MCOperand::CreateImm(0)); 2602 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2603 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 2604 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2605 return true; 2606} 2607 2608/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 2609/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2610/// when they refer multiple MIOperands inside a single one. 2611bool ARMAsmParser:: 2612cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 2613 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2614 // Create a writeback register dummy placeholder. 2615 Inst.addOperand(MCOperand::CreateImm(0)); 2616 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2617 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 2618 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2619 return true; 2620} 2621 2622/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst. 2623/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2624/// when they refer multiple MIOperands inside a single one. 2625bool ARMAsmParser:: 2626cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 2627 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2628 // Rt 2629 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2630 // Create a writeback register dummy placeholder. 2631 Inst.addOperand(MCOperand::CreateImm(0)); 2632 // addr 2633 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 2634 // offset 2635 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 2636 // pred 2637 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2638 return true; 2639} 2640 2641/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst. 2642/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2643/// when they refer multiple MIOperands inside a single one. 2644bool ARMAsmParser:: 2645cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 2646 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2647 // Rt 2648 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2649 // Create a writeback register dummy placeholder. 2650 Inst.addOperand(MCOperand::CreateImm(0)); 2651 // addr 2652 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 2653 // offset 2654 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 2655 // pred 2656 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2657 return true; 2658} 2659 2660/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst. 2661/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2662/// when they refer multiple MIOperands inside a single one. 2663bool ARMAsmParser:: 2664cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 2665 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2666 // Create a writeback register dummy placeholder. 2667 Inst.addOperand(MCOperand::CreateImm(0)); 2668 // Rt 2669 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2670 // addr 2671 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 2672 // offset 2673 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 2674 // pred 2675 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2676 return true; 2677} 2678 2679/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst. 2680/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2681/// when they refer multiple MIOperands inside a single one. 2682bool ARMAsmParser:: 2683cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 2684 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2685 // Create a writeback register dummy placeholder. 2686 Inst.addOperand(MCOperand::CreateImm(0)); 2687 // Rt 2688 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2689 // addr 2690 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 2691 // offset 2692 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 2693 // pred 2694 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2695 return true; 2696} 2697 2698/// cvtLdrdPre - Convert parsed operands to MCInst. 2699/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2700/// when they refer multiple MIOperands inside a single one. 2701bool ARMAsmParser:: 2702cvtLdrdPre(MCInst &Inst, unsigned Opcode, 2703 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2704 // Rt, Rt2 2705 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2706 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 2707 // Create a writeback register dummy placeholder. 2708 Inst.addOperand(MCOperand::CreateImm(0)); 2709 // addr 2710 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 2711 // pred 2712 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2713 return true; 2714} 2715 2716/// cvtStrdPre - Convert parsed operands to MCInst. 2717/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2718/// when they refer multiple MIOperands inside a single one. 2719bool ARMAsmParser:: 2720cvtStrdPre(MCInst &Inst, unsigned Opcode, 2721 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2722 // Create a writeback register dummy placeholder. 2723 Inst.addOperand(MCOperand::CreateImm(0)); 2724 // Rt, Rt2 2725 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2726 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 2727 // addr 2728 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 2729 // pred 2730 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2731 return true; 2732} 2733 2734/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 2735/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2736/// when they refer multiple MIOperands inside a single one. 2737bool ARMAsmParser:: 2738cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 2739 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2740 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 2741 // Create a writeback register dummy placeholder. 2742 Inst.addOperand(MCOperand::CreateImm(0)); 2743 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 2744 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 2745 return true; 2746} 2747 2748/// cvtThumbMultiple- Convert parsed operands to MCInst. 2749/// Needed here because the Asm Gen Matcher can't handle properly tied operands 2750/// when they refer multiple MIOperands inside a single one. 2751bool ARMAsmParser:: 2752cvtThumbMultiply(MCInst &Inst, unsigned Opcode, 2753 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2754 // The second source operand must be the same register as the destination 2755 // operand. 2756 if (Operands.size() == 6 && 2757 (((ARMOperand*)Operands[3])->getReg() != 2758 ((ARMOperand*)Operands[5])->getReg()) && 2759 (((ARMOperand*)Operands[3])->getReg() != 2760 ((ARMOperand*)Operands[4])->getReg())) { 2761 Error(Operands[3]->getStartLoc(), 2762 "destination register must match source register"); 2763 return false; 2764 } 2765 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 2766 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1); 2767 ((ARMOperand*)Operands[4])->addRegOperands(Inst, 1); 2768 // If we have a three-operand form, use that, else the second source operand 2769 // is just the destination operand again. 2770 if (Operands.size() == 6) 2771 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); 2772 else 2773 Inst.addOperand(Inst.getOperand(0)); 2774 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2); 2775 2776 return true; 2777} 2778 2779/// Parse an ARM memory expression, return false if successful else return true 2780/// or an error. The first token must be a '[' when called. 2781bool ARMAsmParser:: 2782parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2783 SMLoc S, E; 2784 assert(Parser.getTok().is(AsmToken::LBrac) && 2785 "Token is not a Left Bracket"); 2786 S = Parser.getTok().getLoc(); 2787 Parser.Lex(); // Eat left bracket token. 2788 2789 const AsmToken &BaseRegTok = Parser.getTok(); 2790 int BaseRegNum = tryParseRegister(); 2791 if (BaseRegNum == -1) 2792 return Error(BaseRegTok.getLoc(), "register expected"); 2793 2794 // The next token must either be a comma or a closing bracket. 2795 const AsmToken &Tok = Parser.getTok(); 2796 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac)) 2797 return Error(Tok.getLoc(), "malformed memory operand"); 2798 2799 if (Tok.is(AsmToken::RBrac)) { 2800 E = Tok.getLoc(); 2801 Parser.Lex(); // Eat right bracket token. 2802 2803 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift, 2804 0, false, S, E)); 2805 2806 // If there's a pre-indexing writeback marker, '!', just add it as a token 2807 // operand. It's rather odd, but syntactically valid. 2808 if (Parser.getTok().is(AsmToken::Exclaim)) { 2809 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 2810 Parser.Lex(); // Eat the '!'. 2811 } 2812 2813 return false; 2814 } 2815 2816 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!"); 2817 Parser.Lex(); // Eat the comma. 2818 2819 // If we have a '#' it's an immediate offset, else assume it's a register 2820 // offset. 2821 if (Parser.getTok().is(AsmToken::Hash)) { 2822 Parser.Lex(); // Eat the '#'. 2823 E = Parser.getTok().getLoc(); 2824 2825 bool isNegative = getParser().getTok().is(AsmToken::Minus); 2826 const MCExpr *Offset; 2827 if (getParser().ParseExpression(Offset)) 2828 return true; 2829 2830 // The expression has to be a constant. Memory references with relocations 2831 // don't come through here, as they use the <label> forms of the relevant 2832 // instructions. 2833 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 2834 if (!CE) 2835 return Error (E, "constant expression expected"); 2836 2837 // If the constant was #-0, represent it as INT32_MIN. 2838 int32_t Val = CE->getValue(); 2839 if (isNegative && Val == 0) 2840 CE = MCConstantExpr::Create(INT32_MIN, getContext()); 2841 2842 // Now we should have the closing ']' 2843 E = Parser.getTok().getLoc(); 2844 if (Parser.getTok().isNot(AsmToken::RBrac)) 2845 return Error(E, "']' expected"); 2846 Parser.Lex(); // Eat right bracket token. 2847 2848 // Don't worry about range checking the value here. That's handled by 2849 // the is*() predicates. 2850 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0, 2851 ARM_AM::no_shift, 0, false, S,E)); 2852 2853 // If there's a pre-indexing writeback marker, '!', just add it as a token 2854 // operand. 2855 if (Parser.getTok().is(AsmToken::Exclaim)) { 2856 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 2857 Parser.Lex(); // Eat the '!'. 2858 } 2859 2860 return false; 2861 } 2862 2863 // The register offset is optionally preceded by a '+' or '-' 2864 bool isNegative = false; 2865 if (Parser.getTok().is(AsmToken::Minus)) { 2866 isNegative = true; 2867 Parser.Lex(); // Eat the '-'. 2868 } else if (Parser.getTok().is(AsmToken::Plus)) { 2869 // Nothing to do. 2870 Parser.Lex(); // Eat the '+'. 2871 } 2872 2873 E = Parser.getTok().getLoc(); 2874 int OffsetRegNum = tryParseRegister(); 2875 if (OffsetRegNum == -1) 2876 return Error(E, "register expected"); 2877 2878 // If there's a shift operator, handle it. 2879 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift; 2880 unsigned ShiftImm = 0; 2881 if (Parser.getTok().is(AsmToken::Comma)) { 2882 Parser.Lex(); // Eat the ','. 2883 if (parseMemRegOffsetShift(ShiftType, ShiftImm)) 2884 return true; 2885 } 2886 2887 // Now we should have the closing ']' 2888 E = Parser.getTok().getLoc(); 2889 if (Parser.getTok().isNot(AsmToken::RBrac)) 2890 return Error(E, "']' expected"); 2891 Parser.Lex(); // Eat right bracket token. 2892 2893 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum, 2894 ShiftType, ShiftImm, isNegative, 2895 S, E)); 2896 2897 // If there's a pre-indexing writeback marker, '!', just add it as a token 2898 // operand. 2899 if (Parser.getTok().is(AsmToken::Exclaim)) { 2900 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 2901 Parser.Lex(); // Eat the '!'. 2902 } 2903 2904 return false; 2905} 2906 2907/// parseMemRegOffsetShift - one of these two: 2908/// ( lsl | lsr | asr | ror ) , # shift_amount 2909/// rrx 2910/// return true if it parses a shift otherwise it returns false. 2911bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St, 2912 unsigned &Amount) { 2913 SMLoc Loc = Parser.getTok().getLoc(); 2914 const AsmToken &Tok = Parser.getTok(); 2915 if (Tok.isNot(AsmToken::Identifier)) 2916 return true; 2917 StringRef ShiftName = Tok.getString(); 2918 if (ShiftName == "lsl" || ShiftName == "LSL") 2919 St = ARM_AM::lsl; 2920 else if (ShiftName == "lsr" || ShiftName == "LSR") 2921 St = ARM_AM::lsr; 2922 else if (ShiftName == "asr" || ShiftName == "ASR") 2923 St = ARM_AM::asr; 2924 else if (ShiftName == "ror" || ShiftName == "ROR") 2925 St = ARM_AM::ror; 2926 else if (ShiftName == "rrx" || ShiftName == "RRX") 2927 St = ARM_AM::rrx; 2928 else 2929 return Error(Loc, "illegal shift operator"); 2930 Parser.Lex(); // Eat shift type token. 2931 2932 // rrx stands alone. 2933 Amount = 0; 2934 if (St != ARM_AM::rrx) { 2935 Loc = Parser.getTok().getLoc(); 2936 // A '#' and a shift amount. 2937 const AsmToken &HashTok = Parser.getTok(); 2938 if (HashTok.isNot(AsmToken::Hash)) 2939 return Error(HashTok.getLoc(), "'#' expected"); 2940 Parser.Lex(); // Eat hash token. 2941 2942 const MCExpr *Expr; 2943 if (getParser().ParseExpression(Expr)) 2944 return true; 2945 // Range check the immediate. 2946 // lsl, ror: 0 <= imm <= 31 2947 // lsr, asr: 0 <= imm <= 32 2948 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 2949 if (!CE) 2950 return Error(Loc, "shift amount must be an immediate"); 2951 int64_t Imm = CE->getValue(); 2952 if (Imm < 0 || 2953 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) || 2954 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32)) 2955 return Error(Loc, "immediate shift value out of range"); 2956 Amount = Imm; 2957 } 2958 2959 return false; 2960} 2961 2962/// Parse a arm instruction operand. For now this parses the operand regardless 2963/// of the mnemonic. 2964bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 2965 StringRef Mnemonic) { 2966 SMLoc S, E; 2967 2968 // Check if the current operand has a custom associated parser, if so, try to 2969 // custom parse the operand, or fallback to the general approach. 2970 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 2971 if (ResTy == MatchOperand_Success) 2972 return false; 2973 // If there wasn't a custom match, try the generic matcher below. Otherwise, 2974 // there was a match, but an error occurred, in which case, just return that 2975 // the operand parsing failed. 2976 if (ResTy == MatchOperand_ParseFail) 2977 return true; 2978 2979 switch (getLexer().getKind()) { 2980 default: 2981 Error(Parser.getTok().getLoc(), "unexpected token in operand"); 2982 return true; 2983 case AsmToken::Identifier: { 2984 if (!tryParseRegisterWithWriteBack(Operands)) 2985 return false; 2986 int Res = tryParseShiftRegister(Operands); 2987 if (Res == 0) // success 2988 return false; 2989 else if (Res == -1) // irrecoverable error 2990 return true; 2991 2992 // Fall though for the Identifier case that is not a register or a 2993 // special name. 2994 } 2995 case AsmToken::Integer: // things like 1f and 2b as a branch targets 2996 case AsmToken::Dot: { // . as a branch target 2997 // This was not a register so parse other operands that start with an 2998 // identifier (like labels) as expressions and create them as immediates. 2999 const MCExpr *IdVal; 3000 S = Parser.getTok().getLoc(); 3001 if (getParser().ParseExpression(IdVal)) 3002 return true; 3003 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 3004 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); 3005 return false; 3006 } 3007 case AsmToken::LBrac: 3008 return parseMemory(Operands); 3009 case AsmToken::LCurly: 3010 return parseRegisterList(Operands); 3011 case AsmToken::Hash: { 3012 // #42 -> immediate. 3013 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate 3014 S = Parser.getTok().getLoc(); 3015 Parser.Lex(); 3016 bool isNegative = Parser.getTok().is(AsmToken::Minus); 3017 const MCExpr *ImmVal; 3018 if (getParser().ParseExpression(ImmVal)) 3019 return true; 3020 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal); 3021 if (!CE) { 3022 Error(S, "constant expression expected"); 3023 return MatchOperand_ParseFail; 3024 } 3025 int32_t Val = CE->getValue(); 3026 if (isNegative && Val == 0) 3027 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext()); 3028 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 3029 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); 3030 return false; 3031 } 3032 case AsmToken::Colon: { 3033 // ":lower16:" and ":upper16:" expression prefixes 3034 // FIXME: Check it's an expression prefix, 3035 // e.g. (FOO - :lower16:BAR) isn't legal. 3036 ARMMCExpr::VariantKind RefKind; 3037 if (parsePrefix(RefKind)) 3038 return true; 3039 3040 const MCExpr *SubExprVal; 3041 if (getParser().ParseExpression(SubExprVal)) 3042 return true; 3043 3044 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal, 3045 getContext()); 3046 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 3047 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); 3048 return false; 3049 } 3050 } 3051} 3052 3053// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. 3054// :lower16: and :upper16:. 3055bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) { 3056 RefKind = ARMMCExpr::VK_ARM_None; 3057 3058 // :lower16: and :upper16: modifiers 3059 assert(getLexer().is(AsmToken::Colon) && "expected a :"); 3060 Parser.Lex(); // Eat ':' 3061 3062 if (getLexer().isNot(AsmToken::Identifier)) { 3063 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); 3064 return true; 3065 } 3066 3067 StringRef IDVal = Parser.getTok().getIdentifier(); 3068 if (IDVal == "lower16") { 3069 RefKind = ARMMCExpr::VK_ARM_LO16; 3070 } else if (IDVal == "upper16") { 3071 RefKind = ARMMCExpr::VK_ARM_HI16; 3072 } else { 3073 Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); 3074 return true; 3075 } 3076 Parser.Lex(); 3077 3078 if (getLexer().isNot(AsmToken::Colon)) { 3079 Error(Parser.getTok().getLoc(), "unexpected token after prefix"); 3080 return true; 3081 } 3082 Parser.Lex(); // Eat the last ':' 3083 return false; 3084} 3085 3086/// \brief Given a mnemonic, split out possible predication code and carry 3087/// setting letters to form a canonical mnemonic and flags. 3088// 3089// FIXME: Would be nice to autogen this. 3090// FIXME: This is a bit of a maze of special cases. 3091StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, 3092 unsigned &PredicationCode, 3093 bool &CarrySetting, 3094 unsigned &ProcessorIMod, 3095 StringRef &ITMask) { 3096 PredicationCode = ARMCC::AL; 3097 CarrySetting = false; 3098 ProcessorIMod = 0; 3099 3100 // Ignore some mnemonics we know aren't predicated forms. 3101 // 3102 // FIXME: Would be nice to autogen this. 3103 if ((Mnemonic == "movs" && isThumb()) || 3104 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" || 3105 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || 3106 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" || 3107 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" || 3108 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" || 3109 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || 3110 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal") 3111 return Mnemonic; 3112 3113 // First, split out any predication code. Ignore mnemonics we know aren't 3114 // predicated but do have a carry-set and so weren't caught above. 3115 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && 3116 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" && 3117 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" && 3118 Mnemonic != "sbcs" && Mnemonic != "rscs") { 3119 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2)) 3120 .Case("eq", ARMCC::EQ) 3121 .Case("ne", ARMCC::NE) 3122 .Case("hs", ARMCC::HS) 3123 .Case("cs", ARMCC::HS) 3124 .Case("lo", ARMCC::LO) 3125 .Case("cc", ARMCC::LO) 3126 .Case("mi", ARMCC::MI) 3127 .Case("pl", ARMCC::PL) 3128 .Case("vs", ARMCC::VS) 3129 .Case("vc", ARMCC::VC) 3130 .Case("hi", ARMCC::HI) 3131 .Case("ls", ARMCC::LS) 3132 .Case("ge", ARMCC::GE) 3133 .Case("lt", ARMCC::LT) 3134 .Case("gt", ARMCC::GT) 3135 .Case("le", ARMCC::LE) 3136 .Case("al", ARMCC::AL) 3137 .Default(~0U); 3138 if (CC != ~0U) { 3139 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); 3140 PredicationCode = CC; 3141 } 3142 } 3143 3144 // Next, determine if we have a carry setting bit. We explicitly ignore all 3145 // the instructions we know end in 's'. 3146 if (Mnemonic.endswith("s") && 3147 !(Mnemonic == "cps" || Mnemonic == "mls" || 3148 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" || 3149 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" || 3150 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" || 3151 Mnemonic == "vrsqrts" || Mnemonic == "srs" || 3152 (Mnemonic == "movs" && isThumb()))) { 3153 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); 3154 CarrySetting = true; 3155 } 3156 3157 // The "cps" instruction can have a interrupt mode operand which is glued into 3158 // the mnemonic. Check if this is the case, split it and parse the imod op 3159 if (Mnemonic.startswith("cps")) { 3160 // Split out any imod code. 3161 unsigned IMod = 3162 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2)) 3163 .Case("ie", ARM_PROC::IE) 3164 .Case("id", ARM_PROC::ID) 3165 .Default(~0U); 3166 if (IMod != ~0U) { 3167 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2); 3168 ProcessorIMod = IMod; 3169 } 3170 } 3171 3172 // The "it" instruction has the condition mask on the end of the mnemonic. 3173 if (Mnemonic.startswith("it")) { 3174 ITMask = Mnemonic.slice(2, Mnemonic.size()); 3175 Mnemonic = Mnemonic.slice(0, 2); 3176 } 3177 3178 return Mnemonic; 3179} 3180 3181/// \brief Given a canonical mnemonic, determine if the instruction ever allows 3182/// inclusion of carry set or predication code operands. 3183// 3184// FIXME: It would be nice to autogen this. 3185void ARMAsmParser:: 3186getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 3187 bool &CanAcceptPredicationCode) { 3188 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || 3189 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || 3190 Mnemonic == "add" || Mnemonic == "adc" || 3191 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" || 3192 Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" || 3193 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || 3194 Mnemonic == "sbc" || Mnemonic == "umull" || Mnemonic == "eor" || 3195 Mnemonic == "neg" || 3196 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" || 3197 Mnemonic == "mla" || Mnemonic == "smlal"))) { 3198 CanAcceptCarrySet = true; 3199 } else 3200 CanAcceptCarrySet = false; 3201 3202 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" || 3203 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" || 3204 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" || 3205 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" || 3206 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" || 3207 (Mnemonic == "clrex" && !isThumb()) || 3208 (Mnemonic == "nop" && isThumbOne()) || 3209 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw") && 3210 !isThumb()) || 3211 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) && 3212 !isThumb()) || 3213 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) { 3214 CanAcceptPredicationCode = false; 3215 } else 3216 CanAcceptPredicationCode = true; 3217 3218 if (isThumb()) { 3219 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" || 3220 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp") 3221 CanAcceptPredicationCode = false; 3222 } 3223} 3224 3225bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic, 3226 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3227 // FIXME: This is all horribly hacky. We really need a better way to deal 3228 // with optional operands like this in the matcher table. 3229 3230 // The 'mov' mnemonic is special. One variant has a cc_out operand, while 3231 // another does not. Specifically, the MOVW instruction does not. So we 3232 // special case it here and remove the defaulted (non-setting) cc_out 3233 // operand if that's the instruction we're trying to match. 3234 // 3235 // We do this as post-processing of the explicit operands rather than just 3236 // conditionally adding the cc_out in the first place because we need 3237 // to check the type of the parsed immediate operand. 3238 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() && 3239 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() && 3240 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() && 3241 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 3242 return true; 3243 3244 // Register-register 'add' for thumb does not have a cc_out operand 3245 // when there are only two register operands. 3246 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && 3247 static_cast<ARMOperand*>(Operands[3])->isReg() && 3248 static_cast<ARMOperand*>(Operands[4])->isReg() && 3249 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 3250 return true; 3251 // Register-register 'add' for thumb does not have a cc_out operand 3252 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do 3253 // have to check the immediate range here since Thumb2 has a variant 3254 // that can handle a different range and has a cc_out operand. 3255 if (((isThumb() && Mnemonic == "add") || 3256 (isThumbTwo() && Mnemonic == "sub")) && 3257 Operands.size() == 6 && 3258 static_cast<ARMOperand*>(Operands[3])->isReg() && 3259 static_cast<ARMOperand*>(Operands[4])->isReg() && 3260 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP && 3261 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 3262 (static_cast<ARMOperand*>(Operands[5])->isReg() || 3263 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4())) 3264 return true; 3265 // For Thumb2, add/sub immediate does not have a cc_out operand for the 3266 // imm0_4095 variant. That's the least-preferred variant when 3267 // selecting via the generic "add" mnemonic, so to know that we 3268 // should remove the cc_out operand, we have to explicitly check that 3269 // it's not one of the other variants. Ugh. 3270 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") && 3271 Operands.size() == 6 && 3272 static_cast<ARMOperand*>(Operands[3])->isReg() && 3273 static_cast<ARMOperand*>(Operands[4])->isReg() && 3274 static_cast<ARMOperand*>(Operands[5])->isImm()) { 3275 // Nest conditions rather than one big 'if' statement for readability. 3276 // 3277 // If either register is a high reg, it's either one of the SP 3278 // variants (handled above) or a 32-bit encoding, so we just 3279 // check against T3. 3280 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 3281 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) && 3282 static_cast<ARMOperand*>(Operands[5])->isT2SOImm()) 3283 return false; 3284 // If both registers are low, we're in an IT block, and the immediate is 3285 // in range, we should use encoding T1 instead, which has a cc_out. 3286 if (inITBlock() && 3287 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) && 3288 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) && 3289 static_cast<ARMOperand*>(Operands[5])->isImm0_7()) 3290 return false; 3291 3292 // Otherwise, we use encoding T4, which does not have a cc_out 3293 // operand. 3294 return true; 3295 } 3296 3297 // The thumb2 multiply instruction doesn't have a CCOut register, so 3298 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to 3299 // use the 16-bit encoding or not. 3300 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 && 3301 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 3302 static_cast<ARMOperand*>(Operands[3])->isReg() && 3303 static_cast<ARMOperand*>(Operands[4])->isReg() && 3304 static_cast<ARMOperand*>(Operands[5])->isReg() && 3305 // If the registers aren't low regs, the destination reg isn't the 3306 // same as one of the source regs, or the cc_out operand is zero 3307 // outside of an IT block, we have to use the 32-bit encoding, so 3308 // remove the cc_out operand. 3309 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 3310 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 3311 !inITBlock() || 3312 (static_cast<ARMOperand*>(Operands[3])->getReg() != 3313 static_cast<ARMOperand*>(Operands[5])->getReg() && 3314 static_cast<ARMOperand*>(Operands[3])->getReg() != 3315 static_cast<ARMOperand*>(Operands[4])->getReg()))) 3316 return true; 3317 3318 3319 3320 // Register-register 'add/sub' for thumb does not have a cc_out operand 3321 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also 3322 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't 3323 // right, this will result in better diagnostics (which operand is off) 3324 // anyway. 3325 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") && 3326 (Operands.size() == 5 || Operands.size() == 6) && 3327 static_cast<ARMOperand*>(Operands[3])->isReg() && 3328 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP && 3329 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 3330 return true; 3331 3332 return false; 3333} 3334 3335/// Parse an arm instruction mnemonic followed by its operands. 3336bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc, 3337 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3338 // Create the leading tokens for the mnemonic, split by '.' characters. 3339 size_t Start = 0, Next = Name.find('.'); 3340 StringRef Mnemonic = Name.slice(Start, Next); 3341 3342 // Split out the predication code and carry setting flag from the mnemonic. 3343 unsigned PredicationCode; 3344 unsigned ProcessorIMod; 3345 bool CarrySetting; 3346 StringRef ITMask; 3347 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting, 3348 ProcessorIMod, ITMask); 3349 3350 // In Thumb1, only the branch (B) instruction can be predicated. 3351 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") { 3352 Parser.EatToEndOfStatement(); 3353 return Error(NameLoc, "conditional execution not supported in Thumb1"); 3354 } 3355 3356 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); 3357 3358 // Handle the IT instruction ITMask. Convert it to a bitmask. This 3359 // is the mask as it will be for the IT encoding if the conditional 3360 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case 3361 // where the conditional bit0 is zero, the instruction post-processing 3362 // will adjust the mask accordingly. 3363 if (Mnemonic == "it") { 3364 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2); 3365 if (ITMask.size() > 3) { 3366 Parser.EatToEndOfStatement(); 3367 return Error(Loc, "too many conditions on IT instruction"); 3368 } 3369 unsigned Mask = 8; 3370 for (unsigned i = ITMask.size(); i != 0; --i) { 3371 char pos = ITMask[i - 1]; 3372 if (pos != 't' && pos != 'e') { 3373 Parser.EatToEndOfStatement(); 3374 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'"); 3375 } 3376 Mask >>= 1; 3377 if (ITMask[i - 1] == 't') 3378 Mask |= 8; 3379 } 3380 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); 3381 } 3382 3383 // FIXME: This is all a pretty gross hack. We should automatically handle 3384 // optional operands like this via tblgen. 3385 3386 // Next, add the CCOut and ConditionCode operands, if needed. 3387 // 3388 // For mnemonics which can ever incorporate a carry setting bit or predication 3389 // code, our matching model involves us always generating CCOut and 3390 // ConditionCode operands to match the mnemonic "as written" and then we let 3391 // the matcher deal with finding the right instruction or generating an 3392 // appropriate error. 3393 bool CanAcceptCarrySet, CanAcceptPredicationCode; 3394 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode); 3395 3396 // If we had a carry-set on an instruction that can't do that, issue an 3397 // error. 3398 if (!CanAcceptCarrySet && CarrySetting) { 3399 Parser.EatToEndOfStatement(); 3400 return Error(NameLoc, "instruction '" + Mnemonic + 3401 "' can not set flags, but 's' suffix specified"); 3402 } 3403 // If we had a predication code on an instruction that can't do that, issue an 3404 // error. 3405 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) { 3406 Parser.EatToEndOfStatement(); 3407 return Error(NameLoc, "instruction '" + Mnemonic + 3408 "' is not predicable, but condition code specified"); 3409 } 3410 3411 // Add the carry setting operand, if necessary. 3412 if (CanAcceptCarrySet) { 3413 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size()); 3414 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, 3415 Loc)); 3416 } 3417 3418 // Add the predication code operand, if necessary. 3419 if (CanAcceptPredicationCode) { 3420 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() + 3421 CarrySetting); 3422 Operands.push_back(ARMOperand::CreateCondCode( 3423 ARMCC::CondCodes(PredicationCode), Loc)); 3424 } 3425 3426 // Add the processor imod operand, if necessary. 3427 if (ProcessorIMod) { 3428 Operands.push_back(ARMOperand::CreateImm( 3429 MCConstantExpr::Create(ProcessorIMod, getContext()), 3430 NameLoc, NameLoc)); 3431 } 3432 3433 // Add the remaining tokens in the mnemonic. 3434 while (Next != StringRef::npos) { 3435 Start = Next; 3436 Next = Name.find('.', Start + 1); 3437 StringRef ExtraToken = Name.slice(Start, Next); 3438 3439 // For now, we're only parsing Thumb1 (for the most part), so 3440 // just ignore ".n" qualifiers. We'll use them to restrict 3441 // matching when we do Thumb2. 3442 if (ExtraToken != ".n") { 3443 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 3444 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc)); 3445 } 3446 } 3447 3448 // Read the remaining operands. 3449 if (getLexer().isNot(AsmToken::EndOfStatement)) { 3450 // Read the first operand. 3451 if (parseOperand(Operands, Mnemonic)) { 3452 Parser.EatToEndOfStatement(); 3453 return true; 3454 } 3455 3456 while (getLexer().is(AsmToken::Comma)) { 3457 Parser.Lex(); // Eat the comma. 3458 3459 // Parse and remember the operand. 3460 if (parseOperand(Operands, Mnemonic)) { 3461 Parser.EatToEndOfStatement(); 3462 return true; 3463 } 3464 } 3465 } 3466 3467 if (getLexer().isNot(AsmToken::EndOfStatement)) { 3468 Parser.EatToEndOfStatement(); 3469 return TokError("unexpected token in argument list"); 3470 } 3471 3472 Parser.Lex(); // Consume the EndOfStatement 3473 3474 // Some instructions, mostly Thumb, have forms for the same mnemonic that 3475 // do and don't have a cc_out optional-def operand. With some spot-checks 3476 // of the operand list, we can figure out which variant we're trying to 3477 // parse and adjust accordingly before actually matching. We shouldn't ever 3478 // try to remove a cc_out operand that was explicitly set on the the 3479 // mnemonic, of course (CarrySetting == true). Reason number #317 the 3480 // table driven matcher doesn't fit well with the ARM instruction set. 3481 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) { 3482 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 3483 Operands.erase(Operands.begin() + 1); 3484 delete Op; 3485 } 3486 3487 // ARM mode 'blx' need special handling, as the register operand version 3488 // is predicable, but the label operand version is not. So, we can't rely 3489 // on the Mnemonic based checking to correctly figure out when to put 3490 // a CondCode operand in the list. If we're trying to match the label 3491 // version, remove the CondCode operand here. 3492 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && 3493 static_cast<ARMOperand*>(Operands[2])->isImm()) { 3494 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 3495 Operands.erase(Operands.begin() + 1); 3496 delete Op; 3497 } 3498 3499 // The vector-compare-to-zero instructions have a literal token "#0" at 3500 // the end that comes to here as an immediate operand. Convert it to a 3501 // token to play nicely with the matcher. 3502 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" || 3503 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 && 3504 static_cast<ARMOperand*>(Operands[5])->isImm()) { 3505 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]); 3506 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 3507 if (CE && CE->getValue() == 0) { 3508 Operands.erase(Operands.begin() + 5); 3509 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 3510 delete Op; 3511 } 3512 } 3513 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the 3514 // end. Convert it to a token here. 3515 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 && 3516 static_cast<ARMOperand*>(Operands[5])->isImm()) { 3517 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]); 3518 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 3519 if (CE && CE->getValue() == 0) { 3520 Operands.erase(Operands.begin() + 5); 3521 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 3522 delete Op; 3523 } 3524 } 3525 3526 return false; 3527} 3528 3529// Validate context-sensitive operand constraints. 3530 3531// return 'true' if register list contains non-low GPR registers, 3532// 'false' otherwise. If Reg is in the register list or is HiReg, set 3533// 'containsReg' to true. 3534static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, 3535 unsigned HiReg, bool &containsReg) { 3536 containsReg = false; 3537 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 3538 unsigned OpReg = Inst.getOperand(i).getReg(); 3539 if (OpReg == Reg) 3540 containsReg = true; 3541 // Anything other than a low register isn't legal here. 3542 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) 3543 return true; 3544 } 3545 return false; 3546} 3547 3548// Check if the specified regisgter is in the register list of the inst, 3549// starting at the indicated operand number. 3550static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) { 3551 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 3552 unsigned OpReg = Inst.getOperand(i).getReg(); 3553 if (OpReg == Reg) 3554 return true; 3555 } 3556 return false; 3557} 3558 3559// FIXME: We would really prefer to have MCInstrInfo (the wrapper around 3560// the ARMInsts array) instead. Getting that here requires awkward 3561// API changes, though. Better way? 3562namespace llvm { 3563extern MCInstrDesc ARMInsts[]; 3564} 3565static MCInstrDesc &getInstDesc(unsigned Opcode) { 3566 return ARMInsts[Opcode]; 3567} 3568 3569// FIXME: We would really like to be able to tablegen'erate this. 3570bool ARMAsmParser:: 3571validateInstruction(MCInst &Inst, 3572 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3573 MCInstrDesc &MCID = getInstDesc(Inst.getOpcode()); 3574 SMLoc Loc = Operands[0]->getStartLoc(); 3575 // Check the IT block state first. 3576 // NOTE: In Thumb mode, the BKPT instruction has the interesting property of 3577 // being allowed in IT blocks, but not being predicable. It just always 3578 // executes. 3579 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT) { 3580 unsigned bit = 1; 3581 if (ITState.FirstCond) 3582 ITState.FirstCond = false; 3583 else 3584 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1; 3585 // The instruction must be predicable. 3586 if (!MCID.isPredicable()) 3587 return Error(Loc, "instructions in IT block must be predicable"); 3588 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm(); 3589 unsigned ITCond = bit ? ITState.Cond : 3590 ARMCC::getOppositeCondition(ITState.Cond); 3591 if (Cond != ITCond) { 3592 // Find the condition code Operand to get its SMLoc information. 3593 SMLoc CondLoc; 3594 for (unsigned i = 1; i < Operands.size(); ++i) 3595 if (static_cast<ARMOperand*>(Operands[i])->isCondCode()) 3596 CondLoc = Operands[i]->getStartLoc(); 3597 return Error(CondLoc, "incorrect condition in IT block; got '" + 3598 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) + 3599 "', but expected '" + 3600 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'"); 3601 } 3602 // Check for non-'al' condition codes outside of the IT block. 3603 } else if (isThumbTwo() && MCID.isPredicable() && 3604 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != 3605 ARMCC::AL && Inst.getOpcode() != ARM::tB && 3606 Inst.getOpcode() != ARM::t2B) 3607 return Error(Loc, "predicated instructions must be in IT block"); 3608 3609 switch (Inst.getOpcode()) { 3610 case ARM::LDRD: 3611 case ARM::LDRD_PRE: 3612 case ARM::LDRD_POST: 3613 case ARM::LDREXD: { 3614 // Rt2 must be Rt + 1. 3615 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg()); 3616 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 3617 if (Rt2 != Rt + 1) 3618 return Error(Operands[3]->getStartLoc(), 3619 "destination operands must be sequential"); 3620 return false; 3621 } 3622 case ARM::STRD: { 3623 // Rt2 must be Rt + 1. 3624 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg()); 3625 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 3626 if (Rt2 != Rt + 1) 3627 return Error(Operands[3]->getStartLoc(), 3628 "source operands must be sequential"); 3629 return false; 3630 } 3631 case ARM::STRD_PRE: 3632 case ARM::STRD_POST: 3633 case ARM::STREXD: { 3634 // Rt2 must be Rt + 1. 3635 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 3636 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg()); 3637 if (Rt2 != Rt + 1) 3638 return Error(Operands[3]->getStartLoc(), 3639 "source operands must be sequential"); 3640 return false; 3641 } 3642 case ARM::SBFX: 3643 case ARM::UBFX: { 3644 // width must be in range [1, 32-lsb] 3645 unsigned lsb = Inst.getOperand(2).getImm(); 3646 unsigned widthm1 = Inst.getOperand(3).getImm(); 3647 if (widthm1 >= 32 - lsb) 3648 return Error(Operands[5]->getStartLoc(), 3649 "bitfield width must be in range [1,32-lsb]"); 3650 return false; 3651 } 3652 case ARM::tLDMIA: { 3653 // If we're parsing Thumb2, the .w variant is available and handles 3654 // most cases that are normally illegal for a Thumb1 LDM 3655 // instruction. We'll make the transformation in processInstruction() 3656 // if necessary. 3657 // 3658 // Thumb LDM instructions are writeback iff the base register is not 3659 // in the register list. 3660 unsigned Rn = Inst.getOperand(0).getReg(); 3661 bool hasWritebackToken = 3662 (static_cast<ARMOperand*>(Operands[3])->isToken() && 3663 static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 3664 bool listContainsBase; 3665 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo()) 3666 return Error(Operands[3 + hasWritebackToken]->getStartLoc(), 3667 "registers must be in range r0-r7"); 3668 // If we should have writeback, then there should be a '!' token. 3669 if (!listContainsBase && !hasWritebackToken && !isThumbTwo()) 3670 return Error(Operands[2]->getStartLoc(), 3671 "writeback operator '!' expected"); 3672 // If we should not have writeback, there must not be a '!'. This is 3673 // true even for the 32-bit wide encodings. 3674 if (listContainsBase && hasWritebackToken) 3675 return Error(Operands[3]->getStartLoc(), 3676 "writeback operator '!' not allowed when base register " 3677 "in register list"); 3678 3679 break; 3680 } 3681 case ARM::t2LDMIA_UPD: { 3682 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) 3683 return Error(Operands[4]->getStartLoc(), 3684 "writeback operator '!' not allowed when base register " 3685 "in register list"); 3686 break; 3687 } 3688 case ARM::tPOP: { 3689 bool listContainsBase; 3690 if (checkLowRegisterList(Inst, 3, 0, ARM::PC, listContainsBase)) 3691 return Error(Operands[2]->getStartLoc(), 3692 "registers must be in range r0-r7 or pc"); 3693 break; 3694 } 3695 case ARM::tPUSH: { 3696 bool listContainsBase; 3697 if (checkLowRegisterList(Inst, 3, 0, ARM::LR, listContainsBase)) 3698 return Error(Operands[2]->getStartLoc(), 3699 "registers must be in range r0-r7 or lr"); 3700 break; 3701 } 3702 case ARM::tSTMIA_UPD: { 3703 bool listContainsBase; 3704 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo()) 3705 return Error(Operands[4]->getStartLoc(), 3706 "registers must be in range r0-r7"); 3707 break; 3708 } 3709 } 3710 3711 return false; 3712} 3713 3714void ARMAsmParser:: 3715processInstruction(MCInst &Inst, 3716 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3717 switch (Inst.getOpcode()) { 3718 case ARM::LDMIA_UPD: 3719 // If this is a load of a single register via a 'pop', then we should use 3720 // a post-indexed LDR instruction instead, per the ARM ARM. 3721 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" && 3722 Inst.getNumOperands() == 5) { 3723 MCInst TmpInst; 3724 TmpInst.setOpcode(ARM::LDR_POST_IMM); 3725 TmpInst.addOperand(Inst.getOperand(4)); // Rt 3726 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 3727 TmpInst.addOperand(Inst.getOperand(1)); // Rn 3728 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset 3729 TmpInst.addOperand(MCOperand::CreateImm(4)); 3730 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 3731 TmpInst.addOperand(Inst.getOperand(3)); 3732 Inst = TmpInst; 3733 } 3734 break; 3735 case ARM::STMDB_UPD: 3736 // If this is a store of a single register via a 'push', then we should use 3737 // a pre-indexed STR instruction instead, per the ARM ARM. 3738 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" && 3739 Inst.getNumOperands() == 5) { 3740 MCInst TmpInst; 3741 TmpInst.setOpcode(ARM::STR_PRE_IMM); 3742 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 3743 TmpInst.addOperand(Inst.getOperand(4)); // Rt 3744 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12 3745 TmpInst.addOperand(MCOperand::CreateImm(-4)); 3746 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 3747 TmpInst.addOperand(Inst.getOperand(3)); 3748 Inst = TmpInst; 3749 } 3750 break; 3751 case ARM::tADDi8: 3752 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 3753 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 3754 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 3755 // to encoding T1 if <Rd> is omitted." 3756 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) 3757 Inst.setOpcode(ARM::tADDi3); 3758 break; 3759 case ARM::tSUBi8: 3760 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 3761 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 3762 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 3763 // to encoding T1 if <Rd> is omitted." 3764 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) 3765 Inst.setOpcode(ARM::tSUBi3); 3766 break; 3767 case ARM::tB: 3768 // A Thumb conditional branch outside of an IT block is a tBcc. 3769 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) 3770 Inst.setOpcode(ARM::tBcc); 3771 break; 3772 case ARM::t2B: 3773 // A Thumb2 conditional branch outside of an IT block is a t2Bcc. 3774 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) 3775 Inst.setOpcode(ARM::t2Bcc); 3776 break; 3777 case ARM::t2Bcc: 3778 // If the conditional is AL or we're in an IT block, we really want t2B. 3779 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) 3780 Inst.setOpcode(ARM::t2B); 3781 break; 3782 case ARM::tBcc: 3783 // If the conditional is AL, we really want tB. 3784 if (Inst.getOperand(1).getImm() == ARMCC::AL) 3785 Inst.setOpcode(ARM::tB); 3786 break; 3787 case ARM::tLDMIA: { 3788 // If the register list contains any high registers, or if the writeback 3789 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding 3790 // instead if we're in Thumb2. Otherwise, this should have generated 3791 // an error in validateInstruction(). 3792 unsigned Rn = Inst.getOperand(0).getReg(); 3793 bool hasWritebackToken = 3794 (static_cast<ARMOperand*>(Operands[3])->isToken() && 3795 static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 3796 bool listContainsBase; 3797 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) || 3798 (!listContainsBase && !hasWritebackToken) || 3799 (listContainsBase && hasWritebackToken)) { 3800 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 3801 assert (isThumbTwo()); 3802 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); 3803 // If we're switching to the updating version, we need to insert 3804 // the writeback tied operand. 3805 if (hasWritebackToken) 3806 Inst.insert(Inst.begin(), 3807 MCOperand::CreateReg(Inst.getOperand(0).getReg())); 3808 } 3809 break; 3810 } 3811 case ARM::tSTMIA_UPD: { 3812 // If the register list contains any high registers, we need to use 3813 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 3814 // should have generated an error in validateInstruction(). 3815 unsigned Rn = Inst.getOperand(0).getReg(); 3816 bool listContainsBase; 3817 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) { 3818 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 3819 assert (isThumbTwo()); 3820 Inst.setOpcode(ARM::t2STMIA_UPD); 3821 } 3822 break; 3823 } 3824 case ARM::t2MOVi: { 3825 // If we can use the 16-bit encoding and the user didn't explicitly 3826 // request the 32-bit variant, transform it here. 3827 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 3828 Inst.getOperand(1).getImm() <= 255 && 3829 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL && 3830 Inst.getOperand(4).getReg() == ARM::CPSR) || 3831 (inITBlock() && Inst.getOperand(4).getReg() == 0)) && 3832 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 3833 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 3834 // The operands aren't in the same order for tMOVi8... 3835 MCInst TmpInst; 3836 TmpInst.setOpcode(ARM::tMOVi8); 3837 TmpInst.addOperand(Inst.getOperand(0)); 3838 TmpInst.addOperand(Inst.getOperand(4)); 3839 TmpInst.addOperand(Inst.getOperand(1)); 3840 TmpInst.addOperand(Inst.getOperand(2)); 3841 TmpInst.addOperand(Inst.getOperand(3)); 3842 Inst = TmpInst; 3843 } 3844 break; 3845 } 3846 case ARM::t2MOVr: { 3847 // If we can use the 16-bit encoding and the user didn't explicitly 3848 // request the 32-bit variant, transform it here. 3849 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 3850 isARMLowRegister(Inst.getOperand(1).getReg()) && 3851 Inst.getOperand(2).getImm() == ARMCC::AL && 3852 Inst.getOperand(4).getReg() == ARM::CPSR && 3853 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 3854 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 3855 // The operands aren't the same for tMOV[S]r... (no cc_out) 3856 MCInst TmpInst; 3857 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr); 3858 TmpInst.addOperand(Inst.getOperand(0)); 3859 TmpInst.addOperand(Inst.getOperand(1)); 3860 TmpInst.addOperand(Inst.getOperand(2)); 3861 TmpInst.addOperand(Inst.getOperand(3)); 3862 Inst = TmpInst; 3863 } 3864 break; 3865 } 3866 case ARM::t2SXTH: 3867 case ARM::t2SXTB: { 3868 // If we can use the 16-bit encoding and the user didn't explicitly 3869 // request the 32-bit variant, transform it here. 3870 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 3871 isARMLowRegister(Inst.getOperand(1).getReg()) && 3872 Inst.getOperand(2).getImm() == 0 && 3873 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 3874 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 3875 unsigned NewOpc = (Inst.getOpcode() == ARM::t2SXTH) ? 3876 ARM::tSXTH : ARM::tSXTB; 3877 // The operands aren't the same for thumb1 (no rotate operand). 3878 MCInst TmpInst; 3879 TmpInst.setOpcode(NewOpc); 3880 TmpInst.addOperand(Inst.getOperand(0)); 3881 TmpInst.addOperand(Inst.getOperand(1)); 3882 TmpInst.addOperand(Inst.getOperand(3)); 3883 TmpInst.addOperand(Inst.getOperand(4)); 3884 Inst = TmpInst; 3885 } 3886 break; 3887 } 3888 case ARM::t2IT: { 3889 // The mask bits for all but the first condition are represented as 3890 // the low bit of the condition code value implies 't'. We currently 3891 // always have 1 implies 't', so XOR toggle the bits if the low bit 3892 // of the condition code is zero. The encoding also expects the low 3893 // bit of the condition to be encoded as bit 4 of the mask operand, 3894 // so mask that in if needed 3895 MCOperand &MO = Inst.getOperand(1); 3896 unsigned Mask = MO.getImm(); 3897 unsigned OrigMask = Mask; 3898 unsigned TZ = CountTrailingZeros_32(Mask); 3899 if ((Inst.getOperand(0).getImm() & 1) == 0) { 3900 assert(Mask && TZ <= 3 && "illegal IT mask value!"); 3901 for (unsigned i = 3; i != TZ; --i) 3902 Mask ^= 1 << i; 3903 } else 3904 Mask |= 0x10; 3905 MO.setImm(Mask); 3906 3907 // Set up the IT block state according to the IT instruction we just 3908 // matched. 3909 assert(!inITBlock() && "nested IT blocks?!"); 3910 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm()); 3911 ITState.Mask = OrigMask; // Use the original mask, not the updated one. 3912 ITState.CurPosition = 0; 3913 ITState.FirstCond = true; 3914 break; 3915 } 3916 } 3917} 3918 3919unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) { 3920 // 16-bit thumb arithmetic instructions either require or preclude the 'S' 3921 // suffix depending on whether they're in an IT block or not. 3922 unsigned Opc = Inst.getOpcode(); 3923 MCInstrDesc &MCID = getInstDesc(Opc); 3924 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) { 3925 assert(MCID.hasOptionalDef() && 3926 "optionally flag setting instruction missing optional def operand"); 3927 assert(MCID.NumOperands == Inst.getNumOperands() && 3928 "operand count mismatch!"); 3929 // Find the optional-def operand (cc_out). 3930 unsigned OpNo; 3931 for (OpNo = 0; 3932 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands; 3933 ++OpNo) 3934 ; 3935 // If we're parsing Thumb1, reject it completely. 3936 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) 3937 return Match_MnemonicFail; 3938 // If we're parsing Thumb2, which form is legal depends on whether we're 3939 // in an IT block. 3940 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && 3941 !inITBlock()) 3942 return Match_RequiresITBlock; 3943 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && 3944 inITBlock()) 3945 return Match_RequiresNotITBlock; 3946 } 3947 // Some high-register supporting Thumb1 encodings only allow both registers 3948 // to be from r0-r7 when in Thumb2. 3949 else if (Opc == ARM::tADDhirr && isThumbOne() && 3950 isARMLowRegister(Inst.getOperand(1).getReg()) && 3951 isARMLowRegister(Inst.getOperand(2).getReg())) 3952 return Match_RequiresThumb2; 3953 // Others only require ARMv6 or later. 3954 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() && 3955 isARMLowRegister(Inst.getOperand(0).getReg()) && 3956 isARMLowRegister(Inst.getOperand(1).getReg())) 3957 return Match_RequiresV6; 3958 return Match_Success; 3959} 3960 3961bool ARMAsmParser:: 3962MatchAndEmitInstruction(SMLoc IDLoc, 3963 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 3964 MCStreamer &Out) { 3965 MCInst Inst; 3966 unsigned ErrorInfo; 3967 unsigned MatchResult; 3968 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo); 3969 switch (MatchResult) { 3970 default: break; 3971 case Match_Success: 3972 // Context sensitive operand constraints aren't handled by the matcher, 3973 // so check them here. 3974 if (validateInstruction(Inst, Operands)) { 3975 // Still progress the IT block, otherwise one wrong condition causes 3976 // nasty cascading errors. 3977 forwardITPosition(); 3978 return true; 3979 } 3980 3981 // Some instructions need post-processing to, for example, tweak which 3982 // encoding is selected. 3983 processInstruction(Inst, Operands); 3984 3985 // Only move forward at the very end so that everything in validate 3986 // and process gets a consistent answer about whether we're in an IT 3987 // block. 3988 forwardITPosition(); 3989 3990 Out.EmitInstruction(Inst); 3991 return false; 3992 case Match_MissingFeature: 3993 Error(IDLoc, "instruction requires a CPU feature not currently enabled"); 3994 return true; 3995 case Match_InvalidOperand: { 3996 SMLoc ErrorLoc = IDLoc; 3997 if (ErrorInfo != ~0U) { 3998 if (ErrorInfo >= Operands.size()) 3999 return Error(IDLoc, "too few operands for instruction"); 4000 4001 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 4002 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 4003 } 4004 4005 return Error(ErrorLoc, "invalid operand for instruction"); 4006 } 4007 case Match_MnemonicFail: 4008 return Error(IDLoc, "invalid instruction"); 4009 case Match_ConversionFail: 4010 // The converter function will have already emited a diagnostic. 4011 return true; 4012 case Match_RequiresNotITBlock: 4013 return Error(IDLoc, "flag setting instruction only valid outside IT block"); 4014 case Match_RequiresITBlock: 4015 return Error(IDLoc, "instruction only valid inside IT block"); 4016 case Match_RequiresV6: 4017 return Error(IDLoc, "instruction variant requires ARMv6 or later"); 4018 case Match_RequiresThumb2: 4019 return Error(IDLoc, "instruction variant requires Thumb2"); 4020 } 4021 4022 llvm_unreachable("Implement any new match types added!"); 4023 return true; 4024} 4025 4026/// parseDirective parses the arm specific directives 4027bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { 4028 StringRef IDVal = DirectiveID.getIdentifier(); 4029 if (IDVal == ".word") 4030 return parseDirectiveWord(4, DirectiveID.getLoc()); 4031 else if (IDVal == ".thumb") 4032 return parseDirectiveThumb(DirectiveID.getLoc()); 4033 else if (IDVal == ".thumb_func") 4034 return parseDirectiveThumbFunc(DirectiveID.getLoc()); 4035 else if (IDVal == ".code") 4036 return parseDirectiveCode(DirectiveID.getLoc()); 4037 else if (IDVal == ".syntax") 4038 return parseDirectiveSyntax(DirectiveID.getLoc()); 4039 return true; 4040} 4041 4042/// parseDirectiveWord 4043/// ::= .word [ expression (, expression)* ] 4044bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) { 4045 if (getLexer().isNot(AsmToken::EndOfStatement)) { 4046 for (;;) { 4047 const MCExpr *Value; 4048 if (getParser().ParseExpression(Value)) 4049 return true; 4050 4051 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/); 4052 4053 if (getLexer().is(AsmToken::EndOfStatement)) 4054 break; 4055 4056 // FIXME: Improve diagnostic. 4057 if (getLexer().isNot(AsmToken::Comma)) 4058 return Error(L, "unexpected token in directive"); 4059 Parser.Lex(); 4060 } 4061 } 4062 4063 Parser.Lex(); 4064 return false; 4065} 4066 4067/// parseDirectiveThumb 4068/// ::= .thumb 4069bool ARMAsmParser::parseDirectiveThumb(SMLoc L) { 4070 if (getLexer().isNot(AsmToken::EndOfStatement)) 4071 return Error(L, "unexpected token in directive"); 4072 Parser.Lex(); 4073 4074 // TODO: set thumb mode 4075 // TODO: tell the MC streamer the mode 4076 // getParser().getStreamer().Emit???(); 4077 return false; 4078} 4079 4080/// parseDirectiveThumbFunc 4081/// ::= .thumbfunc symbol_name 4082bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) { 4083 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo(); 4084 bool isMachO = MAI.hasSubsectionsViaSymbols(); 4085 StringRef Name; 4086 4087 // Darwin asm has function name after .thumb_func direction 4088 // ELF doesn't 4089 if (isMachO) { 4090 const AsmToken &Tok = Parser.getTok(); 4091 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) 4092 return Error(L, "unexpected token in .thumb_func directive"); 4093 Name = Tok.getString(); 4094 Parser.Lex(); // Consume the identifier token. 4095 } 4096 4097 if (getLexer().isNot(AsmToken::EndOfStatement)) 4098 return Error(L, "unexpected token in directive"); 4099 Parser.Lex(); 4100 4101 // FIXME: assuming function name will be the line following .thumb_func 4102 if (!isMachO) { 4103 Name = Parser.getTok().getString(); 4104 } 4105 4106 // Mark symbol as a thumb symbol. 4107 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name); 4108 getParser().getStreamer().EmitThumbFunc(Func); 4109 return false; 4110} 4111 4112/// parseDirectiveSyntax 4113/// ::= .syntax unified | divided 4114bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) { 4115 const AsmToken &Tok = Parser.getTok(); 4116 if (Tok.isNot(AsmToken::Identifier)) 4117 return Error(L, "unexpected token in .syntax directive"); 4118 StringRef Mode = Tok.getString(); 4119 if (Mode == "unified" || Mode == "UNIFIED") 4120 Parser.Lex(); 4121 else if (Mode == "divided" || Mode == "DIVIDED") 4122 return Error(L, "'.syntax divided' arm asssembly not supported"); 4123 else 4124 return Error(L, "unrecognized syntax mode in .syntax directive"); 4125 4126 if (getLexer().isNot(AsmToken::EndOfStatement)) 4127 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 4128 Parser.Lex(); 4129 4130 // TODO tell the MC streamer the mode 4131 // getParser().getStreamer().Emit???(); 4132 return false; 4133} 4134 4135/// parseDirectiveCode 4136/// ::= .code 16 | 32 4137bool ARMAsmParser::parseDirectiveCode(SMLoc L) { 4138 const AsmToken &Tok = Parser.getTok(); 4139 if (Tok.isNot(AsmToken::Integer)) 4140 return Error(L, "unexpected token in .code directive"); 4141 int64_t Val = Parser.getTok().getIntVal(); 4142 if (Val == 16) 4143 Parser.Lex(); 4144 else if (Val == 32) 4145 Parser.Lex(); 4146 else 4147 return Error(L, "invalid operand to .code directive"); 4148 4149 if (getLexer().isNot(AsmToken::EndOfStatement)) 4150 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 4151 Parser.Lex(); 4152 4153 if (Val == 16) { 4154 if (!isThumb()) 4155 SwitchMode(); 4156 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 4157 } else { 4158 if (isThumb()) 4159 SwitchMode(); 4160 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 4161 } 4162 4163 return false; 4164} 4165 4166extern "C" void LLVMInitializeARMAsmLexer(); 4167 4168/// Force static initialization. 4169extern "C" void LLVMInitializeARMAsmParser() { 4170 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget); 4171 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget); 4172 LLVMInitializeARMAsmLexer(); 4173} 4174 4175#define GET_REGISTER_MATCHER 4176#define GET_MATCHER_IMPLEMENTATION 4177#include "ARMGenAsmMatcher.inc" 4178