ARMAsmParser.cpp revision 4334e032525d6c9038605f3871b945e8cbe6fab7 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/ARMBaseInfo.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMMCExpr.h"
13#include "llvm/MC/MCParser/MCAsmLexer.h"
14#include "llvm/MC/MCParser/MCAsmParser.h"
15#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCStreamer.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrDesc.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/MCTargetAsmParser.h"
25#include "llvm/Support/MathExtras.h"
26#include "llvm/Support/SourceMgr.h"
27#include "llvm/Support/TargetRegistry.h"
28#include "llvm/Support/raw_ostream.h"
29#include "llvm/ADT/BitVector.h"
30#include "llvm/ADT/OwningPtr.h"
31#include "llvm/ADT/STLExtras.h"
32#include "llvm/ADT/SmallVector.h"
33#include "llvm/ADT/StringExtras.h"
34#include "llvm/ADT/StringSwitch.h"
35#include "llvm/ADT/Twine.h"
36
37using namespace llvm;
38
39namespace {
40
41class ARMOperand;
42
43class ARMAsmParser : public MCTargetAsmParser {
44  MCSubtargetInfo &STI;
45  MCAsmParser &Parser;
46
47  struct {
48    ARMCC::CondCodes Cond;    // Condition for IT block.
49    unsigned Mask:4;          // Condition mask for instructions.
50                              // Starting at first 1 (from lsb).
51                              //   '1'  condition as indicated in IT.
52                              //   '0'  inverse of condition (else).
53                              // Count of instructions in IT block is
54                              // 4 - trailingzeroes(mask)
55
56    bool FirstCond;           // Explicit flag for when we're parsing the
57                              // First instruction in the IT block. It's
58                              // implied in the mask, so needs special
59                              // handling.
60
61    unsigned CurPosition;     // Current position in parsing of IT
62                              // block. In range [0,3]. Initialized
63                              // according to count of instructions in block.
64                              // ~0U if no active IT block.
65  } ITState;
66  bool inITBlock() { return ITState.CurPosition != ~0U;}
67  void forwardITPosition() {
68    if (!inITBlock()) return;
69    // Move to the next instruction in the IT block, if there is one. If not,
70    // mark the block as done.
71    unsigned TZ = CountTrailingZeros_32(ITState.Mask);
72    if (++ITState.CurPosition == 5 - TZ)
73      ITState.CurPosition = ~0U; // Done with the IT block after this.
74  }
75
76
77  MCAsmParser &getParser() const { return Parser; }
78  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
79
80  void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
81  bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
82
83  int tryParseRegister();
84  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
85  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
86  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
87  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
88  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
89  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
90  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
91                              unsigned &ShiftAmount);
92  bool parseDirectiveWord(unsigned Size, SMLoc L);
93  bool parseDirectiveThumb(SMLoc L);
94  bool parseDirectiveThumbFunc(SMLoc L);
95  bool parseDirectiveCode(SMLoc L);
96  bool parseDirectiveSyntax(SMLoc L);
97
98  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
99                          bool &CarrySetting, unsigned &ProcessorIMod,
100                          StringRef &ITMask);
101  void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
102                             bool &CanAcceptPredicationCode);
103
104  bool isThumb() const {
105    // FIXME: Can tablegen auto-generate this?
106    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
107  }
108  bool isThumbOne() const {
109    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
110  }
111  bool isThumbTwo() const {
112    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
113  }
114  bool hasV6Ops() const {
115    return STI.getFeatureBits() & ARM::HasV6Ops;
116  }
117  bool hasV7Ops() const {
118    return STI.getFeatureBits() & ARM::HasV7Ops;
119  }
120  void SwitchMode() {
121    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
122    setAvailableFeatures(FB);
123  }
124  bool isMClass() const {
125    return STI.getFeatureBits() & ARM::FeatureMClass;
126  }
127
128  /// @name Auto-generated Match Functions
129  /// {
130
131#define GET_ASSEMBLER_HEADER
132#include "ARMGenAsmMatcher.inc"
133
134  /// }
135
136  OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
137  OperandMatchResultTy parseCoprocNumOperand(
138    SmallVectorImpl<MCParsedAsmOperand*>&);
139  OperandMatchResultTy parseCoprocRegOperand(
140    SmallVectorImpl<MCParsedAsmOperand*>&);
141  OperandMatchResultTy parseCoprocOptionOperand(
142    SmallVectorImpl<MCParsedAsmOperand*>&);
143  OperandMatchResultTy parseMemBarrierOptOperand(
144    SmallVectorImpl<MCParsedAsmOperand*>&);
145  OperandMatchResultTy parseProcIFlagsOperand(
146    SmallVectorImpl<MCParsedAsmOperand*>&);
147  OperandMatchResultTy parseMSRMaskOperand(
148    SmallVectorImpl<MCParsedAsmOperand*>&);
149  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
150                                   StringRef Op, int Low, int High);
151  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
152    return parsePKHImm(O, "lsl", 0, 31);
153  }
154  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
155    return parsePKHImm(O, "asr", 1, 32);
156  }
157  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
158  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
159  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
160  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
161  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
162  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
163  OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
164  OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
165
166  // Asm Match Converter Methods
167  bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
168                    const SmallVectorImpl<MCParsedAsmOperand*> &);
169  bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
170                    const SmallVectorImpl<MCParsedAsmOperand*> &);
171  bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
172                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
173  bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
174                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
175  bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
176                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
177  bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
178                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
179  bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
180                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
181  bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
182                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
183  bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
184                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
185  bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
186                             const SmallVectorImpl<MCParsedAsmOperand*> &);
187  bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
188                             const SmallVectorImpl<MCParsedAsmOperand*> &);
189  bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
190                             const SmallVectorImpl<MCParsedAsmOperand*> &);
191  bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
192                             const SmallVectorImpl<MCParsedAsmOperand*> &);
193  bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
194                  const SmallVectorImpl<MCParsedAsmOperand*> &);
195  bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
196                  const SmallVectorImpl<MCParsedAsmOperand*> &);
197  bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
198                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
199  bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
200                        const SmallVectorImpl<MCParsedAsmOperand*> &);
201  bool cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
202                     const SmallVectorImpl<MCParsedAsmOperand*> &);
203  bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
204                        const SmallVectorImpl<MCParsedAsmOperand*> &);
205  bool cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
206                     const SmallVectorImpl<MCParsedAsmOperand*> &);
207  bool cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
208                        const SmallVectorImpl<MCParsedAsmOperand*> &);
209
210  bool validateInstruction(MCInst &Inst,
211                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
212  void processInstruction(MCInst &Inst,
213                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
214  bool shouldOmitCCOutOperand(StringRef Mnemonic,
215                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
216
217public:
218  enum ARMMatchResultTy {
219    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
220    Match_RequiresNotITBlock,
221    Match_RequiresV6,
222    Match_RequiresThumb2
223  };
224
225  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
226    : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
227    MCAsmParserExtension::Initialize(_Parser);
228
229    // Initialize the set of available features.
230    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
231
232    // Not in an ITBlock to start with.
233    ITState.CurPosition = ~0U;
234  }
235
236  // Implementation of the MCTargetAsmParser interface:
237  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
238  bool ParseInstruction(StringRef Name, SMLoc NameLoc,
239                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
240  bool ParseDirective(AsmToken DirectiveID);
241
242  unsigned checkTargetMatchPredicate(MCInst &Inst);
243
244  bool MatchAndEmitInstruction(SMLoc IDLoc,
245                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
246                               MCStreamer &Out);
247};
248} // end anonymous namespace
249
250namespace {
251
252/// ARMOperand - Instances of this class represent a parsed ARM machine
253/// instruction.
254class ARMOperand : public MCParsedAsmOperand {
255  enum KindTy {
256    k_CondCode,
257    k_CCOut,
258    k_ITCondMask,
259    k_CoprocNum,
260    k_CoprocReg,
261    k_CoprocOption,
262    k_Immediate,
263    k_FPImmediate,
264    k_MemBarrierOpt,
265    k_Memory,
266    k_PostIndexRegister,
267    k_MSRMask,
268    k_ProcIFlags,
269    k_VectorIndex,
270    k_Register,
271    k_RegisterList,
272    k_DPRRegisterList,
273    k_SPRRegisterList,
274    k_VectorList,
275    k_ShiftedRegister,
276    k_ShiftedImmediate,
277    k_ShifterImmediate,
278    k_RotateImmediate,
279    k_BitfieldDescriptor,
280    k_Token
281  } Kind;
282
283  SMLoc StartLoc, EndLoc;
284  SmallVector<unsigned, 8> Registers;
285
286  union {
287    struct {
288      ARMCC::CondCodes Val;
289    } CC;
290
291    struct {
292      unsigned Val;
293    } Cop;
294
295    struct {
296      unsigned Val;
297    } CoprocOption;
298
299    struct {
300      unsigned Mask:4;
301    } ITMask;
302
303    struct {
304      ARM_MB::MemBOpt Val;
305    } MBOpt;
306
307    struct {
308      ARM_PROC::IFlags Val;
309    } IFlags;
310
311    struct {
312      unsigned Val;
313    } MMask;
314
315    struct {
316      const char *Data;
317      unsigned Length;
318    } Tok;
319
320    struct {
321      unsigned RegNum;
322    } Reg;
323
324    // A vector register list is a sequential list of 1 to 4 registers.
325    struct {
326      unsigned RegNum;
327      unsigned Count;
328    } VectorList;
329
330    struct {
331      unsigned Val;
332    } VectorIndex;
333
334    struct {
335      const MCExpr *Val;
336    } Imm;
337
338    struct {
339      unsigned Val;       // encoded 8-bit representation
340    } FPImm;
341
342    /// Combined record for all forms of ARM address expressions.
343    struct {
344      unsigned BaseRegNum;
345      // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
346      // was specified.
347      const MCConstantExpr *OffsetImm;  // Offset immediate value
348      unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
349      ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
350      unsigned ShiftImm;        // shift for OffsetReg.
351      unsigned Alignment;       // 0 = no alignment specified
352                                // n = alignment in bytes (8, 16, or 32)
353      unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
354    } Memory;
355
356    struct {
357      unsigned RegNum;
358      bool isAdd;
359      ARM_AM::ShiftOpc ShiftTy;
360      unsigned ShiftImm;
361    } PostIdxReg;
362
363    struct {
364      bool isASR;
365      unsigned Imm;
366    } ShifterImm;
367    struct {
368      ARM_AM::ShiftOpc ShiftTy;
369      unsigned SrcReg;
370      unsigned ShiftReg;
371      unsigned ShiftImm;
372    } RegShiftedReg;
373    struct {
374      ARM_AM::ShiftOpc ShiftTy;
375      unsigned SrcReg;
376      unsigned ShiftImm;
377    } RegShiftedImm;
378    struct {
379      unsigned Imm;
380    } RotImm;
381    struct {
382      unsigned LSB;
383      unsigned Width;
384    } Bitfield;
385  };
386
387  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
388public:
389  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
390    Kind = o.Kind;
391    StartLoc = o.StartLoc;
392    EndLoc = o.EndLoc;
393    switch (Kind) {
394    case k_CondCode:
395      CC = o.CC;
396      break;
397    case k_ITCondMask:
398      ITMask = o.ITMask;
399      break;
400    case k_Token:
401      Tok = o.Tok;
402      break;
403    case k_CCOut:
404    case k_Register:
405      Reg = o.Reg;
406      break;
407    case k_RegisterList:
408    case k_DPRRegisterList:
409    case k_SPRRegisterList:
410      Registers = o.Registers;
411      break;
412    case k_VectorList:
413      VectorList = o.VectorList;
414      break;
415    case k_CoprocNum:
416    case k_CoprocReg:
417      Cop = o.Cop;
418      break;
419    case k_CoprocOption:
420      CoprocOption = o.CoprocOption;
421      break;
422    case k_Immediate:
423      Imm = o.Imm;
424      break;
425    case k_FPImmediate:
426      FPImm = o.FPImm;
427      break;
428    case k_MemBarrierOpt:
429      MBOpt = o.MBOpt;
430      break;
431    case k_Memory:
432      Memory = o.Memory;
433      break;
434    case k_PostIndexRegister:
435      PostIdxReg = o.PostIdxReg;
436      break;
437    case k_MSRMask:
438      MMask = o.MMask;
439      break;
440    case k_ProcIFlags:
441      IFlags = o.IFlags;
442      break;
443    case k_ShifterImmediate:
444      ShifterImm = o.ShifterImm;
445      break;
446    case k_ShiftedRegister:
447      RegShiftedReg = o.RegShiftedReg;
448      break;
449    case k_ShiftedImmediate:
450      RegShiftedImm = o.RegShiftedImm;
451      break;
452    case k_RotateImmediate:
453      RotImm = o.RotImm;
454      break;
455    case k_BitfieldDescriptor:
456      Bitfield = o.Bitfield;
457      break;
458    case k_VectorIndex:
459      VectorIndex = o.VectorIndex;
460      break;
461    }
462  }
463
464  /// getStartLoc - Get the location of the first token of this operand.
465  SMLoc getStartLoc() const { return StartLoc; }
466  /// getEndLoc - Get the location of the last token of this operand.
467  SMLoc getEndLoc() const { return EndLoc; }
468
469  ARMCC::CondCodes getCondCode() const {
470    assert(Kind == k_CondCode && "Invalid access!");
471    return CC.Val;
472  }
473
474  unsigned getCoproc() const {
475    assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
476    return Cop.Val;
477  }
478
479  StringRef getToken() const {
480    assert(Kind == k_Token && "Invalid access!");
481    return StringRef(Tok.Data, Tok.Length);
482  }
483
484  unsigned getReg() const {
485    assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
486    return Reg.RegNum;
487  }
488
489  const SmallVectorImpl<unsigned> &getRegList() const {
490    assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
491            Kind == k_SPRRegisterList) && "Invalid access!");
492    return Registers;
493  }
494
495  const MCExpr *getImm() const {
496    assert(Kind == k_Immediate && "Invalid access!");
497    return Imm.Val;
498  }
499
500  unsigned getFPImm() const {
501    assert(Kind == k_FPImmediate && "Invalid access!");
502    return FPImm.Val;
503  }
504
505  unsigned getVectorIndex() const {
506    assert(Kind == k_VectorIndex && "Invalid access!");
507    return VectorIndex.Val;
508  }
509
510  ARM_MB::MemBOpt getMemBarrierOpt() const {
511    assert(Kind == k_MemBarrierOpt && "Invalid access!");
512    return MBOpt.Val;
513  }
514
515  ARM_PROC::IFlags getProcIFlags() const {
516    assert(Kind == k_ProcIFlags && "Invalid access!");
517    return IFlags.Val;
518  }
519
520  unsigned getMSRMask() const {
521    assert(Kind == k_MSRMask && "Invalid access!");
522    return MMask.Val;
523  }
524
525  bool isCoprocNum() const { return Kind == k_CoprocNum; }
526  bool isCoprocReg() const { return Kind == k_CoprocReg; }
527  bool isCoprocOption() const { return Kind == k_CoprocOption; }
528  bool isCondCode() const { return Kind == k_CondCode; }
529  bool isCCOut() const { return Kind == k_CCOut; }
530  bool isITMask() const { return Kind == k_ITCondMask; }
531  bool isITCondCode() const { return Kind == k_CondCode; }
532  bool isImm() const { return Kind == k_Immediate; }
533  bool isFPImm() const { return Kind == k_FPImmediate; }
534  bool isImm8s4() const {
535    if (Kind != k_Immediate)
536      return false;
537    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
538    if (!CE) return false;
539    int64_t Value = CE->getValue();
540    return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
541  }
542  bool isImm0_1020s4() const {
543    if (Kind != k_Immediate)
544      return false;
545    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
546    if (!CE) return false;
547    int64_t Value = CE->getValue();
548    return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
549  }
550  bool isImm0_508s4() const {
551    if (Kind != k_Immediate)
552      return false;
553    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
554    if (!CE) return false;
555    int64_t Value = CE->getValue();
556    return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
557  }
558  bool isImm0_255() const {
559    if (Kind != k_Immediate)
560      return false;
561    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
562    if (!CE) return false;
563    int64_t Value = CE->getValue();
564    return Value >= 0 && Value < 256;
565  }
566  bool isImm0_7() const {
567    if (Kind != k_Immediate)
568      return false;
569    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
570    if (!CE) return false;
571    int64_t Value = CE->getValue();
572    return Value >= 0 && Value < 8;
573  }
574  bool isImm0_15() const {
575    if (Kind != k_Immediate)
576      return false;
577    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
578    if (!CE) return false;
579    int64_t Value = CE->getValue();
580    return Value >= 0 && Value < 16;
581  }
582  bool isImm0_31() const {
583    if (Kind != k_Immediate)
584      return false;
585    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
586    if (!CE) return false;
587    int64_t Value = CE->getValue();
588    return Value >= 0 && Value < 32;
589  }
590  bool isImm1_16() const {
591    if (Kind != k_Immediate)
592      return false;
593    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
594    if (!CE) return false;
595    int64_t Value = CE->getValue();
596    return Value > 0 && Value < 17;
597  }
598  bool isImm1_32() const {
599    if (Kind != k_Immediate)
600      return false;
601    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
602    if (!CE) return false;
603    int64_t Value = CE->getValue();
604    return Value > 0 && Value < 33;
605  }
606  bool isImm0_65535() const {
607    if (Kind != k_Immediate)
608      return false;
609    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
610    if (!CE) return false;
611    int64_t Value = CE->getValue();
612    return Value >= 0 && Value < 65536;
613  }
614  bool isImm0_65535Expr() const {
615    if (Kind != k_Immediate)
616      return false;
617    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
618    // If it's not a constant expression, it'll generate a fixup and be
619    // handled later.
620    if (!CE) return true;
621    int64_t Value = CE->getValue();
622    return Value >= 0 && Value < 65536;
623  }
624  bool isImm24bit() const {
625    if (Kind != k_Immediate)
626      return false;
627    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
628    if (!CE) return false;
629    int64_t Value = CE->getValue();
630    return Value >= 0 && Value <= 0xffffff;
631  }
632  bool isImmThumbSR() const {
633    if (Kind != k_Immediate)
634      return false;
635    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
636    if (!CE) return false;
637    int64_t Value = CE->getValue();
638    return Value > 0 && Value < 33;
639  }
640  bool isPKHLSLImm() const {
641    if (Kind != k_Immediate)
642      return false;
643    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
644    if (!CE) return false;
645    int64_t Value = CE->getValue();
646    return Value >= 0 && Value < 32;
647  }
648  bool isPKHASRImm() const {
649    if (Kind != k_Immediate)
650      return false;
651    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
652    if (!CE) return false;
653    int64_t Value = CE->getValue();
654    return Value > 0 && Value <= 32;
655  }
656  bool isARMSOImm() const {
657    if (Kind != k_Immediate)
658      return false;
659    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
660    if (!CE) return false;
661    int64_t Value = CE->getValue();
662    return ARM_AM::getSOImmVal(Value) != -1;
663  }
664  bool isARMSOImmNot() const {
665    if (Kind != k_Immediate)
666      return false;
667    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
668    if (!CE) return false;
669    int64_t Value = CE->getValue();
670    return ARM_AM::getSOImmVal(~Value) != -1;
671  }
672  bool isT2SOImm() const {
673    if (Kind != k_Immediate)
674      return false;
675    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
676    if (!CE) return false;
677    int64_t Value = CE->getValue();
678    return ARM_AM::getT2SOImmVal(Value) != -1;
679  }
680  bool isT2SOImmNot() const {
681    if (Kind != k_Immediate)
682      return false;
683    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
684    if (!CE) return false;
685    int64_t Value = CE->getValue();
686    return ARM_AM::getT2SOImmVal(~Value) != -1;
687  }
688  bool isSetEndImm() const {
689    if (Kind != k_Immediate)
690      return false;
691    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
692    if (!CE) return false;
693    int64_t Value = CE->getValue();
694    return Value == 1 || Value == 0;
695  }
696  bool isReg() const { return Kind == k_Register; }
697  bool isRegList() const { return Kind == k_RegisterList; }
698  bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
699  bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
700  bool isToken() const { return Kind == k_Token; }
701  bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
702  bool isMemory() const { return Kind == k_Memory; }
703  bool isShifterImm() const { return Kind == k_ShifterImmediate; }
704  bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
705  bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
706  bool isRotImm() const { return Kind == k_RotateImmediate; }
707  bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
708  bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
709  bool isPostIdxReg() const {
710    return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
711  }
712  bool isMemNoOffset(bool alignOK = false) const {
713    if (!isMemory())
714      return false;
715    // No offset of any kind.
716    return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
717     (alignOK || Memory.Alignment == 0);
718  }
719  bool isAlignedMemory() const {
720    return isMemNoOffset(true);
721  }
722  bool isAddrMode2() const {
723    if (!isMemory() || Memory.Alignment != 0) return false;
724    // Check for register offset.
725    if (Memory.OffsetRegNum) return true;
726    // Immediate offset in range [-4095, 4095].
727    if (!Memory.OffsetImm) return true;
728    int64_t Val = Memory.OffsetImm->getValue();
729    return Val > -4096 && Val < 4096;
730  }
731  bool isAM2OffsetImm() const {
732    if (Kind != k_Immediate)
733      return false;
734    // Immediate offset in range [-4095, 4095].
735    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
736    if (!CE) return false;
737    int64_t Val = CE->getValue();
738    return Val > -4096 && Val < 4096;
739  }
740  bool isAddrMode3() const {
741    if (!isMemory() || Memory.Alignment != 0) return false;
742    // No shifts are legal for AM3.
743    if (Memory.ShiftType != ARM_AM::no_shift) return false;
744    // Check for register offset.
745    if (Memory.OffsetRegNum) return true;
746    // Immediate offset in range [-255, 255].
747    if (!Memory.OffsetImm) return true;
748    int64_t Val = Memory.OffsetImm->getValue();
749    return Val > -256 && Val < 256;
750  }
751  bool isAM3Offset() const {
752    if (Kind != k_Immediate && Kind != k_PostIndexRegister)
753      return false;
754    if (Kind == k_PostIndexRegister)
755      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
756    // Immediate offset in range [-255, 255].
757    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
758    if (!CE) return false;
759    int64_t Val = CE->getValue();
760    // Special case, #-0 is INT32_MIN.
761    return (Val > -256 && Val < 256) || Val == INT32_MIN;
762  }
763  bool isAddrMode5() const {
764    if (!isMemory() || Memory.Alignment != 0) return false;
765    // Check for register offset.
766    if (Memory.OffsetRegNum) return false;
767    // Immediate offset in range [-1020, 1020] and a multiple of 4.
768    if (!Memory.OffsetImm) return true;
769    int64_t Val = Memory.OffsetImm->getValue();
770    return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
771           Val == INT32_MIN;
772  }
773  bool isMemTBB() const {
774    if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
775        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
776      return false;
777    return true;
778  }
779  bool isMemTBH() const {
780    if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
781        Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
782        Memory.Alignment != 0 )
783      return false;
784    return true;
785  }
786  bool isMemRegOffset() const {
787    if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0)
788      return false;
789    return true;
790  }
791  bool isT2MemRegOffset() const {
792    if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
793        Memory.Alignment != 0)
794      return false;
795    // Only lsl #{0, 1, 2, 3} allowed.
796    if (Memory.ShiftType == ARM_AM::no_shift)
797      return true;
798    if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
799      return false;
800    return true;
801  }
802  bool isMemThumbRR() const {
803    // Thumb reg+reg addressing is simple. Just two registers, a base and
804    // an offset. No shifts, negations or any other complicating factors.
805    if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
806        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
807      return false;
808    return isARMLowRegister(Memory.BaseRegNum) &&
809      (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
810  }
811  bool isMemThumbRIs4() const {
812    if (!isMemory() || Memory.OffsetRegNum != 0 ||
813        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
814      return false;
815    // Immediate offset, multiple of 4 in range [0, 124].
816    if (!Memory.OffsetImm) return true;
817    int64_t Val = Memory.OffsetImm->getValue();
818    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
819  }
820  bool isMemThumbRIs2() const {
821    if (!isMemory() || Memory.OffsetRegNum != 0 ||
822        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
823      return false;
824    // Immediate offset, multiple of 4 in range [0, 62].
825    if (!Memory.OffsetImm) return true;
826    int64_t Val = Memory.OffsetImm->getValue();
827    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
828  }
829  bool isMemThumbRIs1() const {
830    if (!isMemory() || Memory.OffsetRegNum != 0 ||
831        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
832      return false;
833    // Immediate offset in range [0, 31].
834    if (!Memory.OffsetImm) return true;
835    int64_t Val = Memory.OffsetImm->getValue();
836    return Val >= 0 && Val <= 31;
837  }
838  bool isMemThumbSPI() const {
839    if (!isMemory() || Memory.OffsetRegNum != 0 ||
840        Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
841      return false;
842    // Immediate offset, multiple of 4 in range [0, 1020].
843    if (!Memory.OffsetImm) return true;
844    int64_t Val = Memory.OffsetImm->getValue();
845    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
846  }
847  bool isMemImm8s4Offset() const {
848    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
849      return false;
850    // Immediate offset a multiple of 4 in range [-1020, 1020].
851    if (!Memory.OffsetImm) return true;
852    int64_t Val = Memory.OffsetImm->getValue();
853    return Val >= -1020 && Val <= 1020 && (Val & 3) == 0;
854  }
855  bool isMemImm0_1020s4Offset() const {
856    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
857      return false;
858    // Immediate offset a multiple of 4 in range [0, 1020].
859    if (!Memory.OffsetImm) return true;
860    int64_t Val = Memory.OffsetImm->getValue();
861    return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
862  }
863  bool isMemImm8Offset() const {
864    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
865      return false;
866    // Immediate offset in range [-255, 255].
867    if (!Memory.OffsetImm) return true;
868    int64_t Val = Memory.OffsetImm->getValue();
869    return (Val == INT32_MIN) || (Val > -256 && Val < 256);
870  }
871  bool isMemPosImm8Offset() const {
872    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
873      return false;
874    // Immediate offset in range [0, 255].
875    if (!Memory.OffsetImm) return true;
876    int64_t Val = Memory.OffsetImm->getValue();
877    return Val >= 0 && Val < 256;
878  }
879  bool isMemNegImm8Offset() const {
880    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
881      return false;
882    // Immediate offset in range [-255, -1].
883    if (!Memory.OffsetImm) return true;
884    int64_t Val = Memory.OffsetImm->getValue();
885    return Val > -256 && Val < 0;
886  }
887  bool isMemUImm12Offset() const {
888    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
889      return false;
890    // Immediate offset in range [0, 4095].
891    if (!Memory.OffsetImm) return true;
892    int64_t Val = Memory.OffsetImm->getValue();
893    return (Val >= 0 && Val < 4096);
894  }
895  bool isMemImm12Offset() const {
896    // If we have an immediate that's not a constant, treat it as a label
897    // reference needing a fixup. If it is a constant, it's something else
898    // and we reject it.
899    if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm()))
900      return true;
901
902    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
903      return false;
904    // Immediate offset in range [-4095, 4095].
905    if (!Memory.OffsetImm) return true;
906    int64_t Val = Memory.OffsetImm->getValue();
907    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
908  }
909  bool isPostIdxImm8() const {
910    if (Kind != k_Immediate)
911      return false;
912    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
913    if (!CE) return false;
914    int64_t Val = CE->getValue();
915    return (Val > -256 && Val < 256) || (Val == INT32_MIN);
916  }
917  bool isPostIdxImm8s4() const {
918    if (Kind != k_Immediate)
919      return false;
920    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
921    if (!CE) return false;
922    int64_t Val = CE->getValue();
923    return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
924      (Val == INT32_MIN);
925  }
926
927  bool isMSRMask() const { return Kind == k_MSRMask; }
928  bool isProcIFlags() const { return Kind == k_ProcIFlags; }
929
930  // NEON operands.
931  bool isVecListOneD() const {
932    if (Kind != k_VectorList) return false;
933    return VectorList.Count == 1;
934  }
935
936  bool isVecListTwoD() const {
937    if (Kind != k_VectorList) return false;
938    return VectorList.Count == 2;
939  }
940
941  bool isVecListThreeD() const {
942    if (Kind != k_VectorList) return false;
943    return VectorList.Count == 3;
944  }
945
946  bool isVecListFourD() const {
947    if (Kind != k_VectorList) return false;
948    return VectorList.Count == 4;
949  }
950
951  bool isVecListTwoQ() const {
952    if (Kind != k_VectorList) return false;
953    //FIXME: We haven't taught the parser to handle by-two register lists
954    // yet, so don't pretend to know one.
955    return VectorList.Count == 2 && false;
956  }
957
958  bool isVectorIndex8() const {
959    if (Kind != k_VectorIndex) return false;
960    return VectorIndex.Val < 8;
961  }
962  bool isVectorIndex16() const {
963    if (Kind != k_VectorIndex) return false;
964    return VectorIndex.Val < 4;
965  }
966  bool isVectorIndex32() const {
967    if (Kind != k_VectorIndex) return false;
968    return VectorIndex.Val < 2;
969  }
970
971  bool isNEONi8splat() const {
972    if (Kind != k_Immediate)
973      return false;
974    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
975    // Must be a constant.
976    if (!CE) return false;
977    int64_t Value = CE->getValue();
978    // i8 value splatted across 8 bytes. The immediate is just the 8 byte
979    // value.
980    return Value >= 0 && Value < 256;
981  }
982
983  bool isNEONi16splat() const {
984    if (Kind != k_Immediate)
985      return false;
986    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
987    // Must be a constant.
988    if (!CE) return false;
989    int64_t Value = CE->getValue();
990    // i16 value in the range [0,255] or [0x0100, 0xff00]
991    return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
992  }
993
994  bool isNEONi32splat() const {
995    if (Kind != k_Immediate)
996      return false;
997    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
998    // Must be a constant.
999    if (!CE) return false;
1000    int64_t Value = CE->getValue();
1001    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1002    return (Value >= 0 && Value < 256) ||
1003      (Value >= 0x0100 && Value <= 0xff00) ||
1004      (Value >= 0x010000 && Value <= 0xff0000) ||
1005      (Value >= 0x01000000 && Value <= 0xff000000);
1006  }
1007
1008  bool isNEONi32vmov() const {
1009    if (Kind != k_Immediate)
1010      return false;
1011    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1012    // Must be a constant.
1013    if (!CE) return false;
1014    int64_t Value = CE->getValue();
1015    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1016    // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1017    return (Value >= 0 && Value < 256) ||
1018      (Value >= 0x0100 && Value <= 0xff00) ||
1019      (Value >= 0x010000 && Value <= 0xff0000) ||
1020      (Value >= 0x01000000 && Value <= 0xff000000) ||
1021      (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1022      (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1023  }
1024
1025  bool isNEONi64splat() const {
1026    if (Kind != k_Immediate)
1027      return false;
1028    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1029    // Must be a constant.
1030    if (!CE) return false;
1031    uint64_t Value = CE->getValue();
1032    // i64 value with each byte being either 0 or 0xff.
1033    for (unsigned i = 0; i < 8; ++i)
1034      if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1035    return true;
1036  }
1037
1038  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1039    // Add as immediates when possible.  Null MCExpr = 0.
1040    if (Expr == 0)
1041      Inst.addOperand(MCOperand::CreateImm(0));
1042    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1043      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1044    else
1045      Inst.addOperand(MCOperand::CreateExpr(Expr));
1046  }
1047
1048  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1049    assert(N == 2 && "Invalid number of operands!");
1050    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1051    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1052    Inst.addOperand(MCOperand::CreateReg(RegNum));
1053  }
1054
1055  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1056    assert(N == 1 && "Invalid number of operands!");
1057    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1058  }
1059
1060  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1061    assert(N == 1 && "Invalid number of operands!");
1062    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1063  }
1064
1065  void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1066    assert(N == 1 && "Invalid number of operands!");
1067    Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1068  }
1069
1070  void addITMaskOperands(MCInst &Inst, unsigned N) const {
1071    assert(N == 1 && "Invalid number of operands!");
1072    Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1073  }
1074
1075  void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1076    assert(N == 1 && "Invalid number of operands!");
1077    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1078  }
1079
1080  void addCCOutOperands(MCInst &Inst, unsigned N) const {
1081    assert(N == 1 && "Invalid number of operands!");
1082    Inst.addOperand(MCOperand::CreateReg(getReg()));
1083  }
1084
1085  void addRegOperands(MCInst &Inst, unsigned N) const {
1086    assert(N == 1 && "Invalid number of operands!");
1087    Inst.addOperand(MCOperand::CreateReg(getReg()));
1088  }
1089
1090  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1091    assert(N == 3 && "Invalid number of operands!");
1092    assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
1093    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1094    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1095    Inst.addOperand(MCOperand::CreateImm(
1096      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1097  }
1098
1099  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1100    assert(N == 2 && "Invalid number of operands!");
1101    assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
1102    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1103    Inst.addOperand(MCOperand::CreateImm(
1104      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
1105  }
1106
1107  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1108    assert(N == 1 && "Invalid number of operands!");
1109    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1110                                         ShifterImm.Imm));
1111  }
1112
1113  void addRegListOperands(MCInst &Inst, unsigned N) const {
1114    assert(N == 1 && "Invalid number of operands!");
1115    const SmallVectorImpl<unsigned> &RegList = getRegList();
1116    for (SmallVectorImpl<unsigned>::const_iterator
1117           I = RegList.begin(), E = RegList.end(); I != E; ++I)
1118      Inst.addOperand(MCOperand::CreateReg(*I));
1119  }
1120
1121  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1122    addRegListOperands(Inst, N);
1123  }
1124
1125  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1126    addRegListOperands(Inst, N);
1127  }
1128
1129  void addRotImmOperands(MCInst &Inst, unsigned N) const {
1130    assert(N == 1 && "Invalid number of operands!");
1131    // Encoded as val>>3. The printer handles display as 8, 16, 24.
1132    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1133  }
1134
1135  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1136    assert(N == 1 && "Invalid number of operands!");
1137    // Munge the lsb/width into a bitfield mask.
1138    unsigned lsb = Bitfield.LSB;
1139    unsigned width = Bitfield.Width;
1140    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1141    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1142                      (32 - (lsb + width)));
1143    Inst.addOperand(MCOperand::CreateImm(Mask));
1144  }
1145
1146  void addImmOperands(MCInst &Inst, unsigned N) const {
1147    assert(N == 1 && "Invalid number of operands!");
1148    addExpr(Inst, getImm());
1149  }
1150
1151  void addFPImmOperands(MCInst &Inst, unsigned N) const {
1152    assert(N == 1 && "Invalid number of operands!");
1153    Inst.addOperand(MCOperand::CreateImm(getFPImm()));
1154  }
1155
1156  void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1157    assert(N == 1 && "Invalid number of operands!");
1158    // FIXME: We really want to scale the value here, but the LDRD/STRD
1159    // instruction don't encode operands that way yet.
1160    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1161    Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1162  }
1163
1164  void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1165    assert(N == 1 && "Invalid number of operands!");
1166    // The immediate is scaled by four in the encoding and is stored
1167    // in the MCInst as such. Lop off the low two bits here.
1168    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1169    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1170  }
1171
1172  void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1173    assert(N == 1 && "Invalid number of operands!");
1174    // The immediate is scaled by four in the encoding and is stored
1175    // in the MCInst as such. Lop off the low two bits here.
1176    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1177    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1178  }
1179
1180  void addImm0_255Operands(MCInst &Inst, unsigned N) const {
1181    assert(N == 1 && "Invalid number of operands!");
1182    addExpr(Inst, getImm());
1183  }
1184
1185  void addImm0_7Operands(MCInst &Inst, unsigned N) const {
1186    assert(N == 1 && "Invalid number of operands!");
1187    addExpr(Inst, getImm());
1188  }
1189
1190  void addImm0_15Operands(MCInst &Inst, unsigned N) const {
1191    assert(N == 1 && "Invalid number of operands!");
1192    addExpr(Inst, getImm());
1193  }
1194
1195  void addImm0_31Operands(MCInst &Inst, unsigned N) const {
1196    assert(N == 1 && "Invalid number of operands!");
1197    addExpr(Inst, getImm());
1198  }
1199
1200  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1201    assert(N == 1 && "Invalid number of operands!");
1202    // The constant encodes as the immediate-1, and we store in the instruction
1203    // the bits as encoded, so subtract off one here.
1204    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1205    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1206  }
1207
1208  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1209    assert(N == 1 && "Invalid number of operands!");
1210    // The constant encodes as the immediate-1, and we store in the instruction
1211    // the bits as encoded, so subtract off one here.
1212    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1213    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1214  }
1215
1216  void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
1217    assert(N == 1 && "Invalid number of operands!");
1218    addExpr(Inst, getImm());
1219  }
1220
1221  void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
1222    assert(N == 1 && "Invalid number of operands!");
1223    addExpr(Inst, getImm());
1224  }
1225
1226  void addImm24bitOperands(MCInst &Inst, unsigned N) const {
1227    assert(N == 1 && "Invalid number of operands!");
1228    addExpr(Inst, getImm());
1229  }
1230
1231  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1232    assert(N == 1 && "Invalid number of operands!");
1233    // The constant encodes as the immediate, except for 32, which encodes as
1234    // zero.
1235    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1236    unsigned Imm = CE->getValue();
1237    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1238  }
1239
1240  void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
1241    assert(N == 1 && "Invalid number of operands!");
1242    addExpr(Inst, getImm());
1243  }
1244
1245  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1246    assert(N == 1 && "Invalid number of operands!");
1247    // An ASR value of 32 encodes as 0, so that's how we want to add it to
1248    // the instruction as well.
1249    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1250    int Val = CE->getValue();
1251    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1252  }
1253
1254  void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
1255    assert(N == 1 && "Invalid number of operands!");
1256    addExpr(Inst, getImm());
1257  }
1258
1259  void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
1260    assert(N == 1 && "Invalid number of operands!");
1261    addExpr(Inst, getImm());
1262  }
1263
1264  void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1265    assert(N == 1 && "Invalid number of operands!");
1266    // The operand is actually a t2_so_imm, but we have its bitwise
1267    // negation in the assembly source, so twiddle it here.
1268    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1269    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1270  }
1271
1272  void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1273    assert(N == 1 && "Invalid number of operands!");
1274    // The operand is actually a so_imm, but we have its bitwise
1275    // negation in the assembly source, so twiddle it here.
1276    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1277    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1278  }
1279
1280  void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
1281    assert(N == 1 && "Invalid number of operands!");
1282    addExpr(Inst, getImm());
1283  }
1284
1285  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1286    assert(N == 1 && "Invalid number of operands!");
1287    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1288  }
1289
1290  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1291    assert(N == 1 && "Invalid number of operands!");
1292    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1293  }
1294
1295  void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1296    assert(N == 2 && "Invalid number of operands!");
1297    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1298    Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1299  }
1300
1301  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1302    assert(N == 3 && "Invalid number of operands!");
1303    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1304    if (!Memory.OffsetRegNum) {
1305      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1306      // Special case for #-0
1307      if (Val == INT32_MIN) Val = 0;
1308      if (Val < 0) Val = -Val;
1309      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1310    } else {
1311      // For register offset, we encode the shift type and negation flag
1312      // here.
1313      Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1314                              Memory.ShiftImm, Memory.ShiftType);
1315    }
1316    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1317    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1318    Inst.addOperand(MCOperand::CreateImm(Val));
1319  }
1320
1321  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1322    assert(N == 2 && "Invalid number of operands!");
1323    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1324    assert(CE && "non-constant AM2OffsetImm operand!");
1325    int32_t Val = CE->getValue();
1326    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1327    // Special case for #-0
1328    if (Val == INT32_MIN) Val = 0;
1329    if (Val < 0) Val = -Val;
1330    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1331    Inst.addOperand(MCOperand::CreateReg(0));
1332    Inst.addOperand(MCOperand::CreateImm(Val));
1333  }
1334
1335  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1336    assert(N == 3 && "Invalid number of operands!");
1337    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1338    if (!Memory.OffsetRegNum) {
1339      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1340      // Special case for #-0
1341      if (Val == INT32_MIN) Val = 0;
1342      if (Val < 0) Val = -Val;
1343      Val = ARM_AM::getAM3Opc(AddSub, Val);
1344    } else {
1345      // For register offset, we encode the shift type and negation flag
1346      // here.
1347      Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1348    }
1349    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1350    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1351    Inst.addOperand(MCOperand::CreateImm(Val));
1352  }
1353
1354  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1355    assert(N == 2 && "Invalid number of operands!");
1356    if (Kind == k_PostIndexRegister) {
1357      int32_t Val =
1358        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1359      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1360      Inst.addOperand(MCOperand::CreateImm(Val));
1361      return;
1362    }
1363
1364    // Constant offset.
1365    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1366    int32_t Val = CE->getValue();
1367    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1368    // Special case for #-0
1369    if (Val == INT32_MIN) Val = 0;
1370    if (Val < 0) Val = -Val;
1371    Val = ARM_AM::getAM3Opc(AddSub, Val);
1372    Inst.addOperand(MCOperand::CreateReg(0));
1373    Inst.addOperand(MCOperand::CreateImm(Val));
1374  }
1375
1376  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1377    assert(N == 2 && "Invalid number of operands!");
1378    // The lower two bits are always zero and as such are not encoded.
1379    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1380    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1381    // Special case for #-0
1382    if (Val == INT32_MIN) Val = 0;
1383    if (Val < 0) Val = -Val;
1384    Val = ARM_AM::getAM5Opc(AddSub, Val);
1385    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1386    Inst.addOperand(MCOperand::CreateImm(Val));
1387  }
1388
1389  void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1390    assert(N == 2 && "Invalid number of operands!");
1391    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1392    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1393    Inst.addOperand(MCOperand::CreateImm(Val));
1394  }
1395
1396  void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1397    assert(N == 2 && "Invalid number of operands!");
1398    // The lower two bits are always zero and as such are not encoded.
1399    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1400    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1401    Inst.addOperand(MCOperand::CreateImm(Val));
1402  }
1403
1404  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1405    assert(N == 2 && "Invalid number of operands!");
1406    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1407    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1408    Inst.addOperand(MCOperand::CreateImm(Val));
1409  }
1410
1411  void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1412    addMemImm8OffsetOperands(Inst, N);
1413  }
1414
1415  void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1416    addMemImm8OffsetOperands(Inst, N);
1417  }
1418
1419  void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1420    assert(N == 2 && "Invalid number of operands!");
1421    // If this is an immediate, it's a label reference.
1422    if (Kind == k_Immediate) {
1423      addExpr(Inst, getImm());
1424      Inst.addOperand(MCOperand::CreateImm(0));
1425      return;
1426    }
1427
1428    // Otherwise, it's a normal memory reg+offset.
1429    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1430    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1431    Inst.addOperand(MCOperand::CreateImm(Val));
1432  }
1433
1434  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1435    assert(N == 2 && "Invalid number of operands!");
1436    // If this is an immediate, it's a label reference.
1437    if (Kind == k_Immediate) {
1438      addExpr(Inst, getImm());
1439      Inst.addOperand(MCOperand::CreateImm(0));
1440      return;
1441    }
1442
1443    // Otherwise, it's a normal memory reg+offset.
1444    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1445    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1446    Inst.addOperand(MCOperand::CreateImm(Val));
1447  }
1448
1449  void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1450    assert(N == 2 && "Invalid number of operands!");
1451    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1452    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1453  }
1454
1455  void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1456    assert(N == 2 && "Invalid number of operands!");
1457    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1458    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1459  }
1460
1461  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1462    assert(N == 3 && "Invalid number of operands!");
1463    unsigned Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1464                                     Memory.ShiftImm, Memory.ShiftType);
1465    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1466    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1467    Inst.addOperand(MCOperand::CreateImm(Val));
1468  }
1469
1470  void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1471    assert(N == 3 && "Invalid number of operands!");
1472    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1473    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1474    Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
1475  }
1476
1477  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1478    assert(N == 2 && "Invalid number of operands!");
1479    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1480    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1481  }
1482
1483  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1484    assert(N == 2 && "Invalid number of operands!");
1485    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1486    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1487    Inst.addOperand(MCOperand::CreateImm(Val));
1488  }
1489
1490  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1491    assert(N == 2 && "Invalid number of operands!");
1492    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
1493    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1494    Inst.addOperand(MCOperand::CreateImm(Val));
1495  }
1496
1497  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1498    assert(N == 2 && "Invalid number of operands!");
1499    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
1500    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1501    Inst.addOperand(MCOperand::CreateImm(Val));
1502  }
1503
1504  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1505    assert(N == 2 && "Invalid number of operands!");
1506    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1507    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1508    Inst.addOperand(MCOperand::CreateImm(Val));
1509  }
1510
1511  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1512    assert(N == 1 && "Invalid number of operands!");
1513    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1514    assert(CE && "non-constant post-idx-imm8 operand!");
1515    int Imm = CE->getValue();
1516    bool isAdd = Imm >= 0;
1517    if (Imm == INT32_MIN) Imm = 0;
1518    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1519    Inst.addOperand(MCOperand::CreateImm(Imm));
1520  }
1521
1522  void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
1523    assert(N == 1 && "Invalid number of operands!");
1524    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1525    assert(CE && "non-constant post-idx-imm8s4 operand!");
1526    int Imm = CE->getValue();
1527    bool isAdd = Imm >= 0;
1528    if (Imm == INT32_MIN) Imm = 0;
1529    // Immediate is scaled by 4.
1530    Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
1531    Inst.addOperand(MCOperand::CreateImm(Imm));
1532  }
1533
1534  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1535    assert(N == 2 && "Invalid number of operands!");
1536    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1537    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1538  }
1539
1540  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1541    assert(N == 2 && "Invalid number of operands!");
1542    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1543    // The sign, shift type, and shift amount are encoded in a single operand
1544    // using the AM2 encoding helpers.
1545    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1546    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1547                                     PostIdxReg.ShiftTy);
1548    Inst.addOperand(MCOperand::CreateImm(Imm));
1549  }
1550
1551  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1552    assert(N == 1 && "Invalid number of operands!");
1553    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1554  }
1555
1556  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1557    assert(N == 1 && "Invalid number of operands!");
1558    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1559  }
1560
1561  void addVecListOneDOperands(MCInst &Inst, unsigned N) const {
1562    assert(N == 1 && "Invalid number of operands!");
1563    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1564  }
1565
1566  void addVecListTwoDOperands(MCInst &Inst, unsigned N) const {
1567    assert(N == 1 && "Invalid number of operands!");
1568    // Only the first register actually goes on the instruction. The rest
1569    // are implied by the opcode.
1570    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1571  }
1572
1573  void addVecListThreeDOperands(MCInst &Inst, unsigned N) const {
1574    assert(N == 1 && "Invalid number of operands!");
1575    // Only the first register actually goes on the instruction. The rest
1576    // are implied by the opcode.
1577    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1578  }
1579
1580  void addVecListFourDOperands(MCInst &Inst, unsigned N) const {
1581    assert(N == 1 && "Invalid number of operands!");
1582    // Only the first register actually goes on the instruction. The rest
1583    // are implied by the opcode.
1584    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1585  }
1586
1587  void addVecListTwoQOperands(MCInst &Inst, unsigned N) const {
1588    assert(N == 1 && "Invalid number of operands!");
1589    // Only the first register actually goes on the instruction. The rest
1590    // are implied by the opcode.
1591    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1592  }
1593
1594  void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
1595    assert(N == 1 && "Invalid number of operands!");
1596    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1597  }
1598
1599  void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
1600    assert(N == 1 && "Invalid number of operands!");
1601    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1602  }
1603
1604  void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
1605    assert(N == 1 && "Invalid number of operands!");
1606    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1607  }
1608
1609  void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
1610    assert(N == 1 && "Invalid number of operands!");
1611    // The immediate encodes the type of constant as well as the value.
1612    // Mask in that this is an i8 splat.
1613    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1614    Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
1615  }
1616
1617  void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
1618    assert(N == 1 && "Invalid number of operands!");
1619    // The immediate encodes the type of constant as well as the value.
1620    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1621    unsigned Value = CE->getValue();
1622    if (Value >= 256)
1623      Value = (Value >> 8) | 0xa00;
1624    else
1625      Value |= 0x800;
1626    Inst.addOperand(MCOperand::CreateImm(Value));
1627  }
1628
1629  void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
1630    assert(N == 1 && "Invalid number of operands!");
1631    // The immediate encodes the type of constant as well as the value.
1632    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1633    unsigned Value = CE->getValue();
1634    if (Value >= 256 && Value <= 0xff00)
1635      Value = (Value >> 8) | 0x200;
1636    else if (Value > 0xffff && Value <= 0xff0000)
1637      Value = (Value >> 16) | 0x400;
1638    else if (Value > 0xffffff)
1639      Value = (Value >> 24) | 0x600;
1640    Inst.addOperand(MCOperand::CreateImm(Value));
1641  }
1642
1643  void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
1644    assert(N == 1 && "Invalid number of operands!");
1645    // The immediate encodes the type of constant as well as the value.
1646    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1647    unsigned Value = CE->getValue();
1648    if (Value >= 256 && Value <= 0xffff)
1649      Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
1650    else if (Value > 0xffff && Value <= 0xffffff)
1651      Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
1652    else if (Value > 0xffffff)
1653      Value = (Value >> 24) | 0x600;
1654    Inst.addOperand(MCOperand::CreateImm(Value));
1655  }
1656
1657  void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
1658    assert(N == 1 && "Invalid number of operands!");
1659    // The immediate encodes the type of constant as well as the value.
1660    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1661    uint64_t Value = CE->getValue();
1662    unsigned Imm = 0;
1663    for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
1664      Imm |= (Value & 1) << i;
1665    }
1666    Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
1667  }
1668
1669  virtual void print(raw_ostream &OS) const;
1670
1671  static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
1672    ARMOperand *Op = new ARMOperand(k_ITCondMask);
1673    Op->ITMask.Mask = Mask;
1674    Op->StartLoc = S;
1675    Op->EndLoc = S;
1676    return Op;
1677  }
1678
1679  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1680    ARMOperand *Op = new ARMOperand(k_CondCode);
1681    Op->CC.Val = CC;
1682    Op->StartLoc = S;
1683    Op->EndLoc = S;
1684    return Op;
1685  }
1686
1687  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1688    ARMOperand *Op = new ARMOperand(k_CoprocNum);
1689    Op->Cop.Val = CopVal;
1690    Op->StartLoc = S;
1691    Op->EndLoc = S;
1692    return Op;
1693  }
1694
1695  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1696    ARMOperand *Op = new ARMOperand(k_CoprocReg);
1697    Op->Cop.Val = CopVal;
1698    Op->StartLoc = S;
1699    Op->EndLoc = S;
1700    return Op;
1701  }
1702
1703  static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
1704    ARMOperand *Op = new ARMOperand(k_CoprocOption);
1705    Op->Cop.Val = Val;
1706    Op->StartLoc = S;
1707    Op->EndLoc = E;
1708    return Op;
1709  }
1710
1711  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1712    ARMOperand *Op = new ARMOperand(k_CCOut);
1713    Op->Reg.RegNum = RegNum;
1714    Op->StartLoc = S;
1715    Op->EndLoc = S;
1716    return Op;
1717  }
1718
1719  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1720    ARMOperand *Op = new ARMOperand(k_Token);
1721    Op->Tok.Data = Str.data();
1722    Op->Tok.Length = Str.size();
1723    Op->StartLoc = S;
1724    Op->EndLoc = S;
1725    return Op;
1726  }
1727
1728  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1729    ARMOperand *Op = new ARMOperand(k_Register);
1730    Op->Reg.RegNum = RegNum;
1731    Op->StartLoc = S;
1732    Op->EndLoc = E;
1733    return Op;
1734  }
1735
1736  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1737                                           unsigned SrcReg,
1738                                           unsigned ShiftReg,
1739                                           unsigned ShiftImm,
1740                                           SMLoc S, SMLoc E) {
1741    ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
1742    Op->RegShiftedReg.ShiftTy = ShTy;
1743    Op->RegShiftedReg.SrcReg = SrcReg;
1744    Op->RegShiftedReg.ShiftReg = ShiftReg;
1745    Op->RegShiftedReg.ShiftImm = ShiftImm;
1746    Op->StartLoc = S;
1747    Op->EndLoc = E;
1748    return Op;
1749  }
1750
1751  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1752                                            unsigned SrcReg,
1753                                            unsigned ShiftImm,
1754                                            SMLoc S, SMLoc E) {
1755    ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
1756    Op->RegShiftedImm.ShiftTy = ShTy;
1757    Op->RegShiftedImm.SrcReg = SrcReg;
1758    Op->RegShiftedImm.ShiftImm = ShiftImm;
1759    Op->StartLoc = S;
1760    Op->EndLoc = E;
1761    return Op;
1762  }
1763
1764  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1765                                   SMLoc S, SMLoc E) {
1766    ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
1767    Op->ShifterImm.isASR = isASR;
1768    Op->ShifterImm.Imm = Imm;
1769    Op->StartLoc = S;
1770    Op->EndLoc = E;
1771    return Op;
1772  }
1773
1774  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1775    ARMOperand *Op = new ARMOperand(k_RotateImmediate);
1776    Op->RotImm.Imm = Imm;
1777    Op->StartLoc = S;
1778    Op->EndLoc = E;
1779    return Op;
1780  }
1781
1782  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1783                                    SMLoc S, SMLoc E) {
1784    ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
1785    Op->Bitfield.LSB = LSB;
1786    Op->Bitfield.Width = Width;
1787    Op->StartLoc = S;
1788    Op->EndLoc = E;
1789    return Op;
1790  }
1791
1792  static ARMOperand *
1793  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1794                SMLoc StartLoc, SMLoc EndLoc) {
1795    KindTy Kind = k_RegisterList;
1796
1797    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
1798      Kind = k_DPRRegisterList;
1799    else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
1800             contains(Regs.front().first))
1801      Kind = k_SPRRegisterList;
1802
1803    ARMOperand *Op = new ARMOperand(Kind);
1804    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1805           I = Regs.begin(), E = Regs.end(); I != E; ++I)
1806      Op->Registers.push_back(I->first);
1807    array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1808    Op->StartLoc = StartLoc;
1809    Op->EndLoc = EndLoc;
1810    return Op;
1811  }
1812
1813  static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
1814                                      SMLoc S, SMLoc E) {
1815    ARMOperand *Op = new ARMOperand(k_VectorList);
1816    Op->VectorList.RegNum = RegNum;
1817    Op->VectorList.Count = Count;
1818    Op->StartLoc = S;
1819    Op->EndLoc = E;
1820    return Op;
1821  }
1822
1823  static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
1824                                       MCContext &Ctx) {
1825    ARMOperand *Op = new ARMOperand(k_VectorIndex);
1826    Op->VectorIndex.Val = Idx;
1827    Op->StartLoc = S;
1828    Op->EndLoc = E;
1829    return Op;
1830  }
1831
1832  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1833    ARMOperand *Op = new ARMOperand(k_Immediate);
1834    Op->Imm.Val = Val;
1835    Op->StartLoc = S;
1836    Op->EndLoc = E;
1837    return Op;
1838  }
1839
1840  static ARMOperand *CreateFPImm(unsigned Val, SMLoc S, MCContext &Ctx) {
1841    ARMOperand *Op = new ARMOperand(k_FPImmediate);
1842    Op->FPImm.Val = Val;
1843    Op->StartLoc = S;
1844    Op->EndLoc = S;
1845    return Op;
1846  }
1847
1848  static ARMOperand *CreateMem(unsigned BaseRegNum,
1849                               const MCConstantExpr *OffsetImm,
1850                               unsigned OffsetRegNum,
1851                               ARM_AM::ShiftOpc ShiftType,
1852                               unsigned ShiftImm,
1853                               unsigned Alignment,
1854                               bool isNegative,
1855                               SMLoc S, SMLoc E) {
1856    ARMOperand *Op = new ARMOperand(k_Memory);
1857    Op->Memory.BaseRegNum = BaseRegNum;
1858    Op->Memory.OffsetImm = OffsetImm;
1859    Op->Memory.OffsetRegNum = OffsetRegNum;
1860    Op->Memory.ShiftType = ShiftType;
1861    Op->Memory.ShiftImm = ShiftImm;
1862    Op->Memory.Alignment = Alignment;
1863    Op->Memory.isNegative = isNegative;
1864    Op->StartLoc = S;
1865    Op->EndLoc = E;
1866    return Op;
1867  }
1868
1869  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1870                                      ARM_AM::ShiftOpc ShiftTy,
1871                                      unsigned ShiftImm,
1872                                      SMLoc S, SMLoc E) {
1873    ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
1874    Op->PostIdxReg.RegNum = RegNum;
1875    Op->PostIdxReg.isAdd = isAdd;
1876    Op->PostIdxReg.ShiftTy = ShiftTy;
1877    Op->PostIdxReg.ShiftImm = ShiftImm;
1878    Op->StartLoc = S;
1879    Op->EndLoc = E;
1880    return Op;
1881  }
1882
1883  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1884    ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
1885    Op->MBOpt.Val = Opt;
1886    Op->StartLoc = S;
1887    Op->EndLoc = S;
1888    return Op;
1889  }
1890
1891  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1892    ARMOperand *Op = new ARMOperand(k_ProcIFlags);
1893    Op->IFlags.Val = IFlags;
1894    Op->StartLoc = S;
1895    Op->EndLoc = S;
1896    return Op;
1897  }
1898
1899  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1900    ARMOperand *Op = new ARMOperand(k_MSRMask);
1901    Op->MMask.Val = MMask;
1902    Op->StartLoc = S;
1903    Op->EndLoc = S;
1904    return Op;
1905  }
1906};
1907
1908} // end anonymous namespace.
1909
1910void ARMOperand::print(raw_ostream &OS) const {
1911  switch (Kind) {
1912  case k_FPImmediate:
1913    OS << "<fpimm " << getFPImm() << "(" << ARM_AM::getFPImmFloat(getFPImm())
1914       << ") >";
1915    break;
1916  case k_CondCode:
1917    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1918    break;
1919  case k_CCOut:
1920    OS << "<ccout " << getReg() << ">";
1921    break;
1922  case k_ITCondMask: {
1923    static const char *MaskStr[] = {
1924      "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
1925      "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
1926    };
1927    assert((ITMask.Mask & 0xf) == ITMask.Mask);
1928    OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
1929    break;
1930  }
1931  case k_CoprocNum:
1932    OS << "<coprocessor number: " << getCoproc() << ">";
1933    break;
1934  case k_CoprocReg:
1935    OS << "<coprocessor register: " << getCoproc() << ">";
1936    break;
1937  case k_CoprocOption:
1938    OS << "<coprocessor option: " << CoprocOption.Val << ">";
1939    break;
1940  case k_MSRMask:
1941    OS << "<mask: " << getMSRMask() << ">";
1942    break;
1943  case k_Immediate:
1944    getImm()->print(OS);
1945    break;
1946  case k_MemBarrierOpt:
1947    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1948    break;
1949  case k_Memory:
1950    OS << "<memory "
1951       << " base:" << Memory.BaseRegNum;
1952    OS << ">";
1953    break;
1954  case k_PostIndexRegister:
1955    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1956       << PostIdxReg.RegNum;
1957    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1958      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1959         << PostIdxReg.ShiftImm;
1960    OS << ">";
1961    break;
1962  case k_ProcIFlags: {
1963    OS << "<ARM_PROC::";
1964    unsigned IFlags = getProcIFlags();
1965    for (int i=2; i >= 0; --i)
1966      if (IFlags & (1 << i))
1967        OS << ARM_PROC::IFlagsToString(1 << i);
1968    OS << ">";
1969    break;
1970  }
1971  case k_Register:
1972    OS << "<register " << getReg() << ">";
1973    break;
1974  case k_ShifterImmediate:
1975    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1976       << " #" << ShifterImm.Imm << ">";
1977    break;
1978  case k_ShiftedRegister:
1979    OS << "<so_reg_reg "
1980       << RegShiftedReg.SrcReg
1981       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1982       << ", " << RegShiftedReg.ShiftReg << ", "
1983       << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1984       << ">";
1985    break;
1986  case k_ShiftedImmediate:
1987    OS << "<so_reg_imm "
1988       << RegShiftedImm.SrcReg
1989       << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1990       << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1991       << ">";
1992    break;
1993  case k_RotateImmediate:
1994    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1995    break;
1996  case k_BitfieldDescriptor:
1997    OS << "<bitfield " << "lsb: " << Bitfield.LSB
1998       << ", width: " << Bitfield.Width << ">";
1999    break;
2000  case k_RegisterList:
2001  case k_DPRRegisterList:
2002  case k_SPRRegisterList: {
2003    OS << "<register_list ";
2004
2005    const SmallVectorImpl<unsigned> &RegList = getRegList();
2006    for (SmallVectorImpl<unsigned>::const_iterator
2007           I = RegList.begin(), E = RegList.end(); I != E; ) {
2008      OS << *I;
2009      if (++I < E) OS << ", ";
2010    }
2011
2012    OS << ">";
2013    break;
2014  }
2015  case k_VectorList:
2016    OS << "<vector_list " << VectorList.Count << " * "
2017       << VectorList.RegNum << ">";
2018    break;
2019  case k_Token:
2020    OS << "'" << getToken() << "'";
2021    break;
2022  case k_VectorIndex:
2023    OS << "<vectorindex " << getVectorIndex() << ">";
2024    break;
2025  }
2026}
2027
2028/// @name Auto-generated Match Functions
2029/// {
2030
2031static unsigned MatchRegisterName(StringRef Name);
2032
2033/// }
2034
2035bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2036                                 SMLoc &StartLoc, SMLoc &EndLoc) {
2037  RegNo = tryParseRegister();
2038
2039  return (RegNo == (unsigned)-1);
2040}
2041
2042/// Try to parse a register name.  The token must be an Identifier when called,
2043/// and if it is a register name the token is eaten and the register number is
2044/// returned.  Otherwise return -1.
2045///
2046int ARMAsmParser::tryParseRegister() {
2047  const AsmToken &Tok = Parser.getTok();
2048  if (Tok.isNot(AsmToken::Identifier)) return -1;
2049
2050  // FIXME: Validate register for the current architecture; we have to do
2051  // validation later, so maybe there is no need for this here.
2052  std::string upperCase = Tok.getString().str();
2053  std::string lowerCase = LowercaseString(upperCase);
2054  unsigned RegNum = MatchRegisterName(lowerCase);
2055  if (!RegNum) {
2056    RegNum = StringSwitch<unsigned>(lowerCase)
2057      .Case("r13", ARM::SP)
2058      .Case("r14", ARM::LR)
2059      .Case("r15", ARM::PC)
2060      .Case("ip", ARM::R12)
2061      .Default(0);
2062  }
2063  if (!RegNum) return -1;
2064
2065  Parser.Lex(); // Eat identifier token.
2066
2067  return RegNum;
2068}
2069
2070// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
2071// If a recoverable error occurs, return 1. If an irrecoverable error
2072// occurs, return -1. An irrecoverable error is one where tokens have been
2073// consumed in the process of trying to parse the shifter (i.e., when it is
2074// indeed a shifter operand, but malformed).
2075int ARMAsmParser::tryParseShiftRegister(
2076                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2077  SMLoc S = Parser.getTok().getLoc();
2078  const AsmToken &Tok = Parser.getTok();
2079  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2080
2081  std::string upperCase = Tok.getString().str();
2082  std::string lowerCase = LowercaseString(upperCase);
2083  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2084      .Case("lsl", ARM_AM::lsl)
2085      .Case("lsr", ARM_AM::lsr)
2086      .Case("asr", ARM_AM::asr)
2087      .Case("ror", ARM_AM::ror)
2088      .Case("rrx", ARM_AM::rrx)
2089      .Default(ARM_AM::no_shift);
2090
2091  if (ShiftTy == ARM_AM::no_shift)
2092    return 1;
2093
2094  Parser.Lex(); // Eat the operator.
2095
2096  // The source register for the shift has already been added to the
2097  // operand list, so we need to pop it off and combine it into the shifted
2098  // register operand instead.
2099  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2100  if (!PrevOp->isReg())
2101    return Error(PrevOp->getStartLoc(), "shift must be of a register");
2102  int SrcReg = PrevOp->getReg();
2103  int64_t Imm = 0;
2104  int ShiftReg = 0;
2105  if (ShiftTy == ARM_AM::rrx) {
2106    // RRX Doesn't have an explicit shift amount. The encoder expects
2107    // the shift register to be the same as the source register. Seems odd,
2108    // but OK.
2109    ShiftReg = SrcReg;
2110  } else {
2111    // Figure out if this is shifted by a constant or a register (for non-RRX).
2112    if (Parser.getTok().is(AsmToken::Hash)) {
2113      Parser.Lex(); // Eat hash.
2114      SMLoc ImmLoc = Parser.getTok().getLoc();
2115      const MCExpr *ShiftExpr = 0;
2116      if (getParser().ParseExpression(ShiftExpr)) {
2117        Error(ImmLoc, "invalid immediate shift value");
2118        return -1;
2119      }
2120      // The expression must be evaluatable as an immediate.
2121      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2122      if (!CE) {
2123        Error(ImmLoc, "invalid immediate shift value");
2124        return -1;
2125      }
2126      // Range check the immediate.
2127      // lsl, ror: 0 <= imm <= 31
2128      // lsr, asr: 0 <= imm <= 32
2129      Imm = CE->getValue();
2130      if (Imm < 0 ||
2131          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2132          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2133        Error(ImmLoc, "immediate shift value out of range");
2134        return -1;
2135      }
2136    } else if (Parser.getTok().is(AsmToken::Identifier)) {
2137      ShiftReg = tryParseRegister();
2138      SMLoc L = Parser.getTok().getLoc();
2139      if (ShiftReg == -1) {
2140        Error (L, "expected immediate or register in shift operand");
2141        return -1;
2142      }
2143    } else {
2144      Error (Parser.getTok().getLoc(),
2145                    "expected immediate or register in shift operand");
2146      return -1;
2147    }
2148  }
2149
2150  if (ShiftReg && ShiftTy != ARM_AM::rrx)
2151    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2152                                                         ShiftReg, Imm,
2153                                               S, Parser.getTok().getLoc()));
2154  else
2155    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2156                                               S, Parser.getTok().getLoc()));
2157
2158  return 0;
2159}
2160
2161
2162/// Try to parse a register name.  The token must be an Identifier when called.
2163/// If it's a register, an AsmOperand is created. Another AsmOperand is created
2164/// if there is a "writeback". 'true' if it's not a register.
2165///
2166/// TODO this is likely to change to allow different register types and or to
2167/// parse for a specific register type.
2168bool ARMAsmParser::
2169tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2170  SMLoc S = Parser.getTok().getLoc();
2171  int RegNo = tryParseRegister();
2172  if (RegNo == -1)
2173    return true;
2174
2175  Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
2176
2177  const AsmToken &ExclaimTok = Parser.getTok();
2178  if (ExclaimTok.is(AsmToken::Exclaim)) {
2179    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2180                                               ExclaimTok.getLoc()));
2181    Parser.Lex(); // Eat exclaim token
2182    return false;
2183  }
2184
2185  // Also check for an index operand. This is only legal for vector registers,
2186  // but that'll get caught OK in operand matching, so we don't need to
2187  // explicitly filter everything else out here.
2188  if (Parser.getTok().is(AsmToken::LBrac)) {
2189    SMLoc SIdx = Parser.getTok().getLoc();
2190    Parser.Lex(); // Eat left bracket token.
2191
2192    const MCExpr *ImmVal;
2193    if (getParser().ParseExpression(ImmVal))
2194      return MatchOperand_ParseFail;
2195    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2196    if (!MCE) {
2197      TokError("immediate value expected for vector index");
2198      return MatchOperand_ParseFail;
2199    }
2200
2201    SMLoc E = Parser.getTok().getLoc();
2202    if (Parser.getTok().isNot(AsmToken::RBrac)) {
2203      Error(E, "']' expected");
2204      return MatchOperand_ParseFail;
2205    }
2206
2207    Parser.Lex(); // Eat right bracket token.
2208
2209    Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2210                                                     SIdx, E,
2211                                                     getContext()));
2212  }
2213
2214  return false;
2215}
2216
2217/// MatchCoprocessorOperandName - Try to parse an coprocessor related
2218/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2219/// "c5", ...
2220static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2221  // Use the same layout as the tablegen'erated register name matcher. Ugly,
2222  // but efficient.
2223  switch (Name.size()) {
2224  default: break;
2225  case 2:
2226    if (Name[0] != CoprocOp)
2227      return -1;
2228    switch (Name[1]) {
2229    default:  return -1;
2230    case '0': return 0;
2231    case '1': return 1;
2232    case '2': return 2;
2233    case '3': return 3;
2234    case '4': return 4;
2235    case '5': return 5;
2236    case '6': return 6;
2237    case '7': return 7;
2238    case '8': return 8;
2239    case '9': return 9;
2240    }
2241    break;
2242  case 3:
2243    if (Name[0] != CoprocOp || Name[1] != '1')
2244      return -1;
2245    switch (Name[2]) {
2246    default:  return -1;
2247    case '0': return 10;
2248    case '1': return 11;
2249    case '2': return 12;
2250    case '3': return 13;
2251    case '4': return 14;
2252    case '5': return 15;
2253    }
2254    break;
2255  }
2256
2257  return -1;
2258}
2259
2260/// parseITCondCode - Try to parse a condition code for an IT instruction.
2261ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2262parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2263  SMLoc S = Parser.getTok().getLoc();
2264  const AsmToken &Tok = Parser.getTok();
2265  if (!Tok.is(AsmToken::Identifier))
2266    return MatchOperand_NoMatch;
2267  unsigned CC = StringSwitch<unsigned>(Tok.getString())
2268    .Case("eq", ARMCC::EQ)
2269    .Case("ne", ARMCC::NE)
2270    .Case("hs", ARMCC::HS)
2271    .Case("cs", ARMCC::HS)
2272    .Case("lo", ARMCC::LO)
2273    .Case("cc", ARMCC::LO)
2274    .Case("mi", ARMCC::MI)
2275    .Case("pl", ARMCC::PL)
2276    .Case("vs", ARMCC::VS)
2277    .Case("vc", ARMCC::VC)
2278    .Case("hi", ARMCC::HI)
2279    .Case("ls", ARMCC::LS)
2280    .Case("ge", ARMCC::GE)
2281    .Case("lt", ARMCC::LT)
2282    .Case("gt", ARMCC::GT)
2283    .Case("le", ARMCC::LE)
2284    .Case("al", ARMCC::AL)
2285    .Default(~0U);
2286  if (CC == ~0U)
2287    return MatchOperand_NoMatch;
2288  Parser.Lex(); // Eat the token.
2289
2290  Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2291
2292  return MatchOperand_Success;
2293}
2294
2295/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2296/// token must be an Identifier when called, and if it is a coprocessor
2297/// number, the token is eaten and the operand is added to the operand list.
2298ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2299parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2300  SMLoc S = Parser.getTok().getLoc();
2301  const AsmToken &Tok = Parser.getTok();
2302  if (Tok.isNot(AsmToken::Identifier))
2303    return MatchOperand_NoMatch;
2304
2305  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2306  if (Num == -1)
2307    return MatchOperand_NoMatch;
2308
2309  Parser.Lex(); // Eat identifier token.
2310  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2311  return MatchOperand_Success;
2312}
2313
2314/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2315/// token must be an Identifier when called, and if it is a coprocessor
2316/// number, the token is eaten and the operand is added to the operand list.
2317ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2318parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2319  SMLoc S = Parser.getTok().getLoc();
2320  const AsmToken &Tok = Parser.getTok();
2321  if (Tok.isNot(AsmToken::Identifier))
2322    return MatchOperand_NoMatch;
2323
2324  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2325  if (Reg == -1)
2326    return MatchOperand_NoMatch;
2327
2328  Parser.Lex(); // Eat identifier token.
2329  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2330  return MatchOperand_Success;
2331}
2332
2333/// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2334/// coproc_option : '{' imm0_255 '}'
2335ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2336parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2337  SMLoc S = Parser.getTok().getLoc();
2338
2339  // If this isn't a '{', this isn't a coprocessor immediate operand.
2340  if (Parser.getTok().isNot(AsmToken::LCurly))
2341    return MatchOperand_NoMatch;
2342  Parser.Lex(); // Eat the '{'
2343
2344  const MCExpr *Expr;
2345  SMLoc Loc = Parser.getTok().getLoc();
2346  if (getParser().ParseExpression(Expr)) {
2347    Error(Loc, "illegal expression");
2348    return MatchOperand_ParseFail;
2349  }
2350  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2351  if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2352    Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2353    return MatchOperand_ParseFail;
2354  }
2355  int Val = CE->getValue();
2356
2357  // Check for and consume the closing '}'
2358  if (Parser.getTok().isNot(AsmToken::RCurly))
2359    return MatchOperand_ParseFail;
2360  SMLoc E = Parser.getTok().getLoc();
2361  Parser.Lex(); // Eat the '}'
2362
2363  Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2364  return MatchOperand_Success;
2365}
2366
2367// For register list parsing, we need to map from raw GPR register numbering
2368// to the enumeration values. The enumeration values aren't sorted by
2369// register number due to our using "sp", "lr" and "pc" as canonical names.
2370static unsigned getNextRegister(unsigned Reg) {
2371  // If this is a GPR, we need to do it manually, otherwise we can rely
2372  // on the sort ordering of the enumeration since the other reg-classes
2373  // are sane.
2374  if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2375    return Reg + 1;
2376  switch(Reg) {
2377  default: assert(0 && "Invalid GPR number!");
2378  case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
2379  case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
2380  case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
2381  case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
2382  case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
2383  case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2384  case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
2385  case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
2386  }
2387}
2388
2389/// Parse a register list.
2390bool ARMAsmParser::
2391parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2392  assert(Parser.getTok().is(AsmToken::LCurly) &&
2393         "Token is not a Left Curly Brace");
2394  SMLoc S = Parser.getTok().getLoc();
2395  Parser.Lex(); // Eat '{' token.
2396  SMLoc RegLoc = Parser.getTok().getLoc();
2397
2398  // Check the first register in the list to see what register class
2399  // this is a list of.
2400  int Reg = tryParseRegister();
2401  if (Reg == -1)
2402    return Error(RegLoc, "register expected");
2403
2404  const MCRegisterClass *RC;
2405  if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2406    RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
2407  else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
2408    RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
2409  else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
2410    RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
2411  else
2412    return Error(RegLoc, "invalid register in register list");
2413
2414  // The reglist instructions have at most 16 registers, so reserve
2415  // space for that many.
2416  SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
2417  // Store the first register.
2418  Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2419
2420  // This starts immediately after the first register token in the list,
2421  // so we can see either a comma or a minus (range separator) as a legal
2422  // next token.
2423  while (Parser.getTok().is(AsmToken::Comma) ||
2424         Parser.getTok().is(AsmToken::Minus)) {
2425    if (Parser.getTok().is(AsmToken::Minus)) {
2426      Parser.Lex(); // Eat the comma.
2427      SMLoc EndLoc = Parser.getTok().getLoc();
2428      int EndReg = tryParseRegister();
2429      if (EndReg == -1)
2430        return Error(EndLoc, "register expected");
2431      // If the register is the same as the start reg, there's nothing
2432      // more to do.
2433      if (Reg == EndReg)
2434        continue;
2435      // The register must be in the same register class as the first.
2436      if (!RC->contains(EndReg))
2437        return Error(EndLoc, "invalid register in register list");
2438      // Ranges must go from low to high.
2439      if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg))
2440        return Error(EndLoc, "bad range in register list");
2441
2442      // Add all the registers in the range to the register list.
2443      while (Reg != EndReg) {
2444        Reg = getNextRegister(Reg);
2445        Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2446      }
2447      continue;
2448    }
2449    Parser.Lex(); // Eat the comma.
2450    RegLoc = Parser.getTok().getLoc();
2451    int OldReg = Reg;
2452    Reg = tryParseRegister();
2453    if (Reg == -1)
2454      return Error(RegLoc, "register expected");
2455    // The register must be in the same register class as the first.
2456    if (!RC->contains(Reg))
2457      return Error(RegLoc, "invalid register in register list");
2458    // List must be monotonically increasing.
2459    if (getARMRegisterNumbering(Reg) <= getARMRegisterNumbering(OldReg))
2460      return Error(RegLoc, "register list not in ascending order");
2461    // VFP register lists must also be contiguous.
2462    // It's OK to use the enumeration values directly here rather, as the
2463    // VFP register classes have the enum sorted properly.
2464    if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
2465        Reg != OldReg + 1)
2466      return Error(RegLoc, "non-contiguous register range");
2467    Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2468  }
2469
2470  SMLoc E = Parser.getTok().getLoc();
2471  if (Parser.getTok().isNot(AsmToken::RCurly))
2472    return Error(E, "'}' expected");
2473  Parser.Lex(); // Eat '}' token.
2474
2475  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
2476  return false;
2477}
2478
2479// Return the low-subreg of a given Q register.
2480static unsigned getDRegFromQReg(unsigned QReg) {
2481  switch (QReg) {
2482  default: llvm_unreachable("expected a Q register!");
2483  case ARM::Q0:  return ARM::D0;
2484  case ARM::Q1:  return ARM::D2;
2485  case ARM::Q2:  return ARM::D4;
2486  case ARM::Q3:  return ARM::D6;
2487  case ARM::Q4:  return ARM::D8;
2488  case ARM::Q5:  return ARM::D10;
2489  case ARM::Q6:  return ARM::D12;
2490  case ARM::Q7:  return ARM::D14;
2491  case ARM::Q8:  return ARM::D16;
2492  case ARM::Q9:  return ARM::D19;
2493  case ARM::Q10: return ARM::D20;
2494  case ARM::Q11: return ARM::D22;
2495  case ARM::Q12: return ARM::D24;
2496  case ARM::Q13: return ARM::D26;
2497  case ARM::Q14: return ARM::D28;
2498  case ARM::Q15: return ARM::D30;
2499  }
2500}
2501
2502// parse a vector register list
2503ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2504parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2505  if(Parser.getTok().isNot(AsmToken::LCurly))
2506    return MatchOperand_NoMatch;
2507
2508  SMLoc S = Parser.getTok().getLoc();
2509  Parser.Lex(); // Eat '{' token.
2510  SMLoc RegLoc = Parser.getTok().getLoc();
2511
2512  int Reg = tryParseRegister();
2513  if (Reg == -1) {
2514    Error(RegLoc, "register expected");
2515    return MatchOperand_ParseFail;
2516  }
2517  unsigned Count = 1;
2518  unsigned FirstReg = Reg;
2519  // The list is of D registers, but we also allow Q regs and just interpret
2520  // them as the two D sub-registers.
2521  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2522    FirstReg = Reg = getDRegFromQReg(Reg);
2523    ++Reg;
2524    ++Count;
2525  }
2526
2527  while (Parser.getTok().is(AsmToken::Comma)) {
2528    Parser.Lex(); // Eat the comma.
2529    RegLoc = Parser.getTok().getLoc();
2530    int OldReg = Reg;
2531    Reg = tryParseRegister();
2532    if (Reg == -1) {
2533      Error(RegLoc, "register expected");
2534      return MatchOperand_ParseFail;
2535    }
2536    // vector register lists must be contiguous.
2537    // It's OK to use the enumeration values directly here rather, as the
2538    // VFP register classes have the enum sorted properly.
2539    //
2540    // The list is of D registers, but we also allow Q regs and just interpret
2541    // them as the two D sub-registers.
2542    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2543      Reg = getDRegFromQReg(Reg);
2544      if (Reg != OldReg + 1) {
2545        Error(RegLoc, "non-contiguous register range");
2546        return MatchOperand_ParseFail;
2547      }
2548      ++Reg;
2549      Count += 2;
2550      continue;
2551    }
2552    // Normal D register. Just check that it's contiguous and keep going.
2553    if (Reg != OldReg + 1) {
2554      Error(RegLoc, "non-contiguous register range");
2555      return MatchOperand_ParseFail;
2556    }
2557    ++Count;
2558  }
2559
2560  SMLoc E = Parser.getTok().getLoc();
2561  if (Parser.getTok().isNot(AsmToken::RCurly)) {
2562    Error(E, "'}' expected");
2563    return MatchOperand_ParseFail;
2564  }
2565  Parser.Lex(); // Eat '}' token.
2566
2567  Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, S, E));
2568  return MatchOperand_Success;
2569}
2570
2571/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
2572ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2573parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2574  SMLoc S = Parser.getTok().getLoc();
2575  const AsmToken &Tok = Parser.getTok();
2576  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2577  StringRef OptStr = Tok.getString();
2578
2579  unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
2580    .Case("sy",    ARM_MB::SY)
2581    .Case("st",    ARM_MB::ST)
2582    .Case("sh",    ARM_MB::ISH)
2583    .Case("ish",   ARM_MB::ISH)
2584    .Case("shst",  ARM_MB::ISHST)
2585    .Case("ishst", ARM_MB::ISHST)
2586    .Case("nsh",   ARM_MB::NSH)
2587    .Case("un",    ARM_MB::NSH)
2588    .Case("nshst", ARM_MB::NSHST)
2589    .Case("unst",  ARM_MB::NSHST)
2590    .Case("osh",   ARM_MB::OSH)
2591    .Case("oshst", ARM_MB::OSHST)
2592    .Default(~0U);
2593
2594  if (Opt == ~0U)
2595    return MatchOperand_NoMatch;
2596
2597  Parser.Lex(); // Eat identifier token.
2598  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
2599  return MatchOperand_Success;
2600}
2601
2602/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
2603ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2604parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2605  SMLoc S = Parser.getTok().getLoc();
2606  const AsmToken &Tok = Parser.getTok();
2607  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2608  StringRef IFlagsStr = Tok.getString();
2609
2610  // An iflags string of "none" is interpreted to mean that none of the AIF
2611  // bits are set.  Not a terribly useful instruction, but a valid encoding.
2612  unsigned IFlags = 0;
2613  if (IFlagsStr != "none") {
2614        for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
2615      unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
2616        .Case("a", ARM_PROC::A)
2617        .Case("i", ARM_PROC::I)
2618        .Case("f", ARM_PROC::F)
2619        .Default(~0U);
2620
2621      // If some specific iflag is already set, it means that some letter is
2622      // present more than once, this is not acceptable.
2623      if (Flag == ~0U || (IFlags & Flag))
2624        return MatchOperand_NoMatch;
2625
2626      IFlags |= Flag;
2627    }
2628  }
2629
2630  Parser.Lex(); // Eat identifier token.
2631  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
2632  return MatchOperand_Success;
2633}
2634
2635/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
2636ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2637parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2638  SMLoc S = Parser.getTok().getLoc();
2639  const AsmToken &Tok = Parser.getTok();
2640  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2641  StringRef Mask = Tok.getString();
2642
2643  if (isMClass()) {
2644    // See ARMv6-M 10.1.1
2645    unsigned FlagsVal = StringSwitch<unsigned>(Mask)
2646      .Case("apsr", 0)
2647      .Case("iapsr", 1)
2648      .Case("eapsr", 2)
2649      .Case("xpsr", 3)
2650      .Case("ipsr", 5)
2651      .Case("epsr", 6)
2652      .Case("iepsr", 7)
2653      .Case("msp", 8)
2654      .Case("psp", 9)
2655      .Case("primask", 16)
2656      .Case("basepri", 17)
2657      .Case("basepri_max", 18)
2658      .Case("faultmask", 19)
2659      .Case("control", 20)
2660      .Default(~0U);
2661
2662    if (FlagsVal == ~0U)
2663      return MatchOperand_NoMatch;
2664
2665    if (!hasV7Ops() && FlagsVal >= 17 && FlagsVal <= 19)
2666      // basepri, basepri_max and faultmask only valid for V7m.
2667      return MatchOperand_NoMatch;
2668
2669    Parser.Lex(); // Eat identifier token.
2670    Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
2671    return MatchOperand_Success;
2672  }
2673
2674  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
2675  size_t Start = 0, Next = Mask.find('_');
2676  StringRef Flags = "";
2677  std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
2678  if (Next != StringRef::npos)
2679    Flags = Mask.slice(Next+1, Mask.size());
2680
2681  // FlagsVal contains the complete mask:
2682  // 3-0: Mask
2683  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2684  unsigned FlagsVal = 0;
2685
2686  if (SpecReg == "apsr") {
2687    FlagsVal = StringSwitch<unsigned>(Flags)
2688    .Case("nzcvq",  0x8) // same as CPSR_f
2689    .Case("g",      0x4) // same as CPSR_s
2690    .Case("nzcvqg", 0xc) // same as CPSR_fs
2691    .Default(~0U);
2692
2693    if (FlagsVal == ~0U) {
2694      if (!Flags.empty())
2695        return MatchOperand_NoMatch;
2696      else
2697        FlagsVal = 8; // No flag
2698    }
2699  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
2700    if (Flags == "all") // cpsr_all is an alias for cpsr_fc
2701      Flags = "fc";
2702    for (int i = 0, e = Flags.size(); i != e; ++i) {
2703      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
2704      .Case("c", 1)
2705      .Case("x", 2)
2706      .Case("s", 4)
2707      .Case("f", 8)
2708      .Default(~0U);
2709
2710      // If some specific flag is already set, it means that some letter is
2711      // present more than once, this is not acceptable.
2712      if (FlagsVal == ~0U || (FlagsVal & Flag))
2713        return MatchOperand_NoMatch;
2714      FlagsVal |= Flag;
2715    }
2716  } else // No match for special register.
2717    return MatchOperand_NoMatch;
2718
2719  // Special register without flags is NOT equivalent to "fc" flags.
2720  // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
2721  // two lines would enable gas compatibility at the expense of breaking
2722  // round-tripping.
2723  //
2724  // if (!FlagsVal)
2725  //  FlagsVal = 0x9;
2726
2727  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2728  if (SpecReg == "spsr")
2729    FlagsVal |= 16;
2730
2731  Parser.Lex(); // Eat identifier token.
2732  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
2733  return MatchOperand_Success;
2734}
2735
2736ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2737parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
2738            int Low, int High) {
2739  const AsmToken &Tok = Parser.getTok();
2740  if (Tok.isNot(AsmToken::Identifier)) {
2741    Error(Parser.getTok().getLoc(), Op + " operand expected.");
2742    return MatchOperand_ParseFail;
2743  }
2744  StringRef ShiftName = Tok.getString();
2745  std::string LowerOp = LowercaseString(Op);
2746  std::string UpperOp = UppercaseString(Op);
2747  if (ShiftName != LowerOp && ShiftName != UpperOp) {
2748    Error(Parser.getTok().getLoc(), Op + " operand expected.");
2749    return MatchOperand_ParseFail;
2750  }
2751  Parser.Lex(); // Eat shift type token.
2752
2753  // There must be a '#' and a shift amount.
2754  if (Parser.getTok().isNot(AsmToken::Hash)) {
2755    Error(Parser.getTok().getLoc(), "'#' expected");
2756    return MatchOperand_ParseFail;
2757  }
2758  Parser.Lex(); // Eat hash token.
2759
2760  const MCExpr *ShiftAmount;
2761  SMLoc Loc = Parser.getTok().getLoc();
2762  if (getParser().ParseExpression(ShiftAmount)) {
2763    Error(Loc, "illegal expression");
2764    return MatchOperand_ParseFail;
2765  }
2766  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2767  if (!CE) {
2768    Error(Loc, "constant expression expected");
2769    return MatchOperand_ParseFail;
2770  }
2771  int Val = CE->getValue();
2772  if (Val < Low || Val > High) {
2773    Error(Loc, "immediate value out of range");
2774    return MatchOperand_ParseFail;
2775  }
2776
2777  Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
2778
2779  return MatchOperand_Success;
2780}
2781
2782ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2783parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2784  const AsmToken &Tok = Parser.getTok();
2785  SMLoc S = Tok.getLoc();
2786  if (Tok.isNot(AsmToken::Identifier)) {
2787    Error(Tok.getLoc(), "'be' or 'le' operand expected");
2788    return MatchOperand_ParseFail;
2789  }
2790  int Val = StringSwitch<int>(Tok.getString())
2791    .Case("be", 1)
2792    .Case("le", 0)
2793    .Default(-1);
2794  Parser.Lex(); // Eat the token.
2795
2796  if (Val == -1) {
2797    Error(Tok.getLoc(), "'be' or 'le' operand expected");
2798    return MatchOperand_ParseFail;
2799  }
2800  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
2801                                                                  getContext()),
2802                                           S, Parser.getTok().getLoc()));
2803  return MatchOperand_Success;
2804}
2805
2806/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
2807/// instructions. Legal values are:
2808///     lsl #n  'n' in [0,31]
2809///     asr #n  'n' in [1,32]
2810///             n == 32 encoded as n == 0.
2811ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2812parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2813  const AsmToken &Tok = Parser.getTok();
2814  SMLoc S = Tok.getLoc();
2815  if (Tok.isNot(AsmToken::Identifier)) {
2816    Error(S, "shift operator 'asr' or 'lsl' expected");
2817    return MatchOperand_ParseFail;
2818  }
2819  StringRef ShiftName = Tok.getString();
2820  bool isASR;
2821  if (ShiftName == "lsl" || ShiftName == "LSL")
2822    isASR = false;
2823  else if (ShiftName == "asr" || ShiftName == "ASR")
2824    isASR = true;
2825  else {
2826    Error(S, "shift operator 'asr' or 'lsl' expected");
2827    return MatchOperand_ParseFail;
2828  }
2829  Parser.Lex(); // Eat the operator.
2830
2831  // A '#' and a shift amount.
2832  if (Parser.getTok().isNot(AsmToken::Hash)) {
2833    Error(Parser.getTok().getLoc(), "'#' expected");
2834    return MatchOperand_ParseFail;
2835  }
2836  Parser.Lex(); // Eat hash token.
2837
2838  const MCExpr *ShiftAmount;
2839  SMLoc E = Parser.getTok().getLoc();
2840  if (getParser().ParseExpression(ShiftAmount)) {
2841    Error(E, "malformed shift expression");
2842    return MatchOperand_ParseFail;
2843  }
2844  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2845  if (!CE) {
2846    Error(E, "shift amount must be an immediate");
2847    return MatchOperand_ParseFail;
2848  }
2849
2850  int64_t Val = CE->getValue();
2851  if (isASR) {
2852    // Shift amount must be in [1,32]
2853    if (Val < 1 || Val > 32) {
2854      Error(E, "'asr' shift amount must be in range [1,32]");
2855      return MatchOperand_ParseFail;
2856    }
2857    // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
2858    if (isThumb() && Val == 32) {
2859      Error(E, "'asr #32' shift amount not allowed in Thumb mode");
2860      return MatchOperand_ParseFail;
2861    }
2862    if (Val == 32) Val = 0;
2863  } else {
2864    // Shift amount must be in [1,32]
2865    if (Val < 0 || Val > 31) {
2866      Error(E, "'lsr' shift amount must be in range [0,31]");
2867      return MatchOperand_ParseFail;
2868    }
2869  }
2870
2871  E = Parser.getTok().getLoc();
2872  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
2873
2874  return MatchOperand_Success;
2875}
2876
2877/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
2878/// of instructions. Legal values are:
2879///     ror #n  'n' in {0, 8, 16, 24}
2880ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2881parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2882  const AsmToken &Tok = Parser.getTok();
2883  SMLoc S = Tok.getLoc();
2884  if (Tok.isNot(AsmToken::Identifier))
2885    return MatchOperand_NoMatch;
2886  StringRef ShiftName = Tok.getString();
2887  if (ShiftName != "ror" && ShiftName != "ROR")
2888    return MatchOperand_NoMatch;
2889  Parser.Lex(); // Eat the operator.
2890
2891  // A '#' and a rotate amount.
2892  if (Parser.getTok().isNot(AsmToken::Hash)) {
2893    Error(Parser.getTok().getLoc(), "'#' expected");
2894    return MatchOperand_ParseFail;
2895  }
2896  Parser.Lex(); // Eat hash token.
2897
2898  const MCExpr *ShiftAmount;
2899  SMLoc E = Parser.getTok().getLoc();
2900  if (getParser().ParseExpression(ShiftAmount)) {
2901    Error(E, "malformed rotate expression");
2902    return MatchOperand_ParseFail;
2903  }
2904  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2905  if (!CE) {
2906    Error(E, "rotate amount must be an immediate");
2907    return MatchOperand_ParseFail;
2908  }
2909
2910  int64_t Val = CE->getValue();
2911  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
2912  // normally, zero is represented in asm by omitting the rotate operand
2913  // entirely.
2914  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
2915    Error(E, "'ror' rotate amount must be 8, 16, or 24");
2916    return MatchOperand_ParseFail;
2917  }
2918
2919  E = Parser.getTok().getLoc();
2920  Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
2921
2922  return MatchOperand_Success;
2923}
2924
2925ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2926parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2927  SMLoc S = Parser.getTok().getLoc();
2928  // The bitfield descriptor is really two operands, the LSB and the width.
2929  if (Parser.getTok().isNot(AsmToken::Hash)) {
2930    Error(Parser.getTok().getLoc(), "'#' expected");
2931    return MatchOperand_ParseFail;
2932  }
2933  Parser.Lex(); // Eat hash token.
2934
2935  const MCExpr *LSBExpr;
2936  SMLoc E = Parser.getTok().getLoc();
2937  if (getParser().ParseExpression(LSBExpr)) {
2938    Error(E, "malformed immediate expression");
2939    return MatchOperand_ParseFail;
2940  }
2941  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
2942  if (!CE) {
2943    Error(E, "'lsb' operand must be an immediate");
2944    return MatchOperand_ParseFail;
2945  }
2946
2947  int64_t LSB = CE->getValue();
2948  // The LSB must be in the range [0,31]
2949  if (LSB < 0 || LSB > 31) {
2950    Error(E, "'lsb' operand must be in the range [0,31]");
2951    return MatchOperand_ParseFail;
2952  }
2953  E = Parser.getTok().getLoc();
2954
2955  // Expect another immediate operand.
2956  if (Parser.getTok().isNot(AsmToken::Comma)) {
2957    Error(Parser.getTok().getLoc(), "too few operands");
2958    return MatchOperand_ParseFail;
2959  }
2960  Parser.Lex(); // Eat hash token.
2961  if (Parser.getTok().isNot(AsmToken::Hash)) {
2962    Error(Parser.getTok().getLoc(), "'#' expected");
2963    return MatchOperand_ParseFail;
2964  }
2965  Parser.Lex(); // Eat hash token.
2966
2967  const MCExpr *WidthExpr;
2968  if (getParser().ParseExpression(WidthExpr)) {
2969    Error(E, "malformed immediate expression");
2970    return MatchOperand_ParseFail;
2971  }
2972  CE = dyn_cast<MCConstantExpr>(WidthExpr);
2973  if (!CE) {
2974    Error(E, "'width' operand must be an immediate");
2975    return MatchOperand_ParseFail;
2976  }
2977
2978  int64_t Width = CE->getValue();
2979  // The LSB must be in the range [1,32-lsb]
2980  if (Width < 1 || Width > 32 - LSB) {
2981    Error(E, "'width' operand must be in the range [1,32-lsb]");
2982    return MatchOperand_ParseFail;
2983  }
2984  E = Parser.getTok().getLoc();
2985
2986  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
2987
2988  return MatchOperand_Success;
2989}
2990
2991ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2992parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2993  // Check for a post-index addressing register operand. Specifically:
2994  // postidx_reg := '+' register {, shift}
2995  //              | '-' register {, shift}
2996  //              | register {, shift}
2997
2998  // This method must return MatchOperand_NoMatch without consuming any tokens
2999  // in the case where there is no match, as other alternatives take other
3000  // parse methods.
3001  AsmToken Tok = Parser.getTok();
3002  SMLoc S = Tok.getLoc();
3003  bool haveEaten = false;
3004  bool isAdd = true;
3005  int Reg = -1;
3006  if (Tok.is(AsmToken::Plus)) {
3007    Parser.Lex(); // Eat the '+' token.
3008    haveEaten = true;
3009  } else if (Tok.is(AsmToken::Minus)) {
3010    Parser.Lex(); // Eat the '-' token.
3011    isAdd = false;
3012    haveEaten = true;
3013  }
3014  if (Parser.getTok().is(AsmToken::Identifier))
3015    Reg = tryParseRegister();
3016  if (Reg == -1) {
3017    if (!haveEaten)
3018      return MatchOperand_NoMatch;
3019    Error(Parser.getTok().getLoc(), "register expected");
3020    return MatchOperand_ParseFail;
3021  }
3022  SMLoc E = Parser.getTok().getLoc();
3023
3024  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3025  unsigned ShiftImm = 0;
3026  if (Parser.getTok().is(AsmToken::Comma)) {
3027    Parser.Lex(); // Eat the ','.
3028    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
3029      return MatchOperand_ParseFail;
3030  }
3031
3032  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
3033                                                  ShiftImm, S, E));
3034
3035  return MatchOperand_Success;
3036}
3037
3038ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3039parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3040  // Check for a post-index addressing register operand. Specifically:
3041  // am3offset := '+' register
3042  //              | '-' register
3043  //              | register
3044  //              | # imm
3045  //              | # + imm
3046  //              | # - imm
3047
3048  // This method must return MatchOperand_NoMatch without consuming any tokens
3049  // in the case where there is no match, as other alternatives take other
3050  // parse methods.
3051  AsmToken Tok = Parser.getTok();
3052  SMLoc S = Tok.getLoc();
3053
3054  // Do immediates first, as we always parse those if we have a '#'.
3055  if (Parser.getTok().is(AsmToken::Hash)) {
3056    Parser.Lex(); // Eat the '#'.
3057    // Explicitly look for a '-', as we need to encode negative zero
3058    // differently.
3059    bool isNegative = Parser.getTok().is(AsmToken::Minus);
3060    const MCExpr *Offset;
3061    if (getParser().ParseExpression(Offset))
3062      return MatchOperand_ParseFail;
3063    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3064    if (!CE) {
3065      Error(S, "constant expression expected");
3066      return MatchOperand_ParseFail;
3067    }
3068    SMLoc E = Tok.getLoc();
3069    // Negative zero is encoded as the flag value INT32_MIN.
3070    int32_t Val = CE->getValue();
3071    if (isNegative && Val == 0)
3072      Val = INT32_MIN;
3073
3074    Operands.push_back(
3075      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
3076
3077    return MatchOperand_Success;
3078  }
3079
3080
3081  bool haveEaten = false;
3082  bool isAdd = true;
3083  int Reg = -1;
3084  if (Tok.is(AsmToken::Plus)) {
3085    Parser.Lex(); // Eat the '+' token.
3086    haveEaten = true;
3087  } else if (Tok.is(AsmToken::Minus)) {
3088    Parser.Lex(); // Eat the '-' token.
3089    isAdd = false;
3090    haveEaten = true;
3091  }
3092  if (Parser.getTok().is(AsmToken::Identifier))
3093    Reg = tryParseRegister();
3094  if (Reg == -1) {
3095    if (!haveEaten)
3096      return MatchOperand_NoMatch;
3097    Error(Parser.getTok().getLoc(), "register expected");
3098    return MatchOperand_ParseFail;
3099  }
3100  SMLoc E = Parser.getTok().getLoc();
3101
3102  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
3103                                                  0, S, E));
3104
3105  return MatchOperand_Success;
3106}
3107
3108/// cvtT2LdrdPre - Convert parsed operands to MCInst.
3109/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3110/// when they refer multiple MIOperands inside a single one.
3111bool ARMAsmParser::
3112cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
3113             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3114  // Rt, Rt2
3115  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3116  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3117  // Create a writeback register dummy placeholder.
3118  Inst.addOperand(MCOperand::CreateReg(0));
3119  // addr
3120  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3121  // pred
3122  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3123  return true;
3124}
3125
3126/// cvtT2StrdPre - Convert parsed operands to MCInst.
3127/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3128/// when they refer multiple MIOperands inside a single one.
3129bool ARMAsmParser::
3130cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
3131             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3132  // Create a writeback register dummy placeholder.
3133  Inst.addOperand(MCOperand::CreateReg(0));
3134  // Rt, Rt2
3135  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3136  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3137  // addr
3138  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3139  // pred
3140  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3141  return true;
3142}
3143
3144/// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3145/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3146/// when they refer multiple MIOperands inside a single one.
3147bool ARMAsmParser::
3148cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3149                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3150  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3151
3152  // Create a writeback register dummy placeholder.
3153  Inst.addOperand(MCOperand::CreateImm(0));
3154
3155  ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3156  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3157  return true;
3158}
3159
3160/// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3161/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3162/// when they refer multiple MIOperands inside a single one.
3163bool ARMAsmParser::
3164cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3165                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3166  // Create a writeback register dummy placeholder.
3167  Inst.addOperand(MCOperand::CreateImm(0));
3168  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3169  ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3170  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3171  return true;
3172}
3173
3174/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3175/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3176/// when they refer multiple MIOperands inside a single one.
3177bool ARMAsmParser::
3178cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3179                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3180  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3181
3182  // Create a writeback register dummy placeholder.
3183  Inst.addOperand(MCOperand::CreateImm(0));
3184
3185  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3186  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3187  return true;
3188}
3189
3190/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3191/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3192/// when they refer multiple MIOperands inside a single one.
3193bool ARMAsmParser::
3194cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3195                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3196  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3197
3198  // Create a writeback register dummy placeholder.
3199  Inst.addOperand(MCOperand::CreateImm(0));
3200
3201  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3202  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3203  return true;
3204}
3205
3206
3207/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3208/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3209/// when they refer multiple MIOperands inside a single one.
3210bool ARMAsmParser::
3211cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3212                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3213  // Create a writeback register dummy placeholder.
3214  Inst.addOperand(MCOperand::CreateImm(0));
3215  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3216  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3217  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3218  return true;
3219}
3220
3221/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3222/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3223/// when they refer multiple MIOperands inside a single one.
3224bool ARMAsmParser::
3225cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3226                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3227  // Create a writeback register dummy placeholder.
3228  Inst.addOperand(MCOperand::CreateImm(0));
3229  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3230  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3231  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3232  return true;
3233}
3234
3235/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3236/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3237/// when they refer multiple MIOperands inside a single one.
3238bool ARMAsmParser::
3239cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3240                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3241  // Create a writeback register dummy placeholder.
3242  Inst.addOperand(MCOperand::CreateImm(0));
3243  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3244  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
3245  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3246  return true;
3247}
3248
3249/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
3250/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3251/// when they refer multiple MIOperands inside a single one.
3252bool ARMAsmParser::
3253cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3254                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3255  // Rt
3256  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3257  // Create a writeback register dummy placeholder.
3258  Inst.addOperand(MCOperand::CreateImm(0));
3259  // addr
3260  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3261  // offset
3262  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3263  // pred
3264  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3265  return true;
3266}
3267
3268/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
3269/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3270/// when they refer multiple MIOperands inside a single one.
3271bool ARMAsmParser::
3272cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3273                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3274  // Rt
3275  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3276  // Create a writeback register dummy placeholder.
3277  Inst.addOperand(MCOperand::CreateImm(0));
3278  // addr
3279  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3280  // offset
3281  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3282  // pred
3283  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3284  return true;
3285}
3286
3287/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
3288/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3289/// when they refer multiple MIOperands inside a single one.
3290bool ARMAsmParser::
3291cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3292                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3293  // Create a writeback register dummy placeholder.
3294  Inst.addOperand(MCOperand::CreateImm(0));
3295  // Rt
3296  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3297  // addr
3298  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3299  // offset
3300  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3301  // pred
3302  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3303  return true;
3304}
3305
3306/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
3307/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3308/// when they refer multiple MIOperands inside a single one.
3309bool ARMAsmParser::
3310cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3311                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3312  // Create a writeback register dummy placeholder.
3313  Inst.addOperand(MCOperand::CreateImm(0));
3314  // Rt
3315  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3316  // addr
3317  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3318  // offset
3319  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3320  // pred
3321  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3322  return true;
3323}
3324
3325/// cvtLdrdPre - Convert parsed operands to MCInst.
3326/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3327/// when they refer multiple MIOperands inside a single one.
3328bool ARMAsmParser::
3329cvtLdrdPre(MCInst &Inst, unsigned Opcode,
3330           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3331  // Rt, Rt2
3332  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3333  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3334  // Create a writeback register dummy placeholder.
3335  Inst.addOperand(MCOperand::CreateImm(0));
3336  // addr
3337  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
3338  // pred
3339  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3340  return true;
3341}
3342
3343/// cvtStrdPre - Convert parsed operands to MCInst.
3344/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3345/// when they refer multiple MIOperands inside a single one.
3346bool ARMAsmParser::
3347cvtStrdPre(MCInst &Inst, unsigned Opcode,
3348           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3349  // Create a writeback register dummy placeholder.
3350  Inst.addOperand(MCOperand::CreateImm(0));
3351  // Rt, Rt2
3352  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3353  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3354  // addr
3355  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
3356  // pred
3357  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3358  return true;
3359}
3360
3361/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3362/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3363/// when they refer multiple MIOperands inside a single one.
3364bool ARMAsmParser::
3365cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3366                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3367  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3368  // Create a writeback register dummy placeholder.
3369  Inst.addOperand(MCOperand::CreateImm(0));
3370  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
3371  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3372  return true;
3373}
3374
3375/// cvtThumbMultiple- Convert parsed operands to MCInst.
3376/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3377/// when they refer multiple MIOperands inside a single one.
3378bool ARMAsmParser::
3379cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
3380           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3381  // The second source operand must be the same register as the destination
3382  // operand.
3383  if (Operands.size() == 6 &&
3384      (((ARMOperand*)Operands[3])->getReg() !=
3385       ((ARMOperand*)Operands[5])->getReg()) &&
3386      (((ARMOperand*)Operands[3])->getReg() !=
3387       ((ARMOperand*)Operands[4])->getReg())) {
3388    Error(Operands[3]->getStartLoc(),
3389          "destination register must match source register");
3390    return false;
3391  }
3392  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3393  ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
3394  ((ARMOperand*)Operands[4])->addRegOperands(Inst, 1);
3395  // If we have a three-operand form, use that, else the second source operand
3396  // is just the destination operand again.
3397  if (Operands.size() == 6)
3398    ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
3399  else
3400    Inst.addOperand(Inst.getOperand(0));
3401  ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
3402
3403  return true;
3404}
3405
3406bool ARMAsmParser::
3407cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
3408              const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3409  // Vd
3410  ((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
3411  // Create a writeback register dummy placeholder.
3412  Inst.addOperand(MCOperand::CreateImm(0));
3413  // Vn
3414  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3415  // pred
3416  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3417  return true;
3418}
3419
3420bool ARMAsmParser::
3421cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
3422                 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3423  // Vd
3424  ((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
3425  // Create a writeback register dummy placeholder.
3426  Inst.addOperand(MCOperand::CreateImm(0));
3427  // Vn
3428  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3429  // Vm
3430  ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
3431  // pred
3432  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3433  return true;
3434}
3435
3436bool ARMAsmParser::
3437cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
3438              const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3439  // Create a writeback register dummy placeholder.
3440  Inst.addOperand(MCOperand::CreateImm(0));
3441  // Vn
3442  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3443  // Vt
3444  ((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
3445  // pred
3446  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3447  return true;
3448}
3449
3450bool ARMAsmParser::
3451cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
3452                 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3453  // Create a writeback register dummy placeholder.
3454  Inst.addOperand(MCOperand::CreateImm(0));
3455  // Vn
3456  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3457  // Vm
3458  ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
3459  // Vt
3460  ((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1);
3461  // pred
3462  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3463  return true;
3464}
3465
3466/// Parse an ARM memory expression, return false if successful else return true
3467/// or an error.  The first token must be a '[' when called.
3468bool ARMAsmParser::
3469parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3470  SMLoc S, E;
3471  assert(Parser.getTok().is(AsmToken::LBrac) &&
3472         "Token is not a Left Bracket");
3473  S = Parser.getTok().getLoc();
3474  Parser.Lex(); // Eat left bracket token.
3475
3476  const AsmToken &BaseRegTok = Parser.getTok();
3477  int BaseRegNum = tryParseRegister();
3478  if (BaseRegNum == -1)
3479    return Error(BaseRegTok.getLoc(), "register expected");
3480
3481  // The next token must either be a comma or a closing bracket.
3482  const AsmToken &Tok = Parser.getTok();
3483  if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
3484    return Error(Tok.getLoc(), "malformed memory operand");
3485
3486  if (Tok.is(AsmToken::RBrac)) {
3487    E = Tok.getLoc();
3488    Parser.Lex(); // Eat right bracket token.
3489
3490    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
3491                                             0, 0, false, S, E));
3492
3493    // If there's a pre-indexing writeback marker, '!', just add it as a token
3494    // operand. It's rather odd, but syntactically valid.
3495    if (Parser.getTok().is(AsmToken::Exclaim)) {
3496      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3497      Parser.Lex(); // Eat the '!'.
3498    }
3499
3500    return false;
3501  }
3502
3503  assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
3504  Parser.Lex(); // Eat the comma.
3505
3506  // If we have a ':', it's an alignment specifier.
3507  if (Parser.getTok().is(AsmToken::Colon)) {
3508    Parser.Lex(); // Eat the ':'.
3509    E = Parser.getTok().getLoc();
3510
3511    const MCExpr *Expr;
3512    if (getParser().ParseExpression(Expr))
3513     return true;
3514
3515    // The expression has to be a constant. Memory references with relocations
3516    // don't come through here, as they use the <label> forms of the relevant
3517    // instructions.
3518    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3519    if (!CE)
3520      return Error (E, "constant expression expected");
3521
3522    unsigned Align = 0;
3523    switch (CE->getValue()) {
3524    default:
3525      return Error(E, "alignment specifier must be 64, 128, or 256 bits");
3526    case 64:  Align = 8; break;
3527    case 128: Align = 16; break;
3528    case 256: Align = 32; break;
3529    }
3530
3531    // Now we should have the closing ']'
3532    E = Parser.getTok().getLoc();
3533    if (Parser.getTok().isNot(AsmToken::RBrac))
3534      return Error(E, "']' expected");
3535    Parser.Lex(); // Eat right bracket token.
3536
3537    // Don't worry about range checking the value here. That's handled by
3538    // the is*() predicates.
3539    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
3540                                             ARM_AM::no_shift, 0, Align,
3541                                             false, S, E));
3542
3543    // If there's a pre-indexing writeback marker, '!', just add it as a token
3544    // operand.
3545    if (Parser.getTok().is(AsmToken::Exclaim)) {
3546      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3547      Parser.Lex(); // Eat the '!'.
3548    }
3549
3550    return false;
3551  }
3552
3553  // If we have a '#', it's an immediate offset, else assume it's a register
3554  // offset.
3555  if (Parser.getTok().is(AsmToken::Hash)) {
3556    Parser.Lex(); // Eat the '#'.
3557    E = Parser.getTok().getLoc();
3558
3559    bool isNegative = getParser().getTok().is(AsmToken::Minus);
3560    const MCExpr *Offset;
3561    if (getParser().ParseExpression(Offset))
3562     return true;
3563
3564    // The expression has to be a constant. Memory references with relocations
3565    // don't come through here, as they use the <label> forms of the relevant
3566    // instructions.
3567    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3568    if (!CE)
3569      return Error (E, "constant expression expected");
3570
3571    // If the constant was #-0, represent it as INT32_MIN.
3572    int32_t Val = CE->getValue();
3573    if (isNegative && Val == 0)
3574      CE = MCConstantExpr::Create(INT32_MIN, getContext());
3575
3576    // Now we should have the closing ']'
3577    E = Parser.getTok().getLoc();
3578    if (Parser.getTok().isNot(AsmToken::RBrac))
3579      return Error(E, "']' expected");
3580    Parser.Lex(); // Eat right bracket token.
3581
3582    // Don't worry about range checking the value here. That's handled by
3583    // the is*() predicates.
3584    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
3585                                             ARM_AM::no_shift, 0, 0,
3586                                             false, S, E));
3587
3588    // If there's a pre-indexing writeback marker, '!', just add it as a token
3589    // operand.
3590    if (Parser.getTok().is(AsmToken::Exclaim)) {
3591      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3592      Parser.Lex(); // Eat the '!'.
3593    }
3594
3595    return false;
3596  }
3597
3598  // The register offset is optionally preceded by a '+' or '-'
3599  bool isNegative = false;
3600  if (Parser.getTok().is(AsmToken::Minus)) {
3601    isNegative = true;
3602    Parser.Lex(); // Eat the '-'.
3603  } else if (Parser.getTok().is(AsmToken::Plus)) {
3604    // Nothing to do.
3605    Parser.Lex(); // Eat the '+'.
3606  }
3607
3608  E = Parser.getTok().getLoc();
3609  int OffsetRegNum = tryParseRegister();
3610  if (OffsetRegNum == -1)
3611    return Error(E, "register expected");
3612
3613  // If there's a shift operator, handle it.
3614  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
3615  unsigned ShiftImm = 0;
3616  if (Parser.getTok().is(AsmToken::Comma)) {
3617    Parser.Lex(); // Eat the ','.
3618    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
3619      return true;
3620  }
3621
3622  // Now we should have the closing ']'
3623  E = Parser.getTok().getLoc();
3624  if (Parser.getTok().isNot(AsmToken::RBrac))
3625    return Error(E, "']' expected");
3626  Parser.Lex(); // Eat right bracket token.
3627
3628  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
3629                                           ShiftType, ShiftImm, 0, isNegative,
3630                                           S, E));
3631
3632  // If there's a pre-indexing writeback marker, '!', just add it as a token
3633  // operand.
3634  if (Parser.getTok().is(AsmToken::Exclaim)) {
3635    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3636    Parser.Lex(); // Eat the '!'.
3637  }
3638
3639  return false;
3640}
3641
3642/// parseMemRegOffsetShift - one of these two:
3643///   ( lsl | lsr | asr | ror ) , # shift_amount
3644///   rrx
3645/// return true if it parses a shift otherwise it returns false.
3646bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
3647                                          unsigned &Amount) {
3648  SMLoc Loc = Parser.getTok().getLoc();
3649  const AsmToken &Tok = Parser.getTok();
3650  if (Tok.isNot(AsmToken::Identifier))
3651    return true;
3652  StringRef ShiftName = Tok.getString();
3653  if (ShiftName == "lsl" || ShiftName == "LSL")
3654    St = ARM_AM::lsl;
3655  else if (ShiftName == "lsr" || ShiftName == "LSR")
3656    St = ARM_AM::lsr;
3657  else if (ShiftName == "asr" || ShiftName == "ASR")
3658    St = ARM_AM::asr;
3659  else if (ShiftName == "ror" || ShiftName == "ROR")
3660    St = ARM_AM::ror;
3661  else if (ShiftName == "rrx" || ShiftName == "RRX")
3662    St = ARM_AM::rrx;
3663  else
3664    return Error(Loc, "illegal shift operator");
3665  Parser.Lex(); // Eat shift type token.
3666
3667  // rrx stands alone.
3668  Amount = 0;
3669  if (St != ARM_AM::rrx) {
3670    Loc = Parser.getTok().getLoc();
3671    // A '#' and a shift amount.
3672    const AsmToken &HashTok = Parser.getTok();
3673    if (HashTok.isNot(AsmToken::Hash))
3674      return Error(HashTok.getLoc(), "'#' expected");
3675    Parser.Lex(); // Eat hash token.
3676
3677    const MCExpr *Expr;
3678    if (getParser().ParseExpression(Expr))
3679      return true;
3680    // Range check the immediate.
3681    // lsl, ror: 0 <= imm <= 31
3682    // lsr, asr: 0 <= imm <= 32
3683    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3684    if (!CE)
3685      return Error(Loc, "shift amount must be an immediate");
3686    int64_t Imm = CE->getValue();
3687    if (Imm < 0 ||
3688        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
3689        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
3690      return Error(Loc, "immediate shift value out of range");
3691    Amount = Imm;
3692  }
3693
3694  return false;
3695}
3696
3697/// parseFPImm - A floating point immediate expression operand.
3698ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3699parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3700  SMLoc S = Parser.getTok().getLoc();
3701
3702  if (Parser.getTok().isNot(AsmToken::Hash))
3703    return MatchOperand_NoMatch;
3704
3705  // Disambiguate the VMOV forms that can accept an FP immediate.
3706  // vmov.f32 <sreg>, #imm
3707  // vmov.f64 <dreg>, #imm
3708  // vmov.f32 <dreg>, #imm  @ vector f32x2
3709  // vmov.f32 <qreg>, #imm  @ vector f32x4
3710  //
3711  // There are also the NEON VMOV instructions which expect an
3712  // integer constant. Make sure we don't try to parse an FPImm
3713  // for these:
3714  // vmov.i{8|16|32|64} <dreg|qreg>, #imm
3715  ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
3716  if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
3717                           TyOp->getToken() != ".f64"))
3718    return MatchOperand_NoMatch;
3719
3720  Parser.Lex(); // Eat the '#'.
3721
3722  // Handle negation, as that still comes through as a separate token.
3723  bool isNegative = false;
3724  if (Parser.getTok().is(AsmToken::Minus)) {
3725    isNegative = true;
3726    Parser.Lex();
3727  }
3728  const AsmToken &Tok = Parser.getTok();
3729  if (Tok.is(AsmToken::Real)) {
3730    APFloat RealVal(APFloat::IEEEdouble, Tok.getString());
3731    uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
3732    // If we had a '-' in front, toggle the sign bit.
3733    IntVal ^= (uint64_t)isNegative << 63;
3734    int Val = ARM_AM::getFP64Imm(APInt(64, IntVal));
3735    Parser.Lex(); // Eat the token.
3736    if (Val == -1) {
3737      TokError("floating point value out of range");
3738      return MatchOperand_ParseFail;
3739    }
3740    Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext()));
3741    return MatchOperand_Success;
3742  }
3743  if (Tok.is(AsmToken::Integer)) {
3744    int64_t Val = Tok.getIntVal();
3745    Parser.Lex(); // Eat the token.
3746    if (Val > 255 || Val < 0) {
3747      TokError("encoded floating point value out of range");
3748      return MatchOperand_ParseFail;
3749    }
3750    Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext()));
3751    return MatchOperand_Success;
3752  }
3753
3754  TokError("invalid floating point immediate");
3755  return MatchOperand_ParseFail;
3756}
3757/// Parse a arm instruction operand.  For now this parses the operand regardless
3758/// of the mnemonic.
3759bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3760                                StringRef Mnemonic) {
3761  SMLoc S, E;
3762
3763  // Check if the current operand has a custom associated parser, if so, try to
3764  // custom parse the operand, or fallback to the general approach.
3765  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
3766  if (ResTy == MatchOperand_Success)
3767    return false;
3768  // If there wasn't a custom match, try the generic matcher below. Otherwise,
3769  // there was a match, but an error occurred, in which case, just return that
3770  // the operand parsing failed.
3771  if (ResTy == MatchOperand_ParseFail)
3772    return true;
3773
3774  switch (getLexer().getKind()) {
3775  default:
3776    Error(Parser.getTok().getLoc(), "unexpected token in operand");
3777    return true;
3778  case AsmToken::Identifier: {
3779    // If this is VMRS, check for the apsr_nzcv operand.
3780    if (!tryParseRegisterWithWriteBack(Operands))
3781      return false;
3782    int Res = tryParseShiftRegister(Operands);
3783    if (Res == 0) // success
3784      return false;
3785    else if (Res == -1) // irrecoverable error
3786      return true;
3787    if (Mnemonic == "vmrs" && Parser.getTok().getString() == "apsr_nzcv") {
3788      S = Parser.getTok().getLoc();
3789      Parser.Lex();
3790      Operands.push_back(ARMOperand::CreateToken("apsr_nzcv", S));
3791      return false;
3792    }
3793
3794    // Fall though for the Identifier case that is not a register or a
3795    // special name.
3796  }
3797  case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
3798  case AsmToken::Integer: // things like 1f and 2b as a branch targets
3799  case AsmToken::Dot: {   // . as a branch target
3800    // This was not a register so parse other operands that start with an
3801    // identifier (like labels) as expressions and create them as immediates.
3802    const MCExpr *IdVal;
3803    S = Parser.getTok().getLoc();
3804    if (getParser().ParseExpression(IdVal))
3805      return true;
3806    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3807    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
3808    return false;
3809  }
3810  case AsmToken::LBrac:
3811    return parseMemory(Operands);
3812  case AsmToken::LCurly:
3813    return parseRegisterList(Operands);
3814  case AsmToken::Hash: {
3815    // #42 -> immediate.
3816    // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
3817    S = Parser.getTok().getLoc();
3818    Parser.Lex();
3819    bool isNegative = Parser.getTok().is(AsmToken::Minus);
3820    const MCExpr *ImmVal;
3821    if (getParser().ParseExpression(ImmVal))
3822      return true;
3823    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
3824    if (!CE) {
3825      Error(S, "constant expression expected");
3826      return MatchOperand_ParseFail;
3827    }
3828    int32_t Val = CE->getValue();
3829    if (isNegative && Val == 0)
3830      ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
3831    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3832    Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
3833    return false;
3834  }
3835  case AsmToken::Colon: {
3836    // ":lower16:" and ":upper16:" expression prefixes
3837    // FIXME: Check it's an expression prefix,
3838    // e.g. (FOO - :lower16:BAR) isn't legal.
3839    ARMMCExpr::VariantKind RefKind;
3840    if (parsePrefix(RefKind))
3841      return true;
3842
3843    const MCExpr *SubExprVal;
3844    if (getParser().ParseExpression(SubExprVal))
3845      return true;
3846
3847    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
3848                                                   getContext());
3849    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3850    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
3851    return false;
3852  }
3853  }
3854}
3855
3856// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
3857//  :lower16: and :upper16:.
3858bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
3859  RefKind = ARMMCExpr::VK_ARM_None;
3860
3861  // :lower16: and :upper16: modifiers
3862  assert(getLexer().is(AsmToken::Colon) && "expected a :");
3863  Parser.Lex(); // Eat ':'
3864
3865  if (getLexer().isNot(AsmToken::Identifier)) {
3866    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
3867    return true;
3868  }
3869
3870  StringRef IDVal = Parser.getTok().getIdentifier();
3871  if (IDVal == "lower16") {
3872    RefKind = ARMMCExpr::VK_ARM_LO16;
3873  } else if (IDVal == "upper16") {
3874    RefKind = ARMMCExpr::VK_ARM_HI16;
3875  } else {
3876    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
3877    return true;
3878  }
3879  Parser.Lex();
3880
3881  if (getLexer().isNot(AsmToken::Colon)) {
3882    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
3883    return true;
3884  }
3885  Parser.Lex(); // Eat the last ':'
3886  return false;
3887}
3888
3889/// \brief Given a mnemonic, split out possible predication code and carry
3890/// setting letters to form a canonical mnemonic and flags.
3891//
3892// FIXME: Would be nice to autogen this.
3893// FIXME: This is a bit of a maze of special cases.
3894StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
3895                                      unsigned &PredicationCode,
3896                                      bool &CarrySetting,
3897                                      unsigned &ProcessorIMod,
3898                                      StringRef &ITMask) {
3899  PredicationCode = ARMCC::AL;
3900  CarrySetting = false;
3901  ProcessorIMod = 0;
3902
3903  // Ignore some mnemonics we know aren't predicated forms.
3904  //
3905  // FIXME: Would be nice to autogen this.
3906  if ((Mnemonic == "movs" && isThumb()) ||
3907      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
3908      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
3909      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
3910      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
3911      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
3912      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
3913      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
3914    return Mnemonic;
3915
3916  // First, split out any predication code. Ignore mnemonics we know aren't
3917  // predicated but do have a carry-set and so weren't caught above.
3918  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
3919      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
3920      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
3921      Mnemonic != "sbcs" && Mnemonic != "rscs") {
3922    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
3923      .Case("eq", ARMCC::EQ)
3924      .Case("ne", ARMCC::NE)
3925      .Case("hs", ARMCC::HS)
3926      .Case("cs", ARMCC::HS)
3927      .Case("lo", ARMCC::LO)
3928      .Case("cc", ARMCC::LO)
3929      .Case("mi", ARMCC::MI)
3930      .Case("pl", ARMCC::PL)
3931      .Case("vs", ARMCC::VS)
3932      .Case("vc", ARMCC::VC)
3933      .Case("hi", ARMCC::HI)
3934      .Case("ls", ARMCC::LS)
3935      .Case("ge", ARMCC::GE)
3936      .Case("lt", ARMCC::LT)
3937      .Case("gt", ARMCC::GT)
3938      .Case("le", ARMCC::LE)
3939      .Case("al", ARMCC::AL)
3940      .Default(~0U);
3941    if (CC != ~0U) {
3942      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
3943      PredicationCode = CC;
3944    }
3945  }
3946
3947  // Next, determine if we have a carry setting bit. We explicitly ignore all
3948  // the instructions we know end in 's'.
3949  if (Mnemonic.endswith("s") &&
3950      !(Mnemonic == "cps" || Mnemonic == "mls" ||
3951        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
3952        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
3953        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
3954        Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
3955        (Mnemonic == "movs" && isThumb()))) {
3956    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
3957    CarrySetting = true;
3958  }
3959
3960  // The "cps" instruction can have a interrupt mode operand which is glued into
3961  // the mnemonic. Check if this is the case, split it and parse the imod op
3962  if (Mnemonic.startswith("cps")) {
3963    // Split out any imod code.
3964    unsigned IMod =
3965      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
3966      .Case("ie", ARM_PROC::IE)
3967      .Case("id", ARM_PROC::ID)
3968      .Default(~0U);
3969    if (IMod != ~0U) {
3970      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
3971      ProcessorIMod = IMod;
3972    }
3973  }
3974
3975  // The "it" instruction has the condition mask on the end of the mnemonic.
3976  if (Mnemonic.startswith("it")) {
3977    ITMask = Mnemonic.slice(2, Mnemonic.size());
3978    Mnemonic = Mnemonic.slice(0, 2);
3979  }
3980
3981  return Mnemonic;
3982}
3983
3984/// \brief Given a canonical mnemonic, determine if the instruction ever allows
3985/// inclusion of carry set or predication code operands.
3986//
3987// FIXME: It would be nice to autogen this.
3988void ARMAsmParser::
3989getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
3990                      bool &CanAcceptPredicationCode) {
3991  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
3992      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
3993      Mnemonic == "add" || Mnemonic == "adc" ||
3994      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
3995      Mnemonic == "orr" || Mnemonic == "mvn" ||
3996      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
3997      Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
3998      (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
3999                      Mnemonic == "mla" || Mnemonic == "smlal" ||
4000                      Mnemonic == "umlal" || Mnemonic == "umull"))) {
4001    CanAcceptCarrySet = true;
4002  } else
4003    CanAcceptCarrySet = false;
4004
4005  if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
4006      Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
4007      Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
4008      Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
4009      Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
4010      (Mnemonic == "clrex" && !isThumb()) ||
4011      (Mnemonic == "nop" && isThumbOne()) ||
4012      ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
4013        Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||
4014        Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) ||
4015      ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
4016       !isThumb()) ||
4017      Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
4018    CanAcceptPredicationCode = false;
4019  } else
4020    CanAcceptPredicationCode = true;
4021
4022  if (isThumb()) {
4023    if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
4024        Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
4025      CanAcceptPredicationCode = false;
4026  }
4027}
4028
4029bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4030                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4031  // FIXME: This is all horribly hacky. We really need a better way to deal
4032  // with optional operands like this in the matcher table.
4033
4034  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4035  // another does not. Specifically, the MOVW instruction does not. So we
4036  // special case it here and remove the defaulted (non-setting) cc_out
4037  // operand if that's the instruction we're trying to match.
4038  //
4039  // We do this as post-processing of the explicit operands rather than just
4040  // conditionally adding the cc_out in the first place because we need
4041  // to check the type of the parsed immediate operand.
4042  if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4043      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4044      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4045      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4046    return true;
4047
4048  // Register-register 'add' for thumb does not have a cc_out operand
4049  // when there are only two register operands.
4050  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4051      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4052      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4053      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4054    return true;
4055  // Register-register 'add' for thumb does not have a cc_out operand
4056  // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4057  // have to check the immediate range here since Thumb2 has a variant
4058  // that can handle a different range and has a cc_out operand.
4059  if (((isThumb() && Mnemonic == "add") ||
4060       (isThumbTwo() && Mnemonic == "sub")) &&
4061      Operands.size() == 6 &&
4062      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4063      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4064      static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4065      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4066      (static_cast<ARMOperand*>(Operands[5])->isReg() ||
4067       static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4068    return true;
4069  // For Thumb2, add/sub immediate does not have a cc_out operand for the
4070  // imm0_4095 variant. That's the least-preferred variant when
4071  // selecting via the generic "add" mnemonic, so to know that we
4072  // should remove the cc_out operand, we have to explicitly check that
4073  // it's not one of the other variants. Ugh.
4074  if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4075      Operands.size() == 6 &&
4076      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4077      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4078      static_cast<ARMOperand*>(Operands[5])->isImm()) {
4079    // Nest conditions rather than one big 'if' statement for readability.
4080    //
4081    // If either register is a high reg, it's either one of the SP
4082    // variants (handled above) or a 32-bit encoding, so we just
4083    // check against T3.
4084    if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4085         !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
4086        static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4087      return false;
4088    // If both registers are low, we're in an IT block, and the immediate is
4089    // in range, we should use encoding T1 instead, which has a cc_out.
4090    if (inITBlock() &&
4091        isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4092        isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4093        static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4094      return false;
4095
4096    // Otherwise, we use encoding T4, which does not have a cc_out
4097    // operand.
4098    return true;
4099  }
4100
4101  // The thumb2 multiply instruction doesn't have a CCOut register, so
4102  // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4103  // use the 16-bit encoding or not.
4104  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4105      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4106      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4107      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4108      static_cast<ARMOperand*>(Operands[5])->isReg() &&
4109      // If the registers aren't low regs, the destination reg isn't the
4110      // same as one of the source regs, or the cc_out operand is zero
4111      // outside of an IT block, we have to use the 32-bit encoding, so
4112      // remove the cc_out operand.
4113      (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4114       !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4115       !inITBlock() ||
4116       (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4117        static_cast<ARMOperand*>(Operands[5])->getReg() &&
4118        static_cast<ARMOperand*>(Operands[3])->getReg() !=
4119        static_cast<ARMOperand*>(Operands[4])->getReg())))
4120    return true;
4121
4122
4123
4124  // Register-register 'add/sub' for thumb does not have a cc_out operand
4125  // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4126  // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4127  // right, this will result in better diagnostics (which operand is off)
4128  // anyway.
4129  if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4130      (Operands.size() == 5 || Operands.size() == 6) &&
4131      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4132      static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4133      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4134    return true;
4135
4136  return false;
4137}
4138
4139/// Parse an arm instruction mnemonic followed by its operands.
4140bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
4141                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4142  // Create the leading tokens for the mnemonic, split by '.' characters.
4143  size_t Start = 0, Next = Name.find('.');
4144  StringRef Mnemonic = Name.slice(Start, Next);
4145
4146  // Split out the predication code and carry setting flag from the mnemonic.
4147  unsigned PredicationCode;
4148  unsigned ProcessorIMod;
4149  bool CarrySetting;
4150  StringRef ITMask;
4151  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
4152                           ProcessorIMod, ITMask);
4153
4154  // In Thumb1, only the branch (B) instruction can be predicated.
4155  if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
4156    Parser.EatToEndOfStatement();
4157    return Error(NameLoc, "conditional execution not supported in Thumb1");
4158  }
4159
4160  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
4161
4162  // Handle the IT instruction ITMask. Convert it to a bitmask. This
4163  // is the mask as it will be for the IT encoding if the conditional
4164  // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
4165  // where the conditional bit0 is zero, the instruction post-processing
4166  // will adjust the mask accordingly.
4167  if (Mnemonic == "it") {
4168    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
4169    if (ITMask.size() > 3) {
4170      Parser.EatToEndOfStatement();
4171      return Error(Loc, "too many conditions on IT instruction");
4172    }
4173    unsigned Mask = 8;
4174    for (unsigned i = ITMask.size(); i != 0; --i) {
4175      char pos = ITMask[i - 1];
4176      if (pos != 't' && pos != 'e') {
4177        Parser.EatToEndOfStatement();
4178        return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
4179      }
4180      Mask >>= 1;
4181      if (ITMask[i - 1] == 't')
4182        Mask |= 8;
4183    }
4184    Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
4185  }
4186
4187  // FIXME: This is all a pretty gross hack. We should automatically handle
4188  // optional operands like this via tblgen.
4189
4190  // Next, add the CCOut and ConditionCode operands, if needed.
4191  //
4192  // For mnemonics which can ever incorporate a carry setting bit or predication
4193  // code, our matching model involves us always generating CCOut and
4194  // ConditionCode operands to match the mnemonic "as written" and then we let
4195  // the matcher deal with finding the right instruction or generating an
4196  // appropriate error.
4197  bool CanAcceptCarrySet, CanAcceptPredicationCode;
4198  getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
4199
4200  // If we had a carry-set on an instruction that can't do that, issue an
4201  // error.
4202  if (!CanAcceptCarrySet && CarrySetting) {
4203    Parser.EatToEndOfStatement();
4204    return Error(NameLoc, "instruction '" + Mnemonic +
4205                 "' can not set flags, but 's' suffix specified");
4206  }
4207  // If we had a predication code on an instruction that can't do that, issue an
4208  // error.
4209  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
4210    Parser.EatToEndOfStatement();
4211    return Error(NameLoc, "instruction '" + Mnemonic +
4212                 "' is not predicable, but condition code specified");
4213  }
4214
4215  // Add the carry setting operand, if necessary.
4216  if (CanAcceptCarrySet) {
4217    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
4218    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
4219                                               Loc));
4220  }
4221
4222  // Add the predication code operand, if necessary.
4223  if (CanAcceptPredicationCode) {
4224    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
4225                                      CarrySetting);
4226    Operands.push_back(ARMOperand::CreateCondCode(
4227                         ARMCC::CondCodes(PredicationCode), Loc));
4228  }
4229
4230  // Add the processor imod operand, if necessary.
4231  if (ProcessorIMod) {
4232    Operands.push_back(ARMOperand::CreateImm(
4233          MCConstantExpr::Create(ProcessorIMod, getContext()),
4234                                 NameLoc, NameLoc));
4235  }
4236
4237  // Add the remaining tokens in the mnemonic.
4238  while (Next != StringRef::npos) {
4239    Start = Next;
4240    Next = Name.find('.', Start + 1);
4241    StringRef ExtraToken = Name.slice(Start, Next);
4242
4243    // For now, we're only parsing Thumb1 (for the most part), so
4244    // just ignore ".n" qualifiers. We'll use them to restrict
4245    // matching when we do Thumb2.
4246    if (ExtraToken != ".n") {
4247      SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
4248      Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
4249    }
4250  }
4251
4252  // Read the remaining operands.
4253  if (getLexer().isNot(AsmToken::EndOfStatement)) {
4254    // Read the first operand.
4255    if (parseOperand(Operands, Mnemonic)) {
4256      Parser.EatToEndOfStatement();
4257      return true;
4258    }
4259
4260    while (getLexer().is(AsmToken::Comma)) {
4261      Parser.Lex();  // Eat the comma.
4262
4263      // Parse and remember the operand.
4264      if (parseOperand(Operands, Mnemonic)) {
4265        Parser.EatToEndOfStatement();
4266        return true;
4267      }
4268    }
4269  }
4270
4271  if (getLexer().isNot(AsmToken::EndOfStatement)) {
4272    SMLoc Loc = getLexer().getLoc();
4273    Parser.EatToEndOfStatement();
4274    return Error(Loc, "unexpected token in argument list");
4275  }
4276
4277  Parser.Lex(); // Consume the EndOfStatement
4278
4279  // Some instructions, mostly Thumb, have forms for the same mnemonic that
4280  // do and don't have a cc_out optional-def operand. With some spot-checks
4281  // of the operand list, we can figure out which variant we're trying to
4282  // parse and adjust accordingly before actually matching. We shouldn't ever
4283  // try to remove a cc_out operand that was explicitly set on the the
4284  // mnemonic, of course (CarrySetting == true). Reason number #317 the
4285  // table driven matcher doesn't fit well with the ARM instruction set.
4286  if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
4287    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
4288    Operands.erase(Operands.begin() + 1);
4289    delete Op;
4290  }
4291
4292  // ARM mode 'blx' need special handling, as the register operand version
4293  // is predicable, but the label operand version is not. So, we can't rely
4294  // on the Mnemonic based checking to correctly figure out when to put
4295  // a k_CondCode operand in the list. If we're trying to match the label
4296  // version, remove the k_CondCode operand here.
4297  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
4298      static_cast<ARMOperand*>(Operands[2])->isImm()) {
4299    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
4300    Operands.erase(Operands.begin() + 1);
4301    delete Op;
4302  }
4303
4304  // The vector-compare-to-zero instructions have a literal token "#0" at
4305  // the end that comes to here as an immediate operand. Convert it to a
4306  // token to play nicely with the matcher.
4307  if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
4308      Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
4309      static_cast<ARMOperand*>(Operands[5])->isImm()) {
4310    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
4311    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4312    if (CE && CE->getValue() == 0) {
4313      Operands.erase(Operands.begin() + 5);
4314      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4315      delete Op;
4316    }
4317  }
4318  // VCMP{E} does the same thing, but with a different operand count.
4319  if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 &&
4320      static_cast<ARMOperand*>(Operands[4])->isImm()) {
4321    ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]);
4322    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4323    if (CE && CE->getValue() == 0) {
4324      Operands.erase(Operands.begin() + 4);
4325      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4326      delete Op;
4327    }
4328  }
4329  // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
4330  // end. Convert it to a token here.
4331  if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
4332      static_cast<ARMOperand*>(Operands[5])->isImm()) {
4333    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
4334    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4335    if (CE && CE->getValue() == 0) {
4336      Operands.erase(Operands.begin() + 5);
4337      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4338      delete Op;
4339    }
4340  }
4341
4342  return false;
4343}
4344
4345// Validate context-sensitive operand constraints.
4346
4347// return 'true' if register list contains non-low GPR registers,
4348// 'false' otherwise. If Reg is in the register list or is HiReg, set
4349// 'containsReg' to true.
4350static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
4351                                 unsigned HiReg, bool &containsReg) {
4352  containsReg = false;
4353  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
4354    unsigned OpReg = Inst.getOperand(i).getReg();
4355    if (OpReg == Reg)
4356      containsReg = true;
4357    // Anything other than a low register isn't legal here.
4358    if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
4359      return true;
4360  }
4361  return false;
4362}
4363
4364// Check if the specified regisgter is in the register list of the inst,
4365// starting at the indicated operand number.
4366static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
4367  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
4368    unsigned OpReg = Inst.getOperand(i).getReg();
4369    if (OpReg == Reg)
4370      return true;
4371  }
4372  return false;
4373}
4374
4375// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
4376// the ARMInsts array) instead. Getting that here requires awkward
4377// API changes, though. Better way?
4378namespace llvm {
4379extern const MCInstrDesc ARMInsts[];
4380}
4381static const MCInstrDesc &getInstDesc(unsigned Opcode) {
4382  return ARMInsts[Opcode];
4383}
4384
4385// FIXME: We would really like to be able to tablegen'erate this.
4386bool ARMAsmParser::
4387validateInstruction(MCInst &Inst,
4388                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4389  const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
4390  SMLoc Loc = Operands[0]->getStartLoc();
4391  // Check the IT block state first.
4392  // NOTE: In Thumb mode, the BKPT instruction has the interesting property of
4393  // being allowed in IT blocks, but not being predicable.  It just always
4394  // executes.
4395  if (inITBlock() && Inst.getOpcode() != ARM::tBKPT) {
4396    unsigned bit = 1;
4397    if (ITState.FirstCond)
4398      ITState.FirstCond = false;
4399    else
4400      bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
4401    // The instruction must be predicable.
4402    if (!MCID.isPredicable())
4403      return Error(Loc, "instructions in IT block must be predicable");
4404    unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
4405    unsigned ITCond = bit ? ITState.Cond :
4406      ARMCC::getOppositeCondition(ITState.Cond);
4407    if (Cond != ITCond) {
4408      // Find the condition code Operand to get its SMLoc information.
4409      SMLoc CondLoc;
4410      for (unsigned i = 1; i < Operands.size(); ++i)
4411        if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
4412          CondLoc = Operands[i]->getStartLoc();
4413      return Error(CondLoc, "incorrect condition in IT block; got '" +
4414                   StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
4415                   "', but expected '" +
4416                   ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
4417    }
4418  // Check for non-'al' condition codes outside of the IT block.
4419  } else if (isThumbTwo() && MCID.isPredicable() &&
4420             Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
4421             ARMCC::AL && Inst.getOpcode() != ARM::tB &&
4422             Inst.getOpcode() != ARM::t2B)
4423    return Error(Loc, "predicated instructions must be in IT block");
4424
4425  switch (Inst.getOpcode()) {
4426  case ARM::LDRD:
4427  case ARM::LDRD_PRE:
4428  case ARM::LDRD_POST:
4429  case ARM::LDREXD: {
4430    // Rt2 must be Rt + 1.
4431    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
4432    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4433    if (Rt2 != Rt + 1)
4434      return Error(Operands[3]->getStartLoc(),
4435                   "destination operands must be sequential");
4436    return false;
4437  }
4438  case ARM::STRD: {
4439    // Rt2 must be Rt + 1.
4440    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
4441    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4442    if (Rt2 != Rt + 1)
4443      return Error(Operands[3]->getStartLoc(),
4444                   "source operands must be sequential");
4445    return false;
4446  }
4447  case ARM::STRD_PRE:
4448  case ARM::STRD_POST:
4449  case ARM::STREXD: {
4450    // Rt2 must be Rt + 1.
4451    unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4452    unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
4453    if (Rt2 != Rt + 1)
4454      return Error(Operands[3]->getStartLoc(),
4455                   "source operands must be sequential");
4456    return false;
4457  }
4458  case ARM::SBFX:
4459  case ARM::UBFX: {
4460    // width must be in range [1, 32-lsb]
4461    unsigned lsb = Inst.getOperand(2).getImm();
4462    unsigned widthm1 = Inst.getOperand(3).getImm();
4463    if (widthm1 >= 32 - lsb)
4464      return Error(Operands[5]->getStartLoc(),
4465                   "bitfield width must be in range [1,32-lsb]");
4466    return false;
4467  }
4468  case ARM::tLDMIA: {
4469    // If we're parsing Thumb2, the .w variant is available and handles
4470    // most cases that are normally illegal for a Thumb1 LDM
4471    // instruction. We'll make the transformation in processInstruction()
4472    // if necessary.
4473    //
4474    // Thumb LDM instructions are writeback iff the base register is not
4475    // in the register list.
4476    unsigned Rn = Inst.getOperand(0).getReg();
4477    bool hasWritebackToken =
4478      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
4479       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
4480    bool listContainsBase;
4481    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
4482      return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
4483                   "registers must be in range r0-r7");
4484    // If we should have writeback, then there should be a '!' token.
4485    if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
4486      return Error(Operands[2]->getStartLoc(),
4487                   "writeback operator '!' expected");
4488    // If we should not have writeback, there must not be a '!'. This is
4489    // true even for the 32-bit wide encodings.
4490    if (listContainsBase && hasWritebackToken)
4491      return Error(Operands[3]->getStartLoc(),
4492                   "writeback operator '!' not allowed when base register "
4493                   "in register list");
4494
4495    break;
4496  }
4497  case ARM::t2LDMIA_UPD: {
4498    if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
4499      return Error(Operands[4]->getStartLoc(),
4500                   "writeback operator '!' not allowed when base register "
4501                   "in register list");
4502    break;
4503  }
4504  case ARM::tPOP: {
4505    bool listContainsBase;
4506    if (checkLowRegisterList(Inst, 3, 0, ARM::PC, listContainsBase))
4507      return Error(Operands[2]->getStartLoc(),
4508                   "registers must be in range r0-r7 or pc");
4509    break;
4510  }
4511  case ARM::tPUSH: {
4512    bool listContainsBase;
4513    if (checkLowRegisterList(Inst, 3, 0, ARM::LR, listContainsBase))
4514      return Error(Operands[2]->getStartLoc(),
4515                   "registers must be in range r0-r7 or lr");
4516    break;
4517  }
4518  case ARM::tSTMIA_UPD: {
4519    bool listContainsBase;
4520    if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
4521      return Error(Operands[4]->getStartLoc(),
4522                   "registers must be in range r0-r7");
4523    break;
4524  }
4525  }
4526
4527  return false;
4528}
4529
4530void ARMAsmParser::
4531processInstruction(MCInst &Inst,
4532                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4533  switch (Inst.getOpcode()) {
4534  case ARM::LDMIA_UPD:
4535    // If this is a load of a single register via a 'pop', then we should use
4536    // a post-indexed LDR instruction instead, per the ARM ARM.
4537    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
4538        Inst.getNumOperands() == 5) {
4539      MCInst TmpInst;
4540      TmpInst.setOpcode(ARM::LDR_POST_IMM);
4541      TmpInst.addOperand(Inst.getOperand(4)); // Rt
4542      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
4543      TmpInst.addOperand(Inst.getOperand(1)); // Rn
4544      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
4545      TmpInst.addOperand(MCOperand::CreateImm(4));
4546      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
4547      TmpInst.addOperand(Inst.getOperand(3));
4548      Inst = TmpInst;
4549    }
4550    break;
4551  case ARM::STMDB_UPD:
4552    // If this is a store of a single register via a 'push', then we should use
4553    // a pre-indexed STR instruction instead, per the ARM ARM.
4554    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
4555        Inst.getNumOperands() == 5) {
4556      MCInst TmpInst;
4557      TmpInst.setOpcode(ARM::STR_PRE_IMM);
4558      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
4559      TmpInst.addOperand(Inst.getOperand(4)); // Rt
4560      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
4561      TmpInst.addOperand(MCOperand::CreateImm(-4));
4562      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
4563      TmpInst.addOperand(Inst.getOperand(3));
4564      Inst = TmpInst;
4565    }
4566    break;
4567  case ARM::tADDi8:
4568    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
4569    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
4570    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
4571    // to encoding T1 if <Rd> is omitted."
4572    if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6)
4573      Inst.setOpcode(ARM::tADDi3);
4574    break;
4575  case ARM::tSUBi8:
4576    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
4577    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
4578    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
4579    // to encoding T1 if <Rd> is omitted."
4580    if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6)
4581      Inst.setOpcode(ARM::tSUBi3);
4582    break;
4583  case ARM::tB:
4584    // A Thumb conditional branch outside of an IT block is a tBcc.
4585    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock())
4586      Inst.setOpcode(ARM::tBcc);
4587    break;
4588  case ARM::t2B:
4589    // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
4590    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock())
4591      Inst.setOpcode(ARM::t2Bcc);
4592    break;
4593  case ARM::t2Bcc:
4594    // If the conditional is AL or we're in an IT block, we really want t2B.
4595    if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock())
4596      Inst.setOpcode(ARM::t2B);
4597    break;
4598  case ARM::tBcc:
4599    // If the conditional is AL, we really want tB.
4600    if (Inst.getOperand(1).getImm() == ARMCC::AL)
4601      Inst.setOpcode(ARM::tB);
4602    break;
4603  case ARM::tLDMIA: {
4604    // If the register list contains any high registers, or if the writeback
4605    // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
4606    // instead if we're in Thumb2. Otherwise, this should have generated
4607    // an error in validateInstruction().
4608    unsigned Rn = Inst.getOperand(0).getReg();
4609    bool hasWritebackToken =
4610      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
4611       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
4612    bool listContainsBase;
4613    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
4614        (!listContainsBase && !hasWritebackToken) ||
4615        (listContainsBase && hasWritebackToken)) {
4616      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
4617      assert (isThumbTwo());
4618      Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
4619      // If we're switching to the updating version, we need to insert
4620      // the writeback tied operand.
4621      if (hasWritebackToken)
4622        Inst.insert(Inst.begin(),
4623                    MCOperand::CreateReg(Inst.getOperand(0).getReg()));
4624    }
4625    break;
4626  }
4627  case ARM::tSTMIA_UPD: {
4628    // If the register list contains any high registers, we need to use
4629    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
4630    // should have generated an error in validateInstruction().
4631    unsigned Rn = Inst.getOperand(0).getReg();
4632    bool listContainsBase;
4633    if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
4634      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
4635      assert (isThumbTwo());
4636      Inst.setOpcode(ARM::t2STMIA_UPD);
4637    }
4638    break;
4639  }
4640  case ARM::t2MOVi: {
4641    // If we can use the 16-bit encoding and the user didn't explicitly
4642    // request the 32-bit variant, transform it here.
4643    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
4644        Inst.getOperand(1).getImm() <= 255 &&
4645        ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
4646         Inst.getOperand(4).getReg() == ARM::CPSR) ||
4647        (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
4648        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
4649         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
4650      // The operands aren't in the same order for tMOVi8...
4651      MCInst TmpInst;
4652      TmpInst.setOpcode(ARM::tMOVi8);
4653      TmpInst.addOperand(Inst.getOperand(0));
4654      TmpInst.addOperand(Inst.getOperand(4));
4655      TmpInst.addOperand(Inst.getOperand(1));
4656      TmpInst.addOperand(Inst.getOperand(2));
4657      TmpInst.addOperand(Inst.getOperand(3));
4658      Inst = TmpInst;
4659    }
4660    break;
4661  }
4662  case ARM::t2MOVr: {
4663    // If we can use the 16-bit encoding and the user didn't explicitly
4664    // request the 32-bit variant, transform it here.
4665    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
4666        isARMLowRegister(Inst.getOperand(1).getReg()) &&
4667        Inst.getOperand(2).getImm() == ARMCC::AL &&
4668        Inst.getOperand(4).getReg() == ARM::CPSR &&
4669        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
4670         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
4671      // The operands aren't the same for tMOV[S]r... (no cc_out)
4672      MCInst TmpInst;
4673      TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
4674      TmpInst.addOperand(Inst.getOperand(0));
4675      TmpInst.addOperand(Inst.getOperand(1));
4676      TmpInst.addOperand(Inst.getOperand(2));
4677      TmpInst.addOperand(Inst.getOperand(3));
4678      Inst = TmpInst;
4679    }
4680    break;
4681  }
4682  case ARM::t2SXTH:
4683  case ARM::t2SXTB:
4684  case ARM::t2UXTH:
4685  case ARM::t2UXTB: {
4686    // If we can use the 16-bit encoding and the user didn't explicitly
4687    // request the 32-bit variant, transform it here.
4688    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
4689        isARMLowRegister(Inst.getOperand(1).getReg()) &&
4690        Inst.getOperand(2).getImm() == 0 &&
4691        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
4692         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
4693      unsigned NewOpc;
4694      switch (Inst.getOpcode()) {
4695      default: llvm_unreachable("Illegal opcode!");
4696      case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
4697      case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
4698      case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
4699      case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
4700      }
4701      // The operands aren't the same for thumb1 (no rotate operand).
4702      MCInst TmpInst;
4703      TmpInst.setOpcode(NewOpc);
4704      TmpInst.addOperand(Inst.getOperand(0));
4705      TmpInst.addOperand(Inst.getOperand(1));
4706      TmpInst.addOperand(Inst.getOperand(3));
4707      TmpInst.addOperand(Inst.getOperand(4));
4708      Inst = TmpInst;
4709    }
4710    break;
4711  }
4712  case ARM::t2IT: {
4713    // The mask bits for all but the first condition are represented as
4714    // the low bit of the condition code value implies 't'. We currently
4715    // always have 1 implies 't', so XOR toggle the bits if the low bit
4716    // of the condition code is zero. The encoding also expects the low
4717    // bit of the condition to be encoded as bit 4 of the mask operand,
4718    // so mask that in if needed
4719    MCOperand &MO = Inst.getOperand(1);
4720    unsigned Mask = MO.getImm();
4721    unsigned OrigMask = Mask;
4722    unsigned TZ = CountTrailingZeros_32(Mask);
4723    if ((Inst.getOperand(0).getImm() & 1) == 0) {
4724      assert(Mask && TZ <= 3 && "illegal IT mask value!");
4725      for (unsigned i = 3; i != TZ; --i)
4726        Mask ^= 1 << i;
4727    } else
4728      Mask |= 0x10;
4729    MO.setImm(Mask);
4730
4731    // Set up the IT block state according to the IT instruction we just
4732    // matched.
4733    assert(!inITBlock() && "nested IT blocks?!");
4734    ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
4735    ITState.Mask = OrigMask; // Use the original mask, not the updated one.
4736    ITState.CurPosition = 0;
4737    ITState.FirstCond = true;
4738    break;
4739  }
4740  }
4741}
4742
4743unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
4744  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
4745  // suffix depending on whether they're in an IT block or not.
4746  unsigned Opc = Inst.getOpcode();
4747  const MCInstrDesc &MCID = getInstDesc(Opc);
4748  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
4749    assert(MCID.hasOptionalDef() &&
4750           "optionally flag setting instruction missing optional def operand");
4751    assert(MCID.NumOperands == Inst.getNumOperands() &&
4752           "operand count mismatch!");
4753    // Find the optional-def operand (cc_out).
4754    unsigned OpNo;
4755    for (OpNo = 0;
4756         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
4757         ++OpNo)
4758      ;
4759    // If we're parsing Thumb1, reject it completely.
4760    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
4761      return Match_MnemonicFail;
4762    // If we're parsing Thumb2, which form is legal depends on whether we're
4763    // in an IT block.
4764    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
4765        !inITBlock())
4766      return Match_RequiresITBlock;
4767    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
4768        inITBlock())
4769      return Match_RequiresNotITBlock;
4770  }
4771  // Some high-register supporting Thumb1 encodings only allow both registers
4772  // to be from r0-r7 when in Thumb2.
4773  else if (Opc == ARM::tADDhirr && isThumbOne() &&
4774           isARMLowRegister(Inst.getOperand(1).getReg()) &&
4775           isARMLowRegister(Inst.getOperand(2).getReg()))
4776    return Match_RequiresThumb2;
4777  // Others only require ARMv6 or later.
4778  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
4779           isARMLowRegister(Inst.getOperand(0).getReg()) &&
4780           isARMLowRegister(Inst.getOperand(1).getReg()))
4781    return Match_RequiresV6;
4782  return Match_Success;
4783}
4784
4785bool ARMAsmParser::
4786MatchAndEmitInstruction(SMLoc IDLoc,
4787                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4788                        MCStreamer &Out) {
4789  MCInst Inst;
4790  unsigned ErrorInfo;
4791  unsigned MatchResult;
4792  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
4793  switch (MatchResult) {
4794  default: break;
4795  case Match_Success:
4796    // Context sensitive operand constraints aren't handled by the matcher,
4797    // so check them here.
4798    if (validateInstruction(Inst, Operands)) {
4799      // Still progress the IT block, otherwise one wrong condition causes
4800      // nasty cascading errors.
4801      forwardITPosition();
4802      return true;
4803    }
4804
4805    // Some instructions need post-processing to, for example, tweak which
4806    // encoding is selected.
4807    processInstruction(Inst, Operands);
4808
4809    // Only move forward at the very end so that everything in validate
4810    // and process gets a consistent answer about whether we're in an IT
4811    // block.
4812    forwardITPosition();
4813
4814    Out.EmitInstruction(Inst);
4815    return false;
4816  case Match_MissingFeature:
4817    Error(IDLoc, "instruction requires a CPU feature not currently enabled");
4818    return true;
4819  case Match_InvalidOperand: {
4820    SMLoc ErrorLoc = IDLoc;
4821    if (ErrorInfo != ~0U) {
4822      if (ErrorInfo >= Operands.size())
4823        return Error(IDLoc, "too few operands for instruction");
4824
4825      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
4826      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
4827    }
4828
4829    return Error(ErrorLoc, "invalid operand for instruction");
4830  }
4831  case Match_MnemonicFail:
4832    return Error(IDLoc, "invalid instruction");
4833  case Match_ConversionFail:
4834    // The converter function will have already emited a diagnostic.
4835    return true;
4836  case Match_RequiresNotITBlock:
4837    return Error(IDLoc, "flag setting instruction only valid outside IT block");
4838  case Match_RequiresITBlock:
4839    return Error(IDLoc, "instruction only valid inside IT block");
4840  case Match_RequiresV6:
4841    return Error(IDLoc, "instruction variant requires ARMv6 or later");
4842  case Match_RequiresThumb2:
4843    return Error(IDLoc, "instruction variant requires Thumb2");
4844  }
4845
4846  llvm_unreachable("Implement any new match types added!");
4847  return true;
4848}
4849
4850/// parseDirective parses the arm specific directives
4851bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
4852  StringRef IDVal = DirectiveID.getIdentifier();
4853  if (IDVal == ".word")
4854    return parseDirectiveWord(4, DirectiveID.getLoc());
4855  else if (IDVal == ".thumb")
4856    return parseDirectiveThumb(DirectiveID.getLoc());
4857  else if (IDVal == ".thumb_func")
4858    return parseDirectiveThumbFunc(DirectiveID.getLoc());
4859  else if (IDVal == ".code")
4860    return parseDirectiveCode(DirectiveID.getLoc());
4861  else if (IDVal == ".syntax")
4862    return parseDirectiveSyntax(DirectiveID.getLoc());
4863  return true;
4864}
4865
4866/// parseDirectiveWord
4867///  ::= .word [ expression (, expression)* ]
4868bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
4869  if (getLexer().isNot(AsmToken::EndOfStatement)) {
4870    for (;;) {
4871      const MCExpr *Value;
4872      if (getParser().ParseExpression(Value))
4873        return true;
4874
4875      getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
4876
4877      if (getLexer().is(AsmToken::EndOfStatement))
4878        break;
4879
4880      // FIXME: Improve diagnostic.
4881      if (getLexer().isNot(AsmToken::Comma))
4882        return Error(L, "unexpected token in directive");
4883      Parser.Lex();
4884    }
4885  }
4886
4887  Parser.Lex();
4888  return false;
4889}
4890
4891/// parseDirectiveThumb
4892///  ::= .thumb
4893bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
4894  if (getLexer().isNot(AsmToken::EndOfStatement))
4895    return Error(L, "unexpected token in directive");
4896  Parser.Lex();
4897
4898  // TODO: set thumb mode
4899  // TODO: tell the MC streamer the mode
4900  // getParser().getStreamer().Emit???();
4901  return false;
4902}
4903
4904/// parseDirectiveThumbFunc
4905///  ::= .thumbfunc symbol_name
4906bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
4907  const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
4908  bool isMachO = MAI.hasSubsectionsViaSymbols();
4909  StringRef Name;
4910
4911  // Darwin asm has function name after .thumb_func direction
4912  // ELF doesn't
4913  if (isMachO) {
4914    const AsmToken &Tok = Parser.getTok();
4915    if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
4916      return Error(L, "unexpected token in .thumb_func directive");
4917    Name = Tok.getString();
4918    Parser.Lex(); // Consume the identifier token.
4919  }
4920
4921  if (getLexer().isNot(AsmToken::EndOfStatement))
4922    return Error(L, "unexpected token in directive");
4923  Parser.Lex();
4924
4925  // FIXME: assuming function name will be the line following .thumb_func
4926  if (!isMachO) {
4927    Name = Parser.getTok().getString();
4928  }
4929
4930  // Mark symbol as a thumb symbol.
4931  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
4932  getParser().getStreamer().EmitThumbFunc(Func);
4933  return false;
4934}
4935
4936/// parseDirectiveSyntax
4937///  ::= .syntax unified | divided
4938bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
4939  const AsmToken &Tok = Parser.getTok();
4940  if (Tok.isNot(AsmToken::Identifier))
4941    return Error(L, "unexpected token in .syntax directive");
4942  StringRef Mode = Tok.getString();
4943  if (Mode == "unified" || Mode == "UNIFIED")
4944    Parser.Lex();
4945  else if (Mode == "divided" || Mode == "DIVIDED")
4946    return Error(L, "'.syntax divided' arm asssembly not supported");
4947  else
4948    return Error(L, "unrecognized syntax mode in .syntax directive");
4949
4950  if (getLexer().isNot(AsmToken::EndOfStatement))
4951    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
4952  Parser.Lex();
4953
4954  // TODO tell the MC streamer the mode
4955  // getParser().getStreamer().Emit???();
4956  return false;
4957}
4958
4959/// parseDirectiveCode
4960///  ::= .code 16 | 32
4961bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
4962  const AsmToken &Tok = Parser.getTok();
4963  if (Tok.isNot(AsmToken::Integer))
4964    return Error(L, "unexpected token in .code directive");
4965  int64_t Val = Parser.getTok().getIntVal();
4966  if (Val == 16)
4967    Parser.Lex();
4968  else if (Val == 32)
4969    Parser.Lex();
4970  else
4971    return Error(L, "invalid operand to .code directive");
4972
4973  if (getLexer().isNot(AsmToken::EndOfStatement))
4974    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
4975  Parser.Lex();
4976
4977  if (Val == 16) {
4978    if (!isThumb())
4979      SwitchMode();
4980    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
4981  } else {
4982    if (isThumb())
4983      SwitchMode();
4984    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
4985  }
4986
4987  return false;
4988}
4989
4990extern "C" void LLVMInitializeARMAsmLexer();
4991
4992/// Force static initialization.
4993extern "C" void LLVMInitializeARMAsmParser() {
4994  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
4995  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
4996  LLVMInitializeARMAsmLexer();
4997}
4998
4999#define GET_REGISTER_MATCHER
5000#define GET_MATCHER_IMPLEMENTATION
5001#include "ARMGenAsmMatcher.inc"
5002