ARMAsmParser.cpp revision 64b3444cbf7f5976502ff4cf6fc89aed4986b59c 
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "MCTargetDesc/ARMBaseInfo.h"
11#include "MCTargetDesc/ARMAddressingModes.h"
12#include "MCTargetDesc/ARMMCExpr.h"
13#include "llvm/MC/MCParser/MCAsmLexer.h"
14#include "llvm/MC/MCParser/MCAsmParser.h"
15#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16#include "llvm/MC/MCAsmInfo.h"
17#include "llvm/MC/MCContext.h"
18#include "llvm/MC/MCStreamer.h"
19#include "llvm/MC/MCExpr.h"
20#include "llvm/MC/MCInst.h"
21#include "llvm/MC/MCInstrDesc.h"
22#include "llvm/MC/MCRegisterInfo.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/MC/MCTargetAsmParser.h"
25#include "llvm/Support/MathExtras.h"
26#include "llvm/Support/SourceMgr.h"
27#include "llvm/Support/TargetRegistry.h"
28#include "llvm/Support/raw_ostream.h"
29#include "llvm/ADT/BitVector.h"
30#include "llvm/ADT/OwningPtr.h"
31#include "llvm/ADT/STLExtras.h"
32#include "llvm/ADT/SmallVector.h"
33#include "llvm/ADT/StringSwitch.h"
34#include "llvm/ADT/Twine.h"
35
36using namespace llvm;
37
38namespace {
39
40class ARMOperand;
41
42enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
43
44class ARMAsmParser : public MCTargetAsmParser {
45  MCSubtargetInfo &STI;
46  MCAsmParser &Parser;
47  const MCRegisterInfo *MRI;
48
49  // Map of register aliases registers via the .req directive.
50  StringMap<unsigned> RegisterReqs;
51
52  struct {
53    ARMCC::CondCodes Cond;    // Condition for IT block.
54    unsigned Mask:4;          // Condition mask for instructions.
55                              // Starting at first 1 (from lsb).
56                              //   '1'  condition as indicated in IT.
57                              //   '0'  inverse of condition (else).
58                              // Count of instructions in IT block is
59                              // 4 - trailingzeroes(mask)
60
61    bool FirstCond;           // Explicit flag for when we're parsing the
62                              // First instruction in the IT block. It's
63                              // implied in the mask, so needs special
64                              // handling.
65
66    unsigned CurPosition;     // Current position in parsing of IT
67                              // block. In range [0,3]. Initialized
68                              // according to count of instructions in block.
69                              // ~0U if no active IT block.
70  } ITState;
71  bool inITBlock() { return ITState.CurPosition != ~0U;}
72  void forwardITPosition() {
73    if (!inITBlock()) return;
74    // Move to the next instruction in the IT block, if there is one. If not,
75    // mark the block as done.
76    unsigned TZ = CountTrailingZeros_32(ITState.Mask);
77    if (++ITState.CurPosition == 5 - TZ)
78      ITState.CurPosition = ~0U; // Done with the IT block after this.
79  }
80
81
82  MCAsmParser &getParser() const { return Parser; }
83  MCAsmLexer &getLexer() const { return Parser.getLexer(); }
84
85  bool Warning(SMLoc L, const Twine &Msg,
86               ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) {
87    return Parser.Warning(L, Msg, Ranges);
88  }
89  bool Error(SMLoc L, const Twine &Msg,
90             ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) {
91    return Parser.Error(L, Msg, Ranges);
92  }
93
94  int tryParseRegister();
95  bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
96  int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
97  bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
98  bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
99  bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
100  bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
101  bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
102                              unsigned &ShiftAmount);
103  bool parseDirectiveWord(unsigned Size, SMLoc L);
104  bool parseDirectiveThumb(SMLoc L);
105  bool parseDirectiveARM(SMLoc L);
106  bool parseDirectiveThumbFunc(SMLoc L);
107  bool parseDirectiveCode(SMLoc L);
108  bool parseDirectiveSyntax(SMLoc L);
109  bool parseDirectiveReq(StringRef Name, SMLoc L);
110  bool parseDirectiveUnreq(SMLoc L);
111  bool parseDirectiveArch(SMLoc L);
112  bool parseDirectiveEabiAttr(SMLoc L);
113
114  StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
115                          bool &CarrySetting, unsigned &ProcessorIMod,
116                          StringRef &ITMask);
117  void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
118                             bool &CanAcceptPredicationCode);
119
120  bool isThumb() const {
121    // FIXME: Can tablegen auto-generate this?
122    return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
123  }
124  bool isThumbOne() const {
125    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
126  }
127  bool isThumbTwo() const {
128    return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
129  }
130  bool hasV6Ops() const {
131    return STI.getFeatureBits() & ARM::HasV6Ops;
132  }
133  bool hasV7Ops() const {
134    return STI.getFeatureBits() & ARM::HasV7Ops;
135  }
136  void SwitchMode() {
137    unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
138    setAvailableFeatures(FB);
139  }
140  bool isMClass() const {
141    return STI.getFeatureBits() & ARM::FeatureMClass;
142  }
143
144  /// @name Auto-generated Match Functions
145  /// {
146
147#define GET_ASSEMBLER_HEADER
148#include "ARMGenAsmMatcher.inc"
149
150  /// }
151
152  OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
153  OperandMatchResultTy parseCoprocNumOperand(
154    SmallVectorImpl<MCParsedAsmOperand*>&);
155  OperandMatchResultTy parseCoprocRegOperand(
156    SmallVectorImpl<MCParsedAsmOperand*>&);
157  OperandMatchResultTy parseCoprocOptionOperand(
158    SmallVectorImpl<MCParsedAsmOperand*>&);
159  OperandMatchResultTy parseMemBarrierOptOperand(
160    SmallVectorImpl<MCParsedAsmOperand*>&);
161  OperandMatchResultTy parseProcIFlagsOperand(
162    SmallVectorImpl<MCParsedAsmOperand*>&);
163  OperandMatchResultTy parseMSRMaskOperand(
164    SmallVectorImpl<MCParsedAsmOperand*>&);
165  OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
166                                   StringRef Op, int Low, int High);
167  OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
168    return parsePKHImm(O, "lsl", 0, 31);
169  }
170  OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
171    return parsePKHImm(O, "asr", 1, 32);
172  }
173  OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
174  OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
175  OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
176  OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
177  OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
178  OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
179  OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
180  OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
181  OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index);
182
183  // Asm Match Converter Methods
184  bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
185                    const SmallVectorImpl<MCParsedAsmOperand*> &);
186  bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
187                    const SmallVectorImpl<MCParsedAsmOperand*> &);
188  bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
189                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
190  bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
191                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
192  bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
193                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
194  bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
195                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
196  bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
197                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
198  bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
199                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
200  bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
201                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
202  bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
203                             const SmallVectorImpl<MCParsedAsmOperand*> &);
204  bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
205                             const SmallVectorImpl<MCParsedAsmOperand*> &);
206  bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
207                             const SmallVectorImpl<MCParsedAsmOperand*> &);
208  bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
209                             const SmallVectorImpl<MCParsedAsmOperand*> &);
210  bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
211                  const SmallVectorImpl<MCParsedAsmOperand*> &);
212  bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
213                  const SmallVectorImpl<MCParsedAsmOperand*> &);
214  bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
215                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
216  bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
217                        const SmallVectorImpl<MCParsedAsmOperand*> &);
218  bool cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
219                     const SmallVectorImpl<MCParsedAsmOperand*> &);
220  bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
221                        const SmallVectorImpl<MCParsedAsmOperand*> &);
222  bool cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
223                     const SmallVectorImpl<MCParsedAsmOperand*> &);
224  bool cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
225                        const SmallVectorImpl<MCParsedAsmOperand*> &);
226
227  bool validateInstruction(MCInst &Inst,
228                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
229  bool processInstruction(MCInst &Inst,
230                          const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
231  bool shouldOmitCCOutOperand(StringRef Mnemonic,
232                              SmallVectorImpl<MCParsedAsmOperand*> &Operands);
233
234public:
235  enum ARMMatchResultTy {
236    Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
237    Match_RequiresNotITBlock,
238    Match_RequiresV6,
239    Match_RequiresThumb2,
240#define GET_OPERAND_DIAGNOSTIC_TYPES
241#include "ARMGenAsmMatcher.inc"
242
243  };
244
245  ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
246    : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
247    MCAsmParserExtension::Initialize(_Parser);
248
249    // Cache the MCRegisterInfo.
250    MRI = &getContext().getRegisterInfo();
251
252    // Initialize the set of available features.
253    setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
254
255    // Not in an ITBlock to start with.
256    ITState.CurPosition = ~0U;
257  }
258
259  // Implementation of the MCTargetAsmParser interface:
260  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
261  bool ParseInstruction(StringRef Name, SMLoc NameLoc,
262                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
263  bool ParseDirective(AsmToken DirectiveID);
264
265  unsigned checkTargetMatchPredicate(MCInst &Inst);
266
267  bool MatchAndEmitInstruction(SMLoc IDLoc,
268                               SmallVectorImpl<MCParsedAsmOperand*> &Operands,
269                               MCStreamer &Out);
270};
271} // end anonymous namespace
272
273namespace {
274
275/// ARMOperand - Instances of this class represent a parsed ARM machine
276/// instruction.
277class ARMOperand : public MCParsedAsmOperand {
278  enum KindTy {
279    k_CondCode,
280    k_CCOut,
281    k_ITCondMask,
282    k_CoprocNum,
283    k_CoprocReg,
284    k_CoprocOption,
285    k_Immediate,
286    k_MemBarrierOpt,
287    k_Memory,
288    k_PostIndexRegister,
289    k_MSRMask,
290    k_ProcIFlags,
291    k_VectorIndex,
292    k_Register,
293    k_RegisterList,
294    k_DPRRegisterList,
295    k_SPRRegisterList,
296    k_VectorList,
297    k_VectorListAllLanes,
298    k_VectorListIndexed,
299    k_ShiftedRegister,
300    k_ShiftedImmediate,
301    k_ShifterImmediate,
302    k_RotateImmediate,
303    k_BitfieldDescriptor,
304    k_Token
305  } Kind;
306
307  SMLoc StartLoc, EndLoc;
308  SmallVector<unsigned, 8> Registers;
309
310  union {
311    struct {
312      ARMCC::CondCodes Val;
313    } CC;
314
315    struct {
316      unsigned Val;
317    } Cop;
318
319    struct {
320      unsigned Val;
321    } CoprocOption;
322
323    struct {
324      unsigned Mask:4;
325    } ITMask;
326
327    struct {
328      ARM_MB::MemBOpt Val;
329    } MBOpt;
330
331    struct {
332      ARM_PROC::IFlags Val;
333    } IFlags;
334
335    struct {
336      unsigned Val;
337    } MMask;
338
339    struct {
340      const char *Data;
341      unsigned Length;
342    } Tok;
343
344    struct {
345      unsigned RegNum;
346    } Reg;
347
348    // A vector register list is a sequential list of 1 to 4 registers.
349    struct {
350      unsigned RegNum;
351      unsigned Count;
352      unsigned LaneIndex;
353      bool isDoubleSpaced;
354    } VectorList;
355
356    struct {
357      unsigned Val;
358    } VectorIndex;
359
360    struct {
361      const MCExpr *Val;
362    } Imm;
363
364    /// Combined record for all forms of ARM address expressions.
365    struct {
366      unsigned BaseRegNum;
367      // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
368      // was specified.
369      const MCConstantExpr *OffsetImm;  // Offset immediate value
370      unsigned OffsetRegNum;    // Offset register num, when OffsetImm == NULL
371      ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
372      unsigned ShiftImm;        // shift for OffsetReg.
373      unsigned Alignment;       // 0 = no alignment specified
374                                // n = alignment in bytes (2, 4, 8, 16, or 32)
375      unsigned isNegative : 1;  // Negated OffsetReg? (~'U' bit)
376    } Memory;
377
378    struct {
379      unsigned RegNum;
380      bool isAdd;
381      ARM_AM::ShiftOpc ShiftTy;
382      unsigned ShiftImm;
383    } PostIdxReg;
384
385    struct {
386      bool isASR;
387      unsigned Imm;
388    } ShifterImm;
389    struct {
390      ARM_AM::ShiftOpc ShiftTy;
391      unsigned SrcReg;
392      unsigned ShiftReg;
393      unsigned ShiftImm;
394    } RegShiftedReg;
395    struct {
396      ARM_AM::ShiftOpc ShiftTy;
397      unsigned SrcReg;
398      unsigned ShiftImm;
399    } RegShiftedImm;
400    struct {
401      unsigned Imm;
402    } RotImm;
403    struct {
404      unsigned LSB;
405      unsigned Width;
406    } Bitfield;
407  };
408
409  ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
410public:
411  ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
412    Kind = o.Kind;
413    StartLoc = o.StartLoc;
414    EndLoc = o.EndLoc;
415    switch (Kind) {
416    case k_CondCode:
417      CC = o.CC;
418      break;
419    case k_ITCondMask:
420      ITMask = o.ITMask;
421      break;
422    case k_Token:
423      Tok = o.Tok;
424      break;
425    case k_CCOut:
426    case k_Register:
427      Reg = o.Reg;
428      break;
429    case k_RegisterList:
430    case k_DPRRegisterList:
431    case k_SPRRegisterList:
432      Registers = o.Registers;
433      break;
434    case k_VectorList:
435    case k_VectorListAllLanes:
436    case k_VectorListIndexed:
437      VectorList = o.VectorList;
438      break;
439    case k_CoprocNum:
440    case k_CoprocReg:
441      Cop = o.Cop;
442      break;
443    case k_CoprocOption:
444      CoprocOption = o.CoprocOption;
445      break;
446    case k_Immediate:
447      Imm = o.Imm;
448      break;
449    case k_MemBarrierOpt:
450      MBOpt = o.MBOpt;
451      break;
452    case k_Memory:
453      Memory = o.Memory;
454      break;
455    case k_PostIndexRegister:
456      PostIdxReg = o.PostIdxReg;
457      break;
458    case k_MSRMask:
459      MMask = o.MMask;
460      break;
461    case k_ProcIFlags:
462      IFlags = o.IFlags;
463      break;
464    case k_ShifterImmediate:
465      ShifterImm = o.ShifterImm;
466      break;
467    case k_ShiftedRegister:
468      RegShiftedReg = o.RegShiftedReg;
469      break;
470    case k_ShiftedImmediate:
471      RegShiftedImm = o.RegShiftedImm;
472      break;
473    case k_RotateImmediate:
474      RotImm = o.RotImm;
475      break;
476    case k_BitfieldDescriptor:
477      Bitfield = o.Bitfield;
478      break;
479    case k_VectorIndex:
480      VectorIndex = o.VectorIndex;
481      break;
482    }
483  }
484
485  /// getStartLoc - Get the location of the first token of this operand.
486  SMLoc getStartLoc() const { return StartLoc; }
487  /// getEndLoc - Get the location of the last token of this operand.
488  SMLoc getEndLoc() const { return EndLoc; }
489
490  SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
491
492  ARMCC::CondCodes getCondCode() const {
493    assert(Kind == k_CondCode && "Invalid access!");
494    return CC.Val;
495  }
496
497  unsigned getCoproc() const {
498    assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
499    return Cop.Val;
500  }
501
502  StringRef getToken() const {
503    assert(Kind == k_Token && "Invalid access!");
504    return StringRef(Tok.Data, Tok.Length);
505  }
506
507  unsigned getReg() const {
508    assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
509    return Reg.RegNum;
510  }
511
512  const SmallVectorImpl<unsigned> &getRegList() const {
513    assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
514            Kind == k_SPRRegisterList) && "Invalid access!");
515    return Registers;
516  }
517
518  const MCExpr *getImm() const {
519    assert(isImm() && "Invalid access!");
520    return Imm.Val;
521  }
522
523  unsigned getVectorIndex() const {
524    assert(Kind == k_VectorIndex && "Invalid access!");
525    return VectorIndex.Val;
526  }
527
528  ARM_MB::MemBOpt getMemBarrierOpt() const {
529    assert(Kind == k_MemBarrierOpt && "Invalid access!");
530    return MBOpt.Val;
531  }
532
533  ARM_PROC::IFlags getProcIFlags() const {
534    assert(Kind == k_ProcIFlags && "Invalid access!");
535    return IFlags.Val;
536  }
537
538  unsigned getMSRMask() const {
539    assert(Kind == k_MSRMask && "Invalid access!");
540    return MMask.Val;
541  }
542
543  bool isCoprocNum() const { return Kind == k_CoprocNum; }
544  bool isCoprocReg() const { return Kind == k_CoprocReg; }
545  bool isCoprocOption() const { return Kind == k_CoprocOption; }
546  bool isCondCode() const { return Kind == k_CondCode; }
547  bool isCCOut() const { return Kind == k_CCOut; }
548  bool isITMask() const { return Kind == k_ITCondMask; }
549  bool isITCondCode() const { return Kind == k_CondCode; }
550  bool isImm() const { return Kind == k_Immediate; }
551  bool isFPImm() const {
552    if (!isImm()) return false;
553    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
554    if (!CE) return false;
555    int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
556    return Val != -1;
557  }
558  bool isFBits16() const {
559    if (!isImm()) return false;
560    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
561    if (!CE) return false;
562    int64_t Value = CE->getValue();
563    return Value >= 0 && Value <= 16;
564  }
565  bool isFBits32() const {
566    if (!isImm()) return false;
567    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
568    if (!CE) return false;
569    int64_t Value = CE->getValue();
570    return Value >= 1 && Value <= 32;
571  }
572  bool isImm8s4() const {
573    if (!isImm()) return false;
574    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
575    if (!CE) return false;
576    int64_t Value = CE->getValue();
577    return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
578  }
579  bool isImm0_1020s4() const {
580    if (!isImm()) return false;
581    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
582    if (!CE) return false;
583    int64_t Value = CE->getValue();
584    return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
585  }
586  bool isImm0_508s4() const {
587    if (!isImm()) return false;
588    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
589    if (!CE) return false;
590    int64_t Value = CE->getValue();
591    return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
592  }
593  bool isImm0_508s4Neg() const {
594    if (!isImm()) return false;
595    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
596    if (!CE) return false;
597    int64_t Value = -CE->getValue();
598    // explicitly exclude zero. we want that to use the normal 0_508 version.
599    return ((Value & 3) == 0) && Value > 0 && Value <= 508;
600  }
601  bool isImm0_255() const {
602    if (!isImm()) return false;
603    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
604    if (!CE) return false;
605    int64_t Value = CE->getValue();
606    return Value >= 0 && Value < 256;
607  }
608  bool isImm0_4095() const {
609    if (!isImm()) return false;
610    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
611    if (!CE) return false;
612    int64_t Value = CE->getValue();
613    return Value >= 0 && Value < 4096;
614  }
615  bool isImm0_4095Neg() const {
616    if (!isImm()) return false;
617    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
618    if (!CE) return false;
619    int64_t Value = -CE->getValue();
620    return Value > 0 && Value < 4096;
621  }
622  bool isImm0_1() const {
623    if (!isImm()) return false;
624    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
625    if (!CE) return false;
626    int64_t Value = CE->getValue();
627    return Value >= 0 && Value < 2;
628  }
629  bool isImm0_3() const {
630    if (!isImm()) return false;
631    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
632    if (!CE) return false;
633    int64_t Value = CE->getValue();
634    return Value >= 0 && Value < 4;
635  }
636  bool isImm0_7() const {
637    if (!isImm()) return false;
638    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
639    if (!CE) return false;
640    int64_t Value = CE->getValue();
641    return Value >= 0 && Value < 8;
642  }
643  bool isImm0_15() const {
644    if (!isImm()) return false;
645    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
646    if (!CE) return false;
647    int64_t Value = CE->getValue();
648    return Value >= 0 && Value < 16;
649  }
650  bool isImm0_31() const {
651    if (!isImm()) return false;
652    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
653    if (!CE) return false;
654    int64_t Value = CE->getValue();
655    return Value >= 0 && Value < 32;
656  }
657  bool isImm0_63() const {
658    if (!isImm()) return false;
659    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
660    if (!CE) return false;
661    int64_t Value = CE->getValue();
662    return Value >= 0 && Value < 64;
663  }
664  bool isImm8() const {
665    if (!isImm()) return false;
666    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
667    if (!CE) return false;
668    int64_t Value = CE->getValue();
669    return Value == 8;
670  }
671  bool isImm16() const {
672    if (!isImm()) return false;
673    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
674    if (!CE) return false;
675    int64_t Value = CE->getValue();
676    return Value == 16;
677  }
678  bool isImm32() const {
679    if (!isImm()) return false;
680    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
681    if (!CE) return false;
682    int64_t Value = CE->getValue();
683    return Value == 32;
684  }
685  bool isShrImm8() const {
686    if (!isImm()) return false;
687    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
688    if (!CE) return false;
689    int64_t Value = CE->getValue();
690    return Value > 0 && Value <= 8;
691  }
692  bool isShrImm16() const {
693    if (!isImm()) return false;
694    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
695    if (!CE) return false;
696    int64_t Value = CE->getValue();
697    return Value > 0 && Value <= 16;
698  }
699  bool isShrImm32() const {
700    if (!isImm()) return false;
701    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
702    if (!CE) return false;
703    int64_t Value = CE->getValue();
704    return Value > 0 && Value <= 32;
705  }
706  bool isShrImm64() const {
707    if (!isImm()) return false;
708    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
709    if (!CE) return false;
710    int64_t Value = CE->getValue();
711    return Value > 0 && Value <= 64;
712  }
713  bool isImm1_7() const {
714    if (!isImm()) return false;
715    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
716    if (!CE) return false;
717    int64_t Value = CE->getValue();
718    return Value > 0 && Value < 8;
719  }
720  bool isImm1_15() const {
721    if (!isImm()) return false;
722    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
723    if (!CE) return false;
724    int64_t Value = CE->getValue();
725    return Value > 0 && Value < 16;
726  }
727  bool isImm1_31() const {
728    if (!isImm()) return false;
729    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
730    if (!CE) return false;
731    int64_t Value = CE->getValue();
732    return Value > 0 && Value < 32;
733  }
734  bool isImm1_16() const {
735    if (!isImm()) return false;
736    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
737    if (!CE) return false;
738    int64_t Value = CE->getValue();
739    return Value > 0 && Value < 17;
740  }
741  bool isImm1_32() const {
742    if (!isImm()) return false;
743    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
744    if (!CE) return false;
745    int64_t Value = CE->getValue();
746    return Value > 0 && Value < 33;
747  }
748  bool isImm0_32() const {
749    if (!isImm()) return false;
750    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
751    if (!CE) return false;
752    int64_t Value = CE->getValue();
753    return Value >= 0 && Value < 33;
754  }
755  bool isImm0_65535() const {
756    if (!isImm()) return false;
757    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
758    if (!CE) return false;
759    int64_t Value = CE->getValue();
760    return Value >= 0 && Value < 65536;
761  }
762  bool isImm0_65535Expr() const {
763    if (!isImm()) return false;
764    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
765    // If it's not a constant expression, it'll generate a fixup and be
766    // handled later.
767    if (!CE) return true;
768    int64_t Value = CE->getValue();
769    return Value >= 0 && Value < 65536;
770  }
771  bool isImm24bit() const {
772    if (!isImm()) return false;
773    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
774    if (!CE) return false;
775    int64_t Value = CE->getValue();
776    return Value >= 0 && Value <= 0xffffff;
777  }
778  bool isImmThumbSR() const {
779    if (!isImm()) return false;
780    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
781    if (!CE) return false;
782    int64_t Value = CE->getValue();
783    return Value > 0 && Value < 33;
784  }
785  bool isPKHLSLImm() const {
786    if (!isImm()) return false;
787    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
788    if (!CE) return false;
789    int64_t Value = CE->getValue();
790    return Value >= 0 && Value < 32;
791  }
792  bool isPKHASRImm() const {
793    if (!isImm()) return false;
794    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
795    if (!CE) return false;
796    int64_t Value = CE->getValue();
797    return Value > 0 && Value <= 32;
798  }
799  bool isAdrLabel() const {
800    // If we have an immediate that's not a constant, treat it as a label
801    // reference needing a fixup. If it is a constant, but it can't fit
802    // into shift immediate encoding, we reject it.
803    if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
804    else return (isARMSOImm() || isARMSOImmNeg());
805  }
806  bool isARMSOImm() const {
807    if (!isImm()) return false;
808    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
809    if (!CE) return false;
810    int64_t Value = CE->getValue();
811    return ARM_AM::getSOImmVal(Value) != -1;
812  }
813  bool isARMSOImmNot() const {
814    if (!isImm()) return false;
815    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
816    if (!CE) return false;
817    int64_t Value = CE->getValue();
818    return ARM_AM::getSOImmVal(~Value) != -1;
819  }
820  bool isARMSOImmNeg() const {
821    if (!isImm()) return false;
822    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
823    if (!CE) return false;
824    int64_t Value = CE->getValue();
825    // Only use this when not representable as a plain so_imm.
826    return ARM_AM::getSOImmVal(Value) == -1 &&
827      ARM_AM::getSOImmVal(-Value) != -1;
828  }
829  bool isT2SOImm() const {
830    if (!isImm()) return false;
831    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
832    if (!CE) return false;
833    int64_t Value = CE->getValue();
834    return ARM_AM::getT2SOImmVal(Value) != -1;
835  }
836  bool isT2SOImmNot() const {
837    if (!isImm()) return false;
838    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
839    if (!CE) return false;
840    int64_t Value = CE->getValue();
841    return ARM_AM::getT2SOImmVal(~Value) != -1;
842  }
843  bool isT2SOImmNeg() const {
844    if (!isImm()) return false;
845    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
846    if (!CE) return false;
847    int64_t Value = CE->getValue();
848    // Only use this when not representable as a plain so_imm.
849    return ARM_AM::getT2SOImmVal(Value) == -1 &&
850      ARM_AM::getT2SOImmVal(-Value) != -1;
851  }
852  bool isSetEndImm() const {
853    if (!isImm()) return false;
854    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
855    if (!CE) return false;
856    int64_t Value = CE->getValue();
857    return Value == 1 || Value == 0;
858  }
859  bool isReg() const { return Kind == k_Register; }
860  bool isRegList() const { return Kind == k_RegisterList; }
861  bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
862  bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
863  bool isToken() const { return Kind == k_Token; }
864  bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
865  bool isMemory() const { return Kind == k_Memory; }
866  bool isShifterImm() const { return Kind == k_ShifterImmediate; }
867  bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
868  bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
869  bool isRotImm() const { return Kind == k_RotateImmediate; }
870  bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
871  bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
872  bool isPostIdxReg() const {
873    return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
874  }
875  bool isMemNoOffset(bool alignOK = false) const {
876    if (!isMemory())
877      return false;
878    // No offset of any kind.
879    return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
880     (alignOK || Memory.Alignment == 0);
881  }
882  bool isMemPCRelImm12() const {
883    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
884      return false;
885    // Base register must be PC.
886    if (Memory.BaseRegNum != ARM::PC)
887      return false;
888    // Immediate offset in range [-4095, 4095].
889    if (!Memory.OffsetImm) return true;
890    int64_t Val = Memory.OffsetImm->getValue();
891    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
892  }
893  bool isAlignedMemory() const {
894    return isMemNoOffset(true);
895  }
896  bool isAddrMode2() const {
897    if (!isMemory() || Memory.Alignment != 0) return false;
898    // Check for register offset.
899    if (Memory.OffsetRegNum) return true;
900    // Immediate offset in range [-4095, 4095].
901    if (!Memory.OffsetImm) return true;
902    int64_t Val = Memory.OffsetImm->getValue();
903    return Val > -4096 && Val < 4096;
904  }
905  bool isAM2OffsetImm() const {
906    if (!isImm()) return false;
907    // Immediate offset in range [-4095, 4095].
908    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
909    if (!CE) return false;
910    int64_t Val = CE->getValue();
911    return Val > -4096 && Val < 4096;
912  }
913  bool isAddrMode3() const {
914    // If we have an immediate that's not a constant, treat it as a label
915    // reference needing a fixup. If it is a constant, it's something else
916    // and we reject it.
917    if (isImm() && !isa<MCConstantExpr>(getImm()))
918      return true;
919    if (!isMemory() || Memory.Alignment != 0) return false;
920    // No shifts are legal for AM3.
921    if (Memory.ShiftType != ARM_AM::no_shift) return false;
922    // Check for register offset.
923    if (Memory.OffsetRegNum) return true;
924    // Immediate offset in range [-255, 255].
925    if (!Memory.OffsetImm) return true;
926    int64_t Val = Memory.OffsetImm->getValue();
927    // The #-0 offset is encoded as INT32_MIN, and we have to check
928    // for this too.
929    return (Val > -256 && Val < 256) || Val == INT32_MIN;
930  }
931  bool isAM3Offset() const {
932    if (Kind != k_Immediate && Kind != k_PostIndexRegister)
933      return false;
934    if (Kind == k_PostIndexRegister)
935      return PostIdxReg.ShiftTy == ARM_AM::no_shift;
936    // Immediate offset in range [-255, 255].
937    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
938    if (!CE) return false;
939    int64_t Val = CE->getValue();
940    // Special case, #-0 is INT32_MIN.
941    return (Val > -256 && Val < 256) || Val == INT32_MIN;
942  }
943  bool isAddrMode5() const {
944    // If we have an immediate that's not a constant, treat it as a label
945    // reference needing a fixup. If it is a constant, it's something else
946    // and we reject it.
947    if (isImm() && !isa<MCConstantExpr>(getImm()))
948      return true;
949    if (!isMemory() || Memory.Alignment != 0) return false;
950    // Check for register offset.
951    if (Memory.OffsetRegNum) return false;
952    // Immediate offset in range [-1020, 1020] and a multiple of 4.
953    if (!Memory.OffsetImm) return true;
954    int64_t Val = Memory.OffsetImm->getValue();
955    return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
956      Val == INT32_MIN;
957  }
958  bool isMemTBB() const {
959    if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
960        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
961      return false;
962    return true;
963  }
964  bool isMemTBH() const {
965    if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
966        Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
967        Memory.Alignment != 0 )
968      return false;
969    return true;
970  }
971  bool isMemRegOffset() const {
972    if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0)
973      return false;
974    return true;
975  }
976  bool isT2MemRegOffset() const {
977    if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
978        Memory.Alignment != 0)
979      return false;
980    // Only lsl #{0, 1, 2, 3} allowed.
981    if (Memory.ShiftType == ARM_AM::no_shift)
982      return true;
983    if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
984      return false;
985    return true;
986  }
987  bool isMemThumbRR() const {
988    // Thumb reg+reg addressing is simple. Just two registers, a base and
989    // an offset. No shifts, negations or any other complicating factors.
990    if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
991        Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
992      return false;
993    return isARMLowRegister(Memory.BaseRegNum) &&
994      (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
995  }
996  bool isMemThumbRIs4() const {
997    if (!isMemory() || Memory.OffsetRegNum != 0 ||
998        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
999      return false;
1000    // Immediate offset, multiple of 4 in range [0, 124].
1001    if (!Memory.OffsetImm) return true;
1002    int64_t Val = Memory.OffsetImm->getValue();
1003    return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1004  }
1005  bool isMemThumbRIs2() const {
1006    if (!isMemory() || Memory.OffsetRegNum != 0 ||
1007        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1008      return false;
1009    // Immediate offset, multiple of 4 in range [0, 62].
1010    if (!Memory.OffsetImm) return true;
1011    int64_t Val = Memory.OffsetImm->getValue();
1012    return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1013  }
1014  bool isMemThumbRIs1() const {
1015    if (!isMemory() || Memory.OffsetRegNum != 0 ||
1016        !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1017      return false;
1018    // Immediate offset in range [0, 31].
1019    if (!Memory.OffsetImm) return true;
1020    int64_t Val = Memory.OffsetImm->getValue();
1021    return Val >= 0 && Val <= 31;
1022  }
1023  bool isMemThumbSPI() const {
1024    if (!isMemory() || Memory.OffsetRegNum != 0 ||
1025        Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1026      return false;
1027    // Immediate offset, multiple of 4 in range [0, 1020].
1028    if (!Memory.OffsetImm) return true;
1029    int64_t Val = Memory.OffsetImm->getValue();
1030    return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1031  }
1032  bool isMemImm8s4Offset() const {
1033    // If we have an immediate that's not a constant, treat it as a label
1034    // reference needing a fixup. If it is a constant, it's something else
1035    // and we reject it.
1036    if (isImm() && !isa<MCConstantExpr>(getImm()))
1037      return true;
1038    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1039      return false;
1040    // Immediate offset a multiple of 4 in range [-1020, 1020].
1041    if (!Memory.OffsetImm) return true;
1042    int64_t Val = Memory.OffsetImm->getValue();
1043    // Special case, #-0 is INT32_MIN.
1044    return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1045  }
1046  bool isMemImm0_1020s4Offset() const {
1047    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1048      return false;
1049    // Immediate offset a multiple of 4 in range [0, 1020].
1050    if (!Memory.OffsetImm) return true;
1051    int64_t Val = Memory.OffsetImm->getValue();
1052    return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1053  }
1054  bool isMemImm8Offset() const {
1055    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1056      return false;
1057    // Base reg of PC isn't allowed for these encodings.
1058    if (Memory.BaseRegNum == ARM::PC) return false;
1059    // Immediate offset in range [-255, 255].
1060    if (!Memory.OffsetImm) return true;
1061    int64_t Val = Memory.OffsetImm->getValue();
1062    return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1063  }
1064  bool isMemPosImm8Offset() const {
1065    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1066      return false;
1067    // Immediate offset in range [0, 255].
1068    if (!Memory.OffsetImm) return true;
1069    int64_t Val = Memory.OffsetImm->getValue();
1070    return Val >= 0 && Val < 256;
1071  }
1072  bool isMemNegImm8Offset() const {
1073    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1074      return false;
1075    // Base reg of PC isn't allowed for these encodings.
1076    if (Memory.BaseRegNum == ARM::PC) return false;
1077    // Immediate offset in range [-255, -1].
1078    if (!Memory.OffsetImm) return false;
1079    int64_t Val = Memory.OffsetImm->getValue();
1080    return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1081  }
1082  bool isMemUImm12Offset() const {
1083    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1084      return false;
1085    // Immediate offset in range [0, 4095].
1086    if (!Memory.OffsetImm) return true;
1087    int64_t Val = Memory.OffsetImm->getValue();
1088    return (Val >= 0 && Val < 4096);
1089  }
1090  bool isMemImm12Offset() const {
1091    // If we have an immediate that's not a constant, treat it as a label
1092    // reference needing a fixup. If it is a constant, it's something else
1093    // and we reject it.
1094    if (isImm() && !isa<MCConstantExpr>(getImm()))
1095      return true;
1096
1097    if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1098      return false;
1099    // Immediate offset in range [-4095, 4095].
1100    if (!Memory.OffsetImm) return true;
1101    int64_t Val = Memory.OffsetImm->getValue();
1102    return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1103  }
1104  bool isPostIdxImm8() const {
1105    if (!isImm()) return false;
1106    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1107    if (!CE) return false;
1108    int64_t Val = CE->getValue();
1109    return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1110  }
1111  bool isPostIdxImm8s4() const {
1112    if (!isImm()) return false;
1113    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1114    if (!CE) return false;
1115    int64_t Val = CE->getValue();
1116    return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1117      (Val == INT32_MIN);
1118  }
1119
1120  bool isMSRMask() const { return Kind == k_MSRMask; }
1121  bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1122
1123  // NEON operands.
1124  bool isSingleSpacedVectorList() const {
1125    return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1126  }
1127  bool isDoubleSpacedVectorList() const {
1128    return Kind == k_VectorList && VectorList.isDoubleSpaced;
1129  }
1130  bool isVecListOneD() const {
1131    if (!isSingleSpacedVectorList()) return false;
1132    return VectorList.Count == 1;
1133  }
1134
1135  bool isVecListDPair() const {
1136    if (!isSingleSpacedVectorList()) return false;
1137    return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1138              .contains(VectorList.RegNum));
1139  }
1140
1141  bool isVecListThreeD() const {
1142    if (!isSingleSpacedVectorList()) return false;
1143    return VectorList.Count == 3;
1144  }
1145
1146  bool isVecListFourD() const {
1147    if (!isSingleSpacedVectorList()) return false;
1148    return VectorList.Count == 4;
1149  }
1150
1151  bool isVecListDPairSpaced() const {
1152    if (isSingleSpacedVectorList()) return false;
1153    return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1154              .contains(VectorList.RegNum));
1155  }
1156
1157  bool isVecListThreeQ() const {
1158    if (!isDoubleSpacedVectorList()) return false;
1159    return VectorList.Count == 3;
1160  }
1161
1162  bool isVecListFourQ() const {
1163    if (!isDoubleSpacedVectorList()) return false;
1164    return VectorList.Count == 4;
1165  }
1166
1167  bool isSingleSpacedVectorAllLanes() const {
1168    return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1169  }
1170  bool isDoubleSpacedVectorAllLanes() const {
1171    return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1172  }
1173  bool isVecListOneDAllLanes() const {
1174    if (!isSingleSpacedVectorAllLanes()) return false;
1175    return VectorList.Count == 1;
1176  }
1177
1178  bool isVecListDPairAllLanes() const {
1179    if (!isSingleSpacedVectorAllLanes()) return false;
1180    return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1181              .contains(VectorList.RegNum));
1182  }
1183
1184  bool isVecListDPairSpacedAllLanes() const {
1185    if (!isDoubleSpacedVectorAllLanes()) return false;
1186    return VectorList.Count == 2;
1187  }
1188
1189  bool isVecListThreeDAllLanes() const {
1190    if (!isSingleSpacedVectorAllLanes()) return false;
1191    return VectorList.Count == 3;
1192  }
1193
1194  bool isVecListThreeQAllLanes() const {
1195    if (!isDoubleSpacedVectorAllLanes()) return false;
1196    return VectorList.Count == 3;
1197  }
1198
1199  bool isVecListFourDAllLanes() const {
1200    if (!isSingleSpacedVectorAllLanes()) return false;
1201    return VectorList.Count == 4;
1202  }
1203
1204  bool isVecListFourQAllLanes() const {
1205    if (!isDoubleSpacedVectorAllLanes()) return false;
1206    return VectorList.Count == 4;
1207  }
1208
1209  bool isSingleSpacedVectorIndexed() const {
1210    return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1211  }
1212  bool isDoubleSpacedVectorIndexed() const {
1213    return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1214  }
1215  bool isVecListOneDByteIndexed() const {
1216    if (!isSingleSpacedVectorIndexed()) return false;
1217    return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1218  }
1219
1220  bool isVecListOneDHWordIndexed() const {
1221    if (!isSingleSpacedVectorIndexed()) return false;
1222    return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1223  }
1224
1225  bool isVecListOneDWordIndexed() const {
1226    if (!isSingleSpacedVectorIndexed()) return false;
1227    return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1228  }
1229
1230  bool isVecListTwoDByteIndexed() const {
1231    if (!isSingleSpacedVectorIndexed()) return false;
1232    return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1233  }
1234
1235  bool isVecListTwoDHWordIndexed() const {
1236    if (!isSingleSpacedVectorIndexed()) return false;
1237    return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1238  }
1239
1240  bool isVecListTwoQWordIndexed() const {
1241    if (!isDoubleSpacedVectorIndexed()) return false;
1242    return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1243  }
1244
1245  bool isVecListTwoQHWordIndexed() const {
1246    if (!isDoubleSpacedVectorIndexed()) return false;
1247    return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1248  }
1249
1250  bool isVecListTwoDWordIndexed() const {
1251    if (!isSingleSpacedVectorIndexed()) return false;
1252    return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1253  }
1254
1255  bool isVecListThreeDByteIndexed() const {
1256    if (!isSingleSpacedVectorIndexed()) return false;
1257    return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1258  }
1259
1260  bool isVecListThreeDHWordIndexed() const {
1261    if (!isSingleSpacedVectorIndexed()) return false;
1262    return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1263  }
1264
1265  bool isVecListThreeQWordIndexed() const {
1266    if (!isDoubleSpacedVectorIndexed()) return false;
1267    return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1268  }
1269
1270  bool isVecListThreeQHWordIndexed() const {
1271    if (!isDoubleSpacedVectorIndexed()) return false;
1272    return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1273  }
1274
1275  bool isVecListThreeDWordIndexed() const {
1276    if (!isSingleSpacedVectorIndexed()) return false;
1277    return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1278  }
1279
1280  bool isVecListFourDByteIndexed() const {
1281    if (!isSingleSpacedVectorIndexed()) return false;
1282    return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1283  }
1284
1285  bool isVecListFourDHWordIndexed() const {
1286    if (!isSingleSpacedVectorIndexed()) return false;
1287    return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1288  }
1289
1290  bool isVecListFourQWordIndexed() const {
1291    if (!isDoubleSpacedVectorIndexed()) return false;
1292    return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1293  }
1294
1295  bool isVecListFourQHWordIndexed() const {
1296    if (!isDoubleSpacedVectorIndexed()) return false;
1297    return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1298  }
1299
1300  bool isVecListFourDWordIndexed() const {
1301    if (!isSingleSpacedVectorIndexed()) return false;
1302    return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1303  }
1304
1305  bool isVectorIndex8() const {
1306    if (Kind != k_VectorIndex) return false;
1307    return VectorIndex.Val < 8;
1308  }
1309  bool isVectorIndex16() const {
1310    if (Kind != k_VectorIndex) return false;
1311    return VectorIndex.Val < 4;
1312  }
1313  bool isVectorIndex32() const {
1314    if (Kind != k_VectorIndex) return false;
1315    return VectorIndex.Val < 2;
1316  }
1317
1318  bool isNEONi8splat() const {
1319    if (!isImm()) return false;
1320    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1321    // Must be a constant.
1322    if (!CE) return false;
1323    int64_t Value = CE->getValue();
1324    // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1325    // value.
1326    return Value >= 0 && Value < 256;
1327  }
1328
1329  bool isNEONi16splat() const {
1330    if (!isImm()) return false;
1331    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1332    // Must be a constant.
1333    if (!CE) return false;
1334    int64_t Value = CE->getValue();
1335    // i16 value in the range [0,255] or [0x0100, 0xff00]
1336    return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1337  }
1338
1339  bool isNEONi32splat() const {
1340    if (!isImm()) return false;
1341    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1342    // Must be a constant.
1343    if (!CE) return false;
1344    int64_t Value = CE->getValue();
1345    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1346    return (Value >= 0 && Value < 256) ||
1347      (Value >= 0x0100 && Value <= 0xff00) ||
1348      (Value >= 0x010000 && Value <= 0xff0000) ||
1349      (Value >= 0x01000000 && Value <= 0xff000000);
1350  }
1351
1352  bool isNEONi32vmov() const {
1353    if (!isImm()) return false;
1354    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1355    // Must be a constant.
1356    if (!CE) return false;
1357    int64_t Value = CE->getValue();
1358    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1359    // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1360    return (Value >= 0 && Value < 256) ||
1361      (Value >= 0x0100 && Value <= 0xff00) ||
1362      (Value >= 0x010000 && Value <= 0xff0000) ||
1363      (Value >= 0x01000000 && Value <= 0xff000000) ||
1364      (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1365      (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1366  }
1367  bool isNEONi32vmovNeg() const {
1368    if (!isImm()) return false;
1369    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1370    // Must be a constant.
1371    if (!CE) return false;
1372    int64_t Value = ~CE->getValue();
1373    // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1374    // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1375    return (Value >= 0 && Value < 256) ||
1376      (Value >= 0x0100 && Value <= 0xff00) ||
1377      (Value >= 0x010000 && Value <= 0xff0000) ||
1378      (Value >= 0x01000000 && Value <= 0xff000000) ||
1379      (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1380      (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1381  }
1382
1383  bool isNEONi64splat() const {
1384    if (!isImm()) return false;
1385    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1386    // Must be a constant.
1387    if (!CE) return false;
1388    uint64_t Value = CE->getValue();
1389    // i64 value with each byte being either 0 or 0xff.
1390    for (unsigned i = 0; i < 8; ++i)
1391      if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1392    return true;
1393  }
1394
1395  void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1396    // Add as immediates when possible.  Null MCExpr = 0.
1397    if (Expr == 0)
1398      Inst.addOperand(MCOperand::CreateImm(0));
1399    else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1400      Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1401    else
1402      Inst.addOperand(MCOperand::CreateExpr(Expr));
1403  }
1404
1405  void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1406    assert(N == 2 && "Invalid number of operands!");
1407    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1408    unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1409    Inst.addOperand(MCOperand::CreateReg(RegNum));
1410  }
1411
1412  void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1413    assert(N == 1 && "Invalid number of operands!");
1414    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1415  }
1416
1417  void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1418    assert(N == 1 && "Invalid number of operands!");
1419    Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1420  }
1421
1422  void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1423    assert(N == 1 && "Invalid number of operands!");
1424    Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1425  }
1426
1427  void addITMaskOperands(MCInst &Inst, unsigned N) const {
1428    assert(N == 1 && "Invalid number of operands!");
1429    Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1430  }
1431
1432  void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1433    assert(N == 1 && "Invalid number of operands!");
1434    Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1435  }
1436
1437  void addCCOutOperands(MCInst &Inst, unsigned N) const {
1438    assert(N == 1 && "Invalid number of operands!");
1439    Inst.addOperand(MCOperand::CreateReg(getReg()));
1440  }
1441
1442  void addRegOperands(MCInst &Inst, unsigned N) const {
1443    assert(N == 1 && "Invalid number of operands!");
1444    Inst.addOperand(MCOperand::CreateReg(getReg()));
1445  }
1446
1447  void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1448    assert(N == 3 && "Invalid number of operands!");
1449    assert(isRegShiftedReg() &&
1450           "addRegShiftedRegOperands() on non RegShiftedReg!");
1451    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1452    Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1453    Inst.addOperand(MCOperand::CreateImm(
1454      ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1455  }
1456
1457  void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1458    assert(N == 2 && "Invalid number of operands!");
1459    assert(isRegShiftedImm() &&
1460           "addRegShiftedImmOperands() on non RegShiftedImm!");
1461    Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1462    // Shift of #32 is encoded as 0 where permitted
1463    unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1464    Inst.addOperand(MCOperand::CreateImm(
1465      ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1466  }
1467
1468  void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1469    assert(N == 1 && "Invalid number of operands!");
1470    Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1471                                         ShifterImm.Imm));
1472  }
1473
1474  void addRegListOperands(MCInst &Inst, unsigned N) const {
1475    assert(N == 1 && "Invalid number of operands!");
1476    const SmallVectorImpl<unsigned> &RegList = getRegList();
1477    for (SmallVectorImpl<unsigned>::const_iterator
1478           I = RegList.begin(), E = RegList.end(); I != E; ++I)
1479      Inst.addOperand(MCOperand::CreateReg(*I));
1480  }
1481
1482  void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1483    addRegListOperands(Inst, N);
1484  }
1485
1486  void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1487    addRegListOperands(Inst, N);
1488  }
1489
1490  void addRotImmOperands(MCInst &Inst, unsigned N) const {
1491    assert(N == 1 && "Invalid number of operands!");
1492    // Encoded as val>>3. The printer handles display as 8, 16, 24.
1493    Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1494  }
1495
1496  void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1497    assert(N == 1 && "Invalid number of operands!");
1498    // Munge the lsb/width into a bitfield mask.
1499    unsigned lsb = Bitfield.LSB;
1500    unsigned width = Bitfield.Width;
1501    // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1502    uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1503                      (32 - (lsb + width)));
1504    Inst.addOperand(MCOperand::CreateImm(Mask));
1505  }
1506
1507  void addImmOperands(MCInst &Inst, unsigned N) const {
1508    assert(N == 1 && "Invalid number of operands!");
1509    addExpr(Inst, getImm());
1510  }
1511
1512  void addFBits16Operands(MCInst &Inst, unsigned N) const {
1513    assert(N == 1 && "Invalid number of operands!");
1514    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1515    Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1516  }
1517
1518  void addFBits32Operands(MCInst &Inst, unsigned N) const {
1519    assert(N == 1 && "Invalid number of operands!");
1520    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1521    Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1522  }
1523
1524  void addFPImmOperands(MCInst &Inst, unsigned N) const {
1525    assert(N == 1 && "Invalid number of operands!");
1526    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1527    int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1528    Inst.addOperand(MCOperand::CreateImm(Val));
1529  }
1530
1531  void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1532    assert(N == 1 && "Invalid number of operands!");
1533    // FIXME: We really want to scale the value here, but the LDRD/STRD
1534    // instruction don't encode operands that way yet.
1535    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1536    Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1537  }
1538
1539  void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1540    assert(N == 1 && "Invalid number of operands!");
1541    // The immediate is scaled by four in the encoding and is stored
1542    // in the MCInst as such. Lop off the low two bits here.
1543    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1544    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1545  }
1546
1547  void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1548    assert(N == 1 && "Invalid number of operands!");
1549    // The immediate is scaled by four in the encoding and is stored
1550    // in the MCInst as such. Lop off the low two bits here.
1551    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1552    Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1553  }
1554
1555  void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1556    assert(N == 1 && "Invalid number of operands!");
1557    // The immediate is scaled by four in the encoding and is stored
1558    // in the MCInst as such. Lop off the low two bits here.
1559    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1560    Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1561  }
1562
1563  void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1564    assert(N == 1 && "Invalid number of operands!");
1565    // The constant encodes as the immediate-1, and we store in the instruction
1566    // the bits as encoded, so subtract off one here.
1567    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1568    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1569  }
1570
1571  void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1572    assert(N == 1 && "Invalid number of operands!");
1573    // The constant encodes as the immediate-1, and we store in the instruction
1574    // the bits as encoded, so subtract off one here.
1575    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1576    Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1577  }
1578
1579  void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1580    assert(N == 1 && "Invalid number of operands!");
1581    // The constant encodes as the immediate, except for 32, which encodes as
1582    // zero.
1583    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1584    unsigned Imm = CE->getValue();
1585    Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1586  }
1587
1588  void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1589    assert(N == 1 && "Invalid number of operands!");
1590    // An ASR value of 32 encodes as 0, so that's how we want to add it to
1591    // the instruction as well.
1592    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1593    int Val = CE->getValue();
1594    Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1595  }
1596
1597  void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1598    assert(N == 1 && "Invalid number of operands!");
1599    // The operand is actually a t2_so_imm, but we have its bitwise
1600    // negation in the assembly source, so twiddle it here.
1601    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1602    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1603  }
1604
1605  void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1606    assert(N == 1 && "Invalid number of operands!");
1607    // The operand is actually a t2_so_imm, but we have its
1608    // negation in the assembly source, so twiddle it here.
1609    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1610    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1611  }
1612
1613  void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1614    assert(N == 1 && "Invalid number of operands!");
1615    // The operand is actually an imm0_4095, but we have its
1616    // negation in the assembly source, so twiddle it here.
1617    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1618    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1619  }
1620
1621  void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1622    assert(N == 1 && "Invalid number of operands!");
1623    // The operand is actually a so_imm, but we have its bitwise
1624    // negation in the assembly source, so twiddle it here.
1625    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1626    Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1627  }
1628
1629  void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1630    assert(N == 1 && "Invalid number of operands!");
1631    // The operand is actually a so_imm, but we have its
1632    // negation in the assembly source, so twiddle it here.
1633    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1634    Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1635  }
1636
1637  void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1638    assert(N == 1 && "Invalid number of operands!");
1639    Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1640  }
1641
1642  void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1643    assert(N == 1 && "Invalid number of operands!");
1644    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1645  }
1646
1647  void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1648    assert(N == 1 && "Invalid number of operands!");
1649    int32_t Imm = Memory.OffsetImm->getValue();
1650    // FIXME: Handle #-0
1651    if (Imm == INT32_MIN) Imm = 0;
1652    Inst.addOperand(MCOperand::CreateImm(Imm));
1653  }
1654
1655  void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1656    assert(N == 1 && "Invalid number of operands!");
1657    assert(isImm() && "Not an immediate!");
1658
1659    // If we have an immediate that's not a constant, treat it as a label
1660    // reference needing a fixup.
1661    if (!isa<MCConstantExpr>(getImm())) {
1662      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1663      return;
1664    }
1665
1666    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1667    int Val = CE->getValue();
1668    Inst.addOperand(MCOperand::CreateImm(Val));
1669  }
1670
1671  void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1672    assert(N == 2 && "Invalid number of operands!");
1673    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1674    Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1675  }
1676
1677  void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1678    assert(N == 3 && "Invalid number of operands!");
1679    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1680    if (!Memory.OffsetRegNum) {
1681      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1682      // Special case for #-0
1683      if (Val == INT32_MIN) Val = 0;
1684      if (Val < 0) Val = -Val;
1685      Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1686    } else {
1687      // For register offset, we encode the shift type and negation flag
1688      // here.
1689      Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1690                              Memory.ShiftImm, Memory.ShiftType);
1691    }
1692    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1693    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1694    Inst.addOperand(MCOperand::CreateImm(Val));
1695  }
1696
1697  void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1698    assert(N == 2 && "Invalid number of operands!");
1699    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1700    assert(CE && "non-constant AM2OffsetImm operand!");
1701    int32_t Val = CE->getValue();
1702    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1703    // Special case for #-0
1704    if (Val == INT32_MIN) Val = 0;
1705    if (Val < 0) Val = -Val;
1706    Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1707    Inst.addOperand(MCOperand::CreateReg(0));
1708    Inst.addOperand(MCOperand::CreateImm(Val));
1709  }
1710
1711  void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1712    assert(N == 3 && "Invalid number of operands!");
1713    // If we have an immediate that's not a constant, treat it as a label
1714    // reference needing a fixup. If it is a constant, it's something else
1715    // and we reject it.
1716    if (isImm()) {
1717      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1718      Inst.addOperand(MCOperand::CreateReg(0));
1719      Inst.addOperand(MCOperand::CreateImm(0));
1720      return;
1721    }
1722
1723    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1724    if (!Memory.OffsetRegNum) {
1725      ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1726      // Special case for #-0
1727      if (Val == INT32_MIN) Val = 0;
1728      if (Val < 0) Val = -Val;
1729      Val = ARM_AM::getAM3Opc(AddSub, Val);
1730    } else {
1731      // For register offset, we encode the shift type and negation flag
1732      // here.
1733      Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1734    }
1735    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1736    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1737    Inst.addOperand(MCOperand::CreateImm(Val));
1738  }
1739
1740  void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1741    assert(N == 2 && "Invalid number of operands!");
1742    if (Kind == k_PostIndexRegister) {
1743      int32_t Val =
1744        ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1745      Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1746      Inst.addOperand(MCOperand::CreateImm(Val));
1747      return;
1748    }
1749
1750    // Constant offset.
1751    const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1752    int32_t Val = CE->getValue();
1753    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1754    // Special case for #-0
1755    if (Val == INT32_MIN) Val = 0;
1756    if (Val < 0) Val = -Val;
1757    Val = ARM_AM::getAM3Opc(AddSub, Val);
1758    Inst.addOperand(MCOperand::CreateReg(0));
1759    Inst.addOperand(MCOperand::CreateImm(Val));
1760  }
1761
1762  void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1763    assert(N == 2 && "Invalid number of operands!");
1764    // If we have an immediate that's not a constant, treat it as a label
1765    // reference needing a fixup. If it is a constant, it's something else
1766    // and we reject it.
1767    if (isImm()) {
1768      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1769      Inst.addOperand(MCOperand::CreateImm(0));
1770      return;
1771    }
1772
1773    // The lower two bits are always zero and as such are not encoded.
1774    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1775    ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1776    // Special case for #-0
1777    if (Val == INT32_MIN) Val = 0;
1778    if (Val < 0) Val = -Val;
1779    Val = ARM_AM::getAM5Opc(AddSub, Val);
1780    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1781    Inst.addOperand(MCOperand::CreateImm(Val));
1782  }
1783
1784  void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1785    assert(N == 2 && "Invalid number of operands!");
1786    // If we have an immediate that's not a constant, treat it as a label
1787    // reference needing a fixup. If it is a constant, it's something else
1788    // and we reject it.
1789    if (isImm()) {
1790      Inst.addOperand(MCOperand::CreateExpr(getImm()));
1791      Inst.addOperand(MCOperand::CreateImm(0));
1792      return;
1793    }
1794
1795    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1796    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1797    Inst.addOperand(MCOperand::CreateImm(Val));
1798  }
1799
1800  void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1801    assert(N == 2 && "Invalid number of operands!");
1802    // The lower two bits are always zero and as such are not encoded.
1803    int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1804    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1805    Inst.addOperand(MCOperand::CreateImm(Val));
1806  }
1807
1808  void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1809    assert(N == 2 && "Invalid number of operands!");
1810    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1811    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1812    Inst.addOperand(MCOperand::CreateImm(Val));
1813  }
1814
1815  void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1816    addMemImm8OffsetOperands(Inst, N);
1817  }
1818
1819  void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1820    addMemImm8OffsetOperands(Inst, N);
1821  }
1822
1823  void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1824    assert(N == 2 && "Invalid number of operands!");
1825    // If this is an immediate, it's a label reference.
1826    if (isImm()) {
1827      addExpr(Inst, getImm());
1828      Inst.addOperand(MCOperand::CreateImm(0));
1829      return;
1830    }
1831
1832    // Otherwise, it's a normal memory reg+offset.
1833    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1834    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1835    Inst.addOperand(MCOperand::CreateImm(Val));
1836  }
1837
1838  void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1839    assert(N == 2 && "Invalid number of operands!");
1840    // If this is an immediate, it's a label reference.
1841    if (isImm()) {
1842      addExpr(Inst, getImm());
1843      Inst.addOperand(MCOperand::CreateImm(0));
1844      return;
1845    }
1846
1847    // Otherwise, it's a normal memory reg+offset.
1848    int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1849    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1850    Inst.addOperand(MCOperand::CreateImm(Val));
1851  }
1852
1853  void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1854    assert(N == 2 && "Invalid number of operands!");
1855    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1856    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1857  }
1858
1859  void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1860    assert(N == 2 && "Invalid number of operands!");
1861    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1862    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1863  }
1864
1865  void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1866    assert(N == 3 && "Invalid number of operands!");
1867    unsigned Val =
1868      ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1869                        Memory.ShiftImm, Memory.ShiftType);
1870    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1871    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1872    Inst.addOperand(MCOperand::CreateImm(Val));
1873  }
1874
1875  void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1876    assert(N == 3 && "Invalid number of operands!");
1877    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1878    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1879    Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
1880  }
1881
1882  void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1883    assert(N == 2 && "Invalid number of operands!");
1884    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1885    Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1886  }
1887
1888  void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1889    assert(N == 2 && "Invalid number of operands!");
1890    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1891    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1892    Inst.addOperand(MCOperand::CreateImm(Val));
1893  }
1894
1895  void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1896    assert(N == 2 && "Invalid number of operands!");
1897    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
1898    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1899    Inst.addOperand(MCOperand::CreateImm(Val));
1900  }
1901
1902  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1903    assert(N == 2 && "Invalid number of operands!");
1904    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
1905    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1906    Inst.addOperand(MCOperand::CreateImm(Val));
1907  }
1908
1909  void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1910    assert(N == 2 && "Invalid number of operands!");
1911    int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1912    Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1913    Inst.addOperand(MCOperand::CreateImm(Val));
1914  }
1915
1916  void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1917    assert(N == 1 && "Invalid number of operands!");
1918    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1919    assert(CE && "non-constant post-idx-imm8 operand!");
1920    int Imm = CE->getValue();
1921    bool isAdd = Imm >= 0;
1922    if (Imm == INT32_MIN) Imm = 0;
1923    Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1924    Inst.addOperand(MCOperand::CreateImm(Imm));
1925  }
1926
1927  void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
1928    assert(N == 1 && "Invalid number of operands!");
1929    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1930    assert(CE && "non-constant post-idx-imm8s4 operand!");
1931    int Imm = CE->getValue();
1932    bool isAdd = Imm >= 0;
1933    if (Imm == INT32_MIN) Imm = 0;
1934    // Immediate is scaled by 4.
1935    Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
1936    Inst.addOperand(MCOperand::CreateImm(Imm));
1937  }
1938
1939  void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1940    assert(N == 2 && "Invalid number of operands!");
1941    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1942    Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1943  }
1944
1945  void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1946    assert(N == 2 && "Invalid number of operands!");
1947    Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1948    // The sign, shift type, and shift amount are encoded in a single operand
1949    // using the AM2 encoding helpers.
1950    ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1951    unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1952                                     PostIdxReg.ShiftTy);
1953    Inst.addOperand(MCOperand::CreateImm(Imm));
1954  }
1955
1956  void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1957    assert(N == 1 && "Invalid number of operands!");
1958    Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1959  }
1960
1961  void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1962    assert(N == 1 && "Invalid number of operands!");
1963    Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1964  }
1965
1966  void addVecListOperands(MCInst &Inst, unsigned N) const {
1967    assert(N == 1 && "Invalid number of operands!");
1968    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1969  }
1970
1971  void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
1972    assert(N == 2 && "Invalid number of operands!");
1973    Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1974    Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
1975  }
1976
1977  void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
1978    assert(N == 1 && "Invalid number of operands!");
1979    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1980  }
1981
1982  void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
1983    assert(N == 1 && "Invalid number of operands!");
1984    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1985  }
1986
1987  void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
1988    assert(N == 1 && "Invalid number of operands!");
1989    Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1990  }
1991
1992  void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
1993    assert(N == 1 && "Invalid number of operands!");
1994    // The immediate encodes the type of constant as well as the value.
1995    // Mask in that this is an i8 splat.
1996    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1997    Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
1998  }
1999
2000  void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2001    assert(N == 1 && "Invalid number of operands!");
2002    // The immediate encodes the type of constant as well as the value.
2003    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2004    unsigned Value = CE->getValue();
2005    if (Value >= 256)
2006      Value = (Value >> 8) | 0xa00;
2007    else
2008      Value |= 0x800;
2009    Inst.addOperand(MCOperand::CreateImm(Value));
2010  }
2011
2012  void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2013    assert(N == 1 && "Invalid number of operands!");
2014    // The immediate encodes the type of constant as well as the value.
2015    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2016    unsigned Value = CE->getValue();
2017    if (Value >= 256 && Value <= 0xff00)
2018      Value = (Value >> 8) | 0x200;
2019    else if (Value > 0xffff && Value <= 0xff0000)
2020      Value = (Value >> 16) | 0x400;
2021    else if (Value > 0xffffff)
2022      Value = (Value >> 24) | 0x600;
2023    Inst.addOperand(MCOperand::CreateImm(Value));
2024  }
2025
2026  void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2027    assert(N == 1 && "Invalid number of operands!");
2028    // The immediate encodes the type of constant as well as the value.
2029    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2030    unsigned Value = CE->getValue();
2031    if (Value >= 256 && Value <= 0xffff)
2032      Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2033    else if (Value > 0xffff && Value <= 0xffffff)
2034      Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2035    else if (Value > 0xffffff)
2036      Value = (Value >> 24) | 0x600;
2037    Inst.addOperand(MCOperand::CreateImm(Value));
2038  }
2039
2040  void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2041    assert(N == 1 && "Invalid number of operands!");
2042    // The immediate encodes the type of constant as well as the value.
2043    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2044    unsigned Value = ~CE->getValue();
2045    if (Value >= 256 && Value <= 0xffff)
2046      Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2047    else if (Value > 0xffff && Value <= 0xffffff)
2048      Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2049    else if (Value > 0xffffff)
2050      Value = (Value >> 24) | 0x600;
2051    Inst.addOperand(MCOperand::CreateImm(Value));
2052  }
2053
2054  void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2055    assert(N == 1 && "Invalid number of operands!");
2056    // The immediate encodes the type of constant as well as the value.
2057    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2058    uint64_t Value = CE->getValue();
2059    unsigned Imm = 0;
2060    for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2061      Imm |= (Value & 1) << i;
2062    }
2063    Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2064  }
2065
2066  virtual void print(raw_ostream &OS) const;
2067
2068  static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2069    ARMOperand *Op = new ARMOperand(k_ITCondMask);
2070    Op->ITMask.Mask = Mask;
2071    Op->StartLoc = S;
2072    Op->EndLoc = S;
2073    return Op;
2074  }
2075
2076  static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2077    ARMOperand *Op = new ARMOperand(k_CondCode);
2078    Op->CC.Val = CC;
2079    Op->StartLoc = S;
2080    Op->EndLoc = S;
2081    return Op;
2082  }
2083
2084  static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2085    ARMOperand *Op = new ARMOperand(k_CoprocNum);
2086    Op->Cop.Val = CopVal;
2087    Op->StartLoc = S;
2088    Op->EndLoc = S;
2089    return Op;
2090  }
2091
2092  static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2093    ARMOperand *Op = new ARMOperand(k_CoprocReg);
2094    Op->Cop.Val = CopVal;
2095    Op->StartLoc = S;
2096    Op->EndLoc = S;
2097    return Op;
2098  }
2099
2100  static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2101    ARMOperand *Op = new ARMOperand(k_CoprocOption);
2102    Op->Cop.Val = Val;
2103    Op->StartLoc = S;
2104    Op->EndLoc = E;
2105    return Op;
2106  }
2107
2108  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2109    ARMOperand *Op = new ARMOperand(k_CCOut);
2110    Op->Reg.RegNum = RegNum;
2111    Op->StartLoc = S;
2112    Op->EndLoc = S;
2113    return Op;
2114  }
2115
2116  static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2117    ARMOperand *Op = new ARMOperand(k_Token);
2118    Op->Tok.Data = Str.data();
2119    Op->Tok.Length = Str.size();
2120    Op->StartLoc = S;
2121    Op->EndLoc = S;
2122    return Op;
2123  }
2124
2125  static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2126    ARMOperand *Op = new ARMOperand(k_Register);
2127    Op->Reg.RegNum = RegNum;
2128    Op->StartLoc = S;
2129    Op->EndLoc = E;
2130    return Op;
2131  }
2132
2133  static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2134                                           unsigned SrcReg,
2135                                           unsigned ShiftReg,
2136                                           unsigned ShiftImm,
2137                                           SMLoc S, SMLoc E) {
2138    ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2139    Op->RegShiftedReg.ShiftTy = ShTy;
2140    Op->RegShiftedReg.SrcReg = SrcReg;
2141    Op->RegShiftedReg.ShiftReg = ShiftReg;
2142    Op->RegShiftedReg.ShiftImm = ShiftImm;
2143    Op->StartLoc = S;
2144    Op->EndLoc = E;
2145    return Op;
2146  }
2147
2148  static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2149                                            unsigned SrcReg,
2150                                            unsigned ShiftImm,
2151                                            SMLoc S, SMLoc E) {
2152    ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2153    Op->RegShiftedImm.ShiftTy = ShTy;
2154    Op->RegShiftedImm.SrcReg = SrcReg;
2155    Op->RegShiftedImm.ShiftImm = ShiftImm;
2156    Op->StartLoc = S;
2157    Op->EndLoc = E;
2158    return Op;
2159  }
2160
2161  static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2162                                   SMLoc S, SMLoc E) {
2163    ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2164    Op->ShifterImm.isASR = isASR;
2165    Op->ShifterImm.Imm = Imm;
2166    Op->StartLoc = S;
2167    Op->EndLoc = E;
2168    return Op;
2169  }
2170
2171  static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2172    ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2173    Op->RotImm.Imm = Imm;
2174    Op->StartLoc = S;
2175    Op->EndLoc = E;
2176    return Op;
2177  }
2178
2179  static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2180                                    SMLoc S, SMLoc E) {
2181    ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2182    Op->Bitfield.LSB = LSB;
2183    Op->Bitfield.Width = Width;
2184    Op->StartLoc = S;
2185    Op->EndLoc = E;
2186    return Op;
2187  }
2188
2189  static ARMOperand *
2190  CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
2191                SMLoc StartLoc, SMLoc EndLoc) {
2192    KindTy Kind = k_RegisterList;
2193
2194    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
2195      Kind = k_DPRRegisterList;
2196    else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2197             contains(Regs.front().first))
2198      Kind = k_SPRRegisterList;
2199
2200    ARMOperand *Op = new ARMOperand(Kind);
2201    for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
2202           I = Regs.begin(), E = Regs.end(); I != E; ++I)
2203      Op->Registers.push_back(I->first);
2204    array_pod_sort(Op->Registers.begin(), Op->Registers.end());
2205    Op->StartLoc = StartLoc;
2206    Op->EndLoc = EndLoc;
2207    return Op;
2208  }
2209
2210  static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2211                                      bool isDoubleSpaced, SMLoc S, SMLoc E) {
2212    ARMOperand *Op = new ARMOperand(k_VectorList);
2213    Op->VectorList.RegNum = RegNum;
2214    Op->VectorList.Count = Count;
2215    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2216    Op->StartLoc = S;
2217    Op->EndLoc = E;
2218    return Op;
2219  }
2220
2221  static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2222                                              bool isDoubleSpaced,
2223                                              SMLoc S, SMLoc E) {
2224    ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2225    Op->VectorList.RegNum = RegNum;
2226    Op->VectorList.Count = Count;
2227    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2228    Op->StartLoc = S;
2229    Op->EndLoc = E;
2230    return Op;
2231  }
2232
2233  static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2234                                             unsigned Index,
2235                                             bool isDoubleSpaced,
2236                                             SMLoc S, SMLoc E) {
2237    ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2238    Op->VectorList.RegNum = RegNum;
2239    Op->VectorList.Count = Count;
2240    Op->VectorList.LaneIndex = Index;
2241    Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2242    Op->StartLoc = S;
2243    Op->EndLoc = E;
2244    return Op;
2245  }
2246
2247  static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2248                                       MCContext &Ctx) {
2249    ARMOperand *Op = new ARMOperand(k_VectorIndex);
2250    Op->VectorIndex.Val = Idx;
2251    Op->StartLoc = S;
2252    Op->EndLoc = E;
2253    return Op;
2254  }
2255
2256  static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2257    ARMOperand *Op = new ARMOperand(k_Immediate);
2258    Op->Imm.Val = Val;
2259    Op->StartLoc = S;
2260    Op->EndLoc = E;
2261    return Op;
2262  }
2263
2264  static ARMOperand *CreateMem(unsigned BaseRegNum,
2265                               const MCConstantExpr *OffsetImm,
2266                               unsigned OffsetRegNum,
2267                               ARM_AM::ShiftOpc ShiftType,
2268                               unsigned ShiftImm,
2269                               unsigned Alignment,
2270                               bool isNegative,
2271                               SMLoc S, SMLoc E) {
2272    ARMOperand *Op = new ARMOperand(k_Memory);
2273    Op->Memory.BaseRegNum = BaseRegNum;
2274    Op->Memory.OffsetImm = OffsetImm;
2275    Op->Memory.OffsetRegNum = OffsetRegNum;
2276    Op->Memory.ShiftType = ShiftType;
2277    Op->Memory.ShiftImm = ShiftImm;
2278    Op->Memory.Alignment = Alignment;
2279    Op->Memory.isNegative = isNegative;
2280    Op->StartLoc = S;
2281    Op->EndLoc = E;
2282    return Op;
2283  }
2284
2285  static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2286                                      ARM_AM::ShiftOpc ShiftTy,
2287                                      unsigned ShiftImm,
2288                                      SMLoc S, SMLoc E) {
2289    ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2290    Op->PostIdxReg.RegNum = RegNum;
2291    Op->PostIdxReg.isAdd = isAdd;
2292    Op->PostIdxReg.ShiftTy = ShiftTy;
2293    Op->PostIdxReg.ShiftImm = ShiftImm;
2294    Op->StartLoc = S;
2295    Op->EndLoc = E;
2296    return Op;
2297  }
2298
2299  static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2300    ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2301    Op->MBOpt.Val = Opt;
2302    Op->StartLoc = S;
2303    Op->EndLoc = S;
2304    return Op;
2305  }
2306
2307  static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2308    ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2309    Op->IFlags.Val = IFlags;
2310    Op->StartLoc = S;
2311    Op->EndLoc = S;
2312    return Op;
2313  }
2314
2315  static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2316    ARMOperand *Op = new ARMOperand(k_MSRMask);
2317    Op->MMask.Val = MMask;
2318    Op->StartLoc = S;
2319    Op->EndLoc = S;
2320    return Op;
2321  }
2322};
2323
2324} // end anonymous namespace.
2325
2326void ARMOperand::print(raw_ostream &OS) const {
2327  switch (Kind) {
2328  case k_CondCode:
2329    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2330    break;
2331  case k_CCOut:
2332    OS << "<ccout " << getReg() << ">";
2333    break;
2334  case k_ITCondMask: {
2335    static const char *const MaskStr[] = {
2336      "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2337      "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2338    };
2339    assert((ITMask.Mask & 0xf) == ITMask.Mask);
2340    OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2341    break;
2342  }
2343  case k_CoprocNum:
2344    OS << "<coprocessor number: " << getCoproc() << ">";
2345    break;
2346  case k_CoprocReg:
2347    OS << "<coprocessor register: " << getCoproc() << ">";
2348    break;
2349  case k_CoprocOption:
2350    OS << "<coprocessor option: " << CoprocOption.Val << ">";
2351    break;
2352  case k_MSRMask:
2353    OS << "<mask: " << getMSRMask() << ">";
2354    break;
2355  case k_Immediate:
2356    getImm()->print(OS);
2357    break;
2358  case k_MemBarrierOpt:
2359    OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
2360    break;
2361  case k_Memory:
2362    OS << "<memory "
2363       << " base:" << Memory.BaseRegNum;
2364    OS << ">";
2365    break;
2366  case k_PostIndexRegister:
2367    OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2368       << PostIdxReg.RegNum;
2369    if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2370      OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2371         << PostIdxReg.ShiftImm;
2372    OS << ">";
2373    break;
2374  case k_ProcIFlags: {
2375    OS << "<ARM_PROC::";
2376    unsigned IFlags = getProcIFlags();
2377    for (int i=2; i >= 0; --i)
2378      if (IFlags & (1 << i))
2379        OS << ARM_PROC::IFlagsToString(1 << i);
2380    OS << ">";
2381    break;
2382  }
2383  case k_Register:
2384    OS << "<register " << getReg() << ">";
2385    break;
2386  case k_ShifterImmediate:
2387    OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2388       << " #" << ShifterImm.Imm << ">";
2389    break;
2390  case k_ShiftedRegister:
2391    OS << "<so_reg_reg "
2392       << RegShiftedReg.SrcReg << " "
2393       << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2394       << " " << RegShiftedReg.ShiftReg << ">";
2395    break;
2396  case k_ShiftedImmediate:
2397    OS << "<so_reg_imm "
2398       << RegShiftedImm.SrcReg << " "
2399       << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2400       << " #" << RegShiftedImm.ShiftImm << ">";
2401    break;
2402  case k_RotateImmediate:
2403    OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2404    break;
2405  case k_BitfieldDescriptor:
2406    OS << "<bitfield " << "lsb: " << Bitfield.LSB
2407       << ", width: " << Bitfield.Width << ">";
2408    break;
2409  case k_RegisterList:
2410  case k_DPRRegisterList:
2411  case k_SPRRegisterList: {
2412    OS << "<register_list ";
2413
2414    const SmallVectorImpl<unsigned> &RegList = getRegList();
2415    for (SmallVectorImpl<unsigned>::const_iterator
2416           I = RegList.begin(), E = RegList.end(); I != E; ) {
2417      OS << *I;
2418      if (++I < E) OS << ", ";
2419    }
2420
2421    OS << ">";
2422    break;
2423  }
2424  case k_VectorList:
2425    OS << "<vector_list " << VectorList.Count << " * "
2426       << VectorList.RegNum << ">";
2427    break;
2428  case k_VectorListAllLanes:
2429    OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2430       << VectorList.RegNum << ">";
2431    break;
2432  case k_VectorListIndexed:
2433    OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2434       << VectorList.Count << " * " << VectorList.RegNum << ">";
2435    break;
2436  case k_Token:
2437    OS << "'" << getToken() << "'";
2438    break;
2439  case k_VectorIndex:
2440    OS << "<vectorindex " << getVectorIndex() << ">";
2441    break;
2442  }
2443}
2444
2445/// @name Auto-generated Match Functions
2446/// {
2447
2448static unsigned MatchRegisterName(StringRef Name);
2449
2450/// }
2451
2452bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2453                                 SMLoc &StartLoc, SMLoc &EndLoc) {
2454  StartLoc = Parser.getTok().getLoc();
2455  RegNo = tryParseRegister();
2456  EndLoc = Parser.getTok().getLoc();
2457
2458  return (RegNo == (unsigned)-1);
2459}
2460
2461/// Try to parse a register name.  The token must be an Identifier when called,
2462/// and if it is a register name the token is eaten and the register number is
2463/// returned.  Otherwise return -1.
2464///
2465int ARMAsmParser::tryParseRegister() {
2466  const AsmToken &Tok = Parser.getTok();
2467  if (Tok.isNot(AsmToken::Identifier)) return -1;
2468
2469  std::string lowerCase = Tok.getString().lower();
2470  unsigned RegNum = MatchRegisterName(lowerCase);
2471  if (!RegNum) {
2472    RegNum = StringSwitch<unsigned>(lowerCase)
2473      .Case("r13", ARM::SP)
2474      .Case("r14", ARM::LR)
2475      .Case("r15", ARM::PC)
2476      .Case("ip", ARM::R12)
2477      // Additional register name aliases for 'gas' compatibility.
2478      .Case("a1", ARM::R0)
2479      .Case("a2", ARM::R1)
2480      .Case("a3", ARM::R2)
2481      .Case("a4", ARM::R3)
2482      .Case("v1", ARM::R4)
2483      .Case("v2", ARM::R5)
2484      .Case("v3", ARM::R6)
2485      .Case("v4", ARM::R7)
2486      .Case("v5", ARM::R8)
2487      .Case("v6", ARM::R9)
2488      .Case("v7", ARM::R10)
2489      .Case("v8", ARM::R11)
2490      .Case("sb", ARM::R9)
2491      .Case("sl", ARM::R10)
2492      .Case("fp", ARM::R11)
2493      .Default(0);
2494  }
2495  if (!RegNum) {
2496    // Check for aliases registered via .req. Canonicalize to lower case.
2497    // That's more consistent since register names are case insensitive, and
2498    // it's how the original entry was passed in from MC/MCParser/AsmParser.
2499    StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2500    // If no match, return failure.
2501    if (Entry == RegisterReqs.end())
2502      return -1;
2503    Parser.Lex(); // Eat identifier token.
2504    return Entry->getValue();
2505  }
2506
2507  Parser.Lex(); // Eat identifier token.
2508
2509  return RegNum;
2510}
2511
2512// Try to parse a shifter  (e.g., "lsl <amt>"). On success, return 0.
2513// If a recoverable error occurs, return 1. If an irrecoverable error
2514// occurs, return -1. An irrecoverable error is one where tokens have been
2515// consumed in the process of trying to parse the shifter (i.e., when it is
2516// indeed a shifter operand, but malformed).
2517int ARMAsmParser::tryParseShiftRegister(
2518                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2519  SMLoc S = Parser.getTok().getLoc();
2520  const AsmToken &Tok = Parser.getTok();
2521  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2522
2523  std::string lowerCase = Tok.getString().lower();
2524  ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2525      .Case("asl", ARM_AM::lsl)
2526      .Case("lsl", ARM_AM::lsl)
2527      .Case("lsr", ARM_AM::lsr)
2528      .Case("asr", ARM_AM::asr)
2529      .Case("ror", ARM_AM::ror)
2530      .Case("rrx", ARM_AM::rrx)
2531      .Default(ARM_AM::no_shift);
2532
2533  if (ShiftTy == ARM_AM::no_shift)
2534    return 1;
2535
2536  Parser.Lex(); // Eat the operator.
2537
2538  // The source register for the shift has already been added to the
2539  // operand list, so we need to pop it off and combine it into the shifted
2540  // register operand instead.
2541  OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2542  if (!PrevOp->isReg())
2543    return Error(PrevOp->getStartLoc(), "shift must be of a register");
2544  int SrcReg = PrevOp->getReg();
2545  int64_t Imm = 0;
2546  int ShiftReg = 0;
2547  if (ShiftTy == ARM_AM::rrx) {
2548    // RRX Doesn't have an explicit shift amount. The encoder expects
2549    // the shift register to be the same as the source register. Seems odd,
2550    // but OK.
2551    ShiftReg = SrcReg;
2552  } else {
2553    // Figure out if this is shifted by a constant or a register (for non-RRX).
2554    if (Parser.getTok().is(AsmToken::Hash) ||
2555        Parser.getTok().is(AsmToken::Dollar)) {
2556      Parser.Lex(); // Eat hash.
2557      SMLoc ImmLoc = Parser.getTok().getLoc();
2558      const MCExpr *ShiftExpr = 0;
2559      if (getParser().ParseExpression(ShiftExpr)) {
2560        Error(ImmLoc, "invalid immediate shift value");
2561        return -1;
2562      }
2563      // The expression must be evaluatable as an immediate.
2564      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2565      if (!CE) {
2566        Error(ImmLoc, "invalid immediate shift value");
2567        return -1;
2568      }
2569      // Range check the immediate.
2570      // lsl, ror: 0 <= imm <= 31
2571      // lsr, asr: 0 <= imm <= 32
2572      Imm = CE->getValue();
2573      if (Imm < 0 ||
2574          ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2575          ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2576        Error(ImmLoc, "immediate shift value out of range");
2577        return -1;
2578      }
2579      // shift by zero is a nop. Always send it through as lsl.
2580      // ('as' compatibility)
2581      if (Imm == 0)
2582        ShiftTy = ARM_AM::lsl;
2583    } else if (Parser.getTok().is(AsmToken::Identifier)) {
2584      ShiftReg = tryParseRegister();
2585      SMLoc L = Parser.getTok().getLoc();
2586      if (ShiftReg == -1) {
2587        Error (L, "expected immediate or register in shift operand");
2588        return -1;
2589      }
2590    } else {
2591      Error (Parser.getTok().getLoc(),
2592                    "expected immediate or register in shift operand");
2593      return -1;
2594    }
2595  }
2596
2597  if (ShiftReg && ShiftTy != ARM_AM::rrx)
2598    Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2599                                                         ShiftReg, Imm,
2600                                               S, Parser.getTok().getLoc()));
2601  else
2602    Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2603                                               S, Parser.getTok().getLoc()));
2604
2605  return 0;
2606}
2607
2608
2609/// Try to parse a register name.  The token must be an Identifier when called.
2610/// If it's a register, an AsmOperand is created. Another AsmOperand is created
2611/// if there is a "writeback". 'true' if it's not a register.
2612///
2613/// TODO this is likely to change to allow different register types and or to
2614/// parse for a specific register type.
2615bool ARMAsmParser::
2616tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2617  SMLoc S = Parser.getTok().getLoc();
2618  int RegNo = tryParseRegister();
2619  if (RegNo == -1)
2620    return true;
2621
2622  Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
2623
2624  const AsmToken &ExclaimTok = Parser.getTok();
2625  if (ExclaimTok.is(AsmToken::Exclaim)) {
2626    Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2627                                               ExclaimTok.getLoc()));
2628    Parser.Lex(); // Eat exclaim token
2629    return false;
2630  }
2631
2632  // Also check for an index operand. This is only legal for vector registers,
2633  // but that'll get caught OK in operand matching, so we don't need to
2634  // explicitly filter everything else out here.
2635  if (Parser.getTok().is(AsmToken::LBrac)) {
2636    SMLoc SIdx = Parser.getTok().getLoc();
2637    Parser.Lex(); // Eat left bracket token.
2638
2639    const MCExpr *ImmVal;
2640    if (getParser().ParseExpression(ImmVal))
2641      return true;
2642    const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2643    if (!MCE)
2644      return TokError("immediate value expected for vector index");
2645
2646    SMLoc E = Parser.getTok().getLoc();
2647    if (Parser.getTok().isNot(AsmToken::RBrac))
2648      return Error(E, "']' expected");
2649
2650    Parser.Lex(); // Eat right bracket token.
2651
2652    Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2653                                                     SIdx, E,
2654                                                     getContext()));
2655  }
2656
2657  return false;
2658}
2659
2660/// MatchCoprocessorOperandName - Try to parse an coprocessor related
2661/// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2662/// "c5", ...
2663static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2664  // Use the same layout as the tablegen'erated register name matcher. Ugly,
2665  // but efficient.
2666  switch (Name.size()) {
2667  default: return -1;
2668  case 2:
2669    if (Name[0] != CoprocOp)
2670      return -1;
2671    switch (Name[1]) {
2672    default:  return -1;
2673    case '0': return 0;
2674    case '1': return 1;
2675    case '2': return 2;
2676    case '3': return 3;
2677    case '4': return 4;
2678    case '5': return 5;
2679    case '6': return 6;
2680    case '7': return 7;
2681    case '8': return 8;
2682    case '9': return 9;
2683    }
2684  case 3:
2685    if (Name[0] != CoprocOp || Name[1] != '1')
2686      return -1;
2687    switch (Name[2]) {
2688    default:  return -1;
2689    case '0': return 10;
2690    case '1': return 11;
2691    case '2': return 12;
2692    case '3': return 13;
2693    case '4': return 14;
2694    case '5': return 15;
2695    }
2696  }
2697}
2698
2699/// parseITCondCode - Try to parse a condition code for an IT instruction.
2700ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2701parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2702  SMLoc S = Parser.getTok().getLoc();
2703  const AsmToken &Tok = Parser.getTok();
2704  if (!Tok.is(AsmToken::Identifier))
2705    return MatchOperand_NoMatch;
2706  unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
2707    .Case("eq", ARMCC::EQ)
2708    .Case("ne", ARMCC::NE)
2709    .Case("hs", ARMCC::HS)
2710    .Case("cs", ARMCC::HS)
2711    .Case("lo", ARMCC::LO)
2712    .Case("cc", ARMCC::LO)
2713    .Case("mi", ARMCC::MI)
2714    .Case("pl", ARMCC::PL)
2715    .Case("vs", ARMCC::VS)
2716    .Case("vc", ARMCC::VC)
2717    .Case("hi", ARMCC::HI)
2718    .Case("ls", ARMCC::LS)
2719    .Case("ge", ARMCC::GE)
2720    .Case("lt", ARMCC::LT)
2721    .Case("gt", ARMCC::GT)
2722    .Case("le", ARMCC::LE)
2723    .Case("al", ARMCC::AL)
2724    .Default(~0U);
2725  if (CC == ~0U)
2726    return MatchOperand_NoMatch;
2727  Parser.Lex(); // Eat the token.
2728
2729  Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2730
2731  return MatchOperand_Success;
2732}
2733
2734/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2735/// token must be an Identifier when called, and if it is a coprocessor
2736/// number, the token is eaten and the operand is added to the operand list.
2737ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2738parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2739  SMLoc S = Parser.getTok().getLoc();
2740  const AsmToken &Tok = Parser.getTok();
2741  if (Tok.isNot(AsmToken::Identifier))
2742    return MatchOperand_NoMatch;
2743
2744  int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2745  if (Num == -1)
2746    return MatchOperand_NoMatch;
2747
2748  Parser.Lex(); // Eat identifier token.
2749  Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2750  return MatchOperand_Success;
2751}
2752
2753/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2754/// token must be an Identifier when called, and if it is a coprocessor
2755/// number, the token is eaten and the operand is added to the operand list.
2756ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2757parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2758  SMLoc S = Parser.getTok().getLoc();
2759  const AsmToken &Tok = Parser.getTok();
2760  if (Tok.isNot(AsmToken::Identifier))
2761    return MatchOperand_NoMatch;
2762
2763  int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2764  if (Reg == -1)
2765    return MatchOperand_NoMatch;
2766
2767  Parser.Lex(); // Eat identifier token.
2768  Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2769  return MatchOperand_Success;
2770}
2771
2772/// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2773/// coproc_option : '{' imm0_255 '}'
2774ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2775parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2776  SMLoc S = Parser.getTok().getLoc();
2777
2778  // If this isn't a '{', this isn't a coprocessor immediate operand.
2779  if (Parser.getTok().isNot(AsmToken::LCurly))
2780    return MatchOperand_NoMatch;
2781  Parser.Lex(); // Eat the '{'
2782
2783  const MCExpr *Expr;
2784  SMLoc Loc = Parser.getTok().getLoc();
2785  if (getParser().ParseExpression(Expr)) {
2786    Error(Loc, "illegal expression");
2787    return MatchOperand_ParseFail;
2788  }
2789  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2790  if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2791    Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2792    return MatchOperand_ParseFail;
2793  }
2794  int Val = CE->getValue();
2795
2796  // Check for and consume the closing '}'
2797  if (Parser.getTok().isNot(AsmToken::RCurly))
2798    return MatchOperand_ParseFail;
2799  SMLoc E = Parser.getTok().getLoc();
2800  Parser.Lex(); // Eat the '}'
2801
2802  Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2803  return MatchOperand_Success;
2804}
2805
2806// For register list parsing, we need to map from raw GPR register numbering
2807// to the enumeration values. The enumeration values aren't sorted by
2808// register number due to our using "sp", "lr" and "pc" as canonical names.
2809static unsigned getNextRegister(unsigned Reg) {
2810  // If this is a GPR, we need to do it manually, otherwise we can rely
2811  // on the sort ordering of the enumeration since the other reg-classes
2812  // are sane.
2813  if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2814    return Reg + 1;
2815  switch(Reg) {
2816  default: llvm_unreachable("Invalid GPR number!");
2817  case ARM::R0:  return ARM::R1;  case ARM::R1:  return ARM::R2;
2818  case ARM::R2:  return ARM::R3;  case ARM::R3:  return ARM::R4;
2819  case ARM::R4:  return ARM::R5;  case ARM::R5:  return ARM::R6;
2820  case ARM::R6:  return ARM::R7;  case ARM::R7:  return ARM::R8;
2821  case ARM::R8:  return ARM::R9;  case ARM::R9:  return ARM::R10;
2822  case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2823  case ARM::R12: return ARM::SP;  case ARM::SP:  return ARM::LR;
2824  case ARM::LR:  return ARM::PC;  case ARM::PC:  return ARM::R0;
2825  }
2826}
2827
2828// Return the low-subreg of a given Q register.
2829static unsigned getDRegFromQReg(unsigned QReg) {
2830  switch (QReg) {
2831  default: llvm_unreachable("expected a Q register!");
2832  case ARM::Q0:  return ARM::D0;
2833  case ARM::Q1:  return ARM::D2;
2834  case ARM::Q2:  return ARM::D4;
2835  case ARM::Q3:  return ARM::D6;
2836  case ARM::Q4:  return ARM::D8;
2837  case ARM::Q5:  return ARM::D10;
2838  case ARM::Q6:  return ARM::D12;
2839  case ARM::Q7:  return ARM::D14;
2840  case ARM::Q8:  return ARM::D16;
2841  case ARM::Q9:  return ARM::D18;
2842  case ARM::Q10: return ARM::D20;
2843  case ARM::Q11: return ARM::D22;
2844  case ARM::Q12: return ARM::D24;
2845  case ARM::Q13: return ARM::D26;
2846  case ARM::Q14: return ARM::D28;
2847  case ARM::Q15: return ARM::D30;
2848  }
2849}
2850
2851/// Parse a register list.
2852bool ARMAsmParser::
2853parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2854  assert(Parser.getTok().is(AsmToken::LCurly) &&
2855         "Token is not a Left Curly Brace");
2856  SMLoc S = Parser.getTok().getLoc();
2857  Parser.Lex(); // Eat '{' token.
2858  SMLoc RegLoc = Parser.getTok().getLoc();
2859
2860  // Check the first register in the list to see what register class
2861  // this is a list of.
2862  int Reg = tryParseRegister();
2863  if (Reg == -1)
2864    return Error(RegLoc, "register expected");
2865
2866  // The reglist instructions have at most 16 registers, so reserve
2867  // space for that many.
2868  SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
2869
2870  // Allow Q regs and just interpret them as the two D sub-registers.
2871  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2872    Reg = getDRegFromQReg(Reg);
2873    Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2874    ++Reg;
2875  }
2876  const MCRegisterClass *RC;
2877  if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2878    RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
2879  else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
2880    RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
2881  else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
2882    RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
2883  else
2884    return Error(RegLoc, "invalid register in register list");
2885
2886  // Store the register.
2887  Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2888
2889  // This starts immediately after the first register token in the list,
2890  // so we can see either a comma or a minus (range separator) as a legal
2891  // next token.
2892  while (Parser.getTok().is(AsmToken::Comma) ||
2893         Parser.getTok().is(AsmToken::Minus)) {
2894    if (Parser.getTok().is(AsmToken::Minus)) {
2895      Parser.Lex(); // Eat the minus.
2896      SMLoc EndLoc = Parser.getTok().getLoc();
2897      int EndReg = tryParseRegister();
2898      if (EndReg == -1)
2899        return Error(EndLoc, "register expected");
2900      // Allow Q regs and just interpret them as the two D sub-registers.
2901      if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
2902        EndReg = getDRegFromQReg(EndReg) + 1;
2903      // If the register is the same as the start reg, there's nothing
2904      // more to do.
2905      if (Reg == EndReg)
2906        continue;
2907      // The register must be in the same register class as the first.
2908      if (!RC->contains(EndReg))
2909        return Error(EndLoc, "invalid register in register list");
2910      // Ranges must go from low to high.
2911      if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
2912        return Error(EndLoc, "bad range in register list");
2913
2914      // Add all the registers in the range to the register list.
2915      while (Reg != EndReg) {
2916        Reg = getNextRegister(Reg);
2917        Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2918      }
2919      continue;
2920    }
2921    Parser.Lex(); // Eat the comma.
2922    RegLoc = Parser.getTok().getLoc();
2923    int OldReg = Reg;
2924    const AsmToken RegTok = Parser.getTok();
2925    Reg = tryParseRegister();
2926    if (Reg == -1)
2927      return Error(RegLoc, "register expected");
2928    // Allow Q regs and just interpret them as the two D sub-registers.
2929    bool isQReg = false;
2930    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2931      Reg = getDRegFromQReg(Reg);
2932      isQReg = true;
2933    }
2934    // The register must be in the same register class as the first.
2935    if (!RC->contains(Reg))
2936      return Error(RegLoc, "invalid register in register list");
2937    // List must be monotonically increasing.
2938    if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
2939      if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2940        Warning(RegLoc, "register list not in ascending order");
2941      else
2942        return Error(RegLoc, "register list not in ascending order");
2943    }
2944    if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
2945      Warning(RegLoc, "duplicated register (" + RegTok.getString() +
2946              ") in register list");
2947      continue;
2948    }
2949    // VFP register lists must also be contiguous.
2950    // It's OK to use the enumeration values directly here rather, as the
2951    // VFP register classes have the enum sorted properly.
2952    if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
2953        Reg != OldReg + 1)
2954      return Error(RegLoc, "non-contiguous register range");
2955    Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2956    if (isQReg)
2957      Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc));
2958  }
2959
2960  SMLoc E = Parser.getTok().getLoc();
2961  if (Parser.getTok().isNot(AsmToken::RCurly))
2962    return Error(E, "'}' expected");
2963  Parser.Lex(); // Eat '}' token.
2964
2965  // Push the register list operand.
2966  Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
2967
2968  // The ARM system instruction variants for LDM/STM have a '^' token here.
2969  if (Parser.getTok().is(AsmToken::Caret)) {
2970    Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
2971    Parser.Lex(); // Eat '^' token.
2972  }
2973
2974  return false;
2975}
2976
2977// Helper function to parse the lane index for vector lists.
2978ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2979parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index) {
2980  Index = 0; // Always return a defined index value.
2981  if (Parser.getTok().is(AsmToken::LBrac)) {
2982    Parser.Lex(); // Eat the '['.
2983    if (Parser.getTok().is(AsmToken::RBrac)) {
2984      // "Dn[]" is the 'all lanes' syntax.
2985      LaneKind = AllLanes;
2986      Parser.Lex(); // Eat the ']'.
2987      return MatchOperand_Success;
2988    }
2989
2990    // There's an optional '#' token here. Normally there wouldn't be, but
2991    // inline assemble puts one in, and it's friendly to accept that.
2992    if (Parser.getTok().is(AsmToken::Hash))
2993      Parser.Lex(); // Eat the '#'
2994
2995    const MCExpr *LaneIndex;
2996    SMLoc Loc = Parser.getTok().getLoc();
2997    if (getParser().ParseExpression(LaneIndex)) {
2998      Error(Loc, "illegal expression");
2999      return MatchOperand_ParseFail;
3000    }
3001    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3002    if (!CE) {
3003      Error(Loc, "lane index must be empty or an integer");
3004      return MatchOperand_ParseFail;
3005    }
3006    if (Parser.getTok().isNot(AsmToken::RBrac)) {
3007      Error(Parser.getTok().getLoc(), "']' expected");
3008      return MatchOperand_ParseFail;
3009    }
3010    Parser.Lex(); // Eat the ']'.
3011    int64_t Val = CE->getValue();
3012
3013    // FIXME: Make this range check context sensitive for .8, .16, .32.
3014    if (Val < 0 || Val > 7) {
3015      Error(Parser.getTok().getLoc(), "lane index out of range");
3016      return MatchOperand_ParseFail;
3017    }
3018    Index = Val;
3019    LaneKind = IndexedLane;
3020    return MatchOperand_Success;
3021  }
3022  LaneKind = NoLanes;
3023  return MatchOperand_Success;
3024}
3025
3026// parse a vector register list
3027ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3028parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3029  VectorLaneTy LaneKind;
3030  unsigned LaneIndex;
3031  SMLoc S = Parser.getTok().getLoc();
3032  // As an extension (to match gas), support a plain D register or Q register
3033  // (without encosing curly braces) as a single or double entry list,
3034  // respectively.
3035  if (Parser.getTok().is(AsmToken::Identifier)) {
3036    int Reg = tryParseRegister();
3037    if (Reg == -1)
3038      return MatchOperand_NoMatch;
3039    SMLoc E = Parser.getTok().getLoc();
3040    if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3041      OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
3042      if (Res != MatchOperand_Success)
3043        return Res;
3044      switch (LaneKind) {
3045      case NoLanes:
3046        E = Parser.getTok().getLoc();
3047        Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3048        break;
3049      case AllLanes:
3050        E = Parser.getTok().getLoc();
3051        Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3052                                                                S, E));
3053        break;
3054      case IndexedLane:
3055        Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3056                                                               LaneIndex,
3057                                                               false, S, E));
3058        break;
3059      }
3060      return MatchOperand_Success;
3061    }
3062    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3063      Reg = getDRegFromQReg(Reg);
3064      OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
3065      if (Res != MatchOperand_Success)
3066        return Res;
3067      switch (LaneKind) {
3068      case NoLanes:
3069        E = Parser.getTok().getLoc();
3070        Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3071                                   &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3072        Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3073        break;
3074      case AllLanes:
3075        E = Parser.getTok().getLoc();
3076        Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3077                                   &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3078        Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3079                                                                S, E));
3080        break;
3081      case IndexedLane:
3082        Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3083                                                               LaneIndex,
3084                                                               false, S, E));
3085        break;
3086      }
3087      return MatchOperand_Success;
3088    }
3089    Error(S, "vector register expected");
3090    return MatchOperand_ParseFail;
3091  }
3092
3093  if (Parser.getTok().isNot(AsmToken::LCurly))
3094    return MatchOperand_NoMatch;
3095
3096  Parser.Lex(); // Eat '{' token.
3097  SMLoc RegLoc = Parser.getTok().getLoc();
3098
3099  int Reg = tryParseRegister();
3100  if (Reg == -1) {
3101    Error(RegLoc, "register expected");
3102    return MatchOperand_ParseFail;
3103  }
3104  unsigned Count = 1;
3105  int Spacing = 0;
3106  unsigned FirstReg = Reg;
3107  // The list is of D registers, but we also allow Q regs and just interpret
3108  // them as the two D sub-registers.
3109  if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3110    FirstReg = Reg = getDRegFromQReg(Reg);
3111    Spacing = 1; // double-spacing requires explicit D registers, otherwise
3112                 // it's ambiguous with four-register single spaced.
3113    ++Reg;
3114    ++Count;
3115  }
3116  if (parseVectorLane(LaneKind, LaneIndex) != MatchOperand_Success)
3117    return MatchOperand_ParseFail;
3118
3119  while (Parser.getTok().is(AsmToken::Comma) ||
3120         Parser.getTok().is(AsmToken::Minus)) {
3121    if (Parser.getTok().is(AsmToken::Minus)) {
3122      if (!Spacing)
3123        Spacing = 1; // Register range implies a single spaced list.
3124      else if (Spacing == 2) {
3125        Error(Parser.getTok().getLoc(),
3126              "sequential registers in double spaced list");
3127        return MatchOperand_ParseFail;
3128      }
3129      Parser.Lex(); // Eat the minus.
3130      SMLoc EndLoc = Parser.getTok().getLoc();
3131      int EndReg = tryParseRegister();
3132      if (EndReg == -1) {
3133        Error(EndLoc, "register expected");
3134        return MatchOperand_ParseFail;
3135      }
3136      // Allow Q regs and just interpret them as the two D sub-registers.
3137      if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3138        EndReg = getDRegFromQReg(EndReg) + 1;
3139      // If the register is the same as the start reg, there's nothing
3140      // more to do.
3141      if (Reg == EndReg)
3142        continue;
3143      // The register must be in the same register class as the first.
3144      if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3145        Error(EndLoc, "invalid register in register list");
3146        return MatchOperand_ParseFail;
3147      }
3148      // Ranges must go from low to high.
3149      if (Reg > EndReg) {
3150        Error(EndLoc, "bad range in register list");
3151        return MatchOperand_ParseFail;
3152      }
3153      // Parse the lane specifier if present.
3154      VectorLaneTy NextLaneKind;
3155      unsigned NextLaneIndex;
3156      if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3157        return MatchOperand_ParseFail;
3158      if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3159        Error(EndLoc, "mismatched lane index in register list");
3160        return MatchOperand_ParseFail;
3161      }
3162      EndLoc = Parser.getTok().getLoc();
3163
3164      // Add all the registers in the range to the register list.
3165      Count += EndReg - Reg;
3166      Reg = EndReg;
3167      continue;
3168    }
3169    Parser.Lex(); // Eat the comma.
3170    RegLoc = Parser.getTok().getLoc();
3171    int OldReg = Reg;
3172    Reg = tryParseRegister();
3173    if (Reg == -1) {
3174      Error(RegLoc, "register expected");
3175      return MatchOperand_ParseFail;
3176    }
3177    // vector register lists must be contiguous.
3178    // It's OK to use the enumeration values directly here rather, as the
3179    // VFP register classes have the enum sorted properly.
3180    //
3181    // The list is of D registers, but we also allow Q regs and just interpret
3182    // them as the two D sub-registers.
3183    if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3184      if (!Spacing)
3185        Spacing = 1; // Register range implies a single spaced list.
3186      else if (Spacing == 2) {
3187        Error(RegLoc,
3188              "invalid register in double-spaced list (must be 'D' register')");
3189        return MatchOperand_ParseFail;
3190      }
3191      Reg = getDRegFromQReg(Reg);
3192      if (Reg != OldReg + 1) {
3193        Error(RegLoc, "non-contiguous register range");
3194        return MatchOperand_ParseFail;
3195      }
3196      ++Reg;
3197      Count += 2;
3198      // Parse the lane specifier if present.
3199      VectorLaneTy NextLaneKind;
3200      unsigned NextLaneIndex;
3201      SMLoc EndLoc = Parser.getTok().getLoc();
3202      if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3203        return MatchOperand_ParseFail;
3204      if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3205        Error(EndLoc, "mismatched lane index in register list");
3206        return MatchOperand_ParseFail;
3207      }
3208      continue;
3209    }
3210    // Normal D register.
3211    // Figure out the register spacing (single or double) of the list if
3212    // we don't know it already.
3213    if (!Spacing)
3214      Spacing = 1 + (Reg == OldReg + 2);
3215
3216    // Just check that it's contiguous and keep going.
3217    if (Reg != OldReg + Spacing) {
3218      Error(RegLoc, "non-contiguous register range");
3219      return MatchOperand_ParseFail;
3220    }
3221    ++Count;
3222    // Parse the lane specifier if present.
3223    VectorLaneTy NextLaneKind;
3224    unsigned NextLaneIndex;
3225    SMLoc EndLoc = Parser.getTok().getLoc();
3226    if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
3227      return MatchOperand_ParseFail;
3228    if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3229      Error(EndLoc, "mismatched lane index in register list");
3230      return MatchOperand_ParseFail;
3231    }
3232  }
3233
3234  SMLoc E = Parser.getTok().getLoc();
3235  if (Parser.getTok().isNot(AsmToken::RCurly)) {
3236    Error(E, "'}' expected");
3237    return MatchOperand_ParseFail;
3238  }
3239  Parser.Lex(); // Eat '}' token.
3240
3241  switch (LaneKind) {
3242  case NoLanes:
3243    // Two-register operands have been converted to the
3244    // composite register classes.
3245    if (Count == 2) {
3246      const MCRegisterClass *RC = (Spacing == 1) ?
3247        &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3248        &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3249      FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3250    }
3251
3252    Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3253                                                    (Spacing == 2), S, E));
3254    break;
3255  case AllLanes:
3256    // Two-register operands have been converted to the
3257    // composite register classes.
3258    if (Count == 2) {
3259      const MCRegisterClass *RC = (Spacing == 1) ?
3260        &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3261        &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3262      FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3263    }
3264    Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3265                                                            (Spacing == 2),
3266                                                            S, E));
3267    break;
3268  case IndexedLane:
3269    Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3270                                                           LaneIndex,
3271                                                           (Spacing == 2),
3272                                                           S, E));
3273    break;
3274  }
3275  return MatchOperand_Success;
3276}
3277
3278/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3279ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3280parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3281  SMLoc S = Parser.getTok().getLoc();
3282  const AsmToken &Tok = Parser.getTok();
3283  unsigned Opt;
3284
3285  if (Tok.is(AsmToken::Identifier)) {
3286    StringRef OptStr = Tok.getString();
3287
3288    Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3289      .Case("sy",    ARM_MB::SY)
3290      .Case("st",    ARM_MB::ST)
3291      .Case("sh",    ARM_MB::ISH)
3292      .Case("ish",   ARM_MB::ISH)
3293      .Case("shst",  ARM_MB::ISHST)
3294      .Case("ishst", ARM_MB::ISHST)
3295      .Case("nsh",   ARM_MB::NSH)
3296      .Case("un",    ARM_MB::NSH)
3297      .Case("nshst", ARM_MB::NSHST)
3298      .Case("unst",  ARM_MB::NSHST)
3299      .Case("osh",   ARM_MB::OSH)
3300      .Case("oshst", ARM_MB::OSHST)
3301      .Default(~0U);
3302
3303    if (Opt == ~0U)
3304      return MatchOperand_NoMatch;
3305
3306    Parser.Lex(); // Eat identifier token.
3307  } else if (Tok.is(AsmToken::Hash) ||
3308             Tok.is(AsmToken::Dollar) ||
3309             Tok.is(AsmToken::Integer)) {
3310    if (Parser.getTok().isNot(AsmToken::Integer))
3311      Parser.Lex(); // Eat the '#'.
3312    SMLoc Loc = Parser.getTok().getLoc();
3313
3314    const MCExpr *MemBarrierID;
3315    if (getParser().ParseExpression(MemBarrierID)) {
3316      Error(Loc, "illegal expression");
3317      return MatchOperand_ParseFail;
3318    }
3319
3320    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3321    if (!CE) {
3322      Error(Loc, "constant expression expected");
3323      return MatchOperand_ParseFail;
3324    }
3325
3326    int Val = CE->getValue();
3327    if (Val & ~0xf) {
3328      Error(Loc, "immediate value out of range");
3329      return MatchOperand_ParseFail;
3330    }
3331
3332    Opt = ARM_MB::RESERVED_0 + Val;
3333  } else
3334    return MatchOperand_ParseFail;
3335
3336  Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3337  return MatchOperand_Success;
3338}
3339
3340/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3341ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3342parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3343  SMLoc S = Parser.getTok().getLoc();
3344  const AsmToken &Tok = Parser.getTok();
3345  if (!Tok.is(AsmToken::Identifier))
3346    return MatchOperand_NoMatch;
3347  StringRef IFlagsStr = Tok.getString();
3348
3349  // An iflags string of "none" is interpreted to mean that none of the AIF
3350  // bits are set.  Not a terribly useful instruction, but a valid encoding.
3351  unsigned IFlags = 0;
3352  if (IFlagsStr != "none") {
3353        for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3354      unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3355        .Case("a", ARM_PROC::A)
3356        .Case("i", ARM_PROC::I)
3357        .Case("f", ARM_PROC::F)
3358        .Default(~0U);
3359
3360      // If some specific iflag is already set, it means that some letter is
3361      // present more than once, this is not acceptable.
3362      if (Flag == ~0U || (IFlags & Flag))
3363        return MatchOperand_NoMatch;
3364
3365      IFlags |= Flag;
3366    }
3367  }
3368
3369  Parser.Lex(); // Eat identifier token.
3370  Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3371  return MatchOperand_Success;
3372}
3373
3374/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3375ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3376parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3377  SMLoc S = Parser.getTok().getLoc();
3378  const AsmToken &Tok = Parser.getTok();
3379  assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
3380  StringRef Mask = Tok.getString();
3381
3382  if (isMClass()) {
3383    // See ARMv6-M 10.1.1
3384    std::string Name = Mask.lower();
3385    unsigned FlagsVal = StringSwitch<unsigned>(Name)
3386      // Note: in the documentation:
3387      //  ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3388      //  for MSR APSR_nzcvq.
3389      // but we do make it an alias here.  This is so to get the "mask encoding"
3390      // bits correct on MSR APSR writes.
3391      //
3392      // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3393      // should really only be allowed when writing a special register.  Note
3394      // they get dropped in the MRS instruction reading a special register as
3395      // the SYSm field is only 8 bits.
3396      //
3397      // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3398      // includes the DSP extension but that is not checked.
3399      .Case("apsr", 0x800)
3400      .Case("apsr_nzcvq", 0x800)
3401      .Case("apsr_g", 0x400)
3402      .Case("apsr_nzcvqg", 0xc00)
3403      .Case("iapsr", 0x801)
3404      .Case("iapsr_nzcvq", 0x801)
3405      .Case("iapsr_g", 0x401)
3406      .Case("iapsr_nzcvqg", 0xc01)
3407      .Case("eapsr", 0x802)
3408      .Case("eapsr_nzcvq", 0x802)
3409      .Case("eapsr_g", 0x402)
3410      .Case("eapsr_nzcvqg", 0xc02)
3411      .Case("xpsr", 0x803)
3412      .Case("xpsr_nzcvq", 0x803)
3413      .Case("xpsr_g", 0x403)
3414      .Case("xpsr_nzcvqg", 0xc03)
3415      .Case("ipsr", 0x805)
3416      .Case("epsr", 0x806)
3417      .Case("iepsr", 0x807)
3418      .Case("msp", 0x808)
3419      .Case("psp", 0x809)
3420      .Case("primask", 0x810)
3421      .Case("basepri", 0x811)
3422      .Case("basepri_max", 0x812)
3423      .Case("faultmask", 0x813)
3424      .Case("control", 0x814)
3425      .Default(~0U);
3426
3427    if (FlagsVal == ~0U)
3428      return MatchOperand_NoMatch;
3429
3430    if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3431      // basepri, basepri_max and faultmask only valid for V7m.
3432      return MatchOperand_NoMatch;
3433
3434    Parser.Lex(); // Eat identifier token.
3435    Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3436    return MatchOperand_Success;
3437  }
3438
3439  // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3440  size_t Start = 0, Next = Mask.find('_');
3441  StringRef Flags = "";
3442  std::string SpecReg = Mask.slice(Start, Next).lower();
3443  if (Next != StringRef::npos)
3444    Flags = Mask.slice(Next+1, Mask.size());
3445
3446  // FlagsVal contains the complete mask:
3447  // 3-0: Mask
3448  // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3449  unsigned FlagsVal = 0;
3450
3451  if (SpecReg == "apsr") {
3452    FlagsVal = StringSwitch<unsigned>(Flags)
3453    .Case("nzcvq",  0x8) // same as CPSR_f
3454    .Case("g",      0x4) // same as CPSR_s
3455    .Case("nzcvqg", 0xc) // same as CPSR_fs
3456    .Default(~0U);
3457
3458    if (FlagsVal == ~0U) {
3459      if (!Flags.empty())
3460        return MatchOperand_NoMatch;
3461      else
3462        FlagsVal = 8; // No flag
3463    }
3464  } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3465    // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3466    if (Flags == "all" || Flags == "")
3467      Flags = "fc";
3468    for (int i = 0, e = Flags.size(); i != e; ++i) {
3469      unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3470      .Case("c", 1)
3471      .Case("x", 2)
3472      .Case("s", 4)
3473      .Case("f", 8)
3474      .Default(~0U);
3475
3476      // If some specific flag is already set, it means that some letter is
3477      // present more than once, this is not acceptable.
3478      if (FlagsVal == ~0U || (FlagsVal & Flag))
3479        return MatchOperand_NoMatch;
3480      FlagsVal |= Flag;
3481    }
3482  } else // No match for special register.
3483    return MatchOperand_NoMatch;
3484
3485  // Special register without flags is NOT equivalent to "fc" flags.
3486  // NOTE: This is a divergence from gas' behavior.  Uncommenting the following
3487  // two lines would enable gas compatibility at the expense of breaking
3488  // round-tripping.
3489  //
3490  // if (!FlagsVal)
3491  //  FlagsVal = 0x9;
3492
3493  // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3494  if (SpecReg == "spsr")
3495    FlagsVal |= 16;
3496
3497  Parser.Lex(); // Eat identifier token.
3498  Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3499  return MatchOperand_Success;
3500}
3501
3502ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3503parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3504            int Low, int High) {
3505  const AsmToken &Tok = Parser.getTok();
3506  if (Tok.isNot(AsmToken::Identifier)) {
3507    Error(Parser.getTok().getLoc(), Op + " operand expected.");
3508    return MatchOperand_ParseFail;
3509  }
3510  StringRef ShiftName = Tok.getString();
3511  std::string LowerOp = Op.lower();
3512  std::string UpperOp = Op.upper();
3513  if (ShiftName != LowerOp && ShiftName != UpperOp) {
3514    Error(Parser.getTok().getLoc(), Op + " operand expected.");
3515    return MatchOperand_ParseFail;
3516  }
3517  Parser.Lex(); // Eat shift type token.
3518
3519  // There must be a '#' and a shift amount.
3520  if (Parser.getTok().isNot(AsmToken::Hash) &&
3521      Parser.getTok().isNot(AsmToken::Dollar)) {
3522    Error(Parser.getTok().getLoc(), "'#' expected");
3523    return MatchOperand_ParseFail;
3524  }
3525  Parser.Lex(); // Eat hash token.
3526
3527  const MCExpr *ShiftAmount;
3528  SMLoc Loc = Parser.getTok().getLoc();
3529  if (getParser().ParseExpression(ShiftAmount)) {
3530    Error(Loc, "illegal expression");
3531    return MatchOperand_ParseFail;
3532  }
3533  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3534  if (!CE) {
3535    Error(Loc, "constant expression expected");
3536    return MatchOperand_ParseFail;
3537  }
3538  int Val = CE->getValue();
3539  if (Val < Low || Val > High) {
3540    Error(Loc, "immediate value out of range");
3541    return MatchOperand_ParseFail;
3542  }
3543
3544  Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
3545
3546  return MatchOperand_Success;
3547}
3548
3549ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3550parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3551  const AsmToken &Tok = Parser.getTok();
3552  SMLoc S = Tok.getLoc();
3553  if (Tok.isNot(AsmToken::Identifier)) {
3554    Error(Tok.getLoc(), "'be' or 'le' operand expected");
3555    return MatchOperand_ParseFail;
3556  }
3557  int Val = StringSwitch<int>(Tok.getString())
3558    .Case("be", 1)
3559    .Case("le", 0)
3560    .Default(-1);
3561  Parser.Lex(); // Eat the token.
3562
3563  if (Val == -1) {
3564    Error(Tok.getLoc(), "'be' or 'le' operand expected");
3565    return MatchOperand_ParseFail;
3566  }
3567  Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3568                                                                  getContext()),
3569                                           S, Parser.getTok().getLoc()));
3570  return MatchOperand_Success;
3571}
3572
3573/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3574/// instructions. Legal values are:
3575///     lsl #n  'n' in [0,31]
3576///     asr #n  'n' in [1,32]
3577///             n == 32 encoded as n == 0.
3578ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3579parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3580  const AsmToken &Tok = Parser.getTok();
3581  SMLoc S = Tok.getLoc();
3582  if (Tok.isNot(AsmToken::Identifier)) {
3583    Error(S, "shift operator 'asr' or 'lsl' expected");
3584    return MatchOperand_ParseFail;
3585  }
3586  StringRef ShiftName = Tok.getString();
3587  bool isASR;
3588  if (ShiftName == "lsl" || ShiftName == "LSL")
3589    isASR = false;
3590  else if (ShiftName == "asr" || ShiftName == "ASR")
3591    isASR = true;
3592  else {
3593    Error(S, "shift operator 'asr' or 'lsl' expected");
3594    return MatchOperand_ParseFail;
3595  }
3596  Parser.Lex(); // Eat the operator.
3597
3598  // A '#' and a shift amount.
3599  if (Parser.getTok().isNot(AsmToken::Hash) &&
3600      Parser.getTok().isNot(AsmToken::Dollar)) {
3601    Error(Parser.getTok().getLoc(), "'#' expected");
3602    return MatchOperand_ParseFail;
3603  }
3604  Parser.Lex(); // Eat hash token.
3605
3606  const MCExpr *ShiftAmount;
3607  SMLoc E = Parser.getTok().getLoc();
3608  if (getParser().ParseExpression(ShiftAmount)) {
3609    Error(E, "malformed shift expression");
3610    return MatchOperand_ParseFail;
3611  }
3612  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3613  if (!CE) {
3614    Error(E, "shift amount must be an immediate");
3615    return MatchOperand_ParseFail;
3616  }
3617
3618  int64_t Val = CE->getValue();
3619  if (isASR) {
3620    // Shift amount must be in [1,32]
3621    if (Val < 1 || Val > 32) {
3622      Error(E, "'asr' shift amount must be in range [1,32]");
3623      return MatchOperand_ParseFail;
3624    }
3625    // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3626    if (isThumb() && Val == 32) {
3627      Error(E, "'asr #32' shift amount not allowed in Thumb mode");
3628      return MatchOperand_ParseFail;
3629    }
3630    if (Val == 32) Val = 0;
3631  } else {
3632    // Shift amount must be in [1,32]
3633    if (Val < 0 || Val > 31) {
3634      Error(E, "'lsr' shift amount must be in range [0,31]");
3635      return MatchOperand_ParseFail;
3636    }
3637  }
3638
3639  E = Parser.getTok().getLoc();
3640  Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
3641
3642  return MatchOperand_Success;
3643}
3644
3645/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3646/// of instructions. Legal values are:
3647///     ror #n  'n' in {0, 8, 16, 24}
3648ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3649parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3650  const AsmToken &Tok = Parser.getTok();
3651  SMLoc S = Tok.getLoc();
3652  if (Tok.isNot(AsmToken::Identifier))
3653    return MatchOperand_NoMatch;
3654  StringRef ShiftName = Tok.getString();
3655  if (ShiftName != "ror" && ShiftName != "ROR")
3656    return MatchOperand_NoMatch;
3657  Parser.Lex(); // Eat the operator.
3658
3659  // A '#' and a rotate amount.
3660  if (Parser.getTok().isNot(AsmToken::Hash) &&
3661      Parser.getTok().isNot(AsmToken::Dollar)) {
3662    Error(Parser.getTok().getLoc(), "'#' expected");
3663    return MatchOperand_ParseFail;
3664  }
3665  Parser.Lex(); // Eat hash token.
3666
3667  const MCExpr *ShiftAmount;
3668  SMLoc E = Parser.getTok().getLoc();
3669  if (getParser().ParseExpression(ShiftAmount)) {
3670    Error(E, "malformed rotate expression");
3671    return MatchOperand_ParseFail;
3672  }
3673  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3674  if (!CE) {
3675    Error(E, "rotate amount must be an immediate");
3676    return MatchOperand_ParseFail;
3677  }
3678
3679  int64_t Val = CE->getValue();
3680  // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3681  // normally, zero is represented in asm by omitting the rotate operand
3682  // entirely.
3683  if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3684    Error(E, "'ror' rotate amount must be 8, 16, or 24");
3685    return MatchOperand_ParseFail;
3686  }
3687
3688  E = Parser.getTok().getLoc();
3689  Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
3690
3691  return MatchOperand_Success;
3692}
3693
3694ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3695parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3696  SMLoc S = Parser.getTok().getLoc();
3697  // The bitfield descriptor is really two operands, the LSB and the width.
3698  if (Parser.getTok().isNot(AsmToken::Hash) &&
3699      Parser.getTok().isNot(AsmToken::Dollar)) {
3700    Error(Parser.getTok().getLoc(), "'#' expected");
3701    return MatchOperand_ParseFail;
3702  }
3703  Parser.Lex(); // Eat hash token.
3704
3705  const MCExpr *LSBExpr;
3706  SMLoc E = Parser.getTok().getLoc();
3707  if (getParser().ParseExpression(LSBExpr)) {
3708    Error(E, "malformed immediate expression");
3709    return MatchOperand_ParseFail;
3710  }
3711  const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3712  if (!CE) {
3713    Error(E, "'lsb' operand must be an immediate");
3714    return MatchOperand_ParseFail;
3715  }
3716
3717  int64_t LSB = CE->getValue();
3718  // The LSB must be in the range [0,31]
3719  if (LSB < 0 || LSB > 31) {
3720    Error(E, "'lsb' operand must be in the range [0,31]");
3721    return MatchOperand_ParseFail;
3722  }
3723  E = Parser.getTok().getLoc();
3724
3725  // Expect another immediate operand.
3726  if (Parser.getTok().isNot(AsmToken::Comma)) {
3727    Error(Parser.getTok().getLoc(), "too few operands");
3728    return MatchOperand_ParseFail;
3729  }
3730  Parser.Lex(); // Eat hash token.
3731  if (Parser.getTok().isNot(AsmToken::Hash) &&
3732      Parser.getTok().isNot(AsmToken::Dollar)) {
3733    Error(Parser.getTok().getLoc(), "'#' expected");
3734    return MatchOperand_ParseFail;
3735  }
3736  Parser.Lex(); // Eat hash token.
3737
3738  const MCExpr *WidthExpr;
3739  if (getParser().ParseExpression(WidthExpr)) {
3740    Error(E, "malformed immediate expression");
3741    return MatchOperand_ParseFail;
3742  }
3743  CE = dyn_cast<MCConstantExpr>(WidthExpr);
3744  if (!CE) {
3745    Error(E, "'width' operand must be an immediate");
3746    return MatchOperand_ParseFail;
3747  }
3748
3749  int64_t Width = CE->getValue();
3750  // The LSB must be in the range [1,32-lsb]
3751  if (Width < 1 || Width > 32 - LSB) {
3752    Error(E, "'width' operand must be in the range [1,32-lsb]");
3753    return MatchOperand_ParseFail;
3754  }
3755  E = Parser.getTok().getLoc();
3756
3757  Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
3758
3759  return MatchOperand_Success;
3760}
3761
3762ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3763parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3764  // Check for a post-index addressing register operand. Specifically:
3765  // postidx_reg := '+' register {, shift}
3766  //              | '-' register {, shift}
3767  //              | register {, shift}
3768
3769  // This method must return MatchOperand_NoMatch without consuming any tokens
3770  // in the case where there is no match, as other alternatives take other
3771  // parse methods.
3772  AsmToken Tok = Parser.getTok();
3773  SMLoc S = Tok.getLoc();
3774  bool haveEaten = false;
3775  bool isAdd = true;
3776  int Reg = -1;
3777  if (Tok.is(AsmToken::Plus)) {
3778    Parser.Lex(); // Eat the '+' token.
3779    haveEaten = true;
3780  } else if (Tok.is(AsmToken::Minus)) {
3781    Parser.Lex(); // Eat the '-' token.
3782    isAdd = false;
3783    haveEaten = true;
3784  }
3785  if (Parser.getTok().is(AsmToken::Identifier))
3786    Reg = tryParseRegister();
3787  if (Reg == -1) {
3788    if (!haveEaten)
3789      return MatchOperand_NoMatch;
3790    Error(Parser.getTok().getLoc(), "register expected");
3791    return MatchOperand_ParseFail;
3792  }
3793  SMLoc E = Parser.getTok().getLoc();
3794
3795  ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3796  unsigned ShiftImm = 0;
3797  if (Parser.getTok().is(AsmToken::Comma)) {
3798    Parser.Lex(); // Eat the ','.
3799    if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
3800      return MatchOperand_ParseFail;
3801  }
3802
3803  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
3804                                                  ShiftImm, S, E));
3805
3806  return MatchOperand_Success;
3807}
3808
3809ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3810parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3811  // Check for a post-index addressing register operand. Specifically:
3812  // am3offset := '+' register
3813  //              | '-' register
3814  //              | register
3815  //              | # imm
3816  //              | # + imm
3817  //              | # - imm
3818
3819  // This method must return MatchOperand_NoMatch without consuming any tokens
3820  // in the case where there is no match, as other alternatives take other
3821  // parse methods.
3822  AsmToken Tok = Parser.getTok();
3823  SMLoc S = Tok.getLoc();
3824
3825  // Do immediates first, as we always parse those if we have a '#'.
3826  if (Parser.getTok().is(AsmToken::Hash) ||
3827      Parser.getTok().is(AsmToken::Dollar)) {
3828    Parser.Lex(); // Eat the '#'.
3829    // Explicitly look for a '-', as we need to encode negative zero
3830    // differently.
3831    bool isNegative = Parser.getTok().is(AsmToken::Minus);
3832    const MCExpr *Offset;
3833    if (getParser().ParseExpression(Offset))
3834      return MatchOperand_ParseFail;
3835    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3836    if (!CE) {
3837      Error(S, "constant expression expected");
3838      return MatchOperand_ParseFail;
3839    }
3840    SMLoc E = Tok.getLoc();
3841    // Negative zero is encoded as the flag value INT32_MIN.
3842    int32_t Val = CE->getValue();
3843    if (isNegative && Val == 0)
3844      Val = INT32_MIN;
3845
3846    Operands.push_back(
3847      ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
3848
3849    return MatchOperand_Success;
3850  }
3851
3852
3853  bool haveEaten = false;
3854  bool isAdd = true;
3855  int Reg = -1;
3856  if (Tok.is(AsmToken::Plus)) {
3857    Parser.Lex(); // Eat the '+' token.
3858    haveEaten = true;
3859  } else if (Tok.is(AsmToken::Minus)) {
3860    Parser.Lex(); // Eat the '-' token.
3861    isAdd = false;
3862    haveEaten = true;
3863  }
3864  if (Parser.getTok().is(AsmToken::Identifier))
3865    Reg = tryParseRegister();
3866  if (Reg == -1) {
3867    if (!haveEaten)
3868      return MatchOperand_NoMatch;
3869    Error(Parser.getTok().getLoc(), "register expected");
3870    return MatchOperand_ParseFail;
3871  }
3872  SMLoc E = Parser.getTok().getLoc();
3873
3874  Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
3875                                                  0, S, E));
3876
3877  return MatchOperand_Success;
3878}
3879
3880/// cvtT2LdrdPre - Convert parsed operands to MCInst.
3881/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3882/// when they refer multiple MIOperands inside a single one.
3883bool ARMAsmParser::
3884cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
3885             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3886  // Rt, Rt2
3887  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3888  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3889  // Create a writeback register dummy placeholder.
3890  Inst.addOperand(MCOperand::CreateReg(0));
3891  // addr
3892  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3893  // pred
3894  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3895  return true;
3896}
3897
3898/// cvtT2StrdPre - Convert parsed operands to MCInst.
3899/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3900/// when they refer multiple MIOperands inside a single one.
3901bool ARMAsmParser::
3902cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
3903             const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3904  // Create a writeback register dummy placeholder.
3905  Inst.addOperand(MCOperand::CreateReg(0));
3906  // Rt, Rt2
3907  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3908  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3909  // addr
3910  ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3911  // pred
3912  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3913  return true;
3914}
3915
3916/// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3917/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3918/// when they refer multiple MIOperands inside a single one.
3919bool ARMAsmParser::
3920cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3921                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3922  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3923
3924  // Create a writeback register dummy placeholder.
3925  Inst.addOperand(MCOperand::CreateImm(0));
3926
3927  ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3928  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3929  return true;
3930}
3931
3932/// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3933/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3934/// when they refer multiple MIOperands inside a single one.
3935bool ARMAsmParser::
3936cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3937                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3938  // Create a writeback register dummy placeholder.
3939  Inst.addOperand(MCOperand::CreateImm(0));
3940  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3941  ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3942  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3943  return true;
3944}
3945
3946/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3947/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3948/// when they refer multiple MIOperands inside a single one.
3949bool ARMAsmParser::
3950cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3951                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3952  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3953
3954  // Create a writeback register dummy placeholder.
3955  Inst.addOperand(MCOperand::CreateImm(0));
3956
3957  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3958  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3959  return true;
3960}
3961
3962/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3963/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3964/// when they refer multiple MIOperands inside a single one.
3965bool ARMAsmParser::
3966cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3967                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3968  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3969
3970  // Create a writeback register dummy placeholder.
3971  Inst.addOperand(MCOperand::CreateImm(0));
3972
3973  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3974  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3975  return true;
3976}
3977
3978
3979/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3980/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3981/// when they refer multiple MIOperands inside a single one.
3982bool ARMAsmParser::
3983cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3984                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3985  // Create a writeback register dummy placeholder.
3986  Inst.addOperand(MCOperand::CreateImm(0));
3987  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3988  ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3989  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3990  return true;
3991}
3992
3993/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3994/// Needed here because the Asm Gen Matcher can't handle properly tied operands
3995/// when they refer multiple MIOperands inside a single one.
3996bool ARMAsmParser::
3997cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3998                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3999  // Create a writeback register dummy placeholder.
4000  Inst.addOperand(MCOperand::CreateImm(0));
4001  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4002  ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
4003  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4004  return true;
4005}
4006
4007/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
4008/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4009/// when they refer multiple MIOperands inside a single one.
4010bool ARMAsmParser::
4011cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
4012                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4013  // Create a writeback register dummy placeholder.
4014  Inst.addOperand(MCOperand::CreateImm(0));
4015  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4016  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4017  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4018  return true;
4019}
4020
4021/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
4022/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4023/// when they refer multiple MIOperands inside a single one.
4024bool ARMAsmParser::
4025cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
4026                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4027  // Rt
4028  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4029  // Create a writeback register dummy placeholder.
4030  Inst.addOperand(MCOperand::CreateImm(0));
4031  // addr
4032  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4033  // offset
4034  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4035  // pred
4036  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4037  return true;
4038}
4039
4040/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
4041/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4042/// when they refer multiple MIOperands inside a single one.
4043bool ARMAsmParser::
4044cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
4045                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4046  // Rt
4047  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4048  // Create a writeback register dummy placeholder.
4049  Inst.addOperand(MCOperand::CreateImm(0));
4050  // addr
4051  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4052  // offset
4053  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4054  // pred
4055  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4056  return true;
4057}
4058
4059/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
4060/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4061/// when they refer multiple MIOperands inside a single one.
4062bool ARMAsmParser::
4063cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
4064                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4065  // Create a writeback register dummy placeholder.
4066  Inst.addOperand(MCOperand::CreateImm(0));
4067  // Rt
4068  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4069  // addr
4070  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4071  // offset
4072  ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4073  // pred
4074  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4075  return true;
4076}
4077
4078/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
4079/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4080/// when they refer multiple MIOperands inside a single one.
4081bool ARMAsmParser::
4082cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
4083                      const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4084  // Create a writeback register dummy placeholder.
4085  Inst.addOperand(MCOperand::CreateImm(0));
4086  // Rt
4087  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4088  // addr
4089  ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4090  // offset
4091  ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4092  // pred
4093  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4094  return true;
4095}
4096
4097/// cvtLdrdPre - Convert parsed operands to MCInst.
4098/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4099/// when they refer multiple MIOperands inside a single one.
4100bool ARMAsmParser::
4101cvtLdrdPre(MCInst &Inst, unsigned Opcode,
4102           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4103  // Rt, Rt2
4104  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4105  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4106  // Create a writeback register dummy placeholder.
4107  Inst.addOperand(MCOperand::CreateImm(0));
4108  // addr
4109  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4110  // pred
4111  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4112  return true;
4113}
4114
4115/// cvtStrdPre - Convert parsed operands to MCInst.
4116/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4117/// when they refer multiple MIOperands inside a single one.
4118bool ARMAsmParser::
4119cvtStrdPre(MCInst &Inst, unsigned Opcode,
4120           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4121  // Create a writeback register dummy placeholder.
4122  Inst.addOperand(MCOperand::CreateImm(0));
4123  // Rt, Rt2
4124  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4125  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4126  // addr
4127  ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4128  // pred
4129  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4130  return true;
4131}
4132
4133/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
4134/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4135/// when they refer multiple MIOperands inside a single one.
4136bool ARMAsmParser::
4137cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
4138                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4139  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4140  // Create a writeback register dummy placeholder.
4141  Inst.addOperand(MCOperand::CreateImm(0));
4142  ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4143  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4144  return true;
4145}
4146
4147/// cvtThumbMultiply - Convert parsed operands to MCInst.
4148/// Needed here because the Asm Gen Matcher can't handle properly tied operands
4149/// when they refer multiple MIOperands inside a single one.
4150bool ARMAsmParser::
4151cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
4152           const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4153  ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4154  ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4155  // If we have a three-operand form, make sure to set Rn to be the operand
4156  // that isn't the same as Rd.
4157  unsigned RegOp = 4;
4158  if (Operands.size() == 6 &&
4159      ((ARMOperand*)Operands[4])->getReg() ==
4160        ((ARMOperand*)Operands[3])->getReg())
4161    RegOp = 5;
4162  ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4163  Inst.addOperand(Inst.getOperand(0));
4164  ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4165
4166  return true;
4167}
4168
4169bool ARMAsmParser::
4170cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
4171              const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4172  // Vd
4173  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4174  // Create a writeback register dummy placeholder.
4175  Inst.addOperand(MCOperand::CreateImm(0));
4176  // Vn
4177  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4178  // pred
4179  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4180  return true;
4181}
4182
4183bool ARMAsmParser::
4184cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
4185                 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4186  // Vd
4187  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4188  // Create a writeback register dummy placeholder.
4189  Inst.addOperand(MCOperand::CreateImm(0));
4190  // Vn
4191  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4192  // Vm
4193  ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4194  // pred
4195  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4196  return true;
4197}
4198
4199bool ARMAsmParser::
4200cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
4201              const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4202  // Create a writeback register dummy placeholder.
4203  Inst.addOperand(MCOperand::CreateImm(0));
4204  // Vn
4205  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4206  // Vt
4207  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4208  // pred
4209  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4210  return true;
4211}
4212
4213bool ARMAsmParser::
4214cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
4215                 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4216  // Create a writeback register dummy placeholder.
4217  Inst.addOperand(MCOperand::CreateImm(0));
4218  // Vn
4219  ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4220  // Vm
4221  ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4222  // Vt
4223  ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4224  // pred
4225  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4226  return true;
4227}
4228
4229/// Parse an ARM memory expression, return false if successful else return true
4230/// or an error.  The first token must be a '[' when called.
4231bool ARMAsmParser::
4232parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4233  SMLoc S, E;
4234  assert(Parser.getTok().is(AsmToken::LBrac) &&
4235         "Token is not a Left Bracket");
4236  S = Parser.getTok().getLoc();
4237  Parser.Lex(); // Eat left bracket token.
4238
4239  const AsmToken &BaseRegTok = Parser.getTok();
4240  int BaseRegNum = tryParseRegister();
4241  if (BaseRegNum == -1)
4242    return Error(BaseRegTok.getLoc(), "register expected");
4243
4244  // The next token must either be a comma or a closing bracket.
4245  const AsmToken &Tok = Parser.getTok();
4246  if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
4247    return Error(Tok.getLoc(), "malformed memory operand");
4248
4249  if (Tok.is(AsmToken::RBrac)) {
4250    E = Tok.getLoc();
4251    Parser.Lex(); // Eat right bracket token.
4252
4253    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4254                                             0, 0, false, S, E));
4255
4256    // If there's a pre-indexing writeback marker, '!', just add it as a token
4257    // operand. It's rather odd, but syntactically valid.
4258    if (Parser.getTok().is(AsmToken::Exclaim)) {
4259      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4260      Parser.Lex(); // Eat the '!'.
4261    }
4262
4263    return false;
4264  }
4265
4266  assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
4267  Parser.Lex(); // Eat the comma.
4268
4269  // If we have a ':', it's an alignment specifier.
4270  if (Parser.getTok().is(AsmToken::Colon)) {
4271    Parser.Lex(); // Eat the ':'.
4272    E = Parser.getTok().getLoc();
4273
4274    const MCExpr *Expr;
4275    if (getParser().ParseExpression(Expr))
4276     return true;
4277
4278    // The expression has to be a constant. Memory references with relocations
4279    // don't come through here, as they use the <label> forms of the relevant
4280    // instructions.
4281    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4282    if (!CE)
4283      return Error (E, "constant expression expected");
4284
4285    unsigned Align = 0;
4286    switch (CE->getValue()) {
4287    default:
4288      return Error(E,
4289                   "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4290    case 16:  Align = 2; break;
4291    case 32:  Align = 4; break;
4292    case 64:  Align = 8; break;
4293    case 128: Align = 16; break;
4294    case 256: Align = 32; break;
4295    }
4296
4297    // Now we should have the closing ']'
4298    E = Parser.getTok().getLoc();
4299    if (Parser.getTok().isNot(AsmToken::RBrac))
4300      return Error(E, "']' expected");
4301    Parser.Lex(); // Eat right bracket token.
4302
4303    // Don't worry about range checking the value here. That's handled by
4304    // the is*() predicates.
4305    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4306                                             ARM_AM::no_shift, 0, Align,
4307                                             false, S, E));
4308
4309    // If there's a pre-indexing writeback marker, '!', just add it as a token
4310    // operand.
4311    if (Parser.getTok().is(AsmToken::Exclaim)) {
4312      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4313      Parser.Lex(); // Eat the '!'.
4314    }
4315
4316    return false;
4317  }
4318
4319  // If we have a '#', it's an immediate offset, else assume it's a register
4320  // offset. Be friendly and also accept a plain integer (without a leading
4321  // hash) for gas compatibility.
4322  if (Parser.getTok().is(AsmToken::Hash) ||
4323      Parser.getTok().is(AsmToken::Dollar) ||
4324      Parser.getTok().is(AsmToken::Integer)) {
4325    if (Parser.getTok().isNot(AsmToken::Integer))
4326      Parser.Lex(); // Eat the '#'.
4327    E = Parser.getTok().getLoc();
4328
4329    bool isNegative = getParser().getTok().is(AsmToken::Minus);
4330    const MCExpr *Offset;
4331    if (getParser().ParseExpression(Offset))
4332     return true;
4333
4334    // The expression has to be a constant. Memory references with relocations
4335    // don't come through here, as they use the <label> forms of the relevant
4336    // instructions.
4337    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4338    if (!CE)
4339      return Error (E, "constant expression expected");
4340
4341    // If the constant was #-0, represent it as INT32_MIN.
4342    int32_t Val = CE->getValue();
4343    if (isNegative && Val == 0)
4344      CE = MCConstantExpr::Create(INT32_MIN, getContext());
4345
4346    // Now we should have the closing ']'
4347    E = Parser.getTok().getLoc();
4348    if (Parser.getTok().isNot(AsmToken::RBrac))
4349      return Error(E, "']' expected");
4350    Parser.Lex(); // Eat right bracket token.
4351
4352    // Don't worry about range checking the value here. That's handled by
4353    // the is*() predicates.
4354    Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4355                                             ARM_AM::no_shift, 0, 0,
4356                                             false, S, E));
4357
4358    // If there's a pre-indexing writeback marker, '!', just add it as a token
4359    // operand.
4360    if (Parser.getTok().is(AsmToken::Exclaim)) {
4361      Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4362      Parser.Lex(); // Eat the '!'.
4363    }
4364
4365    return false;
4366  }
4367
4368  // The register offset is optionally preceded by a '+' or '-'
4369  bool isNegative = false;
4370  if (Parser.getTok().is(AsmToken::Minus)) {
4371    isNegative = true;
4372    Parser.Lex(); // Eat the '-'.
4373  } else if (Parser.getTok().is(AsmToken::Plus)) {
4374    // Nothing to do.
4375    Parser.Lex(); // Eat the '+'.
4376  }
4377
4378  E = Parser.getTok().getLoc();
4379  int OffsetRegNum = tryParseRegister();
4380  if (OffsetRegNum == -1)
4381    return Error(E, "register expected");
4382
4383  // If there's a shift operator, handle it.
4384  ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4385  unsigned ShiftImm = 0;
4386  if (Parser.getTok().is(AsmToken::Comma)) {
4387    Parser.Lex(); // Eat the ','.
4388    if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4389      return true;
4390  }
4391
4392  // Now we should have the closing ']'
4393  E = Parser.getTok().getLoc();
4394  if (Parser.getTok().isNot(AsmToken::RBrac))
4395    return Error(E, "']' expected");
4396  Parser.Lex(); // Eat right bracket token.
4397
4398  Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4399                                           ShiftType, ShiftImm, 0, isNegative,
4400                                           S, E));
4401
4402  // If there's a pre-indexing writeback marker, '!', just add it as a token
4403  // operand.
4404  if (Parser.getTok().is(AsmToken::Exclaim)) {
4405    Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4406    Parser.Lex(); // Eat the '!'.
4407  }
4408
4409  return false;
4410}
4411
4412/// parseMemRegOffsetShift - one of these two:
4413///   ( lsl | lsr | asr | ror ) , # shift_amount
4414///   rrx
4415/// return true if it parses a shift otherwise it returns false.
4416bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4417                                          unsigned &Amount) {
4418  SMLoc Loc = Parser.getTok().getLoc();
4419  const AsmToken &Tok = Parser.getTok();
4420  if (Tok.isNot(AsmToken::Identifier))
4421    return true;
4422  StringRef ShiftName = Tok.getString();
4423  if (ShiftName == "lsl" || ShiftName == "LSL" ||
4424      ShiftName == "asl" || ShiftName == "ASL")
4425    St = ARM_AM::lsl;
4426  else if (ShiftName == "lsr" || ShiftName == "LSR")
4427    St = ARM_AM::lsr;
4428  else if (ShiftName == "asr" || ShiftName == "ASR")
4429    St = ARM_AM::asr;
4430  else if (ShiftName == "ror" || ShiftName == "ROR")
4431    St = ARM_AM::ror;
4432  else if (ShiftName == "rrx" || ShiftName == "RRX")
4433    St = ARM_AM::rrx;
4434  else
4435    return Error(Loc, "illegal shift operator");
4436  Parser.Lex(); // Eat shift type token.
4437
4438  // rrx stands alone.
4439  Amount = 0;
4440  if (St != ARM_AM::rrx) {
4441    Loc = Parser.getTok().getLoc();
4442    // A '#' and a shift amount.
4443    const AsmToken &HashTok = Parser.getTok();
4444    if (HashTok.isNot(AsmToken::Hash) &&
4445        HashTok.isNot(AsmToken::Dollar))
4446      return Error(HashTok.getLoc(), "'#' expected");
4447    Parser.Lex(); // Eat hash token.
4448
4449    const MCExpr *Expr;
4450    if (getParser().ParseExpression(Expr))
4451      return true;
4452    // Range check the immediate.
4453    // lsl, ror: 0 <= imm <= 31
4454    // lsr, asr: 0 <= imm <= 32
4455    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4456    if (!CE)
4457      return Error(Loc, "shift amount must be an immediate");
4458    int64_t Imm = CE->getValue();
4459    if (Imm < 0 ||
4460        ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4461        ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4462      return Error(Loc, "immediate shift value out of range");
4463    Amount = Imm;
4464  }
4465
4466  return false;
4467}
4468
4469/// parseFPImm - A floating point immediate expression operand.
4470ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4471parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4472  // Anything that can accept a floating point constant as an operand
4473  // needs to go through here, as the regular ParseExpression is
4474  // integer only.
4475  //
4476  // This routine still creates a generic Immediate operand, containing
4477  // a bitcast of the 64-bit floating point value. The various operands
4478  // that accept floats can check whether the value is valid for them
4479  // via the standard is*() predicates.
4480
4481  SMLoc S = Parser.getTok().getLoc();
4482
4483  if (Parser.getTok().isNot(AsmToken::Hash) &&
4484      Parser.getTok().isNot(AsmToken::Dollar))
4485    return MatchOperand_NoMatch;
4486
4487  // Disambiguate the VMOV forms that can accept an FP immediate.
4488  // vmov.f32 <sreg>, #imm
4489  // vmov.f64 <dreg>, #imm
4490  // vmov.f32 <dreg>, #imm  @ vector f32x2
4491  // vmov.f32 <qreg>, #imm  @ vector f32x4
4492  //
4493  // There are also the NEON VMOV instructions which expect an
4494  // integer constant. Make sure we don't try to parse an FPImm
4495  // for these:
4496  // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4497  ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4498  if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4499                           TyOp->getToken() != ".f64"))
4500    return MatchOperand_NoMatch;
4501
4502  Parser.Lex(); // Eat the '#'.
4503
4504  // Handle negation, as that still comes through as a separate token.
4505  bool isNegative = false;
4506  if (Parser.getTok().is(AsmToken::Minus)) {
4507    isNegative = true;
4508    Parser.Lex();
4509  }
4510  const AsmToken &Tok = Parser.getTok();
4511  SMLoc Loc = Tok.getLoc();
4512  if (Tok.is(AsmToken::Real)) {
4513    APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4514    uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4515    // If we had a '-' in front, toggle the sign bit.
4516    IntVal ^= (uint64_t)isNegative << 31;
4517    Parser.Lex(); // Eat the token.
4518    Operands.push_back(ARMOperand::CreateImm(
4519          MCConstantExpr::Create(IntVal, getContext()),
4520          S, Parser.getTok().getLoc()));
4521    return MatchOperand_Success;
4522  }
4523  // Also handle plain integers. Instructions which allow floating point
4524  // immediates also allow a raw encoded 8-bit value.
4525  if (Tok.is(AsmToken::Integer)) {
4526    int64_t Val = Tok.getIntVal();
4527    Parser.Lex(); // Eat the token.
4528    if (Val > 255 || Val < 0) {
4529      Error(Loc, "encoded floating point value out of range");
4530      return MatchOperand_ParseFail;
4531    }
4532    double RealVal = ARM_AM::getFPImmFloat(Val);
4533    Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4534    Operands.push_back(ARMOperand::CreateImm(
4535        MCConstantExpr::Create(Val, getContext()), S,
4536        Parser.getTok().getLoc()));
4537    return MatchOperand_Success;
4538  }
4539
4540  Error(Loc, "invalid floating point immediate");
4541  return MatchOperand_ParseFail;
4542}
4543
4544/// Parse a arm instruction operand.  For now this parses the operand regardless
4545/// of the mnemonic.
4546bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4547                                StringRef Mnemonic) {
4548  SMLoc S, E;
4549
4550  // Check if the current operand has a custom associated parser, if so, try to
4551  // custom parse the operand, or fallback to the general approach.
4552  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4553  if (ResTy == MatchOperand_Success)
4554    return false;
4555  // If there wasn't a custom match, try the generic matcher below. Otherwise,
4556  // there was a match, but an error occurred, in which case, just return that
4557  // the operand parsing failed.
4558  if (ResTy == MatchOperand_ParseFail)
4559    return true;
4560
4561  switch (getLexer().getKind()) {
4562  default:
4563    Error(Parser.getTok().getLoc(), "unexpected token in operand");
4564    return true;
4565  case AsmToken::Identifier: {
4566    if (!tryParseRegisterWithWriteBack(Operands))
4567      return false;
4568    int Res = tryParseShiftRegister(Operands);
4569    if (Res == 0) // success
4570      return false;
4571    else if (Res == -1) // irrecoverable error
4572      return true;
4573    // If this is VMRS, check for the apsr_nzcv operand.
4574    if (Mnemonic == "vmrs" &&
4575        Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4576      S = Parser.getTok().getLoc();
4577      Parser.Lex();
4578      Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4579      return false;
4580    }
4581
4582    // Fall though for the Identifier case that is not a register or a
4583    // special name.
4584  }
4585  case AsmToken::LParen:  // parenthesized expressions like (_strcmp-4)
4586  case AsmToken::Integer: // things like 1f and 2b as a branch targets
4587  case AsmToken::String:  // quoted label names.
4588  case AsmToken::Dot: {   // . as a branch target
4589    // This was not a register so parse other operands that start with an
4590    // identifier (like labels) as expressions and create them as immediates.
4591    const MCExpr *IdVal;
4592    S = Parser.getTok().getLoc();
4593    if (getParser().ParseExpression(IdVal))
4594      return true;
4595    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4596    Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4597    return false;
4598  }
4599  case AsmToken::LBrac:
4600    return parseMemory(Operands);
4601  case AsmToken::LCurly:
4602    return parseRegisterList(Operands);
4603  case AsmToken::Dollar:
4604  case AsmToken::Hash: {
4605    // #42 -> immediate.
4606    S = Parser.getTok().getLoc();
4607    Parser.Lex();
4608
4609    if (Parser.getTok().isNot(AsmToken::Colon)) {
4610      bool isNegative = Parser.getTok().is(AsmToken::Minus);
4611      const MCExpr *ImmVal;
4612      if (getParser().ParseExpression(ImmVal))
4613        return true;
4614      const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4615      if (CE) {
4616        int32_t Val = CE->getValue();
4617        if (isNegative && Val == 0)
4618          ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4619      }
4620      E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4621      Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4622      return false;
4623    }
4624    // w/ a ':' after the '#', it's just like a plain ':'.
4625    // FALLTHROUGH
4626  }
4627  case AsmToken::Colon: {
4628    // ":lower16:" and ":upper16:" expression prefixes
4629    // FIXME: Check it's an expression prefix,
4630    // e.g. (FOO - :lower16:BAR) isn't legal.
4631    ARMMCExpr::VariantKind RefKind;
4632    if (parsePrefix(RefKind))
4633      return true;
4634
4635    const MCExpr *SubExprVal;
4636    if (getParser().ParseExpression(SubExprVal))
4637      return true;
4638
4639    const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4640                                                   getContext());
4641    E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4642    Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4643    return false;
4644  }
4645  }
4646}
4647
4648// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4649//  :lower16: and :upper16:.
4650bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4651  RefKind = ARMMCExpr::VK_ARM_None;
4652
4653  // :lower16: and :upper16: modifiers
4654  assert(getLexer().is(AsmToken::Colon) && "expected a :");
4655  Parser.Lex(); // Eat ':'
4656
4657  if (getLexer().isNot(AsmToken::Identifier)) {
4658    Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4659    return true;
4660  }
4661
4662  StringRef IDVal = Parser.getTok().getIdentifier();
4663  if (IDVal == "lower16") {
4664    RefKind = ARMMCExpr::VK_ARM_LO16;
4665  } else if (IDVal == "upper16") {
4666    RefKind = ARMMCExpr::VK_ARM_HI16;
4667  } else {
4668    Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4669    return true;
4670  }
4671  Parser.Lex();
4672
4673  if (getLexer().isNot(AsmToken::Colon)) {
4674    Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4675    return true;
4676  }
4677  Parser.Lex(); // Eat the last ':'
4678  return false;
4679}
4680
4681/// \brief Given a mnemonic, split out possible predication code and carry
4682/// setting letters to form a canonical mnemonic and flags.
4683//
4684// FIXME: Would be nice to autogen this.
4685// FIXME: This is a bit of a maze of special cases.
4686StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4687                                      unsigned &PredicationCode,
4688                                      bool &CarrySetting,
4689                                      unsigned &ProcessorIMod,
4690                                      StringRef &ITMask) {
4691  PredicationCode = ARMCC::AL;
4692  CarrySetting = false;
4693  ProcessorIMod = 0;
4694
4695  // Ignore some mnemonics we know aren't predicated forms.
4696  //
4697  // FIXME: Would be nice to autogen this.
4698  if ((Mnemonic == "movs" && isThumb()) ||
4699      Mnemonic == "teq"   || Mnemonic == "vceq"   || Mnemonic == "svc"   ||
4700      Mnemonic == "mls"   || Mnemonic == "smmls"  || Mnemonic == "vcls"  ||
4701      Mnemonic == "vmls"  || Mnemonic == "vnmls"  || Mnemonic == "vacge" ||
4702      Mnemonic == "vcge"  || Mnemonic == "vclt"   || Mnemonic == "vacgt" ||
4703      Mnemonic == "vcgt"  || Mnemonic == "vcle"   || Mnemonic == "smlal" ||
4704      Mnemonic == "umaal" || Mnemonic == "umlal"  || Mnemonic == "vabal" ||
4705      Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4706      Mnemonic == "fmuls")
4707    return Mnemonic;
4708
4709  // First, split out any predication code. Ignore mnemonics we know aren't
4710  // predicated but do have a carry-set and so weren't caught above.
4711  if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4712      Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4713      Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4714      Mnemonic != "sbcs" && Mnemonic != "rscs") {
4715    unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4716      .Case("eq", ARMCC::EQ)
4717      .Case("ne", ARMCC::NE)
4718      .Case("hs", ARMCC::HS)
4719      .Case("cs", ARMCC::HS)
4720      .Case("lo", ARMCC::LO)
4721      .Case("cc", ARMCC::LO)
4722      .Case("mi", ARMCC::MI)
4723      .Case("pl", ARMCC::PL)
4724      .Case("vs", ARMCC::VS)
4725      .Case("vc", ARMCC::VC)
4726      .Case("hi", ARMCC::HI)
4727      .Case("ls", ARMCC::LS)
4728      .Case("ge", ARMCC::GE)
4729      .Case("lt", ARMCC::LT)
4730      .Case("gt", ARMCC::GT)
4731      .Case("le", ARMCC::LE)
4732      .Case("al", ARMCC::AL)
4733      .Default(~0U);
4734    if (CC != ~0U) {
4735      Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4736      PredicationCode = CC;
4737    }
4738  }
4739
4740  // Next, determine if we have a carry setting bit. We explicitly ignore all
4741  // the instructions we know end in 's'.
4742  if (Mnemonic.endswith("s") &&
4743      !(Mnemonic == "cps" || Mnemonic == "mls" ||
4744        Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4745        Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4746        Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4747        Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4748        Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4749        Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4750        Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4751        Mnemonic == "vfms" || Mnemonic == "vfnms" ||
4752        (Mnemonic == "movs" && isThumb()))) {
4753    Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4754    CarrySetting = true;
4755  }
4756
4757  // The "cps" instruction can have a interrupt mode operand which is glued into
4758  // the mnemonic. Check if this is the case, split it and parse the imod op
4759  if (Mnemonic.startswith("cps")) {
4760    // Split out any imod code.
4761    unsigned IMod =
4762      StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4763      .Case("ie", ARM_PROC::IE)
4764      .Case("id", ARM_PROC::ID)
4765      .Default(~0U);
4766    if (IMod != ~0U) {
4767      Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4768      ProcessorIMod = IMod;
4769    }
4770  }
4771
4772  // The "it" instruction has the condition mask on the end of the mnemonic.
4773  if (Mnemonic.startswith("it")) {
4774    ITMask = Mnemonic.slice(2, Mnemonic.size());
4775    Mnemonic = Mnemonic.slice(0, 2);
4776  }
4777
4778  return Mnemonic;
4779}
4780
4781/// \brief Given a canonical mnemonic, determine if the instruction ever allows
4782/// inclusion of carry set or predication code operands.
4783//
4784// FIXME: It would be nice to autogen this.
4785void ARMAsmParser::
4786getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4787                      bool &CanAcceptPredicationCode) {
4788  if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4789      Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4790      Mnemonic == "add" || Mnemonic == "adc" ||
4791      Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4792      Mnemonic == "orr" || Mnemonic == "mvn" ||
4793      Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4794      Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4795      Mnemonic == "vfm" || Mnemonic == "vfnm" ||
4796      (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4797                      Mnemonic == "mla" || Mnemonic == "smlal" ||
4798                      Mnemonic == "umlal" || Mnemonic == "umull"))) {
4799    CanAcceptCarrySet = true;
4800  } else
4801    CanAcceptCarrySet = false;
4802
4803  if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
4804      Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
4805      Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
4806      Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
4807      Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
4808      (Mnemonic == "clrex" && !isThumb()) ||
4809      (Mnemonic == "nop" && isThumbOne()) ||
4810      ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
4811        Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||
4812        Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) ||
4813      ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
4814       !isThumb()) ||
4815      Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
4816    CanAcceptPredicationCode = false;
4817  } else
4818    CanAcceptPredicationCode = true;
4819
4820  if (isThumb()) {
4821    if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
4822        Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
4823      CanAcceptPredicationCode = false;
4824  }
4825}
4826
4827bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4828                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4829  // FIXME: This is all horribly hacky. We really need a better way to deal
4830  // with optional operands like this in the matcher table.
4831
4832  // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4833  // another does not. Specifically, the MOVW instruction does not. So we
4834  // special case it here and remove the defaulted (non-setting) cc_out
4835  // operand if that's the instruction we're trying to match.
4836  //
4837  // We do this as post-processing of the explicit operands rather than just
4838  // conditionally adding the cc_out in the first place because we need
4839  // to check the type of the parsed immediate operand.
4840  if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4841      !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4842      static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4843      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4844    return true;
4845
4846  // Register-register 'add' for thumb does not have a cc_out operand
4847  // when there are only two register operands.
4848  if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4849      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4850      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4851      static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4852    return true;
4853  // Register-register 'add' for thumb does not have a cc_out operand
4854  // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4855  // have to check the immediate range here since Thumb2 has a variant
4856  // that can handle a different range and has a cc_out operand.
4857  if (((isThumb() && Mnemonic == "add") ||
4858       (isThumbTwo() && Mnemonic == "sub")) &&
4859      Operands.size() == 6 &&
4860      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4861      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4862      static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4863      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4864      ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
4865       static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4866    return true;
4867  // For Thumb2, add/sub immediate does not have a cc_out operand for the
4868  // imm0_4095 variant. That's the least-preferred variant when
4869  // selecting via the generic "add" mnemonic, so to know that we
4870  // should remove the cc_out operand, we have to explicitly check that
4871  // it's not one of the other variants. Ugh.
4872  if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4873      Operands.size() == 6 &&
4874      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4875      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4876      static_cast<ARMOperand*>(Operands[5])->isImm()) {
4877    // Nest conditions rather than one big 'if' statement for readability.
4878    //
4879    // If either register is a high reg, it's either one of the SP
4880    // variants (handled above) or a 32-bit encoding, so we just
4881    // check against T3. If the second register is the PC, this is an
4882    // alternate form of ADR, which uses encoding T4, so check for that too.
4883    if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4884         !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
4885        static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
4886        static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4887      return false;
4888    // If both registers are low, we're in an IT block, and the immediate is
4889    // in range, we should use encoding T1 instead, which has a cc_out.
4890    if (inITBlock() &&
4891        isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4892        isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4893        static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4894      return false;
4895
4896    // Otherwise, we use encoding T4, which does not have a cc_out
4897    // operand.
4898    return true;
4899  }
4900
4901  // The thumb2 multiply instruction doesn't have a CCOut register, so
4902  // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4903  // use the 16-bit encoding or not.
4904  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4905      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4906      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4907      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4908      static_cast<ARMOperand*>(Operands[5])->isReg() &&
4909      // If the registers aren't low regs, the destination reg isn't the
4910      // same as one of the source regs, or the cc_out operand is zero
4911      // outside of an IT block, we have to use the 32-bit encoding, so
4912      // remove the cc_out operand.
4913      (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4914       !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4915       !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
4916       !inITBlock() ||
4917       (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4918        static_cast<ARMOperand*>(Operands[5])->getReg() &&
4919        static_cast<ARMOperand*>(Operands[3])->getReg() !=
4920        static_cast<ARMOperand*>(Operands[4])->getReg())))
4921    return true;
4922
4923  // Also check the 'mul' syntax variant that doesn't specify an explicit
4924  // destination register.
4925  if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
4926      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4927      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4928      static_cast<ARMOperand*>(Operands[4])->isReg() &&
4929      // If the registers aren't low regs  or the cc_out operand is zero
4930      // outside of an IT block, we have to use the 32-bit encoding, so
4931      // remove the cc_out operand.
4932      (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4933       !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4934       !inITBlock()))
4935    return true;
4936
4937
4938
4939  // Register-register 'add/sub' for thumb does not have a cc_out operand
4940  // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4941  // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4942  // right, this will result in better diagnostics (which operand is off)
4943  // anyway.
4944  if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4945      (Operands.size() == 5 || Operands.size() == 6) &&
4946      static_cast<ARMOperand*>(Operands[3])->isReg() &&
4947      static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4948      static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4949      (static_cast<ARMOperand*>(Operands[4])->isImm() ||
4950       (Operands.size() == 6 &&
4951        static_cast<ARMOperand*>(Operands[5])->isImm())))
4952    return true;
4953
4954  return false;
4955}
4956
4957static bool isDataTypeToken(StringRef Tok) {
4958  return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
4959    Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
4960    Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
4961    Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
4962    Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
4963    Tok == ".f" || Tok == ".d";
4964}
4965
4966// FIXME: This bit should probably be handled via an explicit match class
4967// in the .td files that matches the suffix instead of having it be
4968// a literal string token the way it is now.
4969static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
4970  return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
4971}
4972
4973static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features);
4974/// Parse an arm instruction mnemonic followed by its operands.
4975bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
4976                               SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4977  // Apply mnemonic aliases before doing anything else, as the destination
4978  // mnemnonic may include suffices and we want to handle them normally.
4979  // The generic tblgen'erated code does this later, at the start of
4980  // MatchInstructionImpl(), but that's too late for aliases that include
4981  // any sort of suffix.
4982  unsigned AvailableFeatures = getAvailableFeatures();
4983  applyMnemonicAliases(Name, AvailableFeatures);
4984
4985  // First check for the ARM-specific .req directive.
4986  if (Parser.getTok().is(AsmToken::Identifier) &&
4987      Parser.getTok().getIdentifier() == ".req") {
4988    parseDirectiveReq(Name, NameLoc);
4989    // We always return 'error' for this, as we're done with this
4990    // statement and don't need to match the 'instruction."
4991    return true;
4992  }
4993
4994  // Create the leading tokens for the mnemonic, split by '.' characters.
4995  size_t Start = 0, Next = Name.find('.');
4996  StringRef Mnemonic = Name.slice(Start, Next);
4997
4998  // Split out the predication code and carry setting flag from the mnemonic.
4999  unsigned PredicationCode;
5000  unsigned ProcessorIMod;
5001  bool CarrySetting;
5002  StringRef ITMask;
5003  Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5004                           ProcessorIMod, ITMask);
5005
5006  // In Thumb1, only the branch (B) instruction can be predicated.
5007  if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5008    Parser.EatToEndOfStatement();
5009    return Error(NameLoc, "conditional execution not supported in Thumb1");
5010  }
5011
5012  Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5013
5014  // Handle the IT instruction ITMask. Convert it to a bitmask. This
5015  // is the mask as it will be for the IT encoding if the conditional
5016  // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5017  // where the conditional bit0 is zero, the instruction post-processing
5018  // will adjust the mask accordingly.
5019  if (Mnemonic == "it") {
5020    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5021    if (ITMask.size() > 3) {
5022      Parser.EatToEndOfStatement();
5023      return Error(Loc, "too many conditions on IT instruction");
5024    }
5025    unsigned Mask = 8;
5026    for (unsigned i = ITMask.size(); i != 0; --i) {
5027      char pos = ITMask[i - 1];
5028      if (pos != 't' && pos != 'e') {
5029        Parser.EatToEndOfStatement();
5030        return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5031      }
5032      Mask >>= 1;
5033      if (ITMask[i - 1] == 't')
5034        Mask |= 8;
5035    }
5036    Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5037  }
5038
5039  // FIXME: This is all a pretty gross hack. We should automatically handle
5040  // optional operands like this via tblgen.
5041
5042  // Next, add the CCOut and ConditionCode operands, if needed.
5043  //
5044  // For mnemonics which can ever incorporate a carry setting bit or predication
5045  // code, our matching model involves us always generating CCOut and
5046  // ConditionCode operands to match the mnemonic "as written" and then we let
5047  // the matcher deal with finding the right instruction or generating an
5048  // appropriate error.
5049  bool CanAcceptCarrySet, CanAcceptPredicationCode;
5050  getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
5051
5052  // If we had a carry-set on an instruction that can't do that, issue an
5053  // error.
5054  if (!CanAcceptCarrySet && CarrySetting) {
5055    Parser.EatToEndOfStatement();
5056    return Error(NameLoc, "instruction '" + Mnemonic +
5057                 "' can not set flags, but 's' suffix specified");
5058  }
5059  // If we had a predication code on an instruction that can't do that, issue an
5060  // error.
5061  if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5062    Parser.EatToEndOfStatement();
5063    return Error(NameLoc, "instruction '" + Mnemonic +
5064                 "' is not predicable, but condition code specified");
5065  }
5066
5067  // Add the carry setting operand, if necessary.
5068  if (CanAcceptCarrySet) {
5069    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5070    Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5071                                               Loc));
5072  }
5073
5074  // Add the predication code operand, if necessary.
5075  if (CanAcceptPredicationCode) {
5076    SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5077                                      CarrySetting);
5078    Operands.push_back(ARMOperand::CreateCondCode(
5079                         ARMCC::CondCodes(PredicationCode), Loc));
5080  }
5081
5082  // Add the processor imod operand, if necessary.
5083  if (ProcessorIMod) {
5084    Operands.push_back(ARMOperand::CreateImm(
5085          MCConstantExpr::Create(ProcessorIMod, getContext()),
5086                                 NameLoc, NameLoc));
5087  }
5088
5089  // Add the remaining tokens in the mnemonic.
5090  while (Next != StringRef::npos) {
5091    Start = Next;
5092    Next = Name.find('.', Start + 1);
5093    StringRef ExtraToken = Name.slice(Start, Next);
5094
5095    // Some NEON instructions have an optional datatype suffix that is
5096    // completely ignored. Check for that.
5097    if (isDataTypeToken(ExtraToken) &&
5098        doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5099      continue;
5100
5101    if (ExtraToken != ".n") {
5102      SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5103      Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5104    }
5105  }
5106
5107  // Read the remaining operands.
5108  if (getLexer().isNot(AsmToken::EndOfStatement)) {
5109    // Read the first operand.
5110    if (parseOperand(Operands, Mnemonic)) {
5111      Parser.EatToEndOfStatement();
5112      return true;
5113    }
5114
5115    while (getLexer().is(AsmToken::Comma)) {
5116      Parser.Lex();  // Eat the comma.
5117
5118      // Parse and remember the operand.
5119      if (parseOperand(Operands, Mnemonic)) {
5120        Parser.EatToEndOfStatement();
5121        return true;
5122      }
5123    }
5124  }
5125
5126  if (getLexer().isNot(AsmToken::EndOfStatement)) {
5127    SMLoc Loc = getLexer().getLoc();
5128    Parser.EatToEndOfStatement();
5129    return Error(Loc, "unexpected token in argument list");
5130  }
5131
5132  Parser.Lex(); // Consume the EndOfStatement
5133
5134  // Some instructions, mostly Thumb, have forms for the same mnemonic that
5135  // do and don't have a cc_out optional-def operand. With some spot-checks
5136  // of the operand list, we can figure out which variant we're trying to
5137  // parse and adjust accordingly before actually matching. We shouldn't ever
5138  // try to remove a cc_out operand that was explicitly set on the the
5139  // mnemonic, of course (CarrySetting == true). Reason number #317 the
5140  // table driven matcher doesn't fit well with the ARM instruction set.
5141  if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5142    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5143    Operands.erase(Operands.begin() + 1);
5144    delete Op;
5145  }
5146
5147  // ARM mode 'blx' need special handling, as the register operand version
5148  // is predicable, but the label operand version is not. So, we can't rely
5149  // on the Mnemonic based checking to correctly figure out when to put
5150  // a k_CondCode operand in the list. If we're trying to match the label
5151  // version, remove the k_CondCode operand here.
5152  if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5153      static_cast<ARMOperand*>(Operands[2])->isImm()) {
5154    ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5155    Operands.erase(Operands.begin() + 1);
5156    delete Op;
5157  }
5158
5159  // The vector-compare-to-zero instructions have a literal token "#0" at
5160  // the end that comes to here as an immediate operand. Convert it to a
5161  // token to play nicely with the matcher.
5162  if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
5163      Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
5164      static_cast<ARMOperand*>(Operands[5])->isImm()) {
5165    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
5166    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5167    if (CE && CE->getValue() == 0) {
5168      Operands.erase(Operands.begin() + 5);
5169      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5170      delete Op;
5171    }
5172  }
5173  // VCMP{E} does the same thing, but with a different operand count.
5174  if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 &&
5175      static_cast<ARMOperand*>(Operands[4])->isImm()) {
5176    ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]);
5177    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5178    if (CE && CE->getValue() == 0) {
5179      Operands.erase(Operands.begin() + 4);
5180      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5181      delete Op;
5182    }
5183  }
5184  // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
5185  // end. Convert it to a token here. Take care not to convert those
5186  // that should hit the Thumb2 encoding.
5187  if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
5188      static_cast<ARMOperand*>(Operands[3])->isReg() &&
5189      static_cast<ARMOperand*>(Operands[4])->isReg() &&
5190      static_cast<ARMOperand*>(Operands[5])->isImm()) {
5191    ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
5192    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5193    if (CE && CE->getValue() == 0 &&
5194        (isThumbOne() ||
5195         // The cc_out operand matches the IT block.
5196         ((inITBlock() != CarrySetting) &&
5197         // Neither register operand is a high register.
5198         (isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
5199          isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()))))){
5200      Operands.erase(Operands.begin() + 5);
5201      Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5202      delete Op;
5203    }
5204  }
5205
5206  return false;
5207}
5208
5209// Validate context-sensitive operand constraints.
5210
5211// return 'true' if register list contains non-low GPR registers,
5212// 'false' otherwise. If Reg is in the register list or is HiReg, set
5213// 'containsReg' to true.
5214static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5215                                 unsigned HiReg, bool &containsReg) {
5216  containsReg = false;
5217  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5218    unsigned OpReg = Inst.getOperand(i).getReg();
5219    if (OpReg == Reg)
5220      containsReg = true;
5221    // Anything other than a low register isn't legal here.
5222    if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5223      return true;
5224  }
5225  return false;
5226}
5227
5228// Check if the specified regisgter is in the register list of the inst,
5229// starting at the indicated operand number.
5230static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5231  for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5232    unsigned OpReg = Inst.getOperand(i).getReg();
5233    if (OpReg == Reg)
5234      return true;
5235  }
5236  return false;
5237}
5238
5239// FIXME: We would really prefer to have MCInstrInfo (the wrapper around
5240// the ARMInsts array) instead. Getting that here requires awkward
5241// API changes, though. Better way?
5242namespace llvm {
5243extern const MCInstrDesc ARMInsts[];
5244}
5245static const MCInstrDesc &getInstDesc(unsigned Opcode) {
5246  return ARMInsts[Opcode];
5247}
5248
5249// FIXME: We would really like to be able to tablegen'erate this.
5250bool ARMAsmParser::
5251validateInstruction(MCInst &Inst,
5252                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5253  const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
5254  SMLoc Loc = Operands[0]->getStartLoc();
5255  // Check the IT block state first.
5256  // NOTE: BKPT instruction has the interesting property of being
5257  // allowed in IT blocks, but not being predicable.  It just always
5258  // executes.
5259  if (inITBlock() && Inst.getOpcode() != ARM::tBKPT &&
5260      Inst.getOpcode() != ARM::BKPT) {
5261    unsigned bit = 1;
5262    if (ITState.FirstCond)
5263      ITState.FirstCond = false;
5264    else
5265      bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5266    // The instruction must be predicable.
5267    if (!MCID.isPredicable())
5268      return Error(Loc, "instructions in IT block must be predicable");
5269    unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5270    unsigned ITCond = bit ? ITState.Cond :
5271      ARMCC::getOppositeCondition(ITState.Cond);
5272    if (Cond != ITCond) {
5273      // Find the condition code Operand to get its SMLoc information.
5274      SMLoc CondLoc;
5275      for (unsigned i = 1; i < Operands.size(); ++i)
5276        if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
5277          CondLoc = Operands[i]->getStartLoc();
5278      return Error(CondLoc, "incorrect condition in IT block; got '" +
5279                   StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5280                   "', but expected '" +
5281                   ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5282    }
5283  // Check for non-'al' condition codes outside of the IT block.
5284  } else if (isThumbTwo() && MCID.isPredicable() &&
5285             Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5286             ARMCC::AL && Inst.getOpcode() != ARM::tB &&
5287             Inst.getOpcode() != ARM::t2B)
5288    return Error(Loc, "predicated instructions must be in IT block");
5289
5290  switch (Inst.getOpcode()) {
5291  case ARM::LDRD:
5292  case ARM::LDRD_PRE:
5293  case ARM::LDRD_POST:
5294  case ARM::LDREXD: {
5295    // Rt2 must be Rt + 1.
5296    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5297    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5298    if (Rt2 != Rt + 1)
5299      return Error(Operands[3]->getStartLoc(),
5300                   "destination operands must be sequential");
5301    return false;
5302  }
5303  case ARM::STRD: {
5304    // Rt2 must be Rt + 1.
5305    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5306    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5307    if (Rt2 != Rt + 1)
5308      return Error(Operands[3]->getStartLoc(),
5309                   "source operands must be sequential");
5310    return false;
5311  }
5312  case ARM::STRD_PRE:
5313  case ARM::STRD_POST:
5314  case ARM::STREXD: {
5315    // Rt2 must be Rt + 1.
5316    unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5317    unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5318    if (Rt2 != Rt + 1)
5319      return Error(Operands[3]->getStartLoc(),
5320                   "source operands must be sequential");
5321    return false;
5322  }
5323  case ARM::SBFX:
5324  case ARM::UBFX: {
5325    // width must be in range [1, 32-lsb]
5326    unsigned lsb = Inst.getOperand(2).getImm();
5327    unsigned widthm1 = Inst.getOperand(3).getImm();
5328    if (widthm1 >= 32 - lsb)
5329      return Error(Operands[5]->getStartLoc(),
5330                   "bitfield width must be in range [1,32-lsb]");
5331    return false;
5332  }
5333  case ARM::tLDMIA: {
5334    // If we're parsing Thumb2, the .w variant is available and handles
5335    // most cases that are normally illegal for a Thumb1 LDM
5336    // instruction. We'll make the transformation in processInstruction()
5337    // if necessary.
5338    //
5339    // Thumb LDM instructions are writeback iff the base register is not
5340    // in the register list.
5341    unsigned Rn = Inst.getOperand(0).getReg();
5342    bool hasWritebackToken =
5343      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5344       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5345    bool listContainsBase;
5346    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
5347      return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
5348                   "registers must be in range r0-r7");
5349    // If we should have writeback, then there should be a '!' token.
5350    if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
5351      return Error(Operands[2]->getStartLoc(),
5352                   "writeback operator '!' expected");
5353    // If we should not have writeback, there must not be a '!'. This is
5354    // true even for the 32-bit wide encodings.
5355    if (listContainsBase && hasWritebackToken)
5356      return Error(Operands[3]->getStartLoc(),
5357                   "writeback operator '!' not allowed when base register "
5358                   "in register list");
5359
5360    break;
5361  }
5362  case ARM::t2LDMIA_UPD: {
5363    if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5364      return Error(Operands[4]->getStartLoc(),
5365                   "writeback operator '!' not allowed when base register "
5366                   "in register list");
5367    break;
5368  }
5369  case ARM::tMUL: {
5370    // The second source operand must be the same register as the destination
5371    // operand.
5372    if (Operands.size() == 6 &&
5373        (((ARMOperand*)Operands[3])->getReg() !=
5374         ((ARMOperand*)Operands[5])->getReg()) &&
5375        (((ARMOperand*)Operands[3])->getReg() !=
5376         ((ARMOperand*)Operands[4])->getReg())) {
5377      Error(Operands[3]->getStartLoc(),
5378            "destination register must match source register");
5379    }
5380    break;
5381  }
5382  // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5383  // so only issue a diagnostic for thumb1. The instructions will be
5384  // switched to the t2 encodings in processInstruction() if necessary.
5385  case ARM::tPOP: {
5386    bool listContainsBase;
5387    if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5388        !isThumbTwo())
5389      return Error(Operands[2]->getStartLoc(),
5390                   "registers must be in range r0-r7 or pc");
5391    break;
5392  }
5393  case ARM::tPUSH: {
5394    bool listContainsBase;
5395    if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
5396        !isThumbTwo())
5397      return Error(Operands[2]->getStartLoc(),
5398                   "registers must be in range r0-r7 or lr");
5399    break;
5400  }
5401  case ARM::tSTMIA_UPD: {
5402    bool listContainsBase;
5403    if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
5404      return Error(Operands[4]->getStartLoc(),
5405                   "registers must be in range r0-r7");
5406    break;
5407  }
5408  case ARM::tADDrSP: {
5409    // If the non-SP source operand and the destination operand are not the
5410    // same, we need thumb2 (for the wide encoding), or we have an error.
5411    if (!isThumbTwo() &&
5412        Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5413      return Error(Operands[4]->getStartLoc(),
5414                   "source register must be the same as destination");
5415    }
5416    break;
5417  }
5418  }
5419
5420  return false;
5421}
5422
5423static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5424  switch(Opc) {
5425  default: llvm_unreachable("unexpected opcode!");
5426  // VST1LN
5427  case ARM::VST1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5428  case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5429  case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5430  case ARM::VST1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST1LNd8_UPD;
5431  case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5432  case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5433  case ARM::VST1LNdAsm_8:  Spacing = 1; return ARM::VST1LNd8;
5434  case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5435  case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5436
5437  // VST2LN
5438  case ARM::VST2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5439  case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5440  case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5441  case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5442  case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5443
5444  case ARM::VST2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST2LNd8_UPD;
5445  case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5446  case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5447  case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5448  case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5449
5450  case ARM::VST2LNdAsm_8:  Spacing = 1; return ARM::VST2LNd8;
5451  case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5452  case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5453  case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5454  case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5455
5456  // VST3LN
5457  case ARM::VST3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5458  case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5459  case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5460  case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5461  case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5462  case ARM::VST3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST3LNd8_UPD;
5463  case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5464  case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5465  case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5466  case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5467  case ARM::VST3LNdAsm_8:  Spacing = 1; return ARM::VST3LNd8;
5468  case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5469  case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5470  case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5471  case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5472
5473  // VST3
5474  case ARM::VST3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5475  case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5476  case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5477  case ARM::VST3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5478  case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5479  case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5480  case ARM::VST3dWB_register_Asm_8:  Spacing = 1; return ARM::VST3d8_UPD;
5481  case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5482  case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5483  case ARM::VST3qWB_register_Asm_8:  Spacing = 2; return ARM::VST3q8_UPD;
5484  case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5485  case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5486  case ARM::VST3dAsm_8:  Spacing = 1; return ARM::VST3d8;
5487  case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5488  case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5489  case ARM::VST3qAsm_8:  Spacing = 2; return ARM::VST3q8;
5490  case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5491  case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5492
5493  // VST4LN
5494  case ARM::VST4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5495  case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5496  case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5497  case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5498  case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5499  case ARM::VST4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VST4LNd8_UPD;
5500  case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5501  case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5502  case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5503  case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5504  case ARM::VST4LNdAsm_8:  Spacing = 1; return ARM::VST4LNd8;
5505  case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5506  case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5507  case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5508  case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5509
5510  // VST4
5511  case ARM::VST4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5512  case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5513  case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5514  case ARM::VST4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5515  case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5516  case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5517  case ARM::VST4dWB_register_Asm_8:  Spacing = 1; return ARM::VST4d8_UPD;
5518  case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5519  case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5520  case ARM::VST4qWB_register_Asm_8:  Spacing = 2; return ARM::VST4q8_UPD;
5521  case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5522  case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5523  case ARM::VST4dAsm_8:  Spacing = 1; return ARM::VST4d8;
5524  case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5525  case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5526  case ARM::VST4qAsm_8:  Spacing = 2; return ARM::VST4q8;
5527  case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5528  case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5529  }
5530}
5531
5532static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5533  switch(Opc) {
5534  default: llvm_unreachable("unexpected opcode!");
5535  // VLD1LN
5536  case ARM::VLD1LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
5537  case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5538  case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5539  case ARM::VLD1LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD1LNd8_UPD;
5540  case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5541  case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5542  case ARM::VLD1LNdAsm_8:  Spacing = 1; return ARM::VLD1LNd8;
5543  case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5544  case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5545
5546  // VLD2LN
5547  case ARM::VLD2LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
5548  case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5549  case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5550  case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5551  case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5552  case ARM::VLD2LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD2LNd8_UPD;
5553  case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5554  case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5555  case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5556  case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5557  case ARM::VLD2LNdAsm_8:  Spacing = 1; return ARM::VLD2LNd8;
5558  case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5559  case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5560  case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5561  case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5562
5563  // VLD3DUP
5564  case ARM::VLD3DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
5565  case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5566  case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5567  case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5568  case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5569  case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5570  case ARM::VLD3DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3DUPd8_UPD;
5571  case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5572  case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5573  case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5574  case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5575  case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5576  case ARM::VLD3DUPdAsm_8:  Spacing = 1; return ARM::VLD3DUPd8;
5577  case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5578  case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5579  case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5580  case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5581  case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5582
5583  // VLD3LN
5584  case ARM::VLD3LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
5585  case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5586  case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5587  case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5588  case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5589  case ARM::VLD3LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD3LNd8_UPD;
5590  case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5591  case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5592  case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5593  case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5594  case ARM::VLD3LNdAsm_8:  Spacing = 1; return ARM::VLD3LNd8;
5595  case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5596  case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5597  case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5598  case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5599
5600  // VLD3
5601  case ARM::VLD3dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
5602  case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5603  case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5604  case ARM::VLD3qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
5605  case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5606  case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5607  case ARM::VLD3dWB_register_Asm_8:  Spacing = 1; return ARM::VLD3d8_UPD;
5608  case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5609  case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5610  case ARM::VLD3qWB_register_Asm_8:  Spacing = 2; return ARM::VLD3q8_UPD;
5611  case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5612  case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5613  case ARM::VLD3dAsm_8:  Spacing = 1; return ARM::VLD3d8;
5614  case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5615  case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5616  case ARM::VLD3qAsm_8:  Spacing = 2; return ARM::VLD3q8;
5617  case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5618  case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5619
5620  // VLD4LN
5621  case ARM::VLD4LNdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
5622  case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5623  case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5624  case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5625  case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5626  case ARM::VLD4LNdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4LNd8_UPD;
5627  case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5628  case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5629  case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5630  case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5631  case ARM::VLD4LNdAsm_8:  Spacing = 1; return ARM::VLD4LNd8;
5632  case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5633  case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5634  case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5635  case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5636
5637  // VLD4DUP
5638  case ARM::VLD4DUPdWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
5639  case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5640  case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5641  case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5642  case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5643  case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5644  case ARM::VLD4DUPdWB_register_Asm_8:  Spacing = 1; return ARM::VLD4DUPd8_UPD;
5645  case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5646  case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5647  case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5648  case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5649  case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5650  case ARM::VLD4DUPdAsm_8:  Spacing = 1; return ARM::VLD4DUPd8;
5651  case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5652  case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5653  case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5654  case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5655  case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5656
5657  // VLD4
5658  case ARM::VLD4dWB_fixed_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
5659  case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5660  case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5661  case ARM::VLD4qWB_fixed_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
5662  case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5663  case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5664  case ARM::VLD4dWB_register_Asm_8:  Spacing = 1; return ARM::VLD4d8_UPD;
5665  case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5666  case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5667  case ARM::VLD4qWB_register_Asm_8:  Spacing = 2; return ARM::VLD4q8_UPD;
5668  case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5669  case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5670  case ARM::VLD4dAsm_8:  Spacing = 1; return ARM::VLD4d8;
5671  case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5672  case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5673  case ARM::VLD4qAsm_8:  Spacing = 2; return ARM::VLD4q8;
5674  case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5675  case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
5676  }
5677}
5678
5679bool ARMAsmParser::
5680processInstruction(MCInst &Inst,
5681                   const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5682  switch (Inst.getOpcode()) {
5683  // Aliases for alternate PC+imm syntax of LDR instructions.
5684  case ARM::t2LDRpcrel:
5685    Inst.setOpcode(ARM::t2LDRpci);
5686    return true;
5687  case ARM::t2LDRBpcrel:
5688    Inst.setOpcode(ARM::t2LDRBpci);
5689    return true;
5690  case ARM::t2LDRHpcrel:
5691    Inst.setOpcode(ARM::t2LDRHpci);
5692    return true;
5693  case ARM::t2LDRSBpcrel:
5694    Inst.setOpcode(ARM::t2LDRSBpci);
5695    return true;
5696  case ARM::t2LDRSHpcrel:
5697    Inst.setOpcode(ARM::t2LDRSHpci);
5698    return true;
5699  // Handle NEON VST complex aliases.
5700  case ARM::VST1LNdWB_register_Asm_8:
5701  case ARM::VST1LNdWB_register_Asm_16:
5702  case ARM::VST1LNdWB_register_Asm_32: {
5703    MCInst TmpInst;
5704    // Shuffle the operands around so the lane index operand is in the
5705    // right place.
5706    unsigned Spacing;
5707    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5708    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5709    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5710    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5711    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5712    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5713    TmpInst.addOperand(Inst.getOperand(1)); // lane
5714    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5715    TmpInst.addOperand(Inst.getOperand(6));
5716    Inst = TmpInst;
5717    return true;
5718  }
5719
5720  case ARM::VST2LNdWB_register_Asm_8:
5721  case ARM::VST2LNdWB_register_Asm_16:
5722  case ARM::VST2LNdWB_register_Asm_32:
5723  case ARM::VST2LNqWB_register_Asm_16:
5724  case ARM::VST2LNqWB_register_Asm_32: {
5725    MCInst TmpInst;
5726    // Shuffle the operands around so the lane index operand is in the
5727    // right place.
5728    unsigned Spacing;
5729    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5730    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5731    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5732    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5733    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5734    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5735    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5736                                            Spacing));
5737    TmpInst.addOperand(Inst.getOperand(1)); // lane
5738    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5739    TmpInst.addOperand(Inst.getOperand(6));
5740    Inst = TmpInst;
5741    return true;
5742  }
5743
5744  case ARM::VST3LNdWB_register_Asm_8:
5745  case ARM::VST3LNdWB_register_Asm_16:
5746  case ARM::VST3LNdWB_register_Asm_32:
5747  case ARM::VST3LNqWB_register_Asm_16:
5748  case ARM::VST3LNqWB_register_Asm_32: {
5749    MCInst TmpInst;
5750    // Shuffle the operands around so the lane index operand is in the
5751    // right place.
5752    unsigned Spacing;
5753    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5754    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5755    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5756    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5757    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5758    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5759    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5760                                            Spacing));
5761    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5762                                            Spacing * 2));
5763    TmpInst.addOperand(Inst.getOperand(1)); // lane
5764    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5765    TmpInst.addOperand(Inst.getOperand(6));
5766    Inst = TmpInst;
5767    return true;
5768  }
5769
5770  case ARM::VST4LNdWB_register_Asm_8:
5771  case ARM::VST4LNdWB_register_Asm_16:
5772  case ARM::VST4LNdWB_register_Asm_32:
5773  case ARM::VST4LNqWB_register_Asm_16:
5774  case ARM::VST4LNqWB_register_Asm_32: {
5775    MCInst TmpInst;
5776    // Shuffle the operands around so the lane index operand is in the
5777    // right place.
5778    unsigned Spacing;
5779    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5780    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5781    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5782    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5783    TmpInst.addOperand(Inst.getOperand(4)); // Rm
5784    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5785    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5786                                            Spacing));
5787    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5788                                            Spacing * 2));
5789    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5790                                            Spacing * 3));
5791    TmpInst.addOperand(Inst.getOperand(1)); // lane
5792    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5793    TmpInst.addOperand(Inst.getOperand(6));
5794    Inst = TmpInst;
5795    return true;
5796  }
5797
5798  case ARM::VST1LNdWB_fixed_Asm_8:
5799  case ARM::VST1LNdWB_fixed_Asm_16:
5800  case ARM::VST1LNdWB_fixed_Asm_32: {
5801    MCInst TmpInst;
5802    // Shuffle the operands around so the lane index operand is in the
5803    // right place.
5804    unsigned Spacing;
5805    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5806    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5807    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5808    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5809    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5810    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5811    TmpInst.addOperand(Inst.getOperand(1)); // lane
5812    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5813    TmpInst.addOperand(Inst.getOperand(5));
5814    Inst = TmpInst;
5815    return true;
5816  }
5817
5818  case ARM::VST2LNdWB_fixed_Asm_8:
5819  case ARM::VST2LNdWB_fixed_Asm_16:
5820  case ARM::VST2LNdWB_fixed_Asm_32:
5821  case ARM::VST2LNqWB_fixed_Asm_16:
5822  case ARM::VST2LNqWB_fixed_Asm_32: {
5823    MCInst TmpInst;
5824    // Shuffle the operands around so the lane index operand is in the
5825    // right place.
5826    unsigned Spacing;
5827    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5828    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5829    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5830    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5831    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5832    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5833    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5834                                            Spacing));
5835    TmpInst.addOperand(Inst.getOperand(1)); // lane
5836    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5837    TmpInst.addOperand(Inst.getOperand(5));
5838    Inst = TmpInst;
5839    return true;
5840  }
5841
5842  case ARM::VST3LNdWB_fixed_Asm_8:
5843  case ARM::VST3LNdWB_fixed_Asm_16:
5844  case ARM::VST3LNdWB_fixed_Asm_32:
5845  case ARM::VST3LNqWB_fixed_Asm_16:
5846  case ARM::VST3LNqWB_fixed_Asm_32: {
5847    MCInst TmpInst;
5848    // Shuffle the operands around so the lane index operand is in the
5849    // right place.
5850    unsigned Spacing;
5851    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5852    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5853    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5854    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5855    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5856    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5857    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5858                                            Spacing));
5859    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5860                                            Spacing * 2));
5861    TmpInst.addOperand(Inst.getOperand(1)); // lane
5862    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5863    TmpInst.addOperand(Inst.getOperand(5));
5864    Inst = TmpInst;
5865    return true;
5866  }
5867
5868  case ARM::VST4LNdWB_fixed_Asm_8:
5869  case ARM::VST4LNdWB_fixed_Asm_16:
5870  case ARM::VST4LNdWB_fixed_Asm_32:
5871  case ARM::VST4LNqWB_fixed_Asm_16:
5872  case ARM::VST4LNqWB_fixed_Asm_32: {
5873    MCInst TmpInst;
5874    // Shuffle the operands around so the lane index operand is in the
5875    // right place.
5876    unsigned Spacing;
5877    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5878    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5879    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5880    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5881    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5882    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5883    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5884                                            Spacing));
5885    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5886                                            Spacing * 2));
5887    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5888                                            Spacing * 3));
5889    TmpInst.addOperand(Inst.getOperand(1)); // lane
5890    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5891    TmpInst.addOperand(Inst.getOperand(5));
5892    Inst = TmpInst;
5893    return true;
5894  }
5895
5896  case ARM::VST1LNdAsm_8:
5897  case ARM::VST1LNdAsm_16:
5898  case ARM::VST1LNdAsm_32: {
5899    MCInst TmpInst;
5900    // Shuffle the operands around so the lane index operand is in the
5901    // right place.
5902    unsigned Spacing;
5903    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5904    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5905    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5906    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5907    TmpInst.addOperand(Inst.getOperand(1)); // lane
5908    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5909    TmpInst.addOperand(Inst.getOperand(5));
5910    Inst = TmpInst;
5911    return true;
5912  }
5913
5914  case ARM::VST2LNdAsm_8:
5915  case ARM::VST2LNdAsm_16:
5916  case ARM::VST2LNdAsm_32:
5917  case ARM::VST2LNqAsm_16:
5918  case ARM::VST2LNqAsm_32: {
5919    MCInst TmpInst;
5920    // Shuffle the operands around so the lane index operand is in the
5921    // right place.
5922    unsigned Spacing;
5923    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5924    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5925    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5926    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5927    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5928                                            Spacing));
5929    TmpInst.addOperand(Inst.getOperand(1)); // lane
5930    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5931    TmpInst.addOperand(Inst.getOperand(5));
5932    Inst = TmpInst;
5933    return true;
5934  }
5935
5936  case ARM::VST3LNdAsm_8:
5937  case ARM::VST3LNdAsm_16:
5938  case ARM::VST3LNdAsm_32:
5939  case ARM::VST3LNqAsm_16:
5940  case ARM::VST3LNqAsm_32: {
5941    MCInst TmpInst;
5942    // Shuffle the operands around so the lane index operand is in the
5943    // right place.
5944    unsigned Spacing;
5945    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5946    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5947    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5948    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5949    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5950                                            Spacing));
5951    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5952                                            Spacing * 2));
5953    TmpInst.addOperand(Inst.getOperand(1)); // lane
5954    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5955    TmpInst.addOperand(Inst.getOperand(5));
5956    Inst = TmpInst;
5957    return true;
5958  }
5959
5960  case ARM::VST4LNdAsm_8:
5961  case ARM::VST4LNdAsm_16:
5962  case ARM::VST4LNdAsm_32:
5963  case ARM::VST4LNqAsm_16:
5964  case ARM::VST4LNqAsm_32: {
5965    MCInst TmpInst;
5966    // Shuffle the operands around so the lane index operand is in the
5967    // right place.
5968    unsigned Spacing;
5969    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5970    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5971    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5972    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5973    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5974                                            Spacing));
5975    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5976                                            Spacing * 2));
5977    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5978                                            Spacing * 3));
5979    TmpInst.addOperand(Inst.getOperand(1)); // lane
5980    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5981    TmpInst.addOperand(Inst.getOperand(5));
5982    Inst = TmpInst;
5983    return true;
5984  }
5985
5986  // Handle NEON VLD complex aliases.
5987  case ARM::VLD1LNdWB_register_Asm_8:
5988  case ARM::VLD1LNdWB_register_Asm_16:
5989  case ARM::VLD1LNdWB_register_Asm_32: {
5990    MCInst TmpInst;
5991    // Shuffle the operands around so the lane index operand is in the
5992    // right place.
5993    unsigned Spacing;
5994    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
5995    TmpInst.addOperand(Inst.getOperand(0)); // Vd
5996    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5997    TmpInst.addOperand(Inst.getOperand(2)); // Rn
5998    TmpInst.addOperand(Inst.getOperand(3)); // alignment
5999    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6000    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6001    TmpInst.addOperand(Inst.getOperand(1)); // lane
6002    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6003    TmpInst.addOperand(Inst.getOperand(6));
6004    Inst = TmpInst;
6005    return true;
6006  }
6007
6008  case ARM::VLD2LNdWB_register_Asm_8:
6009  case ARM::VLD2LNdWB_register_Asm_16:
6010  case ARM::VLD2LNdWB_register_Asm_32:
6011  case ARM::VLD2LNqWB_register_Asm_16:
6012  case ARM::VLD2LNqWB_register_Asm_32: {
6013    MCInst TmpInst;
6014    // Shuffle the operands around so the lane index operand is in the
6015    // right place.
6016    unsigned Spacing;
6017    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6018    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6019    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6020                                            Spacing));
6021    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6022    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6023    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6024    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6025    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6026    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6027                                            Spacing));
6028    TmpInst.addOperand(Inst.getOperand(1)); // lane
6029    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6030    TmpInst.addOperand(Inst.getOperand(6));
6031    Inst = TmpInst;
6032    return true;
6033  }
6034
6035  case ARM::VLD3LNdWB_register_Asm_8:
6036  case ARM::VLD3LNdWB_register_Asm_16:
6037  case ARM::VLD3LNdWB_register_Asm_32:
6038  case ARM::VLD3LNqWB_register_Asm_16:
6039  case ARM::VLD3LNqWB_register_Asm_32: {
6040    MCInst TmpInst;
6041    // Shuffle the operands around so the lane index operand is in the
6042    // right place.
6043    unsigned Spacing;
6044    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6045    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6046    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6047                                            Spacing));
6048    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6049                                            Spacing * 2));
6050    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6051    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6052    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6053    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6054    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6055    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6056                                            Spacing));
6057    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6058                                            Spacing * 2));
6059    TmpInst.addOperand(Inst.getOperand(1)); // lane
6060    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6061    TmpInst.addOperand(Inst.getOperand(6));
6062    Inst = TmpInst;
6063    return true;
6064  }
6065
6066  case ARM::VLD4LNdWB_register_Asm_8:
6067  case ARM::VLD4LNdWB_register_Asm_16:
6068  case ARM::VLD4LNdWB_register_Asm_32:
6069  case ARM::VLD4LNqWB_register_Asm_16:
6070  case ARM::VLD4LNqWB_register_Asm_32: {
6071    MCInst TmpInst;
6072    // Shuffle the operands around so the lane index operand is in the
6073    // right place.
6074    unsigned Spacing;
6075    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6076    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6077    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6078                                            Spacing));
6079    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6080                                            Spacing * 2));
6081    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6082                                            Spacing * 3));
6083    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6084    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6085    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6086    TmpInst.addOperand(Inst.getOperand(4)); // Rm
6087    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6088    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6089                                            Spacing));
6090    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6091                                            Spacing * 2));
6092    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6093                                            Spacing * 3));
6094    TmpInst.addOperand(Inst.getOperand(1)); // lane
6095    TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6096    TmpInst.addOperand(Inst.getOperand(6));
6097    Inst = TmpInst;
6098    return true;
6099  }
6100
6101  case ARM::VLD1LNdWB_fixed_Asm_8:
6102  case ARM::VLD1LNdWB_fixed_Asm_16:
6103  case ARM::VLD1LNdWB_fixed_Asm_32: {
6104    MCInst TmpInst;
6105    // Shuffle the operands around so the lane index operand is in the
6106    // right place.
6107    unsigned Spacing;
6108    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6109    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6110    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6111    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6112    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6113    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6114    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6115    TmpInst.addOperand(Inst.getOperand(1)); // lane
6116    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6117    TmpInst.addOperand(Inst.getOperand(5));
6118    Inst = TmpInst;
6119    return true;
6120  }
6121
6122  case ARM::VLD2LNdWB_fixed_Asm_8:
6123  case ARM::VLD2LNdWB_fixed_Asm_16:
6124  case ARM::VLD2LNdWB_fixed_Asm_32:
6125  case ARM::VLD2LNqWB_fixed_Asm_16:
6126  case ARM::VLD2LNqWB_fixed_Asm_32: {
6127    MCInst TmpInst;
6128    // Shuffle the operands around so the lane index operand is in the
6129    // right place.
6130    unsigned Spacing;
6131    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6132    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6133    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6134                                            Spacing));
6135    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6136    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6137    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6138    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6139    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6140    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6141                                            Spacing));
6142    TmpInst.addOperand(Inst.getOperand(1)); // lane
6143    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6144    TmpInst.addOperand(Inst.getOperand(5));
6145    Inst = TmpInst;
6146    return true;
6147  }
6148
6149  case ARM::VLD3LNdWB_fixed_Asm_8:
6150  case ARM::VLD3LNdWB_fixed_Asm_16:
6151  case ARM::VLD3LNdWB_fixed_Asm_32:
6152  case ARM::VLD3LNqWB_fixed_Asm_16:
6153  case ARM::VLD3LNqWB_fixed_Asm_32: {
6154    MCInst TmpInst;
6155    // Shuffle the operands around so the lane index operand is in the
6156    // right place.
6157    unsigned Spacing;
6158    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6159    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6160    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6161                                            Spacing));
6162    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6163                                            Spacing * 2));
6164    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6165    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6166    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6167    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6168    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6169    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6170                                            Spacing));
6171    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6172                                            Spacing * 2));
6173    TmpInst.addOperand(Inst.getOperand(1)); // lane
6174    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6175    TmpInst.addOperand(Inst.getOperand(5));
6176    Inst = TmpInst;
6177    return true;
6178  }
6179
6180  case ARM::VLD4LNdWB_fixed_Asm_8:
6181  case ARM::VLD4LNdWB_fixed_Asm_16:
6182  case ARM::VLD4LNdWB_fixed_Asm_32:
6183  case ARM::VLD4LNqWB_fixed_Asm_16:
6184  case ARM::VLD4LNqWB_fixed_Asm_32: {
6185    MCInst TmpInst;
6186    // Shuffle the operands around so the lane index operand is in the
6187    // right place.
6188    unsigned Spacing;
6189    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6190    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6191    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6192                                            Spacing));
6193    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6194                                            Spacing * 2));
6195    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6196                                            Spacing * 3));
6197    TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6198    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6199    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6200    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6201    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6202    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6203                                            Spacing));
6204    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6205                                            Spacing * 2));
6206    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6207                                            Spacing * 3));
6208    TmpInst.addOperand(Inst.getOperand(1)); // lane
6209    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6210    TmpInst.addOperand(Inst.getOperand(5));
6211    Inst = TmpInst;
6212    return true;
6213  }
6214
6215  case ARM::VLD1LNdAsm_8:
6216  case ARM::VLD1LNdAsm_16:
6217  case ARM::VLD1LNdAsm_32: {
6218    MCInst TmpInst;
6219    // Shuffle the operands around so the lane index operand is in the
6220    // right place.
6221    unsigned Spacing;
6222    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6223    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6224    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6225    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6226    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6227    TmpInst.addOperand(Inst.getOperand(1)); // lane
6228    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6229    TmpInst.addOperand(Inst.getOperand(5));
6230    Inst = TmpInst;
6231    return true;
6232  }
6233
6234  case ARM::VLD2LNdAsm_8:
6235  case ARM::VLD2LNdAsm_16:
6236  case ARM::VLD2LNdAsm_32:
6237  case ARM::VLD2LNqAsm_16:
6238  case ARM::VLD2LNqAsm_32: {
6239    MCInst TmpInst;
6240    // Shuffle the operands around so the lane index operand is in the
6241    // right place.
6242    unsigned Spacing;
6243    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6244    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6245    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6246                                            Spacing));
6247    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6248    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6249    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6250    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6251                                            Spacing));
6252    TmpInst.addOperand(Inst.getOperand(1)); // lane
6253    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6254    TmpInst.addOperand(Inst.getOperand(5));
6255    Inst = TmpInst;
6256    return true;
6257  }
6258
6259  case ARM::VLD3LNdAsm_8:
6260  case ARM::VLD3LNdAsm_16:
6261  case ARM::VLD3LNdAsm_32:
6262  case ARM::VLD3LNqAsm_16:
6263  case ARM::VLD3LNqAsm_32: {
6264    MCInst TmpInst;
6265    // Shuffle the operands around so the lane index operand is in the
6266    // right place.
6267    unsigned Spacing;
6268    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6269    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6270    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6271                                            Spacing));
6272    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6273                                            Spacing * 2));
6274    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6275    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6276    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6277    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6278                                            Spacing));
6279    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6280                                            Spacing * 2));
6281    TmpInst.addOperand(Inst.getOperand(1)); // lane
6282    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6283    TmpInst.addOperand(Inst.getOperand(5));
6284    Inst = TmpInst;
6285    return true;
6286  }
6287
6288  case ARM::VLD4LNdAsm_8:
6289  case ARM::VLD4LNdAsm_16:
6290  case ARM::VLD4LNdAsm_32:
6291  case ARM::VLD4LNqAsm_16:
6292  case ARM::VLD4LNqAsm_32: {
6293    MCInst TmpInst;
6294    // Shuffle the operands around so the lane index operand is in the
6295    // right place.
6296    unsigned Spacing;
6297    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6298    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6299    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6300                                            Spacing));
6301    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6302                                            Spacing * 2));
6303    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6304                                            Spacing * 3));
6305    TmpInst.addOperand(Inst.getOperand(2)); // Rn
6306    TmpInst.addOperand(Inst.getOperand(3)); // alignment
6307    TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6308    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6309                                            Spacing));
6310    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6311                                            Spacing * 2));
6312    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6313                                            Spacing * 3));
6314    TmpInst.addOperand(Inst.getOperand(1)); // lane
6315    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6316    TmpInst.addOperand(Inst.getOperand(5));
6317    Inst = TmpInst;
6318    return true;
6319  }
6320
6321  // VLD3DUP single 3-element structure to all lanes instructions.
6322  case ARM::VLD3DUPdAsm_8:
6323  case ARM::VLD3DUPdAsm_16:
6324  case ARM::VLD3DUPdAsm_32:
6325  case ARM::VLD3DUPqAsm_8:
6326  case ARM::VLD3DUPqAsm_16:
6327  case ARM::VLD3DUPqAsm_32: {
6328    MCInst TmpInst;
6329    unsigned Spacing;
6330    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6331    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6332    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6333                                            Spacing));
6334    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6335                                            Spacing * 2));
6336    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6337    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6338    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6339    TmpInst.addOperand(Inst.getOperand(4));
6340    Inst = TmpInst;
6341    return true;
6342  }
6343
6344  case ARM::VLD3DUPdWB_fixed_Asm_8:
6345  case ARM::VLD3DUPdWB_fixed_Asm_16:
6346  case ARM::VLD3DUPdWB_fixed_Asm_32:
6347  case ARM::VLD3DUPqWB_fixed_Asm_8:
6348  case ARM::VLD3DUPqWB_fixed_Asm_16:
6349  case ARM::VLD3DUPqWB_fixed_Asm_32: {
6350    MCInst TmpInst;
6351    unsigned Spacing;
6352    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6353    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6354    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6355                                            Spacing));
6356    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6357                                            Spacing * 2));
6358    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6359    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6360    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6361    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6362    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6363    TmpInst.addOperand(Inst.getOperand(4));
6364    Inst = TmpInst;
6365    return true;
6366  }
6367
6368  case ARM::VLD3DUPdWB_register_Asm_8:
6369  case ARM::VLD3DUPdWB_register_Asm_16:
6370  case ARM::VLD3DUPdWB_register_Asm_32:
6371  case ARM::VLD3DUPqWB_register_Asm_8:
6372  case ARM::VLD3DUPqWB_register_Asm_16:
6373  case ARM::VLD3DUPqWB_register_Asm_32: {
6374    MCInst TmpInst;
6375    unsigned Spacing;
6376    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6377    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6378    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6379                                            Spacing));
6380    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6381                                            Spacing * 2));
6382    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6383    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6384    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6385    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6386    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6387    TmpInst.addOperand(Inst.getOperand(5));
6388    Inst = TmpInst;
6389    return true;
6390  }
6391
6392  // VLD3 multiple 3-element structure instructions.
6393  case ARM::VLD3dAsm_8:
6394  case ARM::VLD3dAsm_16:
6395  case ARM::VLD3dAsm_32:
6396  case ARM::VLD3qAsm_8:
6397  case ARM::VLD3qAsm_16:
6398  case ARM::VLD3qAsm_32: {
6399    MCInst TmpInst;
6400    unsigned Spacing;
6401    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6402    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6403    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6404                                            Spacing));
6405    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6406                                            Spacing * 2));
6407    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6408    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6409    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6410    TmpInst.addOperand(Inst.getOperand(4));
6411    Inst = TmpInst;
6412    return true;
6413  }
6414
6415  case ARM::VLD3dWB_fixed_Asm_8:
6416  case ARM::VLD3dWB_fixed_Asm_16:
6417  case ARM::VLD3dWB_fixed_Asm_32:
6418  case ARM::VLD3qWB_fixed_Asm_8:
6419  case ARM::VLD3qWB_fixed_Asm_16:
6420  case ARM::VLD3qWB_fixed_Asm_32: {
6421    MCInst TmpInst;
6422    unsigned Spacing;
6423    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6424    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6425    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6426                                            Spacing));
6427    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6428                                            Spacing * 2));
6429    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6430    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6431    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6432    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6433    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6434    TmpInst.addOperand(Inst.getOperand(4));
6435    Inst = TmpInst;
6436    return true;
6437  }
6438
6439  case ARM::VLD3dWB_register_Asm_8:
6440  case ARM::VLD3dWB_register_Asm_16:
6441  case ARM::VLD3dWB_register_Asm_32:
6442  case ARM::VLD3qWB_register_Asm_8:
6443  case ARM::VLD3qWB_register_Asm_16:
6444  case ARM::VLD3qWB_register_Asm_32: {
6445    MCInst TmpInst;
6446    unsigned Spacing;
6447    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6448    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6449    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6450                                            Spacing));
6451    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6452                                            Spacing * 2));
6453    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6454    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6455    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6456    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6457    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6458    TmpInst.addOperand(Inst.getOperand(5));
6459    Inst = TmpInst;
6460    return true;
6461  }
6462
6463  // VLD4DUP single 3-element structure to all lanes instructions.
6464  case ARM::VLD4DUPdAsm_8:
6465  case ARM::VLD4DUPdAsm_16:
6466  case ARM::VLD4DUPdAsm_32:
6467  case ARM::VLD4DUPqAsm_8:
6468  case ARM::VLD4DUPqAsm_16:
6469  case ARM::VLD4DUPqAsm_32: {
6470    MCInst TmpInst;
6471    unsigned Spacing;
6472    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6473    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6474    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6475                                            Spacing));
6476    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6477                                            Spacing * 2));
6478    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6479                                            Spacing * 3));
6480    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6481    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6482    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6483    TmpInst.addOperand(Inst.getOperand(4));
6484    Inst = TmpInst;
6485    return true;
6486  }
6487
6488  case ARM::VLD4DUPdWB_fixed_Asm_8:
6489  case ARM::VLD4DUPdWB_fixed_Asm_16:
6490  case ARM::VLD4DUPdWB_fixed_Asm_32:
6491  case ARM::VLD4DUPqWB_fixed_Asm_8:
6492  case ARM::VLD4DUPqWB_fixed_Asm_16:
6493  case ARM::VLD4DUPqWB_fixed_Asm_32: {
6494    MCInst TmpInst;
6495    unsigned Spacing;
6496    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6497    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6498    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6499                                            Spacing));
6500    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6501                                            Spacing * 2));
6502    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6503                                            Spacing * 3));
6504    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6505    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6506    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6507    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6508    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6509    TmpInst.addOperand(Inst.getOperand(4));
6510    Inst = TmpInst;
6511    return true;
6512  }
6513
6514  case ARM::VLD4DUPdWB_register_Asm_8:
6515  case ARM::VLD4DUPdWB_register_Asm_16:
6516  case ARM::VLD4DUPdWB_register_Asm_32:
6517  case ARM::VLD4DUPqWB_register_Asm_8:
6518  case ARM::VLD4DUPqWB_register_Asm_16:
6519  case ARM::VLD4DUPqWB_register_Asm_32: {
6520    MCInst TmpInst;
6521    unsigned Spacing;
6522    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6523    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6524    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6525                                            Spacing));
6526    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6527                                            Spacing * 2));
6528    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6529                                            Spacing * 3));
6530    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6531    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6532    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6533    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6534    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6535    TmpInst.addOperand(Inst.getOperand(5));
6536    Inst = TmpInst;
6537    return true;
6538  }
6539
6540  // VLD4 multiple 4-element structure instructions.
6541  case ARM::VLD4dAsm_8:
6542  case ARM::VLD4dAsm_16:
6543  case ARM::VLD4dAsm_32:
6544  case ARM::VLD4qAsm_8:
6545  case ARM::VLD4qAsm_16:
6546  case ARM::VLD4qAsm_32: {
6547    MCInst TmpInst;
6548    unsigned Spacing;
6549    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6550    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6551    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6552                                            Spacing));
6553    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6554                                            Spacing * 2));
6555    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6556                                            Spacing * 3));
6557    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6558    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6559    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6560    TmpInst.addOperand(Inst.getOperand(4));
6561    Inst = TmpInst;
6562    return true;
6563  }
6564
6565  case ARM::VLD4dWB_fixed_Asm_8:
6566  case ARM::VLD4dWB_fixed_Asm_16:
6567  case ARM::VLD4dWB_fixed_Asm_32:
6568  case ARM::VLD4qWB_fixed_Asm_8:
6569  case ARM::VLD4qWB_fixed_Asm_16:
6570  case ARM::VLD4qWB_fixed_Asm_32: {
6571    MCInst TmpInst;
6572    unsigned Spacing;
6573    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6574    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6575    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6576                                            Spacing));
6577    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6578                                            Spacing * 2));
6579    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6580                                            Spacing * 3));
6581    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6582    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6583    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6584    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6585    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6586    TmpInst.addOperand(Inst.getOperand(4));
6587    Inst = TmpInst;
6588    return true;
6589  }
6590
6591  case ARM::VLD4dWB_register_Asm_8:
6592  case ARM::VLD4dWB_register_Asm_16:
6593  case ARM::VLD4dWB_register_Asm_32:
6594  case ARM::VLD4qWB_register_Asm_8:
6595  case ARM::VLD4qWB_register_Asm_16:
6596  case ARM::VLD4qWB_register_Asm_32: {
6597    MCInst TmpInst;
6598    unsigned Spacing;
6599    TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6600    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6601    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6602                                            Spacing));
6603    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6604                                            Spacing * 2));
6605    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6606                                            Spacing * 3));
6607    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6608    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6609    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6610    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6611    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6612    TmpInst.addOperand(Inst.getOperand(5));
6613    Inst = TmpInst;
6614    return true;
6615  }
6616
6617  // VST3 multiple 3-element structure instructions.
6618  case ARM::VST3dAsm_8:
6619  case ARM::VST3dAsm_16:
6620  case ARM::VST3dAsm_32:
6621  case ARM::VST3qAsm_8:
6622  case ARM::VST3qAsm_16:
6623  case ARM::VST3qAsm_32: {
6624    MCInst TmpInst;
6625    unsigned Spacing;
6626    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6627    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6628    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6629    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6630    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6631                                            Spacing));
6632    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6633                                            Spacing * 2));
6634    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6635    TmpInst.addOperand(Inst.getOperand(4));
6636    Inst = TmpInst;
6637    return true;
6638  }
6639
6640  case ARM::VST3dWB_fixed_Asm_8:
6641  case ARM::VST3dWB_fixed_Asm_16:
6642  case ARM::VST3dWB_fixed_Asm_32:
6643  case ARM::VST3qWB_fixed_Asm_8:
6644  case ARM::VST3qWB_fixed_Asm_16:
6645  case ARM::VST3qWB_fixed_Asm_32: {
6646    MCInst TmpInst;
6647    unsigned Spacing;
6648    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6649    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6650    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6651    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6652    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6653    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6654    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6655                                            Spacing));
6656    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6657                                            Spacing * 2));
6658    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6659    TmpInst.addOperand(Inst.getOperand(4));
6660    Inst = TmpInst;
6661    return true;
6662  }
6663
6664  case ARM::VST3dWB_register_Asm_8:
6665  case ARM::VST3dWB_register_Asm_16:
6666  case ARM::VST3dWB_register_Asm_32:
6667  case ARM::VST3qWB_register_Asm_8:
6668  case ARM::VST3qWB_register_Asm_16:
6669  case ARM::VST3qWB_register_Asm_32: {
6670    MCInst TmpInst;
6671    unsigned Spacing;
6672    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6673    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6674    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6675    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6676    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6677    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6678    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6679                                            Spacing));
6680    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6681                                            Spacing * 2));
6682    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6683    TmpInst.addOperand(Inst.getOperand(5));
6684    Inst = TmpInst;
6685    return true;
6686  }
6687
6688  // VST4 multiple 3-element structure instructions.
6689  case ARM::VST4dAsm_8:
6690  case ARM::VST4dAsm_16:
6691  case ARM::VST4dAsm_32:
6692  case ARM::VST4qAsm_8:
6693  case ARM::VST4qAsm_16:
6694  case ARM::VST4qAsm_32: {
6695    MCInst TmpInst;
6696    unsigned Spacing;
6697    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6698    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6699    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6700    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6701    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6702                                            Spacing));
6703    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6704                                            Spacing * 2));
6705    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6706                                            Spacing * 3));
6707    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6708    TmpInst.addOperand(Inst.getOperand(4));
6709    Inst = TmpInst;
6710    return true;
6711  }
6712
6713  case ARM::VST4dWB_fixed_Asm_8:
6714  case ARM::VST4dWB_fixed_Asm_16:
6715  case ARM::VST4dWB_fixed_Asm_32:
6716  case ARM::VST4qWB_fixed_Asm_8:
6717  case ARM::VST4qWB_fixed_Asm_16:
6718  case ARM::VST4qWB_fixed_Asm_32: {
6719    MCInst TmpInst;
6720    unsigned Spacing;
6721    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6722    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6723    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6724    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6725    TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6726    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6727    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6728                                            Spacing));
6729    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6730                                            Spacing * 2));
6731    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6732                                            Spacing * 3));
6733    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6734    TmpInst.addOperand(Inst.getOperand(4));
6735    Inst = TmpInst;
6736    return true;
6737  }
6738
6739  case ARM::VST4dWB_register_Asm_8:
6740  case ARM::VST4dWB_register_Asm_16:
6741  case ARM::VST4dWB_register_Asm_32:
6742  case ARM::VST4qWB_register_Asm_8:
6743  case ARM::VST4qWB_register_Asm_16:
6744  case ARM::VST4qWB_register_Asm_32: {
6745    MCInst TmpInst;
6746    unsigned Spacing;
6747    TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6748    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6749    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6750    TmpInst.addOperand(Inst.getOperand(2)); // alignment
6751    TmpInst.addOperand(Inst.getOperand(3)); // Rm
6752    TmpInst.addOperand(Inst.getOperand(0)); // Vd
6753    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6754                                            Spacing));
6755    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6756                                            Spacing * 2));
6757    TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6758                                            Spacing * 3));
6759    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6760    TmpInst.addOperand(Inst.getOperand(5));
6761    Inst = TmpInst;
6762    return true;
6763  }
6764
6765  // Handle encoding choice for the shift-immediate instructions.
6766  case ARM::t2LSLri:
6767  case ARM::t2LSRri:
6768  case ARM::t2ASRri: {
6769    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6770        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6771        Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6772        !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
6773         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
6774      unsigned NewOpc;
6775      switch (Inst.getOpcode()) {
6776      default: llvm_unreachable("unexpected opcode");
6777      case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
6778      case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
6779      case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
6780      }
6781      // The Thumb1 operands aren't in the same order. Awesome, eh?
6782      MCInst TmpInst;
6783      TmpInst.setOpcode(NewOpc);
6784      TmpInst.addOperand(Inst.getOperand(0));
6785      TmpInst.addOperand(Inst.getOperand(5));
6786      TmpInst.addOperand(Inst.getOperand(1));
6787      TmpInst.addOperand(Inst.getOperand(2));
6788      TmpInst.addOperand(Inst.getOperand(3));
6789      TmpInst.addOperand(Inst.getOperand(4));
6790      Inst = TmpInst;
6791      return true;
6792    }
6793    return false;
6794  }
6795
6796  // Handle the Thumb2 mode MOV complex aliases.
6797  case ARM::t2MOVsr:
6798  case ARM::t2MOVSsr: {
6799    // Which instruction to expand to depends on the CCOut operand and
6800    // whether we're in an IT block if the register operands are low
6801    // registers.
6802    bool isNarrow = false;
6803    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6804        isARMLowRegister(Inst.getOperand(1).getReg()) &&
6805        isARMLowRegister(Inst.getOperand(2).getReg()) &&
6806        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6807        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
6808      isNarrow = true;
6809    MCInst TmpInst;
6810    unsigned newOpc;
6811    switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
6812    default: llvm_unreachable("unexpected opcode!");
6813    case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
6814    case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
6815    case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
6816    case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR   : ARM::t2RORrr; break;
6817    }
6818    TmpInst.setOpcode(newOpc);
6819    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6820    if (isNarrow)
6821      TmpInst.addOperand(MCOperand::CreateReg(
6822          Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6823    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6824    TmpInst.addOperand(Inst.getOperand(2)); // Rm
6825    TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6826    TmpInst.addOperand(Inst.getOperand(5));
6827    if (!isNarrow)
6828      TmpInst.addOperand(MCOperand::CreateReg(
6829          Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6830    Inst = TmpInst;
6831    return true;
6832  }
6833  case ARM::t2MOVsi:
6834  case ARM::t2MOVSsi: {
6835    // Which instruction to expand to depends on the CCOut operand and
6836    // whether we're in an IT block if the register operands are low
6837    // registers.
6838    bool isNarrow = false;
6839    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6840        isARMLowRegister(Inst.getOperand(1).getReg()) &&
6841        inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
6842      isNarrow = true;
6843    MCInst TmpInst;
6844    unsigned newOpc;
6845    switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
6846    default: llvm_unreachable("unexpected opcode!");
6847    case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
6848    case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
6849    case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
6850    case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
6851    case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
6852    }
6853    unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
6854    if (Amount == 32) Amount = 0;
6855    TmpInst.setOpcode(newOpc);
6856    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6857    if (isNarrow)
6858      TmpInst.addOperand(MCOperand::CreateReg(
6859          Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6860    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6861    if (newOpc != ARM::t2RRX)
6862      TmpInst.addOperand(MCOperand::CreateImm(Amount));
6863    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6864    TmpInst.addOperand(Inst.getOperand(4));
6865    if (!isNarrow)
6866      TmpInst.addOperand(MCOperand::CreateReg(
6867          Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6868    Inst = TmpInst;
6869    return true;
6870  }
6871  // Handle the ARM mode MOV complex aliases.
6872  case ARM::ASRr:
6873  case ARM::LSRr:
6874  case ARM::LSLr:
6875  case ARM::RORr: {
6876    ARM_AM::ShiftOpc ShiftTy;
6877    switch(Inst.getOpcode()) {
6878    default: llvm_unreachable("unexpected opcode!");
6879    case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
6880    case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
6881    case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
6882    case ARM::RORr: ShiftTy = ARM_AM::ror; break;
6883    }
6884    unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
6885    MCInst TmpInst;
6886    TmpInst.setOpcode(ARM::MOVsr);
6887    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6888    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6889    TmpInst.addOperand(Inst.getOperand(2)); // Rm
6890    TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6891    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6892    TmpInst.addOperand(Inst.getOperand(4));
6893    TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6894    Inst = TmpInst;
6895    return true;
6896  }
6897  case ARM::ASRi:
6898  case ARM::LSRi:
6899  case ARM::LSLi:
6900  case ARM::RORi: {
6901    ARM_AM::ShiftOpc ShiftTy;
6902    switch(Inst.getOpcode()) {
6903    default: llvm_unreachable("unexpected opcode!");
6904    case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
6905    case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
6906    case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
6907    case ARM::RORi: ShiftTy = ARM_AM::ror; break;
6908    }
6909    // A shift by zero is a plain MOVr, not a MOVsi.
6910    unsigned Amt = Inst.getOperand(2).getImm();
6911    unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
6912    // A shift by 32 should be encoded as 0 when permitted
6913    if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
6914      Amt = 0;
6915    unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
6916    MCInst TmpInst;
6917    TmpInst.setOpcode(Opc);
6918    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6919    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6920    if (Opc == ARM::MOVsi)
6921      TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6922    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6923    TmpInst.addOperand(Inst.getOperand(4));
6924    TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6925    Inst = TmpInst;
6926    return true;
6927  }
6928  case ARM::RRXi: {
6929    unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
6930    MCInst TmpInst;
6931    TmpInst.setOpcode(ARM::MOVsi);
6932    TmpInst.addOperand(Inst.getOperand(0)); // Rd
6933    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6934    TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6935    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6936    TmpInst.addOperand(Inst.getOperand(3));
6937    TmpInst.addOperand(Inst.getOperand(4)); // cc_out
6938    Inst = TmpInst;
6939    return true;
6940  }
6941  case ARM::t2LDMIA_UPD: {
6942    // If this is a load of a single register, then we should use
6943    // a post-indexed LDR instruction instead, per the ARM ARM.
6944    if (Inst.getNumOperands() != 5)
6945      return false;
6946    MCInst TmpInst;
6947    TmpInst.setOpcode(ARM::t2LDR_POST);
6948    TmpInst.addOperand(Inst.getOperand(4)); // Rt
6949    TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6950    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6951    TmpInst.addOperand(MCOperand::CreateImm(4));
6952    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6953    TmpInst.addOperand(Inst.getOperand(3));
6954    Inst = TmpInst;
6955    return true;
6956  }
6957  case ARM::t2STMDB_UPD: {
6958    // If this is a store of a single register, then we should use
6959    // a pre-indexed STR instruction instead, per the ARM ARM.
6960    if (Inst.getNumOperands() != 5)
6961      return false;
6962    MCInst TmpInst;
6963    TmpInst.setOpcode(ARM::t2STR_PRE);
6964    TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6965    TmpInst.addOperand(Inst.getOperand(4)); // Rt
6966    TmpInst.addOperand(Inst.getOperand(1)); // Rn
6967    TmpInst.addOperand(MCOperand::CreateImm(-4));
6968    TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6969    TmpInst.addOperand(Inst.getOperand(3));
6970    Inst = TmpInst;
6971    return true;
6972  }
6973  case ARM::LDMIA_UPD:
6974    // If this is a load of a single register via a 'pop', then we should use
6975    // a post-indexed LDR instruction instead, per the ARM ARM.
6976    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
6977        Inst.getNumOperands() == 5) {
6978      MCInst TmpInst;
6979      TmpInst.setOpcode(ARM::LDR_POST_IMM);
6980      TmpInst.addOperand(Inst.getOperand(4)); // Rt
6981      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6982      TmpInst.addOperand(Inst.getOperand(1)); // Rn
6983      TmpInst.addOperand(MCOperand::CreateReg(0));  // am2offset
6984      TmpInst.addOperand(MCOperand::CreateImm(4));
6985      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6986      TmpInst.addOperand(Inst.getOperand(3));
6987      Inst = TmpInst;
6988      return true;
6989    }
6990    break;
6991  case ARM::STMDB_UPD:
6992    // If this is a store of a single register via a 'push', then we should use
6993    // a pre-indexed STR instruction instead, per the ARM ARM.
6994    if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
6995        Inst.getNumOperands() == 5) {
6996      MCInst TmpInst;
6997      TmpInst.setOpcode(ARM::STR_PRE_IMM);
6998      TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
6999      TmpInst.addOperand(Inst.getOperand(4)); // Rt
7000      TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7001      TmpInst.addOperand(MCOperand::CreateImm(-4));
7002      TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7003      TmpInst.addOperand(Inst.getOperand(3));
7004      Inst = TmpInst;
7005    }
7006    break;
7007  case ARM::t2ADDri12:
7008    // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7009    // mnemonic was used (not "addw"), encoding T3 is preferred.
7010    if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7011        ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7012      break;
7013    Inst.setOpcode(ARM::t2ADDri);
7014    Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7015    break;
7016  case ARM::t2SUBri12:
7017    // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7018    // mnemonic was used (not "subw"), encoding T3 is preferred.
7019    if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7020        ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7021      break;
7022    Inst.setOpcode(ARM::t2SUBri);
7023    Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7024    break;
7025  case ARM::tADDi8:
7026    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7027    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7028    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7029    // to encoding T1 if <Rd> is omitted."
7030    if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7031      Inst.setOpcode(ARM::tADDi3);
7032      return true;
7033    }
7034    break;
7035  case ARM::tSUBi8:
7036    // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7037    // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7038    // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7039    // to encoding T1 if <Rd> is omitted."
7040    if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7041      Inst.setOpcode(ARM::tSUBi3);
7042      return true;
7043    }
7044    break;
7045  case ARM::t2ADDri:
7046  case ARM::t2SUBri: {
7047    // If the destination and first source operand are the same, and
7048    // the flags are compatible with the current IT status, use encoding T2
7049    // instead of T3. For compatibility with the system 'as'. Make sure the
7050    // wide encoding wasn't explicit.
7051    if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7052        !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7053        (unsigned)Inst.getOperand(2).getImm() > 255 ||
7054        ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7055        (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7056        (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7057         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7058      break;
7059    MCInst TmpInst;
7060    TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7061                      ARM::tADDi8 : ARM::tSUBi8);
7062    TmpInst.addOperand(Inst.getOperand(0));
7063    TmpInst.addOperand(Inst.getOperand(5));
7064    TmpInst.addOperand(Inst.getOperand(0));
7065    TmpInst.addOperand(Inst.getOperand(2));
7066    TmpInst.addOperand(Inst.getOperand(3));
7067    TmpInst.addOperand(Inst.getOperand(4));
7068    Inst = TmpInst;
7069    return true;
7070  }
7071  case ARM::t2ADDrr: {
7072    // If the destination and first source operand are the same, and
7073    // there's no setting of the flags, use encoding T2 instead of T3.
7074    // Note that this is only for ADD, not SUB. This mirrors the system
7075    // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7076    if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7077        Inst.getOperand(5).getReg() != 0 ||
7078        (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7079         static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7080      break;
7081    MCInst TmpInst;
7082    TmpInst.setOpcode(ARM::tADDhirr);
7083    TmpInst.addOperand(Inst.getOperand(0));
7084    TmpInst.addOperand(Inst.getOperand(0));
7085    TmpInst.addOperand(Inst.getOperand(2));
7086    TmpInst.addOperand(Inst.getOperand(3));
7087    TmpInst.addOperand(Inst.getOperand(4));
7088    Inst = TmpInst;
7089    return true;
7090  }
7091  case ARM::tADDrSP: {
7092    // If the non-SP source operand and the destination operand are not the
7093    // same, we need to use the 32-bit encoding if it's available.
7094    if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7095      Inst.setOpcode(ARM::t2ADDrr);
7096      Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7097      return true;
7098    }
7099    break;
7100  }
7101  case ARM::tB:
7102    // A Thumb conditional branch outside of an IT block is a tBcc.
7103    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7104      Inst.setOpcode(ARM::tBcc);
7105      return true;
7106    }
7107    break;
7108  case ARM::t2B:
7109    // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7110    if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7111      Inst.setOpcode(ARM::t2Bcc);
7112      return true;
7113    }
7114    break;
7115  case ARM::t2Bcc:
7116    // If the conditional is AL or we're in an IT block, we really want t2B.
7117    if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7118      Inst.setOpcode(ARM::t2B);
7119      return true;
7120    }
7121    break;
7122  case ARM::tBcc:
7123    // If the conditional is AL, we really want tB.
7124    if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7125      Inst.setOpcode(ARM::tB);
7126      return true;
7127    }
7128    break;
7129  case ARM::tLDMIA: {
7130    // If the register list contains any high registers, or if the writeback
7131    // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7132    // instead if we're in Thumb2. Otherwise, this should have generated
7133    // an error in validateInstruction().
7134    unsigned Rn = Inst.getOperand(0).getReg();
7135    bool hasWritebackToken =
7136      (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7137       static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7138    bool listContainsBase;
7139    if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7140        (!listContainsBase && !hasWritebackToken) ||
7141        (listContainsBase && hasWritebackToken)) {
7142      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7143      assert (isThumbTwo());
7144      Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7145      // If we're switching to the updating version, we need to insert
7146      // the writeback tied operand.
7147      if (hasWritebackToken)
7148        Inst.insert(Inst.begin(),
7149                    MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7150      return true;
7151    }
7152    break;
7153  }
7154  case ARM::tSTMIA_UPD: {
7155    // If the register list contains any high registers, we need to use
7156    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7157    // should have generated an error in validateInstruction().
7158    unsigned Rn = Inst.getOperand(0).getReg();
7159    bool listContainsBase;
7160    if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7161      // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7162      assert (isThumbTwo());
7163      Inst.setOpcode(ARM::t2STMIA_UPD);
7164      return true;
7165    }
7166    break;
7167  }
7168  case ARM::tPOP: {
7169    bool listContainsBase;
7170    // If the register list contains any high registers, we need to use
7171    // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7172    // should have generated an error in validateInstruction().
7173    if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7174      return false;
7175    assert (isThumbTwo());
7176    Inst.setOpcode(ARM::t2LDMIA_UPD);
7177    // Add the base register and writeback operands.
7178    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7179    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7180    return true;
7181  }
7182  case ARM::tPUSH: {
7183    bool listContainsBase;
7184    if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7185      return false;
7186    assert (isThumbTwo());
7187    Inst.setOpcode(ARM::t2STMDB_UPD);
7188    // Add the base register and writeback operands.
7189    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7190    Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7191    return true;
7192  }
7193  case ARM::t2MOVi: {
7194    // If we can use the 16-bit encoding and the user didn't explicitly
7195    // request the 32-bit variant, transform it here.
7196    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7197        (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7198        ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7199         Inst.getOperand(4).getReg() == ARM::CPSR) ||
7200        (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7201        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7202         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7203      // The operands aren't in the same order for tMOVi8...
7204      MCInst TmpInst;
7205      TmpInst.setOpcode(ARM::tMOVi8);
7206      TmpInst.addOperand(Inst.getOperand(0));
7207      TmpInst.addOperand(Inst.getOperand(4));
7208      TmpInst.addOperand(Inst.getOperand(1));
7209      TmpInst.addOperand(Inst.getOperand(2));
7210      TmpInst.addOperand(Inst.getOperand(3));
7211      Inst = TmpInst;
7212      return true;
7213    }
7214    break;
7215  }
7216  case ARM::t2MOVr: {
7217    // If we can use the 16-bit encoding and the user didn't explicitly
7218    // request the 32-bit variant, transform it here.
7219    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7220        isARMLowRegister(Inst.getOperand(1).getReg()) &&
7221        Inst.getOperand(2).getImm() == ARMCC::AL &&
7222        Inst.getOperand(4).getReg() == ARM::CPSR &&
7223        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7224         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7225      // The operands aren't the same for tMOV[S]r... (no cc_out)
7226      MCInst TmpInst;
7227      TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7228      TmpInst.addOperand(Inst.getOperand(0));
7229      TmpInst.addOperand(Inst.getOperand(1));
7230      TmpInst.addOperand(Inst.getOperand(2));
7231      TmpInst.addOperand(Inst.getOperand(3));
7232      Inst = TmpInst;
7233      return true;
7234    }
7235    break;
7236  }
7237  case ARM::t2SXTH:
7238  case ARM::t2SXTB:
7239  case ARM::t2UXTH:
7240  case ARM::t2UXTB: {
7241    // If we can use the 16-bit encoding and the user didn't explicitly
7242    // request the 32-bit variant, transform it here.
7243    if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7244        isARMLowRegister(Inst.getOperand(1).getReg()) &&
7245        Inst.getOperand(2).getImm() == 0 &&
7246        (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7247         static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7248      unsigned NewOpc;
7249      switch (Inst.getOpcode()) {
7250      default: llvm_unreachable("Illegal opcode!");
7251      case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7252      case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7253      case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7254      case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7255      }
7256      // The operands aren't the same for thumb1 (no rotate operand).
7257      MCInst TmpInst;
7258      TmpInst.setOpcode(NewOpc);
7259      TmpInst.addOperand(Inst.getOperand(0));
7260      TmpInst.addOperand(Inst.getOperand(1));
7261      TmpInst.addOperand(Inst.getOperand(3));
7262      TmpInst.addOperand(Inst.getOperand(4));
7263      Inst = TmpInst;
7264      return true;
7265    }
7266    break;
7267  }
7268  case ARM::MOVsi: {
7269    ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7270    // rrx shifts and asr/lsr of #32 is encoded as 0
7271    if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7272      return false;
7273    if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7274      // Shifting by zero is accepted as a vanilla 'MOVr'
7275      MCInst TmpInst;
7276      TmpInst.setOpcode(ARM::MOVr);
7277      TmpInst.addOperand(Inst.getOperand(0));
7278      TmpInst.addOperand(Inst.getOperand(1));
7279      TmpInst.addOperand(Inst.getOperand(3));
7280      TmpInst.addOperand(Inst.getOperand(4));
7281      TmpInst.addOperand(Inst.getOperand(5));
7282      Inst = TmpInst;
7283      return true;
7284    }
7285    return false;
7286  }
7287  case ARM::ANDrsi:
7288  case ARM::ORRrsi:
7289  case ARM::EORrsi:
7290  case ARM::BICrsi:
7291  case ARM::SUBrsi:
7292  case ARM::ADDrsi: {
7293    unsigned newOpc;
7294    ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7295    if (SOpc == ARM_AM::rrx) return false;
7296    switch (Inst.getOpcode()) {
7297    default: llvm_unreachable("unexpected opcode!");
7298    case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7299    case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7300    case ARM::EORrsi: newOpc = ARM::EORrr; break;
7301    case ARM::BICrsi: newOpc = ARM::BICrr; break;
7302    case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7303    case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7304    }
7305    // If the shift is by zero, use the non-shifted instruction definition.
7306    // The exception is for right shifts, where 0 == 32
7307    if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7308        !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7309      MCInst TmpInst;
7310      TmpInst.setOpcode(newOpc);
7311      TmpInst.addOperand(Inst.getOperand(0));
7312      TmpInst.addOperand(Inst.getOperand(1));
7313      TmpInst.addOperand(Inst.getOperand(2));
7314      TmpInst.addOperand(Inst.getOperand(4));
7315      TmpInst.addOperand(Inst.getOperand(5));
7316      TmpInst.addOperand(Inst.getOperand(6));
7317      Inst = TmpInst;
7318      return true;
7319    }
7320    return false;
7321  }
7322  case ARM::ITasm:
7323  case ARM::t2IT: {
7324    // The mask bits for all but the first condition are represented as
7325    // the low bit of the condition code value implies 't'. We currently
7326    // always have 1 implies 't', so XOR toggle the bits if the low bit
7327    // of the condition code is zero.
7328    MCOperand &MO = Inst.getOperand(1);
7329    unsigned Mask = MO.getImm();
7330    unsigned OrigMask = Mask;
7331    unsigned TZ = CountTrailingZeros_32(Mask);
7332    if ((Inst.getOperand(0).getImm() & 1) == 0) {
7333      assert(Mask && TZ <= 3 && "illegal IT mask value!");
7334      for (unsigned i = 3; i != TZ; --i)
7335        Mask ^= 1 << i;
7336    }
7337    MO.setImm(Mask);
7338
7339    // Set up the IT block state according to the IT instruction we just
7340    // matched.
7341    assert(!inITBlock() && "nested IT blocks?!");
7342    ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7343    ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7344    ITState.CurPosition = 0;
7345    ITState.FirstCond = true;
7346    break;
7347  }
7348  case ARM::t2LSLrr:
7349  case ARM::t2LSRrr:
7350  case ARM::t2ASRrr:
7351  case ARM::t2SBCrr:
7352  case ARM::t2RORrr:
7353  case ARM::t2BICrr:
7354  {
7355    // Assemblers should use the narrow encodings of these instructions when permissible.
7356    if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7357         isARMLowRegister(Inst.getOperand(2).getReg())) &&
7358        Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7359        ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7360         (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7361        (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7362         !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7363      unsigned NewOpc;
7364      switch (Inst.getOpcode()) {
7365        default: llvm_unreachable("unexpected opcode");
7366        case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7367        case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7368        case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7369        case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7370        case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7371        case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7372      }
7373      MCInst TmpInst;
7374      TmpInst.setOpcode(NewOpc);
7375      TmpInst.addOperand(Inst.getOperand(0));
7376      TmpInst.addOperand(Inst.getOperand(5));
7377      TmpInst.addOperand(Inst.getOperand(1));
7378      TmpInst.addOperand(Inst.getOperand(2));
7379      TmpInst.addOperand(Inst.getOperand(3));
7380      TmpInst.addOperand(Inst.getOperand(4));
7381      Inst = TmpInst;
7382      return true;
7383    }
7384    return false;
7385  }
7386  case ARM::t2ANDrr:
7387  case ARM::t2EORrr:
7388  case ARM::t2ADCrr:
7389  case ARM::t2ORRrr:
7390  {
7391    // Assemblers should use the narrow encodings of these instructions when permissible.
7392    // These instructions are special in that they are commutable, so shorter encodings
7393    // are available more often.
7394    if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7395         isARMLowRegister(Inst.getOperand(2).getReg())) &&
7396        (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7397         Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7398        ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7399         (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7400        (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7401         !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7402      unsigned NewOpc;
7403      switch (Inst.getOpcode()) {
7404        default: llvm_unreachable("unexpected opcode");
7405        case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7406        case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7407        case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7408        case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7409      }
7410      MCInst TmpInst;
7411      TmpInst.setOpcode(NewOpc);
7412      TmpInst.addOperand(Inst.getOperand(0));
7413      TmpInst.addOperand(Inst.getOperand(5));
7414      if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7415        TmpInst.addOperand(Inst.getOperand(1));
7416        TmpInst.addOperand(Inst.getOperand(2));
7417      } else {
7418        TmpInst.addOperand(Inst.getOperand(2));
7419        TmpInst.addOperand(Inst.getOperand(1));
7420      }
7421      TmpInst.addOperand(Inst.getOperand(3));
7422      TmpInst.addOperand(Inst.getOperand(4));
7423      Inst = TmpInst;
7424      return true;
7425    }
7426    return false;
7427  }
7428  }
7429  return false;
7430}
7431
7432unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7433  // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7434  // suffix depending on whether they're in an IT block or not.
7435  unsigned Opc = Inst.getOpcode();
7436  const MCInstrDesc &MCID = getInstDesc(Opc);
7437  if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7438    assert(MCID.hasOptionalDef() &&
7439           "optionally flag setting instruction missing optional def operand");
7440    assert(MCID.NumOperands == Inst.getNumOperands() &&
7441           "operand count mismatch!");
7442    // Find the optional-def operand (cc_out).
7443    unsigned OpNo;
7444    for (OpNo = 0;
7445         !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7446         ++OpNo)
7447      ;
7448    // If we're parsing Thumb1, reject it completely.
7449    if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7450      return Match_MnemonicFail;
7451    // If we're parsing Thumb2, which form is legal depends on whether we're
7452    // in an IT block.
7453    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7454        !inITBlock())
7455      return Match_RequiresITBlock;
7456    if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7457        inITBlock())
7458      return Match_RequiresNotITBlock;
7459  }
7460  // Some high-register supporting Thumb1 encodings only allow both registers
7461  // to be from r0-r7 when in Thumb2.
7462  else if (Opc == ARM::tADDhirr && isThumbOne() &&
7463           isARMLowRegister(Inst.getOperand(1).getReg()) &&
7464           isARMLowRegister(Inst.getOperand(2).getReg()))
7465    return Match_RequiresThumb2;
7466  // Others only require ARMv6 or later.
7467  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7468           isARMLowRegister(Inst.getOperand(0).getReg()) &&
7469           isARMLowRegister(Inst.getOperand(1).getReg()))
7470    return Match_RequiresV6;
7471  return Match_Success;
7472}
7473
7474static const char *getSubtargetFeatureName(unsigned Val);
7475bool ARMAsmParser::
7476MatchAndEmitInstruction(SMLoc IDLoc,
7477                        SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7478                        MCStreamer &Out) {
7479  MCInst Inst;
7480  unsigned ErrorInfo;
7481  unsigned MatchResult;
7482  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
7483  switch (MatchResult) {
7484  default: break;
7485  case Match_Success:
7486    // Context sensitive operand constraints aren't handled by the matcher,
7487    // so check them here.
7488    if (validateInstruction(Inst, Operands)) {
7489      // Still progress the IT block, otherwise one wrong condition causes
7490      // nasty cascading errors.
7491      forwardITPosition();
7492      return true;
7493    }
7494
7495    // Some instructions need post-processing to, for example, tweak which
7496    // encoding is selected. Loop on it while changes happen so the
7497    // individual transformations can chain off each other. E.g.,
7498    // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7499    while (processInstruction(Inst, Operands))
7500      ;
7501
7502    // Only move forward at the very end so that everything in validate
7503    // and process gets a consistent answer about whether we're in an IT
7504    // block.
7505    forwardITPosition();
7506
7507    // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7508    // doesn't actually encode.
7509    if (Inst.getOpcode() == ARM::ITasm)
7510      return false;
7511
7512    Inst.setLoc(IDLoc);
7513    Out.EmitInstruction(Inst);
7514    return false;
7515  case Match_MissingFeature: {
7516    assert(ErrorInfo && "Unknown missing feature!");
7517    // Special case the error message for the very common case where only
7518    // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7519    std::string Msg = "instruction requires:";
7520    unsigned Mask = 1;
7521    for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7522      if (ErrorInfo & Mask) {
7523        Msg += " ";
7524        Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7525      }
7526      Mask <<= 1;
7527    }
7528    return Error(IDLoc, Msg);
7529  }
7530  case Match_InvalidOperand: {
7531    SMLoc ErrorLoc = IDLoc;
7532    if (ErrorInfo != ~0U) {
7533      if (ErrorInfo >= Operands.size())
7534        return Error(IDLoc, "too few operands for instruction");
7535
7536      ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7537      if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7538    }
7539
7540    return Error(ErrorLoc, "invalid operand for instruction");
7541  }
7542  case Match_MnemonicFail:
7543    return Error(IDLoc, "invalid instruction",
7544                 ((ARMOperand*)Operands[0])->getLocRange());
7545  case Match_ConversionFail:
7546    // The converter function will have already emitted a diagnostic.
7547    return true;
7548  case Match_RequiresNotITBlock:
7549    return Error(IDLoc, "flag setting instruction only valid outside IT block");
7550  case Match_RequiresITBlock:
7551    return Error(IDLoc, "instruction only valid inside IT block");
7552  case Match_RequiresV6:
7553    return Error(IDLoc, "instruction variant requires ARMv6 or later");
7554  case Match_RequiresThumb2:
7555    return Error(IDLoc, "instruction variant requires Thumb2");
7556  case Match_ImmRange0_15: {
7557    SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7558    if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7559    return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7560  }
7561  }
7562
7563  llvm_unreachable("Implement any new match types added!");
7564}
7565
7566/// parseDirective parses the arm specific directives
7567bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7568  StringRef IDVal = DirectiveID.getIdentifier();
7569  if (IDVal == ".word")
7570    return parseDirectiveWord(4, DirectiveID.getLoc());
7571  else if (IDVal == ".thumb")
7572    return parseDirectiveThumb(DirectiveID.getLoc());
7573  else if (IDVal == ".arm")
7574    return parseDirectiveARM(DirectiveID.getLoc());
7575  else if (IDVal == ".thumb_func")
7576    return parseDirectiveThumbFunc(DirectiveID.getLoc());
7577  else if (IDVal == ".code")
7578    return parseDirectiveCode(DirectiveID.getLoc());
7579  else if (IDVal == ".syntax")
7580    return parseDirectiveSyntax(DirectiveID.getLoc());
7581  else if (IDVal == ".unreq")
7582    return parseDirectiveUnreq(DirectiveID.getLoc());
7583  else if (IDVal == ".arch")
7584    return parseDirectiveArch(DirectiveID.getLoc());
7585  else if (IDVal == ".eabi_attribute")
7586    return parseDirectiveEabiAttr(DirectiveID.getLoc());
7587  return true;
7588}
7589
7590/// parseDirectiveWord
7591///  ::= .word [ expression (, expression)* ]
7592bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
7593  if (getLexer().isNot(AsmToken::EndOfStatement)) {
7594    for (;;) {
7595      const MCExpr *Value;
7596      if (getParser().ParseExpression(Value))
7597        return true;
7598
7599      getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
7600
7601      if (getLexer().is(AsmToken::EndOfStatement))
7602        break;
7603
7604      // FIXME: Improve diagnostic.
7605      if (getLexer().isNot(AsmToken::Comma))
7606        return Error(L, "unexpected token in directive");
7607      Parser.Lex();
7608    }
7609  }
7610
7611  Parser.Lex();
7612  return false;
7613}
7614
7615/// parseDirectiveThumb
7616///  ::= .thumb
7617bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
7618  if (getLexer().isNot(AsmToken::EndOfStatement))
7619    return Error(L, "unexpected token in directive");
7620  Parser.Lex();
7621
7622  if (!isThumb())
7623    SwitchMode();
7624  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7625  return false;
7626}
7627
7628/// parseDirectiveARM
7629///  ::= .arm
7630bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
7631  if (getLexer().isNot(AsmToken::EndOfStatement))
7632    return Error(L, "unexpected token in directive");
7633  Parser.Lex();
7634
7635  if (isThumb())
7636    SwitchMode();
7637  getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7638  return false;
7639}
7640
7641/// parseDirectiveThumbFunc
7642///  ::= .thumbfunc symbol_name
7643bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
7644  const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
7645  bool isMachO = MAI.hasSubsectionsViaSymbols();
7646  StringRef Name;
7647  bool needFuncName = true;
7648
7649  // Darwin asm has (optionally) function name after .thumb_func direction
7650  // ELF doesn't
7651  if (isMachO) {
7652    const AsmToken &Tok = Parser.getTok();
7653    if (Tok.isNot(AsmToken::EndOfStatement)) {
7654      if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
7655        return Error(L, "unexpected token in .thumb_func directive");
7656      Name = Tok.getIdentifier();
7657      Parser.Lex(); // Consume the identifier token.
7658      needFuncName = false;
7659    }
7660  }
7661
7662  if (getLexer().isNot(AsmToken::EndOfStatement))
7663    return Error(L, "unexpected token in directive");
7664
7665  // Eat the end of statement and any blank lines that follow.
7666  while (getLexer().is(AsmToken::EndOfStatement))
7667    Parser.Lex();
7668
7669  // FIXME: assuming function name will be the line following .thumb_func
7670  // We really should be checking the next symbol definition even if there's
7671  // stuff in between.
7672  if (needFuncName) {
7673    Name = Parser.getTok().getIdentifier();
7674  }
7675
7676  // Mark symbol as a thumb symbol.
7677  MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
7678  getParser().getStreamer().EmitThumbFunc(Func);
7679  return false;
7680}
7681
7682/// parseDirectiveSyntax
7683///  ::= .syntax unified | divided
7684bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
7685  const AsmToken &Tok = Parser.getTok();
7686  if (Tok.isNot(AsmToken::Identifier))
7687    return Error(L, "unexpected token in .syntax directive");
7688  StringRef Mode = Tok.getString();
7689  if (Mode == "unified" || Mode == "UNIFIED")
7690    Parser.Lex();
7691  else if (Mode == "divided" || Mode == "DIVIDED")
7692    return Error(L, "'.syntax divided' arm asssembly not supported");
7693  else
7694    return Error(L, "unrecognized syntax mode in .syntax directive");
7695
7696  if (getLexer().isNot(AsmToken::EndOfStatement))
7697    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7698  Parser.Lex();
7699
7700  // TODO tell the MC streamer the mode
7701  // getParser().getStreamer().Emit???();
7702  return false;
7703}
7704
7705/// parseDirectiveCode
7706///  ::= .code 16 | 32
7707bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
7708  const AsmToken &Tok = Parser.getTok();
7709  if (Tok.isNot(AsmToken::Integer))
7710    return Error(L, "unexpected token in .code directive");
7711  int64_t Val = Parser.getTok().getIntVal();
7712  if (Val == 16)
7713    Parser.Lex();
7714  else if (Val == 32)
7715    Parser.Lex();
7716  else
7717    return Error(L, "invalid operand to .code directive");
7718
7719  if (getLexer().isNot(AsmToken::EndOfStatement))
7720    return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7721  Parser.Lex();
7722
7723  if (Val == 16) {
7724    if (!isThumb())
7725      SwitchMode();
7726    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7727  } else {
7728    if (isThumb())
7729      SwitchMode();
7730    getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7731  }
7732
7733  return false;
7734}
7735
7736/// parseDirectiveReq
7737///  ::= name .req registername
7738bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
7739  Parser.Lex(); // Eat the '.req' token.
7740  unsigned Reg;
7741  SMLoc SRegLoc, ERegLoc;
7742  if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
7743    Parser.EatToEndOfStatement();
7744    return Error(SRegLoc, "register name expected");
7745  }
7746
7747  // Shouldn't be anything else.
7748  if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
7749    Parser.EatToEndOfStatement();
7750    return Error(Parser.getTok().getLoc(),
7751                 "unexpected input in .req directive.");
7752  }
7753
7754  Parser.Lex(); // Consume the EndOfStatement
7755
7756  if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg)
7757    return Error(SRegLoc, "redefinition of '" + Name +
7758                          "' does not match original.");
7759
7760  return false;
7761}
7762
7763/// parseDirectiveUneq
7764///  ::= .unreq registername
7765bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
7766  if (Parser.getTok().isNot(AsmToken::Identifier)) {
7767    Parser.EatToEndOfStatement();
7768    return Error(L, "unexpected input in .unreq directive.");
7769  }
7770  RegisterReqs.erase(Parser.getTok().getIdentifier());
7771  Parser.Lex(); // Eat the identifier.
7772  return false;
7773}
7774
7775/// parseDirectiveArch
7776///  ::= .arch token
7777bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
7778  return true;
7779}
7780
7781/// parseDirectiveEabiAttr
7782///  ::= .eabi_attribute int, int
7783bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
7784  return true;
7785}
7786
7787extern "C" void LLVMInitializeARMAsmLexer();
7788
7789/// Force static initialization.
7790extern "C" void LLVMInitializeARMAsmParser() {
7791  RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
7792  RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
7793  LLVMInitializeARMAsmLexer();
7794}
7795
7796#define GET_REGISTER_MATCHER
7797#define GET_SUBTARGET_FEATURE_NAME
7798#define GET_MATCHER_IMPLEMENTATION
7799#include "ARMGenAsmMatcher.inc"
7800