ARMAsmParser.cpp revision b41aaab5a1769f4df04d566da37866ac91b6ee9e
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#include "ARM.h" 11#include "ARMAddressingModes.h" 12#include "ARMMCExpr.h" 13#include "ARMBaseRegisterInfo.h" 14#include "ARMSubtarget.h" 15#include "llvm/MC/MCParser/MCAsmLexer.h" 16#include "llvm/MC/MCParser/MCAsmParser.h" 17#include "llvm/MC/MCParser/MCParsedAsmOperand.h" 18#include "llvm/MC/MCContext.h" 19#include "llvm/MC/MCStreamer.h" 20#include "llvm/MC/MCExpr.h" 21#include "llvm/MC/MCInst.h" 22#include "llvm/Target/TargetRegistry.h" 23#include "llvm/Target/TargetAsmParser.h" 24#include "llvm/Support/SourceMgr.h" 25#include "llvm/Support/raw_ostream.h" 26#include "llvm/ADT/SmallVector.h" 27#include "llvm/ADT/StringExtras.h" 28#include "llvm/ADT/StringSwitch.h" 29#include "llvm/ADT/Twine.h" 30using namespace llvm; 31 32namespace { 33 34class ARMOperand; 35 36class ARMAsmParser : public TargetAsmParser { 37 MCAsmParser &Parser; 38 TargetMachine &TM; 39 40 MCAsmParser &getParser() const { return Parser; } 41 MCAsmLexer &getLexer() const { return Parser.getLexer(); } 42 43 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); } 44 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); } 45 46 int TryParseRegister(); 47 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); 48 bool TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &); 49 bool TryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &); 50 bool ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &); 51 bool ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &); 52 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic); 53 bool ParsePrefix(ARMMCExpr::VariantKind &RefKind); 54 const MCExpr *ApplyPrefixToExpr(const MCExpr *E, 55 MCSymbolRefExpr::VariantKind Variant); 56 57 58 bool ParseMemoryOffsetReg(bool &Negative, 59 bool &OffsetRegShifted, 60 enum ARM_AM::ShiftOpc &ShiftType, 61 const MCExpr *&ShiftAmount, 62 const MCExpr *&Offset, 63 bool &OffsetIsReg, 64 int &OffsetRegNum, 65 SMLoc &E); 66 bool ParseShift(enum ARM_AM::ShiftOpc &St, 67 const MCExpr *&ShiftAmount, SMLoc &E); 68 bool ParseDirectiveWord(unsigned Size, SMLoc L); 69 bool ParseDirectiveThumb(SMLoc L); 70 bool ParseDirectiveThumbFunc(SMLoc L); 71 bool ParseDirectiveCode(SMLoc L); 72 bool ParseDirectiveSyntax(SMLoc L); 73 74 bool MatchAndEmitInstruction(SMLoc IDLoc, 75 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 76 MCStreamer &Out); 77 void GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 78 bool &CanAcceptPredicationCode); 79 80 /// @name Auto-generated Match Functions 81 /// { 82 83#define GET_ASSEMBLER_HEADER 84#include "ARMGenAsmMatcher.inc" 85 86 /// } 87 88 OperandMatchResultTy tryParseCoprocNumOperand( 89 SmallVectorImpl<MCParsedAsmOperand*>&); 90 OperandMatchResultTy tryParseCoprocRegOperand( 91 SmallVectorImpl<MCParsedAsmOperand*>&); 92 OperandMatchResultTy tryParseMemBarrierOptOperand( 93 SmallVectorImpl<MCParsedAsmOperand*>&); 94 OperandMatchResultTy tryParseProcIFlagsOperand( 95 SmallVectorImpl<MCParsedAsmOperand*>&); 96 OperandMatchResultTy tryParseMSRMaskOperand( 97 SmallVectorImpl<MCParsedAsmOperand*>&); 98 99public: 100 ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM) 101 : TargetAsmParser(T), Parser(_Parser), TM(_TM) { 102 // Initialize the set of available features. 103 setAvailableFeatures(ComputeAvailableFeatures( 104 &TM.getSubtarget<ARMSubtarget>())); 105 } 106 107 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc, 108 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 109 virtual bool ParseDirective(AsmToken DirectiveID); 110}; 111} // end anonymous namespace 112 113namespace { 114 115/// ARMOperand - Instances of this class represent a parsed ARM machine 116/// instruction. 117class ARMOperand : public MCParsedAsmOperand { 118 enum KindTy { 119 CondCode, 120 CCOut, 121 CoprocNum, 122 CoprocReg, 123 Immediate, 124 MemBarrierOpt, 125 Memory, 126 MSRMask, 127 ProcIFlags, 128 Register, 129 RegisterList, 130 DPRRegisterList, 131 SPRRegisterList, 132 Shifter, 133 Token 134 } Kind; 135 136 SMLoc StartLoc, EndLoc; 137 SmallVector<unsigned, 8> Registers; 138 139 union { 140 struct { 141 ARMCC::CondCodes Val; 142 } CC; 143 144 struct { 145 ARM_MB::MemBOpt Val; 146 } MBOpt; 147 148 struct { 149 unsigned Val; 150 } Cop; 151 152 struct { 153 ARM_PROC::IFlags Val; 154 } IFlags; 155 156 struct { 157 unsigned Val; 158 } MMask; 159 160 struct { 161 const char *Data; 162 unsigned Length; 163 } Tok; 164 165 struct { 166 unsigned RegNum; 167 } Reg; 168 169 struct { 170 const MCExpr *Val; 171 } Imm; 172 173 /// Combined record for all forms of ARM address expressions. 174 struct { 175 unsigned BaseRegNum; 176 union { 177 unsigned RegNum; ///< Offset register num, when OffsetIsReg. 178 const MCExpr *Value; ///< Offset value, when !OffsetIsReg. 179 } Offset; 180 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true 181 enum ARM_AM::ShiftOpc ShiftType; // used when OffsetRegShifted is true 182 unsigned OffsetRegShifted : 1; // only used when OffsetIsReg is true 183 unsigned Preindexed : 1; 184 unsigned Postindexed : 1; 185 unsigned OffsetIsReg : 1; 186 unsigned Negative : 1; // only used when OffsetIsReg is true 187 unsigned Writeback : 1; 188 } Mem; 189 190 struct { 191 ARM_AM::ShiftOpc ShiftTy; 192 unsigned RegNum; 193 } Shift; 194 }; 195 196 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 197public: 198 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() { 199 Kind = o.Kind; 200 StartLoc = o.StartLoc; 201 EndLoc = o.EndLoc; 202 switch (Kind) { 203 case CondCode: 204 CC = o.CC; 205 break; 206 case Token: 207 Tok = o.Tok; 208 break; 209 case CCOut: 210 case Register: 211 Reg = o.Reg; 212 break; 213 case RegisterList: 214 case DPRRegisterList: 215 case SPRRegisterList: 216 Registers = o.Registers; 217 break; 218 case CoprocNum: 219 case CoprocReg: 220 Cop = o.Cop; 221 break; 222 case Immediate: 223 Imm = o.Imm; 224 break; 225 case MemBarrierOpt: 226 MBOpt = o.MBOpt; 227 break; 228 case Memory: 229 Mem = o.Mem; 230 break; 231 case MSRMask: 232 MMask = o.MMask; 233 break; 234 case ProcIFlags: 235 IFlags = o.IFlags; 236 break; 237 case Shifter: 238 Shift = o.Shift; 239 break; 240 } 241 } 242 243 /// getStartLoc - Get the location of the first token of this operand. 244 SMLoc getStartLoc() const { return StartLoc; } 245 /// getEndLoc - Get the location of the last token of this operand. 246 SMLoc getEndLoc() const { return EndLoc; } 247 248 ARMCC::CondCodes getCondCode() const { 249 assert(Kind == CondCode && "Invalid access!"); 250 return CC.Val; 251 } 252 253 unsigned getCoproc() const { 254 assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!"); 255 return Cop.Val; 256 } 257 258 StringRef getToken() const { 259 assert(Kind == Token && "Invalid access!"); 260 return StringRef(Tok.Data, Tok.Length); 261 } 262 263 unsigned getReg() const { 264 assert((Kind == Register || Kind == CCOut) && "Invalid access!"); 265 return Reg.RegNum; 266 } 267 268 const SmallVectorImpl<unsigned> &getRegList() const { 269 assert((Kind == RegisterList || Kind == DPRRegisterList || 270 Kind == SPRRegisterList) && "Invalid access!"); 271 return Registers; 272 } 273 274 const MCExpr *getImm() const { 275 assert(Kind == Immediate && "Invalid access!"); 276 return Imm.Val; 277 } 278 279 ARM_MB::MemBOpt getMemBarrierOpt() const { 280 assert(Kind == MemBarrierOpt && "Invalid access!"); 281 return MBOpt.Val; 282 } 283 284 ARM_PROC::IFlags getProcIFlags() const { 285 assert(Kind == ProcIFlags && "Invalid access!"); 286 return IFlags.Val; 287 } 288 289 unsigned getMSRMask() const { 290 assert(Kind == MSRMask && "Invalid access!"); 291 return MMask.Val; 292 } 293 294 /// @name Memory Operand Accessors 295 /// @{ 296 297 unsigned getMemBaseRegNum() const { 298 return Mem.BaseRegNum; 299 } 300 unsigned getMemOffsetRegNum() const { 301 assert(Mem.OffsetIsReg && "Invalid access!"); 302 return Mem.Offset.RegNum; 303 } 304 const MCExpr *getMemOffset() const { 305 assert(!Mem.OffsetIsReg && "Invalid access!"); 306 return Mem.Offset.Value; 307 } 308 unsigned getMemOffsetRegShifted() const { 309 assert(Mem.OffsetIsReg && "Invalid access!"); 310 return Mem.OffsetRegShifted; 311 } 312 const MCExpr *getMemShiftAmount() const { 313 assert(Mem.OffsetIsReg && Mem.OffsetRegShifted && "Invalid access!"); 314 return Mem.ShiftAmount; 315 } 316 enum ARM_AM::ShiftOpc getMemShiftType() const { 317 assert(Mem.OffsetIsReg && Mem.OffsetRegShifted && "Invalid access!"); 318 return Mem.ShiftType; 319 } 320 bool getMemPreindexed() const { return Mem.Preindexed; } 321 bool getMemPostindexed() const { return Mem.Postindexed; } 322 bool getMemOffsetIsReg() const { return Mem.OffsetIsReg; } 323 bool getMemNegative() const { return Mem.Negative; } 324 bool getMemWriteback() const { return Mem.Writeback; } 325 326 /// @} 327 328 bool isCoprocNum() const { return Kind == CoprocNum; } 329 bool isCoprocReg() const { return Kind == CoprocReg; } 330 bool isCondCode() const { return Kind == CondCode; } 331 bool isCCOut() const { return Kind == CCOut; } 332 bool isImm() const { return Kind == Immediate; } 333 bool isReg() const { return Kind == Register; } 334 bool isRegList() const { return Kind == RegisterList; } 335 bool isDPRRegList() const { return Kind == DPRRegisterList; } 336 bool isSPRRegList() const { return Kind == SPRRegisterList; } 337 bool isToken() const { return Kind == Token; } 338 bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; } 339 bool isMemory() const { return Kind == Memory; } 340 bool isShifter() const { return Kind == Shifter; } 341 bool isMemMode5() const { 342 if (!isMemory() || getMemOffsetIsReg() || getMemWriteback() || 343 getMemNegative()) 344 return false; 345 346 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset()); 347 if (!CE) return false; 348 349 // The offset must be a multiple of 4 in the range 0-1020. 350 int64_t Value = CE->getValue(); 351 return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020); 352 } 353 bool isMemMode7() const { 354 if (!isMemory() || 355 getMemPreindexed() || 356 getMemPostindexed() || 357 getMemOffsetIsReg() || 358 getMemNegative() || 359 getMemWriteback()) 360 return false; 361 362 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset()); 363 if (!CE) return false; 364 365 if (CE->getValue()) 366 return false; 367 368 return true; 369 } 370 bool isMemModeRegThumb() const { 371 if (!isMemory() || !getMemOffsetIsReg() || getMemWriteback()) 372 return false; 373 return true; 374 } 375 bool isMemModeImmThumb() const { 376 if (!isMemory() || getMemOffsetIsReg() || getMemWriteback()) 377 return false; 378 379 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset()); 380 if (!CE) return false; 381 382 // The offset must be a multiple of 4 in the range 0-124. 383 uint64_t Value = CE->getValue(); 384 return ((Value & 0x3) == 0 && Value <= 124); 385 } 386 bool isMSRMask() const { return Kind == MSRMask; } 387 bool isProcIFlags() const { return Kind == ProcIFlags; } 388 389 void addExpr(MCInst &Inst, const MCExpr *Expr) const { 390 // Add as immediates when possible. Null MCExpr = 0. 391 if (Expr == 0) 392 Inst.addOperand(MCOperand::CreateImm(0)); 393 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) 394 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 395 else 396 Inst.addOperand(MCOperand::CreateExpr(Expr)); 397 } 398 399 void addCondCodeOperands(MCInst &Inst, unsigned N) const { 400 assert(N == 2 && "Invalid number of operands!"); 401 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 402 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; 403 Inst.addOperand(MCOperand::CreateReg(RegNum)); 404 } 405 406 void addCoprocNumOperands(MCInst &Inst, unsigned N) const { 407 assert(N == 1 && "Invalid number of operands!"); 408 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 409 } 410 411 void addCoprocRegOperands(MCInst &Inst, unsigned N) const { 412 assert(N == 1 && "Invalid number of operands!"); 413 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 414 } 415 416 void addCCOutOperands(MCInst &Inst, unsigned N) const { 417 assert(N == 1 && "Invalid number of operands!"); 418 Inst.addOperand(MCOperand::CreateReg(getReg())); 419 } 420 421 void addRegOperands(MCInst &Inst, unsigned N) const { 422 assert(N == 1 && "Invalid number of operands!"); 423 Inst.addOperand(MCOperand::CreateReg(getReg())); 424 } 425 426 void addShifterOperands(MCInst &Inst, unsigned N) const { 427 assert(N == 1 && "Invalid number of operands!"); 428 Inst.addOperand(MCOperand::CreateImm( 429 ARM_AM::getSORegOpc(Shift.ShiftTy, 0))); 430 } 431 432 void addRegListOperands(MCInst &Inst, unsigned N) const { 433 assert(N == 1 && "Invalid number of operands!"); 434 const SmallVectorImpl<unsigned> &RegList = getRegList(); 435 for (SmallVectorImpl<unsigned>::const_iterator 436 I = RegList.begin(), E = RegList.end(); I != E; ++I) 437 Inst.addOperand(MCOperand::CreateReg(*I)); 438 } 439 440 void addDPRRegListOperands(MCInst &Inst, unsigned N) const { 441 addRegListOperands(Inst, N); 442 } 443 444 void addSPRRegListOperands(MCInst &Inst, unsigned N) const { 445 addRegListOperands(Inst, N); 446 } 447 448 void addImmOperands(MCInst &Inst, unsigned N) const { 449 assert(N == 1 && "Invalid number of operands!"); 450 addExpr(Inst, getImm()); 451 } 452 453 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { 454 assert(N == 1 && "Invalid number of operands!"); 455 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt()))); 456 } 457 458 void addMemMode7Operands(MCInst &Inst, unsigned N) const { 459 assert(N == 1 && isMemMode7() && "Invalid number of operands!"); 460 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum())); 461 462 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset()); 463 (void)CE; 464 assert((CE || CE->getValue() == 0) && 465 "No offset operand support in mode 7"); 466 } 467 468 void addMemMode5Operands(MCInst &Inst, unsigned N) const { 469 assert(N == 2 && isMemMode5() && "Invalid number of operands!"); 470 471 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum())); 472 assert(!getMemOffsetIsReg() && "Invalid mode 5 operand"); 473 474 // FIXME: #-0 is encoded differently than #0. Does the parser preserve 475 // the difference? 476 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset()); 477 assert(CE && "Non-constant mode 5 offset operand!"); 478 479 // The MCInst offset operand doesn't include the low two bits (like 480 // the instruction encoding). 481 int64_t Offset = CE->getValue() / 4; 482 if (Offset >= 0) 483 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, 484 Offset))); 485 else 486 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, 487 -Offset))); 488 } 489 490 void addMemModeRegThumbOperands(MCInst &Inst, unsigned N) const { 491 assert(N == 2 && isMemModeRegThumb() && "Invalid number of operands!"); 492 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum())); 493 Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum())); 494 } 495 496 void addMemModeImmThumbOperands(MCInst &Inst, unsigned N) const { 497 assert(N == 2 && isMemModeImmThumb() && "Invalid number of operands!"); 498 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum())); 499 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset()); 500 assert(CE && "Non-constant mode offset operand!"); 501 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 502 } 503 504 void addMSRMaskOperands(MCInst &Inst, unsigned N) const { 505 assert(N == 1 && "Invalid number of operands!"); 506 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask()))); 507 } 508 509 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { 510 assert(N == 1 && "Invalid number of operands!"); 511 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags()))); 512 } 513 514 virtual void dump(raw_ostream &OS) const; 515 516 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) { 517 ARMOperand *Op = new ARMOperand(CondCode); 518 Op->CC.Val = CC; 519 Op->StartLoc = S; 520 Op->EndLoc = S; 521 return Op; 522 } 523 524 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) { 525 ARMOperand *Op = new ARMOperand(CoprocNum); 526 Op->Cop.Val = CopVal; 527 Op->StartLoc = S; 528 Op->EndLoc = S; 529 return Op; 530 } 531 532 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) { 533 ARMOperand *Op = new ARMOperand(CoprocReg); 534 Op->Cop.Val = CopVal; 535 Op->StartLoc = S; 536 Op->EndLoc = S; 537 return Op; 538 } 539 540 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) { 541 ARMOperand *Op = new ARMOperand(CCOut); 542 Op->Reg.RegNum = RegNum; 543 Op->StartLoc = S; 544 Op->EndLoc = S; 545 return Op; 546 } 547 548 static ARMOperand *CreateToken(StringRef Str, SMLoc S) { 549 ARMOperand *Op = new ARMOperand(Token); 550 Op->Tok.Data = Str.data(); 551 Op->Tok.Length = Str.size(); 552 Op->StartLoc = S; 553 Op->EndLoc = S; 554 return Op; 555 } 556 557 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { 558 ARMOperand *Op = new ARMOperand(Register); 559 Op->Reg.RegNum = RegNum; 560 Op->StartLoc = S; 561 Op->EndLoc = E; 562 return Op; 563 } 564 565 static ARMOperand *CreateShifter(ARM_AM::ShiftOpc ShTy, 566 SMLoc S, SMLoc E) { 567 ARMOperand *Op = new ARMOperand(Shifter); 568 Op->Shift.ShiftTy = ShTy; 569 Op->StartLoc = S; 570 Op->EndLoc = E; 571 return Op; 572 } 573 574 static ARMOperand * 575 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs, 576 SMLoc StartLoc, SMLoc EndLoc) { 577 KindTy Kind = RegisterList; 578 579 if (ARM::DPRRegClass.contains(Regs.front().first)) 580 Kind = DPRRegisterList; 581 else if (ARM::SPRRegClass.contains(Regs.front().first)) 582 Kind = SPRRegisterList; 583 584 ARMOperand *Op = new ARMOperand(Kind); 585 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator 586 I = Regs.begin(), E = Regs.end(); I != E; ++I) 587 Op->Registers.push_back(I->first); 588 array_pod_sort(Op->Registers.begin(), Op->Registers.end()); 589 Op->StartLoc = StartLoc; 590 Op->EndLoc = EndLoc; 591 return Op; 592 } 593 594 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { 595 ARMOperand *Op = new ARMOperand(Immediate); 596 Op->Imm.Val = Val; 597 Op->StartLoc = S; 598 Op->EndLoc = E; 599 return Op; 600 } 601 602 static ARMOperand *CreateMem(unsigned BaseRegNum, bool OffsetIsReg, 603 const MCExpr *Offset, int OffsetRegNum, 604 bool OffsetRegShifted, 605 enum ARM_AM::ShiftOpc ShiftType, 606 const MCExpr *ShiftAmount, bool Preindexed, 607 bool Postindexed, bool Negative, bool Writeback, 608 SMLoc S, SMLoc E) { 609 assert((OffsetRegNum == -1 || OffsetIsReg) && 610 "OffsetRegNum must imply OffsetIsReg!"); 611 assert((!OffsetRegShifted || OffsetIsReg) && 612 "OffsetRegShifted must imply OffsetIsReg!"); 613 assert((Offset || OffsetIsReg) && 614 "Offset must exists unless register offset is used!"); 615 assert((!ShiftAmount || (OffsetIsReg && OffsetRegShifted)) && 616 "Cannot have shift amount without shifted register offset!"); 617 assert((!Offset || !OffsetIsReg) && 618 "Cannot have expression offset and register offset!"); 619 620 ARMOperand *Op = new ARMOperand(Memory); 621 Op->Mem.BaseRegNum = BaseRegNum; 622 Op->Mem.OffsetIsReg = OffsetIsReg; 623 if (OffsetIsReg) 624 Op->Mem.Offset.RegNum = OffsetRegNum; 625 else 626 Op->Mem.Offset.Value = Offset; 627 Op->Mem.OffsetRegShifted = OffsetRegShifted; 628 Op->Mem.ShiftType = ShiftType; 629 Op->Mem.ShiftAmount = ShiftAmount; 630 Op->Mem.Preindexed = Preindexed; 631 Op->Mem.Postindexed = Postindexed; 632 Op->Mem.Negative = Negative; 633 Op->Mem.Writeback = Writeback; 634 635 Op->StartLoc = S; 636 Op->EndLoc = E; 637 return Op; 638 } 639 640 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) { 641 ARMOperand *Op = new ARMOperand(MemBarrierOpt); 642 Op->MBOpt.Val = Opt; 643 Op->StartLoc = S; 644 Op->EndLoc = S; 645 return Op; 646 } 647 648 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) { 649 ARMOperand *Op = new ARMOperand(ProcIFlags); 650 Op->IFlags.Val = IFlags; 651 Op->StartLoc = S; 652 Op->EndLoc = S; 653 return Op; 654 } 655 656 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) { 657 ARMOperand *Op = new ARMOperand(MSRMask); 658 Op->MMask.Val = MMask; 659 Op->StartLoc = S; 660 Op->EndLoc = S; 661 return Op; 662 } 663}; 664 665} // end anonymous namespace. 666 667void ARMOperand::dump(raw_ostream &OS) const { 668 switch (Kind) { 669 case CondCode: 670 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; 671 break; 672 case CCOut: 673 OS << "<ccout " << getReg() << ">"; 674 break; 675 case CoprocNum: 676 OS << "<coprocessor number: " << getCoproc() << ">"; 677 break; 678 case CoprocReg: 679 OS << "<coprocessor register: " << getCoproc() << ">"; 680 break; 681 case MSRMask: 682 OS << "<mask: " << getMSRMask() << ">"; 683 break; 684 case Immediate: 685 getImm()->print(OS); 686 break; 687 case MemBarrierOpt: 688 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">"; 689 break; 690 case Memory: 691 OS << "<memory " 692 << "base:" << getMemBaseRegNum(); 693 if (getMemOffsetIsReg()) { 694 OS << " offset:<register " << getMemOffsetRegNum(); 695 if (getMemOffsetRegShifted()) { 696 OS << " offset-shift-type:" << getMemShiftType(); 697 OS << " offset-shift-amount:" << *getMemShiftAmount(); 698 } 699 } else { 700 OS << " offset:" << *getMemOffset(); 701 } 702 if (getMemOffsetIsReg()) 703 OS << " (offset-is-reg)"; 704 if (getMemPreindexed()) 705 OS << " (pre-indexed)"; 706 if (getMemPostindexed()) 707 OS << " (post-indexed)"; 708 if (getMemNegative()) 709 OS << " (negative)"; 710 if (getMemWriteback()) 711 OS << " (writeback)"; 712 OS << ">"; 713 break; 714 case ProcIFlags: { 715 OS << "<ARM_PROC::"; 716 unsigned IFlags = getProcIFlags(); 717 for (int i=2; i >= 0; --i) 718 if (IFlags & (1 << i)) 719 OS << ARM_PROC::IFlagsToString(1 << i); 720 OS << ">"; 721 break; 722 } 723 case Register: 724 OS << "<register " << getReg() << ">"; 725 break; 726 case Shifter: 727 OS << "<shifter " << getShiftOpcStr(Shift.ShiftTy) << ">"; 728 break; 729 case RegisterList: 730 case DPRRegisterList: 731 case SPRRegisterList: { 732 OS << "<register_list "; 733 734 const SmallVectorImpl<unsigned> &RegList = getRegList(); 735 for (SmallVectorImpl<unsigned>::const_iterator 736 I = RegList.begin(), E = RegList.end(); I != E; ) { 737 OS << *I; 738 if (++I < E) OS << ", "; 739 } 740 741 OS << ">"; 742 break; 743 } 744 case Token: 745 OS << "'" << getToken() << "'"; 746 break; 747 } 748} 749 750/// @name Auto-generated Match Functions 751/// { 752 753static unsigned MatchRegisterName(StringRef Name); 754 755/// } 756 757bool ARMAsmParser::ParseRegister(unsigned &RegNo, 758 SMLoc &StartLoc, SMLoc &EndLoc) { 759 RegNo = TryParseRegister(); 760 761 return (RegNo == (unsigned)-1); 762} 763 764/// Try to parse a register name. The token must be an Identifier when called, 765/// and if it is a register name the token is eaten and the register number is 766/// returned. Otherwise return -1. 767/// 768int ARMAsmParser::TryParseRegister() { 769 const AsmToken &Tok = Parser.getTok(); 770 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 771 772 // FIXME: Validate register for the current architecture; we have to do 773 // validation later, so maybe there is no need for this here. 774 std::string upperCase = Tok.getString().str(); 775 std::string lowerCase = LowercaseString(upperCase); 776 unsigned RegNum = MatchRegisterName(lowerCase); 777 if (!RegNum) { 778 RegNum = StringSwitch<unsigned>(lowerCase) 779 .Case("r13", ARM::SP) 780 .Case("r14", ARM::LR) 781 .Case("r15", ARM::PC) 782 .Case("ip", ARM::R12) 783 .Default(0); 784 } 785 if (!RegNum) return -1; 786 787 Parser.Lex(); // Eat identifier token. 788 return RegNum; 789} 790 791/// Try to parse a register name. The token must be an Identifier when called, 792/// and if it is a register name the token is eaten and the register number is 793/// returned. Otherwise return -1. 794/// 795bool ARMAsmParser::TryParseShiftRegister( 796 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 797 SMLoc S = Parser.getTok().getLoc(); 798 const AsmToken &Tok = Parser.getTok(); 799 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 800 801 std::string upperCase = Tok.getString().str(); 802 std::string lowerCase = LowercaseString(upperCase); 803 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) 804 .Case("lsl", ARM_AM::lsl) 805 .Case("lsr", ARM_AM::lsr) 806 .Case("asr", ARM_AM::asr) 807 .Case("ror", ARM_AM::ror) 808 .Case("rrx", ARM_AM::rrx) 809 .Default(ARM_AM::no_shift); 810 811 if (ShiftTy == ARM_AM::no_shift) 812 return true; 813 814 Parser.Lex(); // Eat shift-type operand; 815 int RegNum = TryParseRegister(); 816 if (RegNum == -1) 817 return Error(Parser.getTok().getLoc(), "register expected"); 818 819 Operands.push_back(ARMOperand::CreateReg(RegNum,S, Parser.getTok().getLoc())); 820 Operands.push_back(ARMOperand::CreateShifter(ShiftTy, 821 S, Parser.getTok().getLoc())); 822 823 return false; 824} 825 826 827/// Try to parse a register name. The token must be an Identifier when called. 828/// If it's a register, an AsmOperand is created. Another AsmOperand is created 829/// if there is a "writeback". 'true' if it's not a register. 830/// 831/// TODO this is likely to change to allow different register types and or to 832/// parse for a specific register type. 833bool ARMAsmParser:: 834TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 835 SMLoc S = Parser.getTok().getLoc(); 836 int RegNo = TryParseRegister(); 837 if (RegNo == -1) 838 return true; 839 840 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc())); 841 842 const AsmToken &ExclaimTok = Parser.getTok(); 843 if (ExclaimTok.is(AsmToken::Exclaim)) { 844 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), 845 ExclaimTok.getLoc())); 846 Parser.Lex(); // Eat exclaim token 847 } 848 849 return false; 850} 851 852/// MatchCoprocessorOperandName - Try to parse an coprocessor related 853/// instruction with a symbolic operand name. Example: "p1", "p7", "c3", 854/// "c5", ... 855static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { 856 // Use the same layout as the tablegen'erated register name matcher. Ugly, 857 // but efficient. 858 switch (Name.size()) { 859 default: break; 860 case 2: 861 if (Name[0] != CoprocOp) 862 return -1; 863 switch (Name[1]) { 864 default: return -1; 865 case '0': return 0; 866 case '1': return 1; 867 case '2': return 2; 868 case '3': return 3; 869 case '4': return 4; 870 case '5': return 5; 871 case '6': return 6; 872 case '7': return 7; 873 case '8': return 8; 874 case '9': return 9; 875 } 876 break; 877 case 3: 878 if (Name[0] != CoprocOp || Name[1] != '1') 879 return -1; 880 switch (Name[2]) { 881 default: return -1; 882 case '0': return 10; 883 case '1': return 11; 884 case '2': return 12; 885 case '3': return 13; 886 case '4': return 14; 887 case '5': return 15; 888 } 889 break; 890 } 891 892 return -1; 893} 894 895/// tryParseCoprocNumOperand - Try to parse an coprocessor number operand. The 896/// token must be an Identifier when called, and if it is a coprocessor 897/// number, the token is eaten and the operand is added to the operand list. 898ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 899tryParseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 900 SMLoc S = Parser.getTok().getLoc(); 901 const AsmToken &Tok = Parser.getTok(); 902 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 903 904 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p'); 905 if (Num == -1) 906 return MatchOperand_NoMatch; 907 908 Parser.Lex(); // Eat identifier token. 909 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); 910 return MatchOperand_Success; 911} 912 913/// tryParseCoprocRegOperand - Try to parse an coprocessor register operand. The 914/// token must be an Identifier when called, and if it is a coprocessor 915/// number, the token is eaten and the operand is added to the operand list. 916ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 917tryParseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 918 SMLoc S = Parser.getTok().getLoc(); 919 const AsmToken &Tok = Parser.getTok(); 920 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 921 922 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); 923 if (Reg == -1) 924 return MatchOperand_NoMatch; 925 926 Parser.Lex(); // Eat identifier token. 927 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); 928 return MatchOperand_Success; 929} 930 931/// Parse a register list, return it if successful else return null. The first 932/// token must be a '{' when called. 933bool ARMAsmParser:: 934ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 935 assert(Parser.getTok().is(AsmToken::LCurly) && 936 "Token is not a Left Curly Brace"); 937 SMLoc S = Parser.getTok().getLoc(); 938 939 // Read the rest of the registers in the list. 940 unsigned PrevRegNum = 0; 941 SmallVector<std::pair<unsigned, SMLoc>, 32> Registers; 942 943 do { 944 bool IsRange = Parser.getTok().is(AsmToken::Minus); 945 Parser.Lex(); // Eat non-identifier token. 946 947 const AsmToken &RegTok = Parser.getTok(); 948 SMLoc RegLoc = RegTok.getLoc(); 949 if (RegTok.isNot(AsmToken::Identifier)) { 950 Error(RegLoc, "register expected"); 951 return true; 952 } 953 954 int RegNum = TryParseRegister(); 955 if (RegNum == -1) { 956 Error(RegLoc, "register expected"); 957 return true; 958 } 959 960 if (IsRange) { 961 int Reg = PrevRegNum; 962 do { 963 ++Reg; 964 Registers.push_back(std::make_pair(Reg, RegLoc)); 965 } while (Reg != RegNum); 966 } else { 967 Registers.push_back(std::make_pair(RegNum, RegLoc)); 968 } 969 970 PrevRegNum = RegNum; 971 } while (Parser.getTok().is(AsmToken::Comma) || 972 Parser.getTok().is(AsmToken::Minus)); 973 974 // Process the right curly brace of the list. 975 const AsmToken &RCurlyTok = Parser.getTok(); 976 if (RCurlyTok.isNot(AsmToken::RCurly)) { 977 Error(RCurlyTok.getLoc(), "'}' expected"); 978 return true; 979 } 980 981 SMLoc E = RCurlyTok.getLoc(); 982 Parser.Lex(); // Eat right curly brace token. 983 984 // Verify the register list. 985 SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator 986 RI = Registers.begin(), RE = Registers.end(); 987 988 unsigned HighRegNum = getARMRegisterNumbering(RI->first); 989 bool EmittedWarning = false; 990 991 DenseMap<unsigned, bool> RegMap; 992 RegMap[HighRegNum] = true; 993 994 for (++RI; RI != RE; ++RI) { 995 const std::pair<unsigned, SMLoc> &RegInfo = *RI; 996 unsigned Reg = getARMRegisterNumbering(RegInfo.first); 997 998 if (RegMap[Reg]) { 999 Error(RegInfo.second, "register duplicated in register list"); 1000 return true; 1001 } 1002 1003 if (!EmittedWarning && Reg < HighRegNum) 1004 Warning(RegInfo.second, 1005 "register not in ascending order in register list"); 1006 1007 RegMap[Reg] = true; 1008 HighRegNum = std::max(Reg, HighRegNum); 1009 } 1010 1011 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); 1012 return false; 1013} 1014 1015/// tryParseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. 1016ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1017tryParseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1018 SMLoc S = Parser.getTok().getLoc(); 1019 const AsmToken &Tok = Parser.getTok(); 1020 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1021 StringRef OptStr = Tok.getString(); 1022 1023 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size())) 1024 .Case("sy", ARM_MB::SY) 1025 .Case("st", ARM_MB::ST) 1026 .Case("ish", ARM_MB::ISH) 1027 .Case("ishst", ARM_MB::ISHST) 1028 .Case("nsh", ARM_MB::NSH) 1029 .Case("nshst", ARM_MB::NSHST) 1030 .Case("osh", ARM_MB::OSH) 1031 .Case("oshst", ARM_MB::OSHST) 1032 .Default(~0U); 1033 1034 if (Opt == ~0U) 1035 return MatchOperand_NoMatch; 1036 1037 Parser.Lex(); // Eat identifier token. 1038 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); 1039 return MatchOperand_Success; 1040} 1041 1042/// tryParseProcIFlagsOperand - Try to parse iflags from CPS instruction. 1043ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1044tryParseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1045 SMLoc S = Parser.getTok().getLoc(); 1046 const AsmToken &Tok = Parser.getTok(); 1047 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1048 StringRef IFlagsStr = Tok.getString(); 1049 1050 unsigned IFlags = 0; 1051 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { 1052 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1)) 1053 .Case("a", ARM_PROC::A) 1054 .Case("i", ARM_PROC::I) 1055 .Case("f", ARM_PROC::F) 1056 .Default(~0U); 1057 1058 // If some specific iflag is already set, it means that some letter is 1059 // present more than once, this is not acceptable. 1060 if (Flag == ~0U || (IFlags & Flag)) 1061 return MatchOperand_NoMatch; 1062 1063 IFlags |= Flag; 1064 } 1065 1066 Parser.Lex(); // Eat identifier token. 1067 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); 1068 return MatchOperand_Success; 1069} 1070 1071/// tryParseMSRMaskOperand - Try to parse mask flags from MSR instruction. 1072ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 1073tryParseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1074 SMLoc S = Parser.getTok().getLoc(); 1075 const AsmToken &Tok = Parser.getTok(); 1076 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 1077 StringRef Mask = Tok.getString(); 1078 1079 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" 1080 size_t Start = 0, Next = Mask.find('_'); 1081 StringRef Flags = ""; 1082 StringRef SpecReg = Mask.slice(Start, Next); 1083 if (Next != StringRef::npos) 1084 Flags = Mask.slice(Next+1, Mask.size()); 1085 1086 // FlagsVal contains the complete mask: 1087 // 3-0: Mask 1088 // 4: Special Reg (cpsr, apsr => 0; spsr => 1) 1089 unsigned FlagsVal = 0; 1090 1091 if (SpecReg == "apsr") { 1092 FlagsVal = StringSwitch<unsigned>(Flags) 1093 .Case("nzcvq", 0x8) // same as CPSR_c 1094 .Case("g", 0x4) // same as CPSR_s 1095 .Case("nzcvqg", 0xc) // same as CPSR_fs 1096 .Default(~0U); 1097 1098 if (FlagsVal == ~0U) { 1099 if (!Flags.empty()) 1100 return MatchOperand_NoMatch; 1101 else 1102 FlagsVal = 0; // No flag 1103 } 1104 } else if (SpecReg == "cpsr" || SpecReg == "spsr") { 1105 for (int i = 0, e = Flags.size(); i != e; ++i) { 1106 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1)) 1107 .Case("c", 1) 1108 .Case("x", 2) 1109 .Case("s", 4) 1110 .Case("f", 8) 1111 .Default(~0U); 1112 1113 // If some specific flag is already set, it means that some letter is 1114 // present more than once, this is not acceptable. 1115 if (FlagsVal == ~0U || (FlagsVal & Flag)) 1116 return MatchOperand_NoMatch; 1117 FlagsVal |= Flag; 1118 } 1119 } else // No match for special register. 1120 return MatchOperand_NoMatch; 1121 1122 // Special register without flags are equivalent to "fc" flags. 1123 if (!FlagsVal) 1124 FlagsVal = 0x9; 1125 1126 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) 1127 if (SpecReg == "spsr") 1128 FlagsVal |= 16; 1129 1130 Parser.Lex(); // Eat identifier token. 1131 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 1132 return MatchOperand_Success; 1133} 1134 1135/// Parse an ARM memory expression, return false if successful else return true 1136/// or an error. The first token must be a '[' when called. 1137/// 1138/// TODO Only preindexing and postindexing addressing are started, unindexed 1139/// with option, etc are still to do. 1140bool ARMAsmParser:: 1141ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1142 SMLoc S, E; 1143 assert(Parser.getTok().is(AsmToken::LBrac) && 1144 "Token is not a Left Bracket"); 1145 S = Parser.getTok().getLoc(); 1146 Parser.Lex(); // Eat left bracket token. 1147 1148 const AsmToken &BaseRegTok = Parser.getTok(); 1149 if (BaseRegTok.isNot(AsmToken::Identifier)) { 1150 Error(BaseRegTok.getLoc(), "register expected"); 1151 return true; 1152 } 1153 int BaseRegNum = TryParseRegister(); 1154 if (BaseRegNum == -1) { 1155 Error(BaseRegTok.getLoc(), "register expected"); 1156 return true; 1157 } 1158 1159 // The next token must either be a comma or a closing bracket. 1160 const AsmToken &Tok = Parser.getTok(); 1161 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac)) 1162 return true; 1163 1164 bool Preindexed = false; 1165 bool Postindexed = false; 1166 bool OffsetIsReg = false; 1167 bool Negative = false; 1168 bool Writeback = false; 1169 ARMOperand *WBOp = 0; 1170 int OffsetRegNum = -1; 1171 bool OffsetRegShifted = false; 1172 enum ARM_AM::ShiftOpc ShiftType = ARM_AM::lsl; 1173 const MCExpr *ShiftAmount = 0; 1174 const MCExpr *Offset = 0; 1175 1176 // First look for preindexed address forms, that is after the "[Rn" we now 1177 // have to see if the next token is a comma. 1178 if (Tok.is(AsmToken::Comma)) { 1179 Preindexed = true; 1180 Parser.Lex(); // Eat comma token. 1181 1182 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount, 1183 Offset, OffsetIsReg, OffsetRegNum, E)) 1184 return true; 1185 const AsmToken &RBracTok = Parser.getTok(); 1186 if (RBracTok.isNot(AsmToken::RBrac)) { 1187 Error(RBracTok.getLoc(), "']' expected"); 1188 return true; 1189 } 1190 E = RBracTok.getLoc(); 1191 Parser.Lex(); // Eat right bracket token. 1192 1193 const AsmToken &ExclaimTok = Parser.getTok(); 1194 if (ExclaimTok.is(AsmToken::Exclaim)) { 1195 WBOp = ARMOperand::CreateToken(ExclaimTok.getString(), 1196 ExclaimTok.getLoc()); 1197 Writeback = true; 1198 Parser.Lex(); // Eat exclaim token 1199 } 1200 } else { 1201 // The "[Rn" we have so far was not followed by a comma. 1202 1203 // If there's anything other than the right brace, this is a post indexing 1204 // addressing form. 1205 E = Tok.getLoc(); 1206 Parser.Lex(); // Eat right bracket token. 1207 1208 const AsmToken &NextTok = Parser.getTok(); 1209 1210 if (NextTok.isNot(AsmToken::EndOfStatement)) { 1211 Postindexed = true; 1212 Writeback = true; 1213 1214 if (NextTok.isNot(AsmToken::Comma)) { 1215 Error(NextTok.getLoc(), "',' expected"); 1216 return true; 1217 } 1218 1219 Parser.Lex(); // Eat comma token. 1220 1221 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, 1222 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum, 1223 E)) 1224 return true; 1225 } 1226 } 1227 1228 // Force Offset to exist if used. 1229 if (!OffsetIsReg) { 1230 if (!Offset) 1231 Offset = MCConstantExpr::Create(0, getContext()); 1232 } 1233 1234 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, 1235 OffsetRegNum, OffsetRegShifted, 1236 ShiftType, ShiftAmount, Preindexed, 1237 Postindexed, Negative, Writeback, 1238 S, E)); 1239 if (WBOp) 1240 Operands.push_back(WBOp); 1241 1242 return false; 1243} 1244 1245/// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn]," 1246/// we will parse the following (were +/- means that a plus or minus is 1247/// optional): 1248/// +/-Rm 1249/// +/-Rm, shift 1250/// #offset 1251/// we return false on success or an error otherwise. 1252bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative, 1253 bool &OffsetRegShifted, 1254 enum ARM_AM::ShiftOpc &ShiftType, 1255 const MCExpr *&ShiftAmount, 1256 const MCExpr *&Offset, 1257 bool &OffsetIsReg, 1258 int &OffsetRegNum, 1259 SMLoc &E) { 1260 Negative = false; 1261 OffsetRegShifted = false; 1262 OffsetIsReg = false; 1263 OffsetRegNum = -1; 1264 const AsmToken &NextTok = Parser.getTok(); 1265 E = NextTok.getLoc(); 1266 if (NextTok.is(AsmToken::Plus)) 1267 Parser.Lex(); // Eat plus token. 1268 else if (NextTok.is(AsmToken::Minus)) { 1269 Negative = true; 1270 Parser.Lex(); // Eat minus token 1271 } 1272 // See if there is a register following the "[Rn," or "[Rn]," we have so far. 1273 const AsmToken &OffsetRegTok = Parser.getTok(); 1274 if (OffsetRegTok.is(AsmToken::Identifier)) { 1275 SMLoc CurLoc = OffsetRegTok.getLoc(); 1276 OffsetRegNum = TryParseRegister(); 1277 if (OffsetRegNum != -1) { 1278 OffsetIsReg = true; 1279 E = CurLoc; 1280 } 1281 } 1282 1283 // If we parsed a register as the offset then there can be a shift after that. 1284 if (OffsetRegNum != -1) { 1285 // Look for a comma then a shift 1286 const AsmToken &Tok = Parser.getTok(); 1287 if (Tok.is(AsmToken::Comma)) { 1288 Parser.Lex(); // Eat comma token. 1289 1290 const AsmToken &Tok = Parser.getTok(); 1291 if (ParseShift(ShiftType, ShiftAmount, E)) 1292 return Error(Tok.getLoc(), "shift expected"); 1293 OffsetRegShifted = true; 1294 } 1295 } 1296 else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm" 1297 // Look for #offset following the "[Rn," or "[Rn]," 1298 const AsmToken &HashTok = Parser.getTok(); 1299 if (HashTok.isNot(AsmToken::Hash)) 1300 return Error(HashTok.getLoc(), "'#' expected"); 1301 1302 Parser.Lex(); // Eat hash token. 1303 1304 if (getParser().ParseExpression(Offset)) 1305 return true; 1306 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1307 } 1308 return false; 1309} 1310 1311/// ParseShift as one of these two: 1312/// ( lsl | lsr | asr | ror ) , # shift_amount 1313/// rrx 1314/// and returns true if it parses a shift otherwise it returns false. 1315bool ARMAsmParser::ParseShift(ARM_AM::ShiftOpc &St, 1316 const MCExpr *&ShiftAmount, SMLoc &E) { 1317 const AsmToken &Tok = Parser.getTok(); 1318 if (Tok.isNot(AsmToken::Identifier)) 1319 return true; 1320 StringRef ShiftName = Tok.getString(); 1321 if (ShiftName == "lsl" || ShiftName == "LSL") 1322 St = ARM_AM::lsl; 1323 else if (ShiftName == "lsr" || ShiftName == "LSR") 1324 St = ARM_AM::lsr; 1325 else if (ShiftName == "asr" || ShiftName == "ASR") 1326 St = ARM_AM::asr; 1327 else if (ShiftName == "ror" || ShiftName == "ROR") 1328 St = ARM_AM::ror; 1329 else if (ShiftName == "rrx" || ShiftName == "RRX") 1330 St = ARM_AM::rrx; 1331 else 1332 return true; 1333 Parser.Lex(); // Eat shift type token. 1334 1335 // Rrx stands alone. 1336 if (St == ARM_AM::rrx) 1337 return false; 1338 1339 // Otherwise, there must be a '#' and a shift amount. 1340 const AsmToken &HashTok = Parser.getTok(); 1341 if (HashTok.isNot(AsmToken::Hash)) 1342 return Error(HashTok.getLoc(), "'#' expected"); 1343 Parser.Lex(); // Eat hash token. 1344 1345 if (getParser().ParseExpression(ShiftAmount)) 1346 return true; 1347 1348 return false; 1349} 1350 1351/// Parse a arm instruction operand. For now this parses the operand regardless 1352/// of the mnemonic. 1353bool ARMAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 1354 StringRef Mnemonic) { 1355 SMLoc S, E; 1356 1357 // Check if the current operand has a custom associated parser, if so, try to 1358 // custom parse the operand, or fallback to the general approach. 1359 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 1360 if (ResTy == MatchOperand_Success) 1361 return false; 1362 // If there wasn't a custom match, try the generic matcher below. Otherwise, 1363 // there was a match, but an error occurred, in which case, just return that 1364 // the operand parsing failed. 1365 if (ResTy == MatchOperand_ParseFail) 1366 return true; 1367 1368 switch (getLexer().getKind()) { 1369 default: 1370 Error(Parser.getTok().getLoc(), "unexpected token in operand"); 1371 return true; 1372 case AsmToken::Identifier: 1373 if (!TryParseRegisterWithWriteBack(Operands)) 1374 return false; 1375 if (!TryParseShiftRegister(Operands)) 1376 return false; 1377 1378 1379 // Fall though for the Identifier case that is not a register or a 1380 // special name. 1381 case AsmToken::Integer: // things like 1f and 2b as a branch targets 1382 case AsmToken::Dot: { // . as a branch target 1383 // This was not a register so parse other operands that start with an 1384 // identifier (like labels) as expressions and create them as immediates. 1385 const MCExpr *IdVal; 1386 S = Parser.getTok().getLoc(); 1387 if (getParser().ParseExpression(IdVal)) 1388 return true; 1389 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1390 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); 1391 return false; 1392 } 1393 case AsmToken::LBrac: 1394 return ParseMemory(Operands); 1395 case AsmToken::LCurly: 1396 return ParseRegisterList(Operands); 1397 case AsmToken::Hash: 1398 // #42 -> immediate. 1399 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate 1400 S = Parser.getTok().getLoc(); 1401 Parser.Lex(); 1402 const MCExpr *ImmVal; 1403 if (getParser().ParseExpression(ImmVal)) 1404 return true; 1405 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1406 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); 1407 return false; 1408 case AsmToken::Colon: { 1409 // ":lower16:" and ":upper16:" expression prefixes 1410 // FIXME: Check it's an expression prefix, 1411 // e.g. (FOO - :lower16:BAR) isn't legal. 1412 ARMMCExpr::VariantKind RefKind; 1413 if (ParsePrefix(RefKind)) 1414 return true; 1415 1416 const MCExpr *SubExprVal; 1417 if (getParser().ParseExpression(SubExprVal)) 1418 return true; 1419 1420 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal, 1421 getContext()); 1422 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1423 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); 1424 return false; 1425 } 1426 } 1427} 1428 1429// ParsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. 1430// :lower16: and :upper16:. 1431bool ARMAsmParser::ParsePrefix(ARMMCExpr::VariantKind &RefKind) { 1432 RefKind = ARMMCExpr::VK_ARM_None; 1433 1434 // :lower16: and :upper16: modifiers 1435 assert(getLexer().is(AsmToken::Colon) && "expected a :"); 1436 Parser.Lex(); // Eat ':' 1437 1438 if (getLexer().isNot(AsmToken::Identifier)) { 1439 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); 1440 return true; 1441 } 1442 1443 StringRef IDVal = Parser.getTok().getIdentifier(); 1444 if (IDVal == "lower16") { 1445 RefKind = ARMMCExpr::VK_ARM_LO16; 1446 } else if (IDVal == "upper16") { 1447 RefKind = ARMMCExpr::VK_ARM_HI16; 1448 } else { 1449 Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); 1450 return true; 1451 } 1452 Parser.Lex(); 1453 1454 if (getLexer().isNot(AsmToken::Colon)) { 1455 Error(Parser.getTok().getLoc(), "unexpected token after prefix"); 1456 return true; 1457 } 1458 Parser.Lex(); // Eat the last ':' 1459 return false; 1460} 1461 1462const MCExpr * 1463ARMAsmParser::ApplyPrefixToExpr(const MCExpr *E, 1464 MCSymbolRefExpr::VariantKind Variant) { 1465 // Recurse over the given expression, rebuilding it to apply the given variant 1466 // to the leftmost symbol. 1467 if (Variant == MCSymbolRefExpr::VK_None) 1468 return E; 1469 1470 switch (E->getKind()) { 1471 case MCExpr::Target: 1472 llvm_unreachable("Can't handle target expr yet"); 1473 case MCExpr::Constant: 1474 llvm_unreachable("Can't handle lower16/upper16 of constant yet"); 1475 1476 case MCExpr::SymbolRef: { 1477 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 1478 1479 if (SRE->getKind() != MCSymbolRefExpr::VK_None) 1480 return 0; 1481 1482 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext()); 1483 } 1484 1485 case MCExpr::Unary: 1486 llvm_unreachable("Can't handle unary expressions yet"); 1487 1488 case MCExpr::Binary: { 1489 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 1490 const MCExpr *LHS = ApplyPrefixToExpr(BE->getLHS(), Variant); 1491 const MCExpr *RHS = BE->getRHS(); 1492 if (!LHS) 1493 return 0; 1494 1495 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext()); 1496 } 1497 } 1498 1499 assert(0 && "Invalid expression kind!"); 1500 return 0; 1501} 1502 1503/// \brief Given a mnemonic, split out possible predication code and carry 1504/// setting letters to form a canonical mnemonic and flags. 1505// 1506// FIXME: Would be nice to autogen this. 1507static StringRef SplitMnemonic(StringRef Mnemonic, 1508 unsigned &PredicationCode, 1509 bool &CarrySetting, 1510 unsigned &ProcessorIMod) { 1511 PredicationCode = ARMCC::AL; 1512 CarrySetting = false; 1513 ProcessorIMod = 0; 1514 1515 // Ignore some mnemonics we know aren't predicated forms. 1516 // 1517 // FIXME: Would be nice to autogen this. 1518 if (Mnemonic == "teq" || Mnemonic == "vceq" || 1519 Mnemonic == "movs" || 1520 Mnemonic == "svc" || 1521 (Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || 1522 Mnemonic == "vmls" || Mnemonic == "vnmls") || 1523 Mnemonic == "vacge" || Mnemonic == "vcge" || 1524 Mnemonic == "vclt" || 1525 Mnemonic == "vacgt" || Mnemonic == "vcgt" || 1526 Mnemonic == "vcle" || 1527 (Mnemonic == "smlal" || Mnemonic == "umaal" || Mnemonic == "umlal" || 1528 Mnemonic == "vabal" || Mnemonic == "vmlal" || Mnemonic == "vpadal" || 1529 Mnemonic == "vqdmlal")) 1530 return Mnemonic; 1531 1532 // First, split out any predication code. 1533 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2)) 1534 .Case("eq", ARMCC::EQ) 1535 .Case("ne", ARMCC::NE) 1536 .Case("hs", ARMCC::HS) 1537 .Case("lo", ARMCC::LO) 1538 .Case("mi", ARMCC::MI) 1539 .Case("pl", ARMCC::PL) 1540 .Case("vs", ARMCC::VS) 1541 .Case("vc", ARMCC::VC) 1542 .Case("hi", ARMCC::HI) 1543 .Case("ls", ARMCC::LS) 1544 .Case("ge", ARMCC::GE) 1545 .Case("lt", ARMCC::LT) 1546 .Case("gt", ARMCC::GT) 1547 .Case("le", ARMCC::LE) 1548 .Case("al", ARMCC::AL) 1549 .Default(~0U); 1550 if (CC != ~0U) { 1551 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); 1552 PredicationCode = CC; 1553 } 1554 1555 // Next, determine if we have a carry setting bit. We explicitly ignore all 1556 // the instructions we know end in 's'. 1557 if (Mnemonic.endswith("s") && 1558 !(Mnemonic == "asrs" || Mnemonic == "cps" || Mnemonic == "mls" || 1559 Mnemonic == "movs" || Mnemonic == "mrs" || Mnemonic == "smmls" || 1560 Mnemonic == "vabs" || Mnemonic == "vcls" || Mnemonic == "vmls" || 1561 Mnemonic == "vmrs" || Mnemonic == "vnmls" || Mnemonic == "vqabs" || 1562 Mnemonic == "vrecps" || Mnemonic == "vrsqrts")) { 1563 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); 1564 CarrySetting = true; 1565 } 1566 1567 // The "cps" instruction can have a interrupt mode operand which is glued into 1568 // the mnemonic. Check if this is the case, split it and parse the imod op 1569 if (Mnemonic.startswith("cps")) { 1570 // Split out any imod code. 1571 unsigned IMod = 1572 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2)) 1573 .Case("ie", ARM_PROC::IE) 1574 .Case("id", ARM_PROC::ID) 1575 .Default(~0U); 1576 if (IMod != ~0U) { 1577 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2); 1578 ProcessorIMod = IMod; 1579 } 1580 } 1581 1582 return Mnemonic; 1583} 1584 1585/// \brief Given a canonical mnemonic, determine if the instruction ever allows 1586/// inclusion of carry set or predication code operands. 1587// 1588// FIXME: It would be nice to autogen this. 1589void ARMAsmParser:: 1590GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 1591 bool &CanAcceptPredicationCode) { 1592 bool isThumb = TM.getSubtarget<ARMSubtarget>().isThumb(); 1593 1594 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || 1595 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || 1596 Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" || 1597 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" || 1598 Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mov" || 1599 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || 1600 Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" || 1601 Mnemonic == "eor" || Mnemonic == "smlal" || Mnemonic == "mvn") { 1602 CanAcceptCarrySet = true; 1603 } else { 1604 CanAcceptCarrySet = false; 1605 } 1606 1607 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" || 1608 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" || 1609 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" || 1610 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" || 1611 Mnemonic == "dsb" || Mnemonic == "movs" || Mnemonic == "isb" || 1612 Mnemonic == "clrex" || Mnemonic.startswith("cps")) { 1613 CanAcceptPredicationCode = false; 1614 } else { 1615 CanAcceptPredicationCode = true; 1616 } 1617 1618 if (isThumb) 1619 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" || 1620 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp") 1621 CanAcceptPredicationCode = false; 1622} 1623 1624/// Parse an arm instruction mnemonic followed by its operands. 1625bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc, 1626 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1627 // Create the leading tokens for the mnemonic, split by '.' characters. 1628 size_t Start = 0, Next = Name.find('.'); 1629 StringRef Head = Name.slice(Start, Next); 1630 1631 // Split out the predication code and carry setting flag from the mnemonic. 1632 unsigned PredicationCode; 1633 unsigned ProcessorIMod; 1634 bool CarrySetting; 1635 Head = SplitMnemonic(Head, PredicationCode, CarrySetting, 1636 ProcessorIMod); 1637 1638 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc)); 1639 1640 // Next, add the CCOut and ConditionCode operands, if needed. 1641 // 1642 // For mnemonics which can ever incorporate a carry setting bit or predication 1643 // code, our matching model involves us always generating CCOut and 1644 // ConditionCode operands to match the mnemonic "as written" and then we let 1645 // the matcher deal with finding the right instruction or generating an 1646 // appropriate error. 1647 bool CanAcceptCarrySet, CanAcceptPredicationCode; 1648 GetMnemonicAcceptInfo(Head, CanAcceptCarrySet, CanAcceptPredicationCode); 1649 1650 // Add the carry setting operand, if necessary. 1651 // 1652 // FIXME: It would be awesome if we could somehow invent a location such that 1653 // match errors on this operand would print a nice diagnostic about how the 1654 // 's' character in the mnemonic resulted in a CCOut operand. 1655 if (CanAcceptCarrySet) { 1656 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, 1657 NameLoc)); 1658 } else { 1659 // This mnemonic can't ever accept a carry set, but the user wrote one (or 1660 // misspelled another mnemonic). 1661 1662 // FIXME: Issue a nice error. 1663 } 1664 1665 // Add the predication code operand, if necessary. 1666 if (CanAcceptPredicationCode) { 1667 Operands.push_back(ARMOperand::CreateCondCode( 1668 ARMCC::CondCodes(PredicationCode), NameLoc)); 1669 } else { 1670 // This mnemonic can't ever accept a predication code, but the user wrote 1671 // one (or misspelled another mnemonic). 1672 1673 // FIXME: Issue a nice error. 1674 } 1675 1676 // Add the processor imod operand, if necessary. 1677 if (ProcessorIMod) { 1678 Operands.push_back(ARMOperand::CreateImm( 1679 MCConstantExpr::Create(ProcessorIMod, getContext()), 1680 NameLoc, NameLoc)); 1681 } else { 1682 // This mnemonic can't ever accept a imod, but the user wrote 1683 // one (or misspelled another mnemonic). 1684 1685 // FIXME: Issue a nice error. 1686 } 1687 1688 // Add the remaining tokens in the mnemonic. 1689 while (Next != StringRef::npos) { 1690 Start = Next; 1691 Next = Name.find('.', Start + 1); 1692 StringRef ExtraToken = Name.slice(Start, Next); 1693 1694 Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc)); 1695 } 1696 1697 // Read the remaining operands. 1698 if (getLexer().isNot(AsmToken::EndOfStatement)) { 1699 // Read the first operand. 1700 if (ParseOperand(Operands, Head)) { 1701 Parser.EatToEndOfStatement(); 1702 return true; 1703 } 1704 1705 while (getLexer().is(AsmToken::Comma)) { 1706 Parser.Lex(); // Eat the comma. 1707 1708 // Parse and remember the operand. 1709 if (ParseOperand(Operands, Head)) { 1710 Parser.EatToEndOfStatement(); 1711 return true; 1712 } 1713 } 1714 } 1715 1716 if (getLexer().isNot(AsmToken::EndOfStatement)) { 1717 Parser.EatToEndOfStatement(); 1718 return TokError("unexpected token in argument list"); 1719 } 1720 1721 Parser.Lex(); // Consume the EndOfStatement 1722 return false; 1723} 1724 1725bool ARMAsmParser:: 1726MatchAndEmitInstruction(SMLoc IDLoc, 1727 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 1728 MCStreamer &Out) { 1729 MCInst Inst; 1730 unsigned ErrorInfo; 1731 MatchResultTy MatchResult, MatchResult2; 1732 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo); 1733 if (MatchResult != Match_Success) { 1734 // If we get a Match_InvalidOperand it might be some arithmetic instruction 1735 // that does not update the condition codes. So try adding a CCOut operand 1736 // with a value of reg0. 1737 if (MatchResult == Match_InvalidOperand) { 1738 Operands.insert(Operands.begin() + 1, 1739 ARMOperand::CreateCCOut(0, 1740 ((ARMOperand*)Operands[0])->getStartLoc())); 1741 MatchResult2 = MatchInstructionImpl(Operands, Inst, ErrorInfo); 1742 if (MatchResult2 == Match_Success) 1743 MatchResult = Match_Success; 1744 else { 1745 ARMOperand *CCOut = ((ARMOperand*)Operands[1]); 1746 Operands.erase(Operands.begin() + 1); 1747 delete CCOut; 1748 } 1749 } 1750 // If we get a Match_MnemonicFail it might be some arithmetic instruction 1751 // that updates the condition codes if it ends in 's'. So see if the 1752 // mnemonic ends in 's' and if so try removing the 's' and adding a CCOut 1753 // operand with a value of CPSR. 1754 else if(MatchResult == Match_MnemonicFail) { 1755 // Get the instruction mnemonic, which is the first token. 1756 StringRef Mnemonic = ((ARMOperand*)Operands[0])->getToken(); 1757 if (Mnemonic.substr(Mnemonic.size()-1) == "s") { 1758 // removed the 's' from the mnemonic for matching. 1759 StringRef MnemonicNoS = Mnemonic.slice(0, Mnemonic.size() - 1); 1760 SMLoc NameLoc = ((ARMOperand*)Operands[0])->getStartLoc(); 1761 ARMOperand *OldMnemonic = ((ARMOperand*)Operands[0]); 1762 Operands.erase(Operands.begin()); 1763 delete OldMnemonic; 1764 Operands.insert(Operands.begin(), 1765 ARMOperand::CreateToken(MnemonicNoS, NameLoc)); 1766 Operands.insert(Operands.begin() + 1, 1767 ARMOperand::CreateCCOut(ARM::CPSR, NameLoc)); 1768 MatchResult2 = MatchInstructionImpl(Operands, Inst, ErrorInfo); 1769 if (MatchResult2 == Match_Success) 1770 MatchResult = Match_Success; 1771 else { 1772 ARMOperand *OldMnemonic = ((ARMOperand*)Operands[0]); 1773 Operands.erase(Operands.begin()); 1774 delete OldMnemonic; 1775 Operands.insert(Operands.begin(), 1776 ARMOperand::CreateToken(Mnemonic, NameLoc)); 1777 ARMOperand *CCOut = ((ARMOperand*)Operands[1]); 1778 Operands.erase(Operands.begin() + 1); 1779 delete CCOut; 1780 } 1781 } 1782 } 1783 } 1784 switch (MatchResult) { 1785 case Match_Success: 1786 Out.EmitInstruction(Inst); 1787 return false; 1788 case Match_MissingFeature: 1789 Error(IDLoc, "instruction requires a CPU feature not currently enabled"); 1790 return true; 1791 case Match_InvalidOperand: { 1792 SMLoc ErrorLoc = IDLoc; 1793 if (ErrorInfo != ~0U) { 1794 if (ErrorInfo >= Operands.size()) 1795 return Error(IDLoc, "too few operands for instruction"); 1796 1797 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 1798 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 1799 } 1800 1801 return Error(ErrorLoc, "invalid operand for instruction"); 1802 } 1803 case Match_MnemonicFail: 1804 return Error(IDLoc, "unrecognized instruction mnemonic"); 1805 case Match_ConversionFail: 1806 return Error(IDLoc, "unable to convert operands to instruction"); 1807 } 1808 1809 llvm_unreachable("Implement any new match types added!"); 1810 return true; 1811} 1812 1813/// ParseDirective parses the arm specific directives 1814bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { 1815 StringRef IDVal = DirectiveID.getIdentifier(); 1816 if (IDVal == ".word") 1817 return ParseDirectiveWord(4, DirectiveID.getLoc()); 1818 else if (IDVal == ".thumb") 1819 return ParseDirectiveThumb(DirectiveID.getLoc()); 1820 else if (IDVal == ".thumb_func") 1821 return ParseDirectiveThumbFunc(DirectiveID.getLoc()); 1822 else if (IDVal == ".code") 1823 return ParseDirectiveCode(DirectiveID.getLoc()); 1824 else if (IDVal == ".syntax") 1825 return ParseDirectiveSyntax(DirectiveID.getLoc()); 1826 return true; 1827} 1828 1829/// ParseDirectiveWord 1830/// ::= .word [ expression (, expression)* ] 1831bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) { 1832 if (getLexer().isNot(AsmToken::EndOfStatement)) { 1833 for (;;) { 1834 const MCExpr *Value; 1835 if (getParser().ParseExpression(Value)) 1836 return true; 1837 1838 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/); 1839 1840 if (getLexer().is(AsmToken::EndOfStatement)) 1841 break; 1842 1843 // FIXME: Improve diagnostic. 1844 if (getLexer().isNot(AsmToken::Comma)) 1845 return Error(L, "unexpected token in directive"); 1846 Parser.Lex(); 1847 } 1848 } 1849 1850 Parser.Lex(); 1851 return false; 1852} 1853 1854/// ParseDirectiveThumb 1855/// ::= .thumb 1856bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) { 1857 if (getLexer().isNot(AsmToken::EndOfStatement)) 1858 return Error(L, "unexpected token in directive"); 1859 Parser.Lex(); 1860 1861 // TODO: set thumb mode 1862 // TODO: tell the MC streamer the mode 1863 // getParser().getStreamer().Emit???(); 1864 return false; 1865} 1866 1867/// ParseDirectiveThumbFunc 1868/// ::= .thumbfunc symbol_name 1869bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) { 1870 const AsmToken &Tok = Parser.getTok(); 1871 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) 1872 return Error(L, "unexpected token in .thumb_func directive"); 1873 StringRef Name = Tok.getString(); 1874 Parser.Lex(); // Consume the identifier token. 1875 if (getLexer().isNot(AsmToken::EndOfStatement)) 1876 return Error(L, "unexpected token in directive"); 1877 Parser.Lex(); 1878 1879 // Mark symbol as a thumb symbol. 1880 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name); 1881 getParser().getStreamer().EmitThumbFunc(Func); 1882 return false; 1883} 1884 1885/// ParseDirectiveSyntax 1886/// ::= .syntax unified | divided 1887bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) { 1888 const AsmToken &Tok = Parser.getTok(); 1889 if (Tok.isNot(AsmToken::Identifier)) 1890 return Error(L, "unexpected token in .syntax directive"); 1891 StringRef Mode = Tok.getString(); 1892 if (Mode == "unified" || Mode == "UNIFIED") 1893 Parser.Lex(); 1894 else if (Mode == "divided" || Mode == "DIVIDED") 1895 return Error(L, "'.syntax divided' arm asssembly not supported"); 1896 else 1897 return Error(L, "unrecognized syntax mode in .syntax directive"); 1898 1899 if (getLexer().isNot(AsmToken::EndOfStatement)) 1900 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 1901 Parser.Lex(); 1902 1903 // TODO tell the MC streamer the mode 1904 // getParser().getStreamer().Emit???(); 1905 return false; 1906} 1907 1908/// ParseDirectiveCode 1909/// ::= .code 16 | 32 1910bool ARMAsmParser::ParseDirectiveCode(SMLoc L) { 1911 const AsmToken &Tok = Parser.getTok(); 1912 if (Tok.isNot(AsmToken::Integer)) 1913 return Error(L, "unexpected token in .code directive"); 1914 int64_t Val = Parser.getTok().getIntVal(); 1915 if (Val == 16) 1916 Parser.Lex(); 1917 else if (Val == 32) 1918 Parser.Lex(); 1919 else 1920 return Error(L, "invalid operand to .code directive"); 1921 1922 if (getLexer().isNot(AsmToken::EndOfStatement)) 1923 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 1924 Parser.Lex(); 1925 1926 // FIXME: We need to be able switch subtargets at this point so that 1927 // MatchInstructionImpl() will work when it gets the AvailableFeatures which 1928 // includes Feature_IsThumb or not to match the right instructions. This is 1929 // blocked on the FIXME in llvm-mc.cpp when creating the TargetMachine. 1930 if (Val == 16){ 1931 assert(TM.getSubtarget<ARMSubtarget>().isThumb() && 1932 "switching between arm/thumb not yet suppported via .code 16)"); 1933 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 1934 } 1935 else{ 1936 assert(!TM.getSubtarget<ARMSubtarget>().isThumb() && 1937 "switching between thumb/arm not yet suppported via .code 32)"); 1938 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 1939 } 1940 1941 return false; 1942} 1943 1944extern "C" void LLVMInitializeARMAsmLexer(); 1945 1946/// Force static initialization. 1947extern "C" void LLVMInitializeARMAsmParser() { 1948 RegisterAsmParser<ARMAsmParser> X(TheARMTarget); 1949 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget); 1950 LLVMInitializeARMAsmLexer(); 1951} 1952 1953#define GET_REGISTER_MATCHER 1954#define GET_MATCHER_IMPLEMENTATION 1955#include "ARMGenAsmMatcher.inc" 1956