ARMAsmParser.cpp revision ed6a0c5243f4dc13169edc8e342c679f1bfc201c
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#include "MCTargetDesc/ARMBaseInfo.h" 11#include "MCTargetDesc/ARMAddressingModes.h" 12#include "MCTargetDesc/ARMMCExpr.h" 13#include "llvm/MC/MCParser/MCAsmLexer.h" 14#include "llvm/MC/MCParser/MCAsmParser.h" 15#include "llvm/MC/MCParser/MCParsedAsmOperand.h" 16#include "llvm/MC/MCAsmInfo.h" 17#include "llvm/MC/MCContext.h" 18#include "llvm/MC/MCStreamer.h" 19#include "llvm/MC/MCExpr.h" 20#include "llvm/MC/MCInst.h" 21#include "llvm/MC/MCInstrDesc.h" 22#include "llvm/MC/MCRegisterInfo.h" 23#include "llvm/MC/MCSubtargetInfo.h" 24#include "llvm/MC/MCTargetAsmParser.h" 25#include "llvm/Support/MathExtras.h" 26#include "llvm/Support/SourceMgr.h" 27#include "llvm/Support/TargetRegistry.h" 28#include "llvm/Support/raw_ostream.h" 29#include "llvm/ADT/BitVector.h" 30#include "llvm/ADT/OwningPtr.h" 31#include "llvm/ADT/STLExtras.h" 32#include "llvm/ADT/SmallVector.h" 33#include "llvm/ADT/StringExtras.h" 34#include "llvm/ADT/StringSwitch.h" 35#include "llvm/ADT/Twine.h" 36 37using namespace llvm; 38 39namespace { 40 41class ARMOperand; 42 43class ARMAsmParser : public MCTargetAsmParser { 44 MCSubtargetInfo &STI; 45 MCAsmParser &Parser; 46 47 struct { 48 ARMCC::CondCodes Cond; // Condition for IT block. 49 unsigned Mask:4; // Condition mask for instructions. 50 // Starting at first 1 (from lsb). 51 // '1' condition as indicated in IT. 52 // '0' inverse of condition (else). 53 // Count of instructions in IT block is 54 // 4 - trailingzeroes(mask) 55 56 bool FirstCond; // Explicit flag for when we're parsing the 57 // First instruction in the IT block. It's 58 // implied in the mask, so needs special 59 // handling. 60 61 unsigned CurPosition; // Current position in parsing of IT 62 // block. In range [0,3]. Initialized 63 // according to count of instructions in block. 64 // ~0U if no active IT block. 65 } ITState; 66 bool inITBlock() { return ITState.CurPosition != ~0U;} 67 void forwardITPosition() { 68 if (!inITBlock()) return; 69 // Move to the next instruction in the IT block, if there is one. If not, 70 // mark the block as done. 71 unsigned TZ = CountTrailingZeros_32(ITState.Mask); 72 if (++ITState.CurPosition == 5 - TZ) 73 ITState.CurPosition = ~0U; // Done with the IT block after this. 74 } 75 76 77 MCAsmParser &getParser() const { return Parser; } 78 MCAsmLexer &getLexer() const { return Parser.getLexer(); } 79 80 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); } 81 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); } 82 83 int tryParseRegister(); 84 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &); 85 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &); 86 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &); 87 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &); 88 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic); 89 bool parsePrefix(ARMMCExpr::VariantKind &RefKind); 90 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, 91 unsigned &ShiftAmount); 92 bool parseDirectiveWord(unsigned Size, SMLoc L); 93 bool parseDirectiveThumb(SMLoc L); 94 bool parseDirectiveThumbFunc(SMLoc L); 95 bool parseDirectiveCode(SMLoc L); 96 bool parseDirectiveSyntax(SMLoc L); 97 98 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, 99 bool &CarrySetting, unsigned &ProcessorIMod, 100 StringRef &ITMask); 101 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 102 bool &CanAcceptPredicationCode); 103 104 bool isThumb() const { 105 // FIXME: Can tablegen auto-generate this? 106 return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 107 } 108 bool isThumbOne() const { 109 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0; 110 } 111 bool isThumbTwo() const { 112 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2); 113 } 114 bool hasV6Ops() const { 115 return STI.getFeatureBits() & ARM::HasV6Ops; 116 } 117 bool hasV7Ops() const { 118 return STI.getFeatureBits() & ARM::HasV7Ops; 119 } 120 void SwitchMode() { 121 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); 122 setAvailableFeatures(FB); 123 } 124 bool isMClass() const { 125 return STI.getFeatureBits() & ARM::FeatureMClass; 126 } 127 128 /// @name Auto-generated Match Functions 129 /// { 130 131#define GET_ASSEMBLER_HEADER 132#include "ARMGenAsmMatcher.inc" 133 134 /// } 135 136 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&); 137 OperandMatchResultTy parseCoprocNumOperand( 138 SmallVectorImpl<MCParsedAsmOperand*>&); 139 OperandMatchResultTy parseCoprocRegOperand( 140 SmallVectorImpl<MCParsedAsmOperand*>&); 141 OperandMatchResultTy parseCoprocOptionOperand( 142 SmallVectorImpl<MCParsedAsmOperand*>&); 143 OperandMatchResultTy parseMemBarrierOptOperand( 144 SmallVectorImpl<MCParsedAsmOperand*>&); 145 OperandMatchResultTy parseProcIFlagsOperand( 146 SmallVectorImpl<MCParsedAsmOperand*>&); 147 OperandMatchResultTy parseMSRMaskOperand( 148 SmallVectorImpl<MCParsedAsmOperand*>&); 149 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O, 150 StringRef Op, int Low, int High); 151 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 152 return parsePKHImm(O, "lsl", 0, 31); 153 } 154 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 155 return parsePKHImm(O, "asr", 1, 32); 156 } 157 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&); 158 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&); 159 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&); 160 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&); 161 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&); 162 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&); 163 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&); 164 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&); 165 166 // Asm Match Converter Methods 167 bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode, 168 const SmallVectorImpl<MCParsedAsmOperand*> &); 169 bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode, 170 const SmallVectorImpl<MCParsedAsmOperand*> &); 171 bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 172 const SmallVectorImpl<MCParsedAsmOperand*> &); 173 bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 174 const SmallVectorImpl<MCParsedAsmOperand*> &); 175 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 176 const SmallVectorImpl<MCParsedAsmOperand*> &); 177 bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 178 const SmallVectorImpl<MCParsedAsmOperand*> &); 179 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 180 const SmallVectorImpl<MCParsedAsmOperand*> &); 181 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 182 const SmallVectorImpl<MCParsedAsmOperand*> &); 183 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 184 const SmallVectorImpl<MCParsedAsmOperand*> &); 185 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 186 const SmallVectorImpl<MCParsedAsmOperand*> &); 187 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 188 const SmallVectorImpl<MCParsedAsmOperand*> &); 189 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 190 const SmallVectorImpl<MCParsedAsmOperand*> &); 191 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 192 const SmallVectorImpl<MCParsedAsmOperand*> &); 193 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode, 194 const SmallVectorImpl<MCParsedAsmOperand*> &); 195 bool cvtStrdPre(MCInst &Inst, unsigned Opcode, 196 const SmallVectorImpl<MCParsedAsmOperand*> &); 197 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 198 const SmallVectorImpl<MCParsedAsmOperand*> &); 199 bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode, 200 const SmallVectorImpl<MCParsedAsmOperand*> &); 201 bool cvtVLDwbFixed(MCInst &Inst, unsigned Opcode, 202 const SmallVectorImpl<MCParsedAsmOperand*> &); 203 bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode, 204 const SmallVectorImpl<MCParsedAsmOperand*> &); 205 bool cvtVSTwbFixed(MCInst &Inst, unsigned Opcode, 206 const SmallVectorImpl<MCParsedAsmOperand*> &); 207 bool cvtVSTwbRegister(MCInst &Inst, unsigned Opcode, 208 const SmallVectorImpl<MCParsedAsmOperand*> &); 209 210 bool validateInstruction(MCInst &Inst, 211 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 212 void processInstruction(MCInst &Inst, 213 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 214 bool shouldOmitCCOutOperand(StringRef Mnemonic, 215 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 216 217public: 218 enum ARMMatchResultTy { 219 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY, 220 Match_RequiresNotITBlock, 221 Match_RequiresV6, 222 Match_RequiresThumb2 223 }; 224 225 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser) 226 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) { 227 MCAsmParserExtension::Initialize(_Parser); 228 229 // Initialize the set of available features. 230 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 231 232 // Not in an ITBlock to start with. 233 ITState.CurPosition = ~0U; 234 } 235 236 // Implementation of the MCTargetAsmParser interface: 237 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); 238 bool ParseInstruction(StringRef Name, SMLoc NameLoc, 239 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 240 bool ParseDirective(AsmToken DirectiveID); 241 242 unsigned checkTargetMatchPredicate(MCInst &Inst); 243 244 bool MatchAndEmitInstruction(SMLoc IDLoc, 245 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 246 MCStreamer &Out); 247}; 248} // end anonymous namespace 249 250namespace { 251 252/// ARMOperand - Instances of this class represent a parsed ARM machine 253/// instruction. 254class ARMOperand : public MCParsedAsmOperand { 255 enum KindTy { 256 k_CondCode, 257 k_CCOut, 258 k_ITCondMask, 259 k_CoprocNum, 260 k_CoprocReg, 261 k_CoprocOption, 262 k_Immediate, 263 k_FPImmediate, 264 k_MemBarrierOpt, 265 k_Memory, 266 k_PostIndexRegister, 267 k_MSRMask, 268 k_ProcIFlags, 269 k_VectorIndex, 270 k_Register, 271 k_RegisterList, 272 k_DPRRegisterList, 273 k_SPRRegisterList, 274 k_VectorList, 275 k_ShiftedRegister, 276 k_ShiftedImmediate, 277 k_ShifterImmediate, 278 k_RotateImmediate, 279 k_BitfieldDescriptor, 280 k_Token 281 } Kind; 282 283 SMLoc StartLoc, EndLoc; 284 SmallVector<unsigned, 8> Registers; 285 286 union { 287 struct { 288 ARMCC::CondCodes Val; 289 } CC; 290 291 struct { 292 unsigned Val; 293 } Cop; 294 295 struct { 296 unsigned Val; 297 } CoprocOption; 298 299 struct { 300 unsigned Mask:4; 301 } ITMask; 302 303 struct { 304 ARM_MB::MemBOpt Val; 305 } MBOpt; 306 307 struct { 308 ARM_PROC::IFlags Val; 309 } IFlags; 310 311 struct { 312 unsigned Val; 313 } MMask; 314 315 struct { 316 const char *Data; 317 unsigned Length; 318 } Tok; 319 320 struct { 321 unsigned RegNum; 322 } Reg; 323 324 // A vector register list is a sequential list of 1 to 4 registers. 325 struct { 326 unsigned RegNum; 327 unsigned Count; 328 } VectorList; 329 330 struct { 331 unsigned Val; 332 } VectorIndex; 333 334 struct { 335 const MCExpr *Val; 336 } Imm; 337 338 struct { 339 unsigned Val; // encoded 8-bit representation 340 } FPImm; 341 342 /// Combined record for all forms of ARM address expressions. 343 struct { 344 unsigned BaseRegNum; 345 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset 346 // was specified. 347 const MCConstantExpr *OffsetImm; // Offset immediate value 348 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL 349 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg 350 unsigned ShiftImm; // shift for OffsetReg. 351 unsigned Alignment; // 0 = no alignment specified 352 // n = alignment in bytes (8, 16, or 32) 353 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit) 354 } Memory; 355 356 struct { 357 unsigned RegNum; 358 bool isAdd; 359 ARM_AM::ShiftOpc ShiftTy; 360 unsigned ShiftImm; 361 } PostIdxReg; 362 363 struct { 364 bool isASR; 365 unsigned Imm; 366 } ShifterImm; 367 struct { 368 ARM_AM::ShiftOpc ShiftTy; 369 unsigned SrcReg; 370 unsigned ShiftReg; 371 unsigned ShiftImm; 372 } RegShiftedReg; 373 struct { 374 ARM_AM::ShiftOpc ShiftTy; 375 unsigned SrcReg; 376 unsigned ShiftImm; 377 } RegShiftedImm; 378 struct { 379 unsigned Imm; 380 } RotImm; 381 struct { 382 unsigned LSB; 383 unsigned Width; 384 } Bitfield; 385 }; 386 387 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 388public: 389 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() { 390 Kind = o.Kind; 391 StartLoc = o.StartLoc; 392 EndLoc = o.EndLoc; 393 switch (Kind) { 394 case k_CondCode: 395 CC = o.CC; 396 break; 397 case k_ITCondMask: 398 ITMask = o.ITMask; 399 break; 400 case k_Token: 401 Tok = o.Tok; 402 break; 403 case k_CCOut: 404 case k_Register: 405 Reg = o.Reg; 406 break; 407 case k_RegisterList: 408 case k_DPRRegisterList: 409 case k_SPRRegisterList: 410 Registers = o.Registers; 411 break; 412 case k_VectorList: 413 VectorList = o.VectorList; 414 break; 415 case k_CoprocNum: 416 case k_CoprocReg: 417 Cop = o.Cop; 418 break; 419 case k_CoprocOption: 420 CoprocOption = o.CoprocOption; 421 break; 422 case k_Immediate: 423 Imm = o.Imm; 424 break; 425 case k_FPImmediate: 426 FPImm = o.FPImm; 427 break; 428 case k_MemBarrierOpt: 429 MBOpt = o.MBOpt; 430 break; 431 case k_Memory: 432 Memory = o.Memory; 433 break; 434 case k_PostIndexRegister: 435 PostIdxReg = o.PostIdxReg; 436 break; 437 case k_MSRMask: 438 MMask = o.MMask; 439 break; 440 case k_ProcIFlags: 441 IFlags = o.IFlags; 442 break; 443 case k_ShifterImmediate: 444 ShifterImm = o.ShifterImm; 445 break; 446 case k_ShiftedRegister: 447 RegShiftedReg = o.RegShiftedReg; 448 break; 449 case k_ShiftedImmediate: 450 RegShiftedImm = o.RegShiftedImm; 451 break; 452 case k_RotateImmediate: 453 RotImm = o.RotImm; 454 break; 455 case k_BitfieldDescriptor: 456 Bitfield = o.Bitfield; 457 break; 458 case k_VectorIndex: 459 VectorIndex = o.VectorIndex; 460 break; 461 } 462 } 463 464 /// getStartLoc - Get the location of the first token of this operand. 465 SMLoc getStartLoc() const { return StartLoc; } 466 /// getEndLoc - Get the location of the last token of this operand. 467 SMLoc getEndLoc() const { return EndLoc; } 468 469 ARMCC::CondCodes getCondCode() const { 470 assert(Kind == k_CondCode && "Invalid access!"); 471 return CC.Val; 472 } 473 474 unsigned getCoproc() const { 475 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!"); 476 return Cop.Val; 477 } 478 479 StringRef getToken() const { 480 assert(Kind == k_Token && "Invalid access!"); 481 return StringRef(Tok.Data, Tok.Length); 482 } 483 484 unsigned getReg() const { 485 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!"); 486 return Reg.RegNum; 487 } 488 489 const SmallVectorImpl<unsigned> &getRegList() const { 490 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList || 491 Kind == k_SPRRegisterList) && "Invalid access!"); 492 return Registers; 493 } 494 495 const MCExpr *getImm() const { 496 assert(Kind == k_Immediate && "Invalid access!"); 497 return Imm.Val; 498 } 499 500 unsigned getFPImm() const { 501 assert(Kind == k_FPImmediate && "Invalid access!"); 502 return FPImm.Val; 503 } 504 505 unsigned getVectorIndex() const { 506 assert(Kind == k_VectorIndex && "Invalid access!"); 507 return VectorIndex.Val; 508 } 509 510 ARM_MB::MemBOpt getMemBarrierOpt() const { 511 assert(Kind == k_MemBarrierOpt && "Invalid access!"); 512 return MBOpt.Val; 513 } 514 515 ARM_PROC::IFlags getProcIFlags() const { 516 assert(Kind == k_ProcIFlags && "Invalid access!"); 517 return IFlags.Val; 518 } 519 520 unsigned getMSRMask() const { 521 assert(Kind == k_MSRMask && "Invalid access!"); 522 return MMask.Val; 523 } 524 525 bool isCoprocNum() const { return Kind == k_CoprocNum; } 526 bool isCoprocReg() const { return Kind == k_CoprocReg; } 527 bool isCoprocOption() const { return Kind == k_CoprocOption; } 528 bool isCondCode() const { return Kind == k_CondCode; } 529 bool isCCOut() const { return Kind == k_CCOut; } 530 bool isITMask() const { return Kind == k_ITCondMask; } 531 bool isITCondCode() const { return Kind == k_CondCode; } 532 bool isImm() const { return Kind == k_Immediate; } 533 bool isFPImm() const { return Kind == k_FPImmediate; } 534 bool isImm8s4() const { 535 if (Kind != k_Immediate) 536 return false; 537 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 538 if (!CE) return false; 539 int64_t Value = CE->getValue(); 540 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020; 541 } 542 bool isImm0_1020s4() const { 543 if (Kind != k_Immediate) 544 return false; 545 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 546 if (!CE) return false; 547 int64_t Value = CE->getValue(); 548 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020; 549 } 550 bool isImm0_508s4() const { 551 if (Kind != k_Immediate) 552 return false; 553 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 554 if (!CE) return false; 555 int64_t Value = CE->getValue(); 556 return ((Value & 3) == 0) && Value >= 0 && Value <= 508; 557 } 558 bool isImm0_255() const { 559 if (Kind != k_Immediate) 560 return false; 561 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 562 if (!CE) return false; 563 int64_t Value = CE->getValue(); 564 return Value >= 0 && Value < 256; 565 } 566 bool isImm0_7() const { 567 if (Kind != k_Immediate) 568 return false; 569 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 570 if (!CE) return false; 571 int64_t Value = CE->getValue(); 572 return Value >= 0 && Value < 8; 573 } 574 bool isImm0_15() const { 575 if (Kind != k_Immediate) 576 return false; 577 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 578 if (!CE) return false; 579 int64_t Value = CE->getValue(); 580 return Value >= 0 && Value < 16; 581 } 582 bool isImm0_31() const { 583 if (Kind != k_Immediate) 584 return false; 585 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 586 if (!CE) return false; 587 int64_t Value = CE->getValue(); 588 return Value >= 0 && Value < 32; 589 } 590 bool isImm1_16() const { 591 if (Kind != k_Immediate) 592 return false; 593 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 594 if (!CE) return false; 595 int64_t Value = CE->getValue(); 596 return Value > 0 && Value < 17; 597 } 598 bool isImm1_32() const { 599 if (Kind != k_Immediate) 600 return false; 601 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 602 if (!CE) return false; 603 int64_t Value = CE->getValue(); 604 return Value > 0 && Value < 33; 605 } 606 bool isImm0_65535() const { 607 if (Kind != k_Immediate) 608 return false; 609 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 610 if (!CE) return false; 611 int64_t Value = CE->getValue(); 612 return Value >= 0 && Value < 65536; 613 } 614 bool isImm0_65535Expr() const { 615 if (Kind != k_Immediate) 616 return false; 617 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 618 // If it's not a constant expression, it'll generate a fixup and be 619 // handled later. 620 if (!CE) return true; 621 int64_t Value = CE->getValue(); 622 return Value >= 0 && Value < 65536; 623 } 624 bool isImm24bit() const { 625 if (Kind != k_Immediate) 626 return false; 627 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 628 if (!CE) return false; 629 int64_t Value = CE->getValue(); 630 return Value >= 0 && Value <= 0xffffff; 631 } 632 bool isImmThumbSR() const { 633 if (Kind != k_Immediate) 634 return false; 635 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 636 if (!CE) return false; 637 int64_t Value = CE->getValue(); 638 return Value > 0 && Value < 33; 639 } 640 bool isPKHLSLImm() const { 641 if (Kind != k_Immediate) 642 return false; 643 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 644 if (!CE) return false; 645 int64_t Value = CE->getValue(); 646 return Value >= 0 && Value < 32; 647 } 648 bool isPKHASRImm() const { 649 if (Kind != k_Immediate) 650 return false; 651 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 652 if (!CE) return false; 653 int64_t Value = CE->getValue(); 654 return Value > 0 && Value <= 32; 655 } 656 bool isARMSOImm() const { 657 if (Kind != k_Immediate) 658 return false; 659 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 660 if (!CE) return false; 661 int64_t Value = CE->getValue(); 662 return ARM_AM::getSOImmVal(Value) != -1; 663 } 664 bool isARMSOImmNot() const { 665 if (Kind != k_Immediate) 666 return false; 667 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 668 if (!CE) return false; 669 int64_t Value = CE->getValue(); 670 return ARM_AM::getSOImmVal(~Value) != -1; 671 } 672 bool isT2SOImm() const { 673 if (Kind != k_Immediate) 674 return false; 675 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 676 if (!CE) return false; 677 int64_t Value = CE->getValue(); 678 return ARM_AM::getT2SOImmVal(Value) != -1; 679 } 680 bool isT2SOImmNot() const { 681 if (Kind != k_Immediate) 682 return false; 683 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 684 if (!CE) return false; 685 int64_t Value = CE->getValue(); 686 return ARM_AM::getT2SOImmVal(~Value) != -1; 687 } 688 bool isSetEndImm() const { 689 if (Kind != k_Immediate) 690 return false; 691 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 692 if (!CE) return false; 693 int64_t Value = CE->getValue(); 694 return Value == 1 || Value == 0; 695 } 696 bool isReg() const { return Kind == k_Register; } 697 bool isRegList() const { return Kind == k_RegisterList; } 698 bool isDPRRegList() const { return Kind == k_DPRRegisterList; } 699 bool isSPRRegList() const { return Kind == k_SPRRegisterList; } 700 bool isToken() const { return Kind == k_Token; } 701 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; } 702 bool isMemory() const { return Kind == k_Memory; } 703 bool isShifterImm() const { return Kind == k_ShifterImmediate; } 704 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; } 705 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; } 706 bool isRotImm() const { return Kind == k_RotateImmediate; } 707 bool isBitfield() const { return Kind == k_BitfieldDescriptor; } 708 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; } 709 bool isPostIdxReg() const { 710 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift; 711 } 712 bool isMemNoOffset(bool alignOK = false) const { 713 if (!isMemory()) 714 return false; 715 // No offset of any kind. 716 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 && 717 (alignOK || Memory.Alignment == 0); 718 } 719 bool isAlignedMemory() const { 720 return isMemNoOffset(true); 721 } 722 bool isAddrMode2() const { 723 if (!isMemory() || Memory.Alignment != 0) return false; 724 // Check for register offset. 725 if (Memory.OffsetRegNum) return true; 726 // Immediate offset in range [-4095, 4095]. 727 if (!Memory.OffsetImm) return true; 728 int64_t Val = Memory.OffsetImm->getValue(); 729 return Val > -4096 && Val < 4096; 730 } 731 bool isAM2OffsetImm() const { 732 if (Kind != k_Immediate) 733 return false; 734 // Immediate offset in range [-4095, 4095]. 735 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 736 if (!CE) return false; 737 int64_t Val = CE->getValue(); 738 return Val > -4096 && Val < 4096; 739 } 740 bool isAddrMode3() const { 741 if (!isMemory() || Memory.Alignment != 0) return false; 742 // No shifts are legal for AM3. 743 if (Memory.ShiftType != ARM_AM::no_shift) return false; 744 // Check for register offset. 745 if (Memory.OffsetRegNum) return true; 746 // Immediate offset in range [-255, 255]. 747 if (!Memory.OffsetImm) return true; 748 int64_t Val = Memory.OffsetImm->getValue(); 749 return Val > -256 && Val < 256; 750 } 751 bool isAM3Offset() const { 752 if (Kind != k_Immediate && Kind != k_PostIndexRegister) 753 return false; 754 if (Kind == k_PostIndexRegister) 755 return PostIdxReg.ShiftTy == ARM_AM::no_shift; 756 // Immediate offset in range [-255, 255]. 757 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 758 if (!CE) return false; 759 int64_t Val = CE->getValue(); 760 // Special case, #-0 is INT32_MIN. 761 return (Val > -256 && Val < 256) || Val == INT32_MIN; 762 } 763 bool isAddrMode5() const { 764 // If we have an immediate that's not a constant, treat it as a label 765 // reference needing a fixup. If it is a constant, it's something else 766 // and we reject it. 767 if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm())) 768 return true; 769 if (!isMemory() || Memory.Alignment != 0) return false; 770 // Check for register offset. 771 if (Memory.OffsetRegNum) return false; 772 // Immediate offset in range [-1020, 1020] and a multiple of 4. 773 if (!Memory.OffsetImm) return true; 774 int64_t Val = Memory.OffsetImm->getValue(); 775 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) || 776 Val == INT32_MIN; 777 } 778 bool isMemTBB() const { 779 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 780 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 781 return false; 782 return true; 783 } 784 bool isMemTBH() const { 785 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 786 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || 787 Memory.Alignment != 0 ) 788 return false; 789 return true; 790 } 791 bool isMemRegOffset() const { 792 if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0) 793 return false; 794 return true; 795 } 796 bool isT2MemRegOffset() const { 797 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 798 Memory.Alignment != 0) 799 return false; 800 // Only lsl #{0, 1, 2, 3} allowed. 801 if (Memory.ShiftType == ARM_AM::no_shift) 802 return true; 803 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) 804 return false; 805 return true; 806 } 807 bool isMemThumbRR() const { 808 // Thumb reg+reg addressing is simple. Just two registers, a base and 809 // an offset. No shifts, negations or any other complicating factors. 810 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 811 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 812 return false; 813 return isARMLowRegister(Memory.BaseRegNum) && 814 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); 815 } 816 bool isMemThumbRIs4() const { 817 if (!isMemory() || Memory.OffsetRegNum != 0 || 818 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 819 return false; 820 // Immediate offset, multiple of 4 in range [0, 124]. 821 if (!Memory.OffsetImm) return true; 822 int64_t Val = Memory.OffsetImm->getValue(); 823 return Val >= 0 && Val <= 124 && (Val % 4) == 0; 824 } 825 bool isMemThumbRIs2() const { 826 if (!isMemory() || Memory.OffsetRegNum != 0 || 827 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 828 return false; 829 // Immediate offset, multiple of 4 in range [0, 62]. 830 if (!Memory.OffsetImm) return true; 831 int64_t Val = Memory.OffsetImm->getValue(); 832 return Val >= 0 && Val <= 62 && (Val % 2) == 0; 833 } 834 bool isMemThumbRIs1() const { 835 if (!isMemory() || Memory.OffsetRegNum != 0 || 836 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 837 return false; 838 // Immediate offset in range [0, 31]. 839 if (!Memory.OffsetImm) return true; 840 int64_t Val = Memory.OffsetImm->getValue(); 841 return Val >= 0 && Val <= 31; 842 } 843 bool isMemThumbSPI() const { 844 if (!isMemory() || Memory.OffsetRegNum != 0 || 845 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) 846 return false; 847 // Immediate offset, multiple of 4 in range [0, 1020]. 848 if (!Memory.OffsetImm) return true; 849 int64_t Val = Memory.OffsetImm->getValue(); 850 return Val >= 0 && Val <= 1020 && (Val % 4) == 0; 851 } 852 bool isMemImm8s4Offset() const { 853 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 854 return false; 855 // Immediate offset a multiple of 4 in range [-1020, 1020]. 856 if (!Memory.OffsetImm) return true; 857 int64_t Val = Memory.OffsetImm->getValue(); 858 return Val >= -1020 && Val <= 1020 && (Val & 3) == 0; 859 } 860 bool isMemImm0_1020s4Offset() const { 861 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 862 return false; 863 // Immediate offset a multiple of 4 in range [0, 1020]. 864 if (!Memory.OffsetImm) return true; 865 int64_t Val = Memory.OffsetImm->getValue(); 866 return Val >= 0 && Val <= 1020 && (Val & 3) == 0; 867 } 868 bool isMemImm8Offset() const { 869 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 870 return false; 871 // Immediate offset in range [-255, 255]. 872 if (!Memory.OffsetImm) return true; 873 int64_t Val = Memory.OffsetImm->getValue(); 874 return (Val == INT32_MIN) || (Val > -256 && Val < 256); 875 } 876 bool isMemPosImm8Offset() const { 877 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 878 return false; 879 // Immediate offset in range [0, 255]. 880 if (!Memory.OffsetImm) return true; 881 int64_t Val = Memory.OffsetImm->getValue(); 882 return Val >= 0 && Val < 256; 883 } 884 bool isMemNegImm8Offset() const { 885 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 886 return false; 887 // Immediate offset in range [-255, -1]. 888 if (!Memory.OffsetImm) return true; 889 int64_t Val = Memory.OffsetImm->getValue(); 890 return Val > -256 && Val < 0; 891 } 892 bool isMemUImm12Offset() const { 893 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 894 return false; 895 // Immediate offset in range [0, 4095]. 896 if (!Memory.OffsetImm) return true; 897 int64_t Val = Memory.OffsetImm->getValue(); 898 return (Val >= 0 && Val < 4096); 899 } 900 bool isMemImm12Offset() const { 901 // If we have an immediate that's not a constant, treat it as a label 902 // reference needing a fixup. If it is a constant, it's something else 903 // and we reject it. 904 if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm())) 905 return true; 906 907 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 908 return false; 909 // Immediate offset in range [-4095, 4095]. 910 if (!Memory.OffsetImm) return true; 911 int64_t Val = Memory.OffsetImm->getValue(); 912 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 913 } 914 bool isPostIdxImm8() const { 915 if (Kind != k_Immediate) 916 return false; 917 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 918 if (!CE) return false; 919 int64_t Val = CE->getValue(); 920 return (Val > -256 && Val < 256) || (Val == INT32_MIN); 921 } 922 bool isPostIdxImm8s4() const { 923 if (Kind != k_Immediate) 924 return false; 925 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 926 if (!CE) return false; 927 int64_t Val = CE->getValue(); 928 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) || 929 (Val == INT32_MIN); 930 } 931 932 bool isMSRMask() const { return Kind == k_MSRMask; } 933 bool isProcIFlags() const { return Kind == k_ProcIFlags; } 934 935 // NEON operands. 936 bool isVecListOneD() const { 937 if (Kind != k_VectorList) return false; 938 return VectorList.Count == 1; 939 } 940 941 bool isVecListTwoD() const { 942 if (Kind != k_VectorList) return false; 943 return VectorList.Count == 2; 944 } 945 946 bool isVecListThreeD() const { 947 if (Kind != k_VectorList) return false; 948 return VectorList.Count == 3; 949 } 950 951 bool isVecListFourD() const { 952 if (Kind != k_VectorList) return false; 953 return VectorList.Count == 4; 954 } 955 956 bool isVecListTwoQ() const { 957 if (Kind != k_VectorList) return false; 958 //FIXME: We haven't taught the parser to handle by-two register lists 959 // yet, so don't pretend to know one. 960 return VectorList.Count == 2 && false; 961 } 962 963 bool isVectorIndex8() const { 964 if (Kind != k_VectorIndex) return false; 965 return VectorIndex.Val < 8; 966 } 967 bool isVectorIndex16() const { 968 if (Kind != k_VectorIndex) return false; 969 return VectorIndex.Val < 4; 970 } 971 bool isVectorIndex32() const { 972 if (Kind != k_VectorIndex) return false; 973 return VectorIndex.Val < 2; 974 } 975 976 bool isNEONi8splat() const { 977 if (Kind != k_Immediate) 978 return false; 979 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 980 // Must be a constant. 981 if (!CE) return false; 982 int64_t Value = CE->getValue(); 983 // i8 value splatted across 8 bytes. The immediate is just the 8 byte 984 // value. 985 return Value >= 0 && Value < 256; 986 } 987 988 bool isNEONi16splat() const { 989 if (Kind != k_Immediate) 990 return false; 991 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 992 // Must be a constant. 993 if (!CE) return false; 994 int64_t Value = CE->getValue(); 995 // i16 value in the range [0,255] or [0x0100, 0xff00] 996 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00); 997 } 998 999 bool isNEONi32splat() const { 1000 if (Kind != k_Immediate) 1001 return false; 1002 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1003 // Must be a constant. 1004 if (!CE) return false; 1005 int64_t Value = CE->getValue(); 1006 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X. 1007 return (Value >= 0 && Value < 256) || 1008 (Value >= 0x0100 && Value <= 0xff00) || 1009 (Value >= 0x010000 && Value <= 0xff0000) || 1010 (Value >= 0x01000000 && Value <= 0xff000000); 1011 } 1012 1013 bool isNEONi32vmov() const { 1014 if (Kind != k_Immediate) 1015 return false; 1016 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1017 // Must be a constant. 1018 if (!CE) return false; 1019 int64_t Value = CE->getValue(); 1020 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1021 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1022 return (Value >= 0 && Value < 256) || 1023 (Value >= 0x0100 && Value <= 0xff00) || 1024 (Value >= 0x010000 && Value <= 0xff0000) || 1025 (Value >= 0x01000000 && Value <= 0xff000000) || 1026 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1027 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1028 } 1029 1030 bool isNEONi64splat() const { 1031 if (Kind != k_Immediate) 1032 return false; 1033 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1034 // Must be a constant. 1035 if (!CE) return false; 1036 uint64_t Value = CE->getValue(); 1037 // i64 value with each byte being either 0 or 0xff. 1038 for (unsigned i = 0; i < 8; ++i) 1039 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false; 1040 return true; 1041 } 1042 1043 void addExpr(MCInst &Inst, const MCExpr *Expr) const { 1044 // Add as immediates when possible. Null MCExpr = 0. 1045 if (Expr == 0) 1046 Inst.addOperand(MCOperand::CreateImm(0)); 1047 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) 1048 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1049 else 1050 Inst.addOperand(MCOperand::CreateExpr(Expr)); 1051 } 1052 1053 void addCondCodeOperands(MCInst &Inst, unsigned N) const { 1054 assert(N == 2 && "Invalid number of operands!"); 1055 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 1056 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; 1057 Inst.addOperand(MCOperand::CreateReg(RegNum)); 1058 } 1059 1060 void addCoprocNumOperands(MCInst &Inst, unsigned N) const { 1061 assert(N == 1 && "Invalid number of operands!"); 1062 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1063 } 1064 1065 void addCoprocRegOperands(MCInst &Inst, unsigned N) const { 1066 assert(N == 1 && "Invalid number of operands!"); 1067 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1068 } 1069 1070 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const { 1071 assert(N == 1 && "Invalid number of operands!"); 1072 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val)); 1073 } 1074 1075 void addITMaskOperands(MCInst &Inst, unsigned N) const { 1076 assert(N == 1 && "Invalid number of operands!"); 1077 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask)); 1078 } 1079 1080 void addITCondCodeOperands(MCInst &Inst, unsigned N) const { 1081 assert(N == 1 && "Invalid number of operands!"); 1082 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 1083 } 1084 1085 void addCCOutOperands(MCInst &Inst, unsigned N) const { 1086 assert(N == 1 && "Invalid number of operands!"); 1087 Inst.addOperand(MCOperand::CreateReg(getReg())); 1088 } 1089 1090 void addRegOperands(MCInst &Inst, unsigned N) const { 1091 assert(N == 1 && "Invalid number of operands!"); 1092 Inst.addOperand(MCOperand::CreateReg(getReg())); 1093 } 1094 1095 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { 1096 assert(N == 3 && "Invalid number of operands!"); 1097 assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!"); 1098 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); 1099 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); 1100 Inst.addOperand(MCOperand::CreateImm( 1101 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); 1102 } 1103 1104 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { 1105 assert(N == 2 && "Invalid number of operands!"); 1106 assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!"); 1107 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); 1108 Inst.addOperand(MCOperand::CreateImm( 1109 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm))); 1110 } 1111 1112 void addShifterImmOperands(MCInst &Inst, unsigned N) const { 1113 assert(N == 1 && "Invalid number of operands!"); 1114 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) | 1115 ShifterImm.Imm)); 1116 } 1117 1118 void addRegListOperands(MCInst &Inst, unsigned N) const { 1119 assert(N == 1 && "Invalid number of operands!"); 1120 const SmallVectorImpl<unsigned> &RegList = getRegList(); 1121 for (SmallVectorImpl<unsigned>::const_iterator 1122 I = RegList.begin(), E = RegList.end(); I != E; ++I) 1123 Inst.addOperand(MCOperand::CreateReg(*I)); 1124 } 1125 1126 void addDPRRegListOperands(MCInst &Inst, unsigned N) const { 1127 addRegListOperands(Inst, N); 1128 } 1129 1130 void addSPRRegListOperands(MCInst &Inst, unsigned N) const { 1131 addRegListOperands(Inst, N); 1132 } 1133 1134 void addRotImmOperands(MCInst &Inst, unsigned N) const { 1135 assert(N == 1 && "Invalid number of operands!"); 1136 // Encoded as val>>3. The printer handles display as 8, 16, 24. 1137 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3)); 1138 } 1139 1140 void addBitfieldOperands(MCInst &Inst, unsigned N) const { 1141 assert(N == 1 && "Invalid number of operands!"); 1142 // Munge the lsb/width into a bitfield mask. 1143 unsigned lsb = Bitfield.LSB; 1144 unsigned width = Bitfield.Width; 1145 // Make a 32-bit mask w/ the referenced bits clear and all other bits set. 1146 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> 1147 (32 - (lsb + width))); 1148 Inst.addOperand(MCOperand::CreateImm(Mask)); 1149 } 1150 1151 void addImmOperands(MCInst &Inst, unsigned N) const { 1152 assert(N == 1 && "Invalid number of operands!"); 1153 addExpr(Inst, getImm()); 1154 } 1155 1156 void addFPImmOperands(MCInst &Inst, unsigned N) const { 1157 assert(N == 1 && "Invalid number of operands!"); 1158 Inst.addOperand(MCOperand::CreateImm(getFPImm())); 1159 } 1160 1161 void addImm8s4Operands(MCInst &Inst, unsigned N) const { 1162 assert(N == 1 && "Invalid number of operands!"); 1163 // FIXME: We really want to scale the value here, but the LDRD/STRD 1164 // instruction don't encode operands that way yet. 1165 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1166 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1167 } 1168 1169 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { 1170 assert(N == 1 && "Invalid number of operands!"); 1171 // The immediate is scaled by four in the encoding and is stored 1172 // in the MCInst as such. Lop off the low two bits here. 1173 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1174 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 1175 } 1176 1177 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { 1178 assert(N == 1 && "Invalid number of operands!"); 1179 // The immediate is scaled by four in the encoding and is stored 1180 // in the MCInst as such. Lop off the low two bits here. 1181 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1182 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 1183 } 1184 1185 void addImm0_255Operands(MCInst &Inst, unsigned N) const { 1186 assert(N == 1 && "Invalid number of operands!"); 1187 addExpr(Inst, getImm()); 1188 } 1189 1190 void addImm0_7Operands(MCInst &Inst, unsigned N) const { 1191 assert(N == 1 && "Invalid number of operands!"); 1192 addExpr(Inst, getImm()); 1193 } 1194 1195 void addImm0_15Operands(MCInst &Inst, unsigned N) const { 1196 assert(N == 1 && "Invalid number of operands!"); 1197 addExpr(Inst, getImm()); 1198 } 1199 1200 void addImm0_31Operands(MCInst &Inst, unsigned N) const { 1201 assert(N == 1 && "Invalid number of operands!"); 1202 addExpr(Inst, getImm()); 1203 } 1204 1205 void addImm1_16Operands(MCInst &Inst, unsigned N) const { 1206 assert(N == 1 && "Invalid number of operands!"); 1207 // The constant encodes as the immediate-1, and we store in the instruction 1208 // the bits as encoded, so subtract off one here. 1209 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1210 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1211 } 1212 1213 void addImm1_32Operands(MCInst &Inst, unsigned N) const { 1214 assert(N == 1 && "Invalid number of operands!"); 1215 // The constant encodes as the immediate-1, and we store in the instruction 1216 // the bits as encoded, so subtract off one here. 1217 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1218 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1219 } 1220 1221 void addImm0_65535Operands(MCInst &Inst, unsigned N) const { 1222 assert(N == 1 && "Invalid number of operands!"); 1223 addExpr(Inst, getImm()); 1224 } 1225 1226 void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const { 1227 assert(N == 1 && "Invalid number of operands!"); 1228 addExpr(Inst, getImm()); 1229 } 1230 1231 void addImm24bitOperands(MCInst &Inst, unsigned N) const { 1232 assert(N == 1 && "Invalid number of operands!"); 1233 addExpr(Inst, getImm()); 1234 } 1235 1236 void addImmThumbSROperands(MCInst &Inst, unsigned N) const { 1237 assert(N == 1 && "Invalid number of operands!"); 1238 // The constant encodes as the immediate, except for 32, which encodes as 1239 // zero. 1240 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1241 unsigned Imm = CE->getValue(); 1242 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm))); 1243 } 1244 1245 void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const { 1246 assert(N == 1 && "Invalid number of operands!"); 1247 addExpr(Inst, getImm()); 1248 } 1249 1250 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { 1251 assert(N == 1 && "Invalid number of operands!"); 1252 // An ASR value of 32 encodes as 0, so that's how we want to add it to 1253 // the instruction as well. 1254 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1255 int Val = CE->getValue(); 1256 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val)); 1257 } 1258 1259 void addARMSOImmOperands(MCInst &Inst, unsigned N) const { 1260 assert(N == 1 && "Invalid number of operands!"); 1261 addExpr(Inst, getImm()); 1262 } 1263 1264 void addT2SOImmOperands(MCInst &Inst, unsigned N) const { 1265 assert(N == 1 && "Invalid number of operands!"); 1266 addExpr(Inst, getImm()); 1267 } 1268 1269 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const { 1270 assert(N == 1 && "Invalid number of operands!"); 1271 // The operand is actually a t2_so_imm, but we have its bitwise 1272 // negation in the assembly source, so twiddle it here. 1273 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1274 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1275 } 1276 1277 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const { 1278 assert(N == 1 && "Invalid number of operands!"); 1279 // The operand is actually a so_imm, but we have its bitwise 1280 // negation in the assembly source, so twiddle it here. 1281 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1282 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1283 } 1284 1285 void addSetEndImmOperands(MCInst &Inst, unsigned N) const { 1286 assert(N == 1 && "Invalid number of operands!"); 1287 addExpr(Inst, getImm()); 1288 } 1289 1290 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { 1291 assert(N == 1 && "Invalid number of operands!"); 1292 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt()))); 1293 } 1294 1295 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { 1296 assert(N == 1 && "Invalid number of operands!"); 1297 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1298 } 1299 1300 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const { 1301 assert(N == 2 && "Invalid number of operands!"); 1302 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1303 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment)); 1304 } 1305 1306 void addAddrMode2Operands(MCInst &Inst, unsigned N) const { 1307 assert(N == 3 && "Invalid number of operands!"); 1308 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1309 if (!Memory.OffsetRegNum) { 1310 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1311 // Special case for #-0 1312 if (Val == INT32_MIN) Val = 0; 1313 if (Val < 0) Val = -Val; 1314 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1315 } else { 1316 // For register offset, we encode the shift type and negation flag 1317 // here. 1318 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 1319 Memory.ShiftImm, Memory.ShiftType); 1320 } 1321 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1322 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1323 Inst.addOperand(MCOperand::CreateImm(Val)); 1324 } 1325 1326 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { 1327 assert(N == 2 && "Invalid number of operands!"); 1328 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1329 assert(CE && "non-constant AM2OffsetImm operand!"); 1330 int32_t Val = CE->getValue(); 1331 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1332 // Special case for #-0 1333 if (Val == INT32_MIN) Val = 0; 1334 if (Val < 0) Val = -Val; 1335 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1336 Inst.addOperand(MCOperand::CreateReg(0)); 1337 Inst.addOperand(MCOperand::CreateImm(Val)); 1338 } 1339 1340 void addAddrMode3Operands(MCInst &Inst, unsigned N) const { 1341 assert(N == 3 && "Invalid number of operands!"); 1342 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1343 if (!Memory.OffsetRegNum) { 1344 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1345 // Special case for #-0 1346 if (Val == INT32_MIN) Val = 0; 1347 if (Val < 0) Val = -Val; 1348 Val = ARM_AM::getAM3Opc(AddSub, Val); 1349 } else { 1350 // For register offset, we encode the shift type and negation flag 1351 // here. 1352 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0); 1353 } 1354 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1355 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1356 Inst.addOperand(MCOperand::CreateImm(Val)); 1357 } 1358 1359 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { 1360 assert(N == 2 && "Invalid number of operands!"); 1361 if (Kind == k_PostIndexRegister) { 1362 int32_t Val = 1363 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); 1364 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1365 Inst.addOperand(MCOperand::CreateImm(Val)); 1366 return; 1367 } 1368 1369 // Constant offset. 1370 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm()); 1371 int32_t Val = CE->getValue(); 1372 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1373 // Special case for #-0 1374 if (Val == INT32_MIN) Val = 0; 1375 if (Val < 0) Val = -Val; 1376 Val = ARM_AM::getAM3Opc(AddSub, Val); 1377 Inst.addOperand(MCOperand::CreateReg(0)); 1378 Inst.addOperand(MCOperand::CreateImm(Val)); 1379 } 1380 1381 void addAddrMode5Operands(MCInst &Inst, unsigned N) const { 1382 assert(N == 2 && "Invalid number of operands!"); 1383 // If we have an immediate that's not a constant, treat it as a label 1384 // reference needing a fixup. If it is a constant, it's something else 1385 // and we reject it. 1386 if (isImm()) { 1387 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1388 Inst.addOperand(MCOperand::CreateImm(0)); 1389 return; 1390 } 1391 1392 // The lower two bits are always zero and as such are not encoded. 1393 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 1394 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1395 // Special case for #-0 1396 if (Val == INT32_MIN) Val = 0; 1397 if (Val < 0) Val = -Val; 1398 Val = ARM_AM::getAM5Opc(AddSub, Val); 1399 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1400 Inst.addOperand(MCOperand::CreateImm(Val)); 1401 } 1402 1403 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const { 1404 assert(N == 2 && "Invalid number of operands!"); 1405 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1406 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1407 Inst.addOperand(MCOperand::CreateImm(Val)); 1408 } 1409 1410 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const { 1411 assert(N == 2 && "Invalid number of operands!"); 1412 // The lower two bits are always zero and as such are not encoded. 1413 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 1414 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1415 Inst.addOperand(MCOperand::CreateImm(Val)); 1416 } 1417 1418 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1419 assert(N == 2 && "Invalid number of operands!"); 1420 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1421 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1422 Inst.addOperand(MCOperand::CreateImm(Val)); 1423 } 1424 1425 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1426 addMemImm8OffsetOperands(Inst, N); 1427 } 1428 1429 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1430 addMemImm8OffsetOperands(Inst, N); 1431 } 1432 1433 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { 1434 assert(N == 2 && "Invalid number of operands!"); 1435 // If this is an immediate, it's a label reference. 1436 if (Kind == k_Immediate) { 1437 addExpr(Inst, getImm()); 1438 Inst.addOperand(MCOperand::CreateImm(0)); 1439 return; 1440 } 1441 1442 // Otherwise, it's a normal memory reg+offset. 1443 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1444 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1445 Inst.addOperand(MCOperand::CreateImm(Val)); 1446 } 1447 1448 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { 1449 assert(N == 2 && "Invalid number of operands!"); 1450 // If this is an immediate, it's a label reference. 1451 if (Kind == k_Immediate) { 1452 addExpr(Inst, getImm()); 1453 Inst.addOperand(MCOperand::CreateImm(0)); 1454 return; 1455 } 1456 1457 // Otherwise, it's a normal memory reg+offset. 1458 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1459 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1460 Inst.addOperand(MCOperand::CreateImm(Val)); 1461 } 1462 1463 void addMemTBBOperands(MCInst &Inst, unsigned N) const { 1464 assert(N == 2 && "Invalid number of operands!"); 1465 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1466 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1467 } 1468 1469 void addMemTBHOperands(MCInst &Inst, unsigned N) const { 1470 assert(N == 2 && "Invalid number of operands!"); 1471 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1472 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1473 } 1474 1475 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { 1476 assert(N == 3 && "Invalid number of operands!"); 1477 unsigned Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 1478 Memory.ShiftImm, Memory.ShiftType); 1479 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1480 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1481 Inst.addOperand(MCOperand::CreateImm(Val)); 1482 } 1483 1484 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { 1485 assert(N == 3 && "Invalid number of operands!"); 1486 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1487 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1488 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm)); 1489 } 1490 1491 void addMemThumbRROperands(MCInst &Inst, unsigned N) const { 1492 assert(N == 2 && "Invalid number of operands!"); 1493 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1494 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1495 } 1496 1497 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const { 1498 assert(N == 2 && "Invalid number of operands!"); 1499 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 1500 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1501 Inst.addOperand(MCOperand::CreateImm(Val)); 1502 } 1503 1504 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const { 1505 assert(N == 2 && "Invalid number of operands!"); 1506 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0; 1507 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1508 Inst.addOperand(MCOperand::CreateImm(Val)); 1509 } 1510 1511 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { 1512 assert(N == 2 && "Invalid number of operands!"); 1513 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0; 1514 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1515 Inst.addOperand(MCOperand::CreateImm(Val)); 1516 } 1517 1518 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { 1519 assert(N == 2 && "Invalid number of operands!"); 1520 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 1521 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1522 Inst.addOperand(MCOperand::CreateImm(Val)); 1523 } 1524 1525 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { 1526 assert(N == 1 && "Invalid number of operands!"); 1527 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1528 assert(CE && "non-constant post-idx-imm8 operand!"); 1529 int Imm = CE->getValue(); 1530 bool isAdd = Imm >= 0; 1531 if (Imm == INT32_MIN) Imm = 0; 1532 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; 1533 Inst.addOperand(MCOperand::CreateImm(Imm)); 1534 } 1535 1536 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const { 1537 assert(N == 1 && "Invalid number of operands!"); 1538 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1539 assert(CE && "non-constant post-idx-imm8s4 operand!"); 1540 int Imm = CE->getValue(); 1541 bool isAdd = Imm >= 0; 1542 if (Imm == INT32_MIN) Imm = 0; 1543 // Immediate is scaled by 4. 1544 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; 1545 Inst.addOperand(MCOperand::CreateImm(Imm)); 1546 } 1547 1548 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { 1549 assert(N == 2 && "Invalid number of operands!"); 1550 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1551 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd)); 1552 } 1553 1554 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { 1555 assert(N == 2 && "Invalid number of operands!"); 1556 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1557 // The sign, shift type, and shift amount are encoded in a single operand 1558 // using the AM2 encoding helpers. 1559 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; 1560 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, 1561 PostIdxReg.ShiftTy); 1562 Inst.addOperand(MCOperand::CreateImm(Imm)); 1563 } 1564 1565 void addMSRMaskOperands(MCInst &Inst, unsigned N) const { 1566 assert(N == 1 && "Invalid number of operands!"); 1567 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask()))); 1568 } 1569 1570 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { 1571 assert(N == 1 && "Invalid number of operands!"); 1572 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags()))); 1573 } 1574 1575 void addVecListOneDOperands(MCInst &Inst, unsigned N) const { 1576 assert(N == 1 && "Invalid number of operands!"); 1577 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 1578 } 1579 1580 void addVecListTwoDOperands(MCInst &Inst, unsigned N) const { 1581 assert(N == 1 && "Invalid number of operands!"); 1582 // Only the first register actually goes on the instruction. The rest 1583 // are implied by the opcode. 1584 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 1585 } 1586 1587 void addVecListThreeDOperands(MCInst &Inst, unsigned N) const { 1588 assert(N == 1 && "Invalid number of operands!"); 1589 // Only the first register actually goes on the instruction. The rest 1590 // are implied by the opcode. 1591 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 1592 } 1593 1594 void addVecListFourDOperands(MCInst &Inst, unsigned N) const { 1595 assert(N == 1 && "Invalid number of operands!"); 1596 // Only the first register actually goes on the instruction. The rest 1597 // are implied by the opcode. 1598 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 1599 } 1600 1601 void addVecListTwoQOperands(MCInst &Inst, unsigned N) const { 1602 assert(N == 1 && "Invalid number of operands!"); 1603 // Only the first register actually goes on the instruction. The rest 1604 // are implied by the opcode. 1605 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 1606 } 1607 1608 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const { 1609 assert(N == 1 && "Invalid number of operands!"); 1610 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1611 } 1612 1613 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const { 1614 assert(N == 1 && "Invalid number of operands!"); 1615 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1616 } 1617 1618 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const { 1619 assert(N == 1 && "Invalid number of operands!"); 1620 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1621 } 1622 1623 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const { 1624 assert(N == 1 && "Invalid number of operands!"); 1625 // The immediate encodes the type of constant as well as the value. 1626 // Mask in that this is an i8 splat. 1627 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1628 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00)); 1629 } 1630 1631 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const { 1632 assert(N == 1 && "Invalid number of operands!"); 1633 // The immediate encodes the type of constant as well as the value. 1634 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1635 unsigned Value = CE->getValue(); 1636 if (Value >= 256) 1637 Value = (Value >> 8) | 0xa00; 1638 else 1639 Value |= 0x800; 1640 Inst.addOperand(MCOperand::CreateImm(Value)); 1641 } 1642 1643 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const { 1644 assert(N == 1 && "Invalid number of operands!"); 1645 // The immediate encodes the type of constant as well as the value. 1646 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1647 unsigned Value = CE->getValue(); 1648 if (Value >= 256 && Value <= 0xff00) 1649 Value = (Value >> 8) | 0x200; 1650 else if (Value > 0xffff && Value <= 0xff0000) 1651 Value = (Value >> 16) | 0x400; 1652 else if (Value > 0xffffff) 1653 Value = (Value >> 24) | 0x600; 1654 Inst.addOperand(MCOperand::CreateImm(Value)); 1655 } 1656 1657 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const { 1658 assert(N == 1 && "Invalid number of operands!"); 1659 // The immediate encodes the type of constant as well as the value. 1660 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1661 unsigned Value = CE->getValue(); 1662 if (Value >= 256 && Value <= 0xffff) 1663 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 1664 else if (Value > 0xffff && Value <= 0xffffff) 1665 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 1666 else if (Value > 0xffffff) 1667 Value = (Value >> 24) | 0x600; 1668 Inst.addOperand(MCOperand::CreateImm(Value)); 1669 } 1670 1671 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const { 1672 assert(N == 1 && "Invalid number of operands!"); 1673 // The immediate encodes the type of constant as well as the value. 1674 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1675 uint64_t Value = CE->getValue(); 1676 unsigned Imm = 0; 1677 for (unsigned i = 0; i < 8; ++i, Value >>= 8) { 1678 Imm |= (Value & 1) << i; 1679 } 1680 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00)); 1681 } 1682 1683 virtual void print(raw_ostream &OS) const; 1684 1685 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) { 1686 ARMOperand *Op = new ARMOperand(k_ITCondMask); 1687 Op->ITMask.Mask = Mask; 1688 Op->StartLoc = S; 1689 Op->EndLoc = S; 1690 return Op; 1691 } 1692 1693 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) { 1694 ARMOperand *Op = new ARMOperand(k_CondCode); 1695 Op->CC.Val = CC; 1696 Op->StartLoc = S; 1697 Op->EndLoc = S; 1698 return Op; 1699 } 1700 1701 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) { 1702 ARMOperand *Op = new ARMOperand(k_CoprocNum); 1703 Op->Cop.Val = CopVal; 1704 Op->StartLoc = S; 1705 Op->EndLoc = S; 1706 return Op; 1707 } 1708 1709 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) { 1710 ARMOperand *Op = new ARMOperand(k_CoprocReg); 1711 Op->Cop.Val = CopVal; 1712 Op->StartLoc = S; 1713 Op->EndLoc = S; 1714 return Op; 1715 } 1716 1717 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) { 1718 ARMOperand *Op = new ARMOperand(k_CoprocOption); 1719 Op->Cop.Val = Val; 1720 Op->StartLoc = S; 1721 Op->EndLoc = E; 1722 return Op; 1723 } 1724 1725 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) { 1726 ARMOperand *Op = new ARMOperand(k_CCOut); 1727 Op->Reg.RegNum = RegNum; 1728 Op->StartLoc = S; 1729 Op->EndLoc = S; 1730 return Op; 1731 } 1732 1733 static ARMOperand *CreateToken(StringRef Str, SMLoc S) { 1734 ARMOperand *Op = new ARMOperand(k_Token); 1735 Op->Tok.Data = Str.data(); 1736 Op->Tok.Length = Str.size(); 1737 Op->StartLoc = S; 1738 Op->EndLoc = S; 1739 return Op; 1740 } 1741 1742 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { 1743 ARMOperand *Op = new ARMOperand(k_Register); 1744 Op->Reg.RegNum = RegNum; 1745 Op->StartLoc = S; 1746 Op->EndLoc = E; 1747 return Op; 1748 } 1749 1750 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, 1751 unsigned SrcReg, 1752 unsigned ShiftReg, 1753 unsigned ShiftImm, 1754 SMLoc S, SMLoc E) { 1755 ARMOperand *Op = new ARMOperand(k_ShiftedRegister); 1756 Op->RegShiftedReg.ShiftTy = ShTy; 1757 Op->RegShiftedReg.SrcReg = SrcReg; 1758 Op->RegShiftedReg.ShiftReg = ShiftReg; 1759 Op->RegShiftedReg.ShiftImm = ShiftImm; 1760 Op->StartLoc = S; 1761 Op->EndLoc = E; 1762 return Op; 1763 } 1764 1765 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, 1766 unsigned SrcReg, 1767 unsigned ShiftImm, 1768 SMLoc S, SMLoc E) { 1769 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate); 1770 Op->RegShiftedImm.ShiftTy = ShTy; 1771 Op->RegShiftedImm.SrcReg = SrcReg; 1772 Op->RegShiftedImm.ShiftImm = ShiftImm; 1773 Op->StartLoc = S; 1774 Op->EndLoc = E; 1775 return Op; 1776 } 1777 1778 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm, 1779 SMLoc S, SMLoc E) { 1780 ARMOperand *Op = new ARMOperand(k_ShifterImmediate); 1781 Op->ShifterImm.isASR = isASR; 1782 Op->ShifterImm.Imm = Imm; 1783 Op->StartLoc = S; 1784 Op->EndLoc = E; 1785 return Op; 1786 } 1787 1788 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) { 1789 ARMOperand *Op = new ARMOperand(k_RotateImmediate); 1790 Op->RotImm.Imm = Imm; 1791 Op->StartLoc = S; 1792 Op->EndLoc = E; 1793 return Op; 1794 } 1795 1796 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width, 1797 SMLoc S, SMLoc E) { 1798 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor); 1799 Op->Bitfield.LSB = LSB; 1800 Op->Bitfield.Width = Width; 1801 Op->StartLoc = S; 1802 Op->EndLoc = E; 1803 return Op; 1804 } 1805 1806 static ARMOperand * 1807 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs, 1808 SMLoc StartLoc, SMLoc EndLoc) { 1809 KindTy Kind = k_RegisterList; 1810 1811 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first)) 1812 Kind = k_DPRRegisterList; 1813 else if (ARMMCRegisterClasses[ARM::SPRRegClassID]. 1814 contains(Regs.front().first)) 1815 Kind = k_SPRRegisterList; 1816 1817 ARMOperand *Op = new ARMOperand(Kind); 1818 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator 1819 I = Regs.begin(), E = Regs.end(); I != E; ++I) 1820 Op->Registers.push_back(I->first); 1821 array_pod_sort(Op->Registers.begin(), Op->Registers.end()); 1822 Op->StartLoc = StartLoc; 1823 Op->EndLoc = EndLoc; 1824 return Op; 1825 } 1826 1827 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count, 1828 SMLoc S, SMLoc E) { 1829 ARMOperand *Op = new ARMOperand(k_VectorList); 1830 Op->VectorList.RegNum = RegNum; 1831 Op->VectorList.Count = Count; 1832 Op->StartLoc = S; 1833 Op->EndLoc = E; 1834 return Op; 1835 } 1836 1837 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, 1838 MCContext &Ctx) { 1839 ARMOperand *Op = new ARMOperand(k_VectorIndex); 1840 Op->VectorIndex.Val = Idx; 1841 Op->StartLoc = S; 1842 Op->EndLoc = E; 1843 return Op; 1844 } 1845 1846 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { 1847 ARMOperand *Op = new ARMOperand(k_Immediate); 1848 Op->Imm.Val = Val; 1849 Op->StartLoc = S; 1850 Op->EndLoc = E; 1851 return Op; 1852 } 1853 1854 static ARMOperand *CreateFPImm(unsigned Val, SMLoc S, MCContext &Ctx) { 1855 ARMOperand *Op = new ARMOperand(k_FPImmediate); 1856 Op->FPImm.Val = Val; 1857 Op->StartLoc = S; 1858 Op->EndLoc = S; 1859 return Op; 1860 } 1861 1862 static ARMOperand *CreateMem(unsigned BaseRegNum, 1863 const MCConstantExpr *OffsetImm, 1864 unsigned OffsetRegNum, 1865 ARM_AM::ShiftOpc ShiftType, 1866 unsigned ShiftImm, 1867 unsigned Alignment, 1868 bool isNegative, 1869 SMLoc S, SMLoc E) { 1870 ARMOperand *Op = new ARMOperand(k_Memory); 1871 Op->Memory.BaseRegNum = BaseRegNum; 1872 Op->Memory.OffsetImm = OffsetImm; 1873 Op->Memory.OffsetRegNum = OffsetRegNum; 1874 Op->Memory.ShiftType = ShiftType; 1875 Op->Memory.ShiftImm = ShiftImm; 1876 Op->Memory.Alignment = Alignment; 1877 Op->Memory.isNegative = isNegative; 1878 Op->StartLoc = S; 1879 Op->EndLoc = E; 1880 return Op; 1881 } 1882 1883 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd, 1884 ARM_AM::ShiftOpc ShiftTy, 1885 unsigned ShiftImm, 1886 SMLoc S, SMLoc E) { 1887 ARMOperand *Op = new ARMOperand(k_PostIndexRegister); 1888 Op->PostIdxReg.RegNum = RegNum; 1889 Op->PostIdxReg.isAdd = isAdd; 1890 Op->PostIdxReg.ShiftTy = ShiftTy; 1891 Op->PostIdxReg.ShiftImm = ShiftImm; 1892 Op->StartLoc = S; 1893 Op->EndLoc = E; 1894 return Op; 1895 } 1896 1897 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) { 1898 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt); 1899 Op->MBOpt.Val = Opt; 1900 Op->StartLoc = S; 1901 Op->EndLoc = S; 1902 return Op; 1903 } 1904 1905 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) { 1906 ARMOperand *Op = new ARMOperand(k_ProcIFlags); 1907 Op->IFlags.Val = IFlags; 1908 Op->StartLoc = S; 1909 Op->EndLoc = S; 1910 return Op; 1911 } 1912 1913 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) { 1914 ARMOperand *Op = new ARMOperand(k_MSRMask); 1915 Op->MMask.Val = MMask; 1916 Op->StartLoc = S; 1917 Op->EndLoc = S; 1918 return Op; 1919 } 1920}; 1921 1922} // end anonymous namespace. 1923 1924void ARMOperand::print(raw_ostream &OS) const { 1925 switch (Kind) { 1926 case k_FPImmediate: 1927 OS << "<fpimm " << getFPImm() << "(" << ARM_AM::getFPImmFloat(getFPImm()) 1928 << ") >"; 1929 break; 1930 case k_CondCode: 1931 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; 1932 break; 1933 case k_CCOut: 1934 OS << "<ccout " << getReg() << ">"; 1935 break; 1936 case k_ITCondMask: { 1937 static const char *MaskStr[] = { 1938 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)", 1939 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)" 1940 }; 1941 assert((ITMask.Mask & 0xf) == ITMask.Mask); 1942 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">"; 1943 break; 1944 } 1945 case k_CoprocNum: 1946 OS << "<coprocessor number: " << getCoproc() << ">"; 1947 break; 1948 case k_CoprocReg: 1949 OS << "<coprocessor register: " << getCoproc() << ">"; 1950 break; 1951 case k_CoprocOption: 1952 OS << "<coprocessor option: " << CoprocOption.Val << ">"; 1953 break; 1954 case k_MSRMask: 1955 OS << "<mask: " << getMSRMask() << ">"; 1956 break; 1957 case k_Immediate: 1958 getImm()->print(OS); 1959 break; 1960 case k_MemBarrierOpt: 1961 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">"; 1962 break; 1963 case k_Memory: 1964 OS << "<memory " 1965 << " base:" << Memory.BaseRegNum; 1966 OS << ">"; 1967 break; 1968 case k_PostIndexRegister: 1969 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") 1970 << PostIdxReg.RegNum; 1971 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) 1972 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " 1973 << PostIdxReg.ShiftImm; 1974 OS << ">"; 1975 break; 1976 case k_ProcIFlags: { 1977 OS << "<ARM_PROC::"; 1978 unsigned IFlags = getProcIFlags(); 1979 for (int i=2; i >= 0; --i) 1980 if (IFlags & (1 << i)) 1981 OS << ARM_PROC::IFlagsToString(1 << i); 1982 OS << ">"; 1983 break; 1984 } 1985 case k_Register: 1986 OS << "<register " << getReg() << ">"; 1987 break; 1988 case k_ShifterImmediate: 1989 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl") 1990 << " #" << ShifterImm.Imm << ">"; 1991 break; 1992 case k_ShiftedRegister: 1993 OS << "<so_reg_reg " 1994 << RegShiftedReg.SrcReg 1995 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm)) 1996 << ", " << RegShiftedReg.ShiftReg << ", " 1997 << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm) 1998 << ">"; 1999 break; 2000 case k_ShiftedImmediate: 2001 OS << "<so_reg_imm " 2002 << RegShiftedImm.SrcReg 2003 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm)) 2004 << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm) 2005 << ">"; 2006 break; 2007 case k_RotateImmediate: 2008 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">"; 2009 break; 2010 case k_BitfieldDescriptor: 2011 OS << "<bitfield " << "lsb: " << Bitfield.LSB 2012 << ", width: " << Bitfield.Width << ">"; 2013 break; 2014 case k_RegisterList: 2015 case k_DPRRegisterList: 2016 case k_SPRRegisterList: { 2017 OS << "<register_list "; 2018 2019 const SmallVectorImpl<unsigned> &RegList = getRegList(); 2020 for (SmallVectorImpl<unsigned>::const_iterator 2021 I = RegList.begin(), E = RegList.end(); I != E; ) { 2022 OS << *I; 2023 if (++I < E) OS << ", "; 2024 } 2025 2026 OS << ">"; 2027 break; 2028 } 2029 case k_VectorList: 2030 OS << "<vector_list " << VectorList.Count << " * " 2031 << VectorList.RegNum << ">"; 2032 break; 2033 case k_Token: 2034 OS << "'" << getToken() << "'"; 2035 break; 2036 case k_VectorIndex: 2037 OS << "<vectorindex " << getVectorIndex() << ">"; 2038 break; 2039 } 2040} 2041 2042/// @name Auto-generated Match Functions 2043/// { 2044 2045static unsigned MatchRegisterName(StringRef Name); 2046 2047/// } 2048 2049bool ARMAsmParser::ParseRegister(unsigned &RegNo, 2050 SMLoc &StartLoc, SMLoc &EndLoc) { 2051 RegNo = tryParseRegister(); 2052 2053 return (RegNo == (unsigned)-1); 2054} 2055 2056/// Try to parse a register name. The token must be an Identifier when called, 2057/// and if it is a register name the token is eaten and the register number is 2058/// returned. Otherwise return -1. 2059/// 2060int ARMAsmParser::tryParseRegister() { 2061 const AsmToken &Tok = Parser.getTok(); 2062 if (Tok.isNot(AsmToken::Identifier)) return -1; 2063 2064 // FIXME: Validate register for the current architecture; we have to do 2065 // validation later, so maybe there is no need for this here. 2066 std::string upperCase = Tok.getString().str(); 2067 std::string lowerCase = LowercaseString(upperCase); 2068 unsigned RegNum = MatchRegisterName(lowerCase); 2069 if (!RegNum) { 2070 RegNum = StringSwitch<unsigned>(lowerCase) 2071 .Case("r13", ARM::SP) 2072 .Case("r14", ARM::LR) 2073 .Case("r15", ARM::PC) 2074 .Case("ip", ARM::R12) 2075 .Default(0); 2076 } 2077 if (!RegNum) return -1; 2078 2079 Parser.Lex(); // Eat identifier token. 2080 2081 return RegNum; 2082} 2083 2084// Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. 2085// If a recoverable error occurs, return 1. If an irrecoverable error 2086// occurs, return -1. An irrecoverable error is one where tokens have been 2087// consumed in the process of trying to parse the shifter (i.e., when it is 2088// indeed a shifter operand, but malformed). 2089int ARMAsmParser::tryParseShiftRegister( 2090 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2091 SMLoc S = Parser.getTok().getLoc(); 2092 const AsmToken &Tok = Parser.getTok(); 2093 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 2094 2095 std::string upperCase = Tok.getString().str(); 2096 std::string lowerCase = LowercaseString(upperCase); 2097 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) 2098 .Case("lsl", ARM_AM::lsl) 2099 .Case("lsr", ARM_AM::lsr) 2100 .Case("asr", ARM_AM::asr) 2101 .Case("ror", ARM_AM::ror) 2102 .Case("rrx", ARM_AM::rrx) 2103 .Default(ARM_AM::no_shift); 2104 2105 if (ShiftTy == ARM_AM::no_shift) 2106 return 1; 2107 2108 Parser.Lex(); // Eat the operator. 2109 2110 // The source register for the shift has already been added to the 2111 // operand list, so we need to pop it off and combine it into the shifted 2112 // register operand instead. 2113 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val()); 2114 if (!PrevOp->isReg()) 2115 return Error(PrevOp->getStartLoc(), "shift must be of a register"); 2116 int SrcReg = PrevOp->getReg(); 2117 int64_t Imm = 0; 2118 int ShiftReg = 0; 2119 if (ShiftTy == ARM_AM::rrx) { 2120 // RRX Doesn't have an explicit shift amount. The encoder expects 2121 // the shift register to be the same as the source register. Seems odd, 2122 // but OK. 2123 ShiftReg = SrcReg; 2124 } else { 2125 // Figure out if this is shifted by a constant or a register (for non-RRX). 2126 if (Parser.getTok().is(AsmToken::Hash)) { 2127 Parser.Lex(); // Eat hash. 2128 SMLoc ImmLoc = Parser.getTok().getLoc(); 2129 const MCExpr *ShiftExpr = 0; 2130 if (getParser().ParseExpression(ShiftExpr)) { 2131 Error(ImmLoc, "invalid immediate shift value"); 2132 return -1; 2133 } 2134 // The expression must be evaluatable as an immediate. 2135 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr); 2136 if (!CE) { 2137 Error(ImmLoc, "invalid immediate shift value"); 2138 return -1; 2139 } 2140 // Range check the immediate. 2141 // lsl, ror: 0 <= imm <= 31 2142 // lsr, asr: 0 <= imm <= 32 2143 Imm = CE->getValue(); 2144 if (Imm < 0 || 2145 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || 2146 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { 2147 Error(ImmLoc, "immediate shift value out of range"); 2148 return -1; 2149 } 2150 } else if (Parser.getTok().is(AsmToken::Identifier)) { 2151 ShiftReg = tryParseRegister(); 2152 SMLoc L = Parser.getTok().getLoc(); 2153 if (ShiftReg == -1) { 2154 Error (L, "expected immediate or register in shift operand"); 2155 return -1; 2156 } 2157 } else { 2158 Error (Parser.getTok().getLoc(), 2159 "expected immediate or register in shift operand"); 2160 return -1; 2161 } 2162 } 2163 2164 if (ShiftReg && ShiftTy != ARM_AM::rrx) 2165 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, 2166 ShiftReg, Imm, 2167 S, Parser.getTok().getLoc())); 2168 else 2169 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, 2170 S, Parser.getTok().getLoc())); 2171 2172 return 0; 2173} 2174 2175 2176/// Try to parse a register name. The token must be an Identifier when called. 2177/// If it's a register, an AsmOperand is created. Another AsmOperand is created 2178/// if there is a "writeback". 'true' if it's not a register. 2179/// 2180/// TODO this is likely to change to allow different register types and or to 2181/// parse for a specific register type. 2182bool ARMAsmParser:: 2183tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2184 SMLoc S = Parser.getTok().getLoc(); 2185 int RegNo = tryParseRegister(); 2186 if (RegNo == -1) 2187 return true; 2188 2189 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc())); 2190 2191 const AsmToken &ExclaimTok = Parser.getTok(); 2192 if (ExclaimTok.is(AsmToken::Exclaim)) { 2193 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), 2194 ExclaimTok.getLoc())); 2195 Parser.Lex(); // Eat exclaim token 2196 return false; 2197 } 2198 2199 // Also check for an index operand. This is only legal for vector registers, 2200 // but that'll get caught OK in operand matching, so we don't need to 2201 // explicitly filter everything else out here. 2202 if (Parser.getTok().is(AsmToken::LBrac)) { 2203 SMLoc SIdx = Parser.getTok().getLoc(); 2204 Parser.Lex(); // Eat left bracket token. 2205 2206 const MCExpr *ImmVal; 2207 if (getParser().ParseExpression(ImmVal)) 2208 return MatchOperand_ParseFail; 2209 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal); 2210 if (!MCE) { 2211 TokError("immediate value expected for vector index"); 2212 return MatchOperand_ParseFail; 2213 } 2214 2215 SMLoc E = Parser.getTok().getLoc(); 2216 if (Parser.getTok().isNot(AsmToken::RBrac)) { 2217 Error(E, "']' expected"); 2218 return MatchOperand_ParseFail; 2219 } 2220 2221 Parser.Lex(); // Eat right bracket token. 2222 2223 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), 2224 SIdx, E, 2225 getContext())); 2226 } 2227 2228 return false; 2229} 2230 2231/// MatchCoprocessorOperandName - Try to parse an coprocessor related 2232/// instruction with a symbolic operand name. Example: "p1", "p7", "c3", 2233/// "c5", ... 2234static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { 2235 // Use the same layout as the tablegen'erated register name matcher. Ugly, 2236 // but efficient. 2237 switch (Name.size()) { 2238 default: break; 2239 case 2: 2240 if (Name[0] != CoprocOp) 2241 return -1; 2242 switch (Name[1]) { 2243 default: return -1; 2244 case '0': return 0; 2245 case '1': return 1; 2246 case '2': return 2; 2247 case '3': return 3; 2248 case '4': return 4; 2249 case '5': return 5; 2250 case '6': return 6; 2251 case '7': return 7; 2252 case '8': return 8; 2253 case '9': return 9; 2254 } 2255 break; 2256 case 3: 2257 if (Name[0] != CoprocOp || Name[1] != '1') 2258 return -1; 2259 switch (Name[2]) { 2260 default: return -1; 2261 case '0': return 10; 2262 case '1': return 11; 2263 case '2': return 12; 2264 case '3': return 13; 2265 case '4': return 14; 2266 case '5': return 15; 2267 } 2268 break; 2269 } 2270 2271 return -1; 2272} 2273 2274/// parseITCondCode - Try to parse a condition code for an IT instruction. 2275ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2276parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2277 SMLoc S = Parser.getTok().getLoc(); 2278 const AsmToken &Tok = Parser.getTok(); 2279 if (!Tok.is(AsmToken::Identifier)) 2280 return MatchOperand_NoMatch; 2281 unsigned CC = StringSwitch<unsigned>(Tok.getString()) 2282 .Case("eq", ARMCC::EQ) 2283 .Case("ne", ARMCC::NE) 2284 .Case("hs", ARMCC::HS) 2285 .Case("cs", ARMCC::HS) 2286 .Case("lo", ARMCC::LO) 2287 .Case("cc", ARMCC::LO) 2288 .Case("mi", ARMCC::MI) 2289 .Case("pl", ARMCC::PL) 2290 .Case("vs", ARMCC::VS) 2291 .Case("vc", ARMCC::VC) 2292 .Case("hi", ARMCC::HI) 2293 .Case("ls", ARMCC::LS) 2294 .Case("ge", ARMCC::GE) 2295 .Case("lt", ARMCC::LT) 2296 .Case("gt", ARMCC::GT) 2297 .Case("le", ARMCC::LE) 2298 .Case("al", ARMCC::AL) 2299 .Default(~0U); 2300 if (CC == ~0U) 2301 return MatchOperand_NoMatch; 2302 Parser.Lex(); // Eat the token. 2303 2304 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); 2305 2306 return MatchOperand_Success; 2307} 2308 2309/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The 2310/// token must be an Identifier when called, and if it is a coprocessor 2311/// number, the token is eaten and the operand is added to the operand list. 2312ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2313parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2314 SMLoc S = Parser.getTok().getLoc(); 2315 const AsmToken &Tok = Parser.getTok(); 2316 if (Tok.isNot(AsmToken::Identifier)) 2317 return MatchOperand_NoMatch; 2318 2319 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p'); 2320 if (Num == -1) 2321 return MatchOperand_NoMatch; 2322 2323 Parser.Lex(); // Eat identifier token. 2324 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); 2325 return MatchOperand_Success; 2326} 2327 2328/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The 2329/// token must be an Identifier when called, and if it is a coprocessor 2330/// number, the token is eaten and the operand is added to the operand list. 2331ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2332parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2333 SMLoc S = Parser.getTok().getLoc(); 2334 const AsmToken &Tok = Parser.getTok(); 2335 if (Tok.isNot(AsmToken::Identifier)) 2336 return MatchOperand_NoMatch; 2337 2338 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); 2339 if (Reg == -1) 2340 return MatchOperand_NoMatch; 2341 2342 Parser.Lex(); // Eat identifier token. 2343 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); 2344 return MatchOperand_Success; 2345} 2346 2347/// parseCoprocOptionOperand - Try to parse an coprocessor option operand. 2348/// coproc_option : '{' imm0_255 '}' 2349ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2350parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2351 SMLoc S = Parser.getTok().getLoc(); 2352 2353 // If this isn't a '{', this isn't a coprocessor immediate operand. 2354 if (Parser.getTok().isNot(AsmToken::LCurly)) 2355 return MatchOperand_NoMatch; 2356 Parser.Lex(); // Eat the '{' 2357 2358 const MCExpr *Expr; 2359 SMLoc Loc = Parser.getTok().getLoc(); 2360 if (getParser().ParseExpression(Expr)) { 2361 Error(Loc, "illegal expression"); 2362 return MatchOperand_ParseFail; 2363 } 2364 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 2365 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) { 2366 Error(Loc, "coprocessor option must be an immediate in range [0, 255]"); 2367 return MatchOperand_ParseFail; 2368 } 2369 int Val = CE->getValue(); 2370 2371 // Check for and consume the closing '}' 2372 if (Parser.getTok().isNot(AsmToken::RCurly)) 2373 return MatchOperand_ParseFail; 2374 SMLoc E = Parser.getTok().getLoc(); 2375 Parser.Lex(); // Eat the '}' 2376 2377 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); 2378 return MatchOperand_Success; 2379} 2380 2381// For register list parsing, we need to map from raw GPR register numbering 2382// to the enumeration values. The enumeration values aren't sorted by 2383// register number due to our using "sp", "lr" and "pc" as canonical names. 2384static unsigned getNextRegister(unsigned Reg) { 2385 // If this is a GPR, we need to do it manually, otherwise we can rely 2386 // on the sort ordering of the enumeration since the other reg-classes 2387 // are sane. 2388 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2389 return Reg + 1; 2390 switch(Reg) { 2391 default: assert(0 && "Invalid GPR number!"); 2392 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; 2393 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; 2394 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; 2395 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; 2396 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; 2397 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; 2398 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; 2399 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; 2400 } 2401} 2402 2403/// Parse a register list. 2404bool ARMAsmParser:: 2405parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2406 assert(Parser.getTok().is(AsmToken::LCurly) && 2407 "Token is not a Left Curly Brace"); 2408 SMLoc S = Parser.getTok().getLoc(); 2409 Parser.Lex(); // Eat '{' token. 2410 SMLoc RegLoc = Parser.getTok().getLoc(); 2411 2412 // Check the first register in the list to see what register class 2413 // this is a list of. 2414 int Reg = tryParseRegister(); 2415 if (Reg == -1) 2416 return Error(RegLoc, "register expected"); 2417 2418 const MCRegisterClass *RC; 2419 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2420 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; 2421 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) 2422 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; 2423 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) 2424 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; 2425 else 2426 return Error(RegLoc, "invalid register in register list"); 2427 2428 // The reglist instructions have at most 16 registers, so reserve 2429 // space for that many. 2430 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers; 2431 // Store the first register. 2432 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2433 2434 // This starts immediately after the first register token in the list, 2435 // so we can see either a comma or a minus (range separator) as a legal 2436 // next token. 2437 while (Parser.getTok().is(AsmToken::Comma) || 2438 Parser.getTok().is(AsmToken::Minus)) { 2439 if (Parser.getTok().is(AsmToken::Minus)) { 2440 Parser.Lex(); // Eat the comma. 2441 SMLoc EndLoc = Parser.getTok().getLoc(); 2442 int EndReg = tryParseRegister(); 2443 if (EndReg == -1) 2444 return Error(EndLoc, "register expected"); 2445 // If the register is the same as the start reg, there's nothing 2446 // more to do. 2447 if (Reg == EndReg) 2448 continue; 2449 // The register must be in the same register class as the first. 2450 if (!RC->contains(EndReg)) 2451 return Error(EndLoc, "invalid register in register list"); 2452 // Ranges must go from low to high. 2453 if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg)) 2454 return Error(EndLoc, "bad range in register list"); 2455 2456 // Add all the registers in the range to the register list. 2457 while (Reg != EndReg) { 2458 Reg = getNextRegister(Reg); 2459 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2460 } 2461 continue; 2462 } 2463 Parser.Lex(); // Eat the comma. 2464 RegLoc = Parser.getTok().getLoc(); 2465 int OldReg = Reg; 2466 Reg = tryParseRegister(); 2467 if (Reg == -1) 2468 return Error(RegLoc, "register expected"); 2469 // The register must be in the same register class as the first. 2470 if (!RC->contains(Reg)) 2471 return Error(RegLoc, "invalid register in register list"); 2472 // List must be monotonically increasing. 2473 if (getARMRegisterNumbering(Reg) <= getARMRegisterNumbering(OldReg)) 2474 return Error(RegLoc, "register list not in ascending order"); 2475 // VFP register lists must also be contiguous. 2476 // It's OK to use the enumeration values directly here rather, as the 2477 // VFP register classes have the enum sorted properly. 2478 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && 2479 Reg != OldReg + 1) 2480 return Error(RegLoc, "non-contiguous register range"); 2481 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2482 } 2483 2484 SMLoc E = Parser.getTok().getLoc(); 2485 if (Parser.getTok().isNot(AsmToken::RCurly)) 2486 return Error(E, "'}' expected"); 2487 Parser.Lex(); // Eat '}' token. 2488 2489 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); 2490 return false; 2491} 2492 2493// Return the low-subreg of a given Q register. 2494static unsigned getDRegFromQReg(unsigned QReg) { 2495 switch (QReg) { 2496 default: llvm_unreachable("expected a Q register!"); 2497 case ARM::Q0: return ARM::D0; 2498 case ARM::Q1: return ARM::D2; 2499 case ARM::Q2: return ARM::D4; 2500 case ARM::Q3: return ARM::D6; 2501 case ARM::Q4: return ARM::D8; 2502 case ARM::Q5: return ARM::D10; 2503 case ARM::Q6: return ARM::D12; 2504 case ARM::Q7: return ARM::D14; 2505 case ARM::Q8: return ARM::D16; 2506 case ARM::Q9: return ARM::D19; 2507 case ARM::Q10: return ARM::D20; 2508 case ARM::Q11: return ARM::D22; 2509 case ARM::Q12: return ARM::D24; 2510 case ARM::Q13: return ARM::D26; 2511 case ARM::Q14: return ARM::D28; 2512 case ARM::Q15: return ARM::D30; 2513 } 2514} 2515 2516// parse a vector register list 2517ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2518parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2519 if(Parser.getTok().isNot(AsmToken::LCurly)) 2520 return MatchOperand_NoMatch; 2521 2522 SMLoc S = Parser.getTok().getLoc(); 2523 Parser.Lex(); // Eat '{' token. 2524 SMLoc RegLoc = Parser.getTok().getLoc(); 2525 2526 int Reg = tryParseRegister(); 2527 if (Reg == -1) { 2528 Error(RegLoc, "register expected"); 2529 return MatchOperand_ParseFail; 2530 } 2531 unsigned Count = 1; 2532 unsigned FirstReg = Reg; 2533 // The list is of D registers, but we also allow Q regs and just interpret 2534 // them as the two D sub-registers. 2535 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 2536 FirstReg = Reg = getDRegFromQReg(Reg); 2537 ++Reg; 2538 ++Count; 2539 } 2540 2541 while (Parser.getTok().is(AsmToken::Comma)) { 2542 Parser.Lex(); // Eat the comma. 2543 RegLoc = Parser.getTok().getLoc(); 2544 int OldReg = Reg; 2545 Reg = tryParseRegister(); 2546 if (Reg == -1) { 2547 Error(RegLoc, "register expected"); 2548 return MatchOperand_ParseFail; 2549 } 2550 // vector register lists must be contiguous. 2551 // It's OK to use the enumeration values directly here rather, as the 2552 // VFP register classes have the enum sorted properly. 2553 // 2554 // The list is of D registers, but we also allow Q regs and just interpret 2555 // them as the two D sub-registers. 2556 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 2557 Reg = getDRegFromQReg(Reg); 2558 if (Reg != OldReg + 1) { 2559 Error(RegLoc, "non-contiguous register range"); 2560 return MatchOperand_ParseFail; 2561 } 2562 ++Reg; 2563 Count += 2; 2564 continue; 2565 } 2566 // Normal D register. Just check that it's contiguous and keep going. 2567 if (Reg != OldReg + 1) { 2568 Error(RegLoc, "non-contiguous register range"); 2569 return MatchOperand_ParseFail; 2570 } 2571 ++Count; 2572 } 2573 2574 SMLoc E = Parser.getTok().getLoc(); 2575 if (Parser.getTok().isNot(AsmToken::RCurly)) { 2576 Error(E, "'}' expected"); 2577 return MatchOperand_ParseFail; 2578 } 2579 Parser.Lex(); // Eat '}' token. 2580 2581 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, S, E)); 2582 return MatchOperand_Success; 2583} 2584 2585/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. 2586ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2587parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2588 SMLoc S = Parser.getTok().getLoc(); 2589 const AsmToken &Tok = Parser.getTok(); 2590 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 2591 StringRef OptStr = Tok.getString(); 2592 2593 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size())) 2594 .Case("sy", ARM_MB::SY) 2595 .Case("st", ARM_MB::ST) 2596 .Case("sh", ARM_MB::ISH) 2597 .Case("ish", ARM_MB::ISH) 2598 .Case("shst", ARM_MB::ISHST) 2599 .Case("ishst", ARM_MB::ISHST) 2600 .Case("nsh", ARM_MB::NSH) 2601 .Case("un", ARM_MB::NSH) 2602 .Case("nshst", ARM_MB::NSHST) 2603 .Case("unst", ARM_MB::NSHST) 2604 .Case("osh", ARM_MB::OSH) 2605 .Case("oshst", ARM_MB::OSHST) 2606 .Default(~0U); 2607 2608 if (Opt == ~0U) 2609 return MatchOperand_NoMatch; 2610 2611 Parser.Lex(); // Eat identifier token. 2612 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); 2613 return MatchOperand_Success; 2614} 2615 2616/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. 2617ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2618parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2619 SMLoc S = Parser.getTok().getLoc(); 2620 const AsmToken &Tok = Parser.getTok(); 2621 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 2622 StringRef IFlagsStr = Tok.getString(); 2623 2624 // An iflags string of "none" is interpreted to mean that none of the AIF 2625 // bits are set. Not a terribly useful instruction, but a valid encoding. 2626 unsigned IFlags = 0; 2627 if (IFlagsStr != "none") { 2628 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { 2629 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1)) 2630 .Case("a", ARM_PROC::A) 2631 .Case("i", ARM_PROC::I) 2632 .Case("f", ARM_PROC::F) 2633 .Default(~0U); 2634 2635 // If some specific iflag is already set, it means that some letter is 2636 // present more than once, this is not acceptable. 2637 if (Flag == ~0U || (IFlags & Flag)) 2638 return MatchOperand_NoMatch; 2639 2640 IFlags |= Flag; 2641 } 2642 } 2643 2644 Parser.Lex(); // Eat identifier token. 2645 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); 2646 return MatchOperand_Success; 2647} 2648 2649/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. 2650ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2651parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2652 SMLoc S = Parser.getTok().getLoc(); 2653 const AsmToken &Tok = Parser.getTok(); 2654 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 2655 StringRef Mask = Tok.getString(); 2656 2657 if (isMClass()) { 2658 // See ARMv6-M 10.1.1 2659 unsigned FlagsVal = StringSwitch<unsigned>(Mask) 2660 .Case("apsr", 0) 2661 .Case("iapsr", 1) 2662 .Case("eapsr", 2) 2663 .Case("xpsr", 3) 2664 .Case("ipsr", 5) 2665 .Case("epsr", 6) 2666 .Case("iepsr", 7) 2667 .Case("msp", 8) 2668 .Case("psp", 9) 2669 .Case("primask", 16) 2670 .Case("basepri", 17) 2671 .Case("basepri_max", 18) 2672 .Case("faultmask", 19) 2673 .Case("control", 20) 2674 .Default(~0U); 2675 2676 if (FlagsVal == ~0U) 2677 return MatchOperand_NoMatch; 2678 2679 if (!hasV7Ops() && FlagsVal >= 17 && FlagsVal <= 19) 2680 // basepri, basepri_max and faultmask only valid for V7m. 2681 return MatchOperand_NoMatch; 2682 2683 Parser.Lex(); // Eat identifier token. 2684 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 2685 return MatchOperand_Success; 2686 } 2687 2688 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" 2689 size_t Start = 0, Next = Mask.find('_'); 2690 StringRef Flags = ""; 2691 std::string SpecReg = LowercaseString(Mask.slice(Start, Next)); 2692 if (Next != StringRef::npos) 2693 Flags = Mask.slice(Next+1, Mask.size()); 2694 2695 // FlagsVal contains the complete mask: 2696 // 3-0: Mask 2697 // 4: Special Reg (cpsr, apsr => 0; spsr => 1) 2698 unsigned FlagsVal = 0; 2699 2700 if (SpecReg == "apsr") { 2701 FlagsVal = StringSwitch<unsigned>(Flags) 2702 .Case("nzcvq", 0x8) // same as CPSR_f 2703 .Case("g", 0x4) // same as CPSR_s 2704 .Case("nzcvqg", 0xc) // same as CPSR_fs 2705 .Default(~0U); 2706 2707 if (FlagsVal == ~0U) { 2708 if (!Flags.empty()) 2709 return MatchOperand_NoMatch; 2710 else 2711 FlagsVal = 8; // No flag 2712 } 2713 } else if (SpecReg == "cpsr" || SpecReg == "spsr") { 2714 if (Flags == "all") // cpsr_all is an alias for cpsr_fc 2715 Flags = "fc"; 2716 for (int i = 0, e = Flags.size(); i != e; ++i) { 2717 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1)) 2718 .Case("c", 1) 2719 .Case("x", 2) 2720 .Case("s", 4) 2721 .Case("f", 8) 2722 .Default(~0U); 2723 2724 // If some specific flag is already set, it means that some letter is 2725 // present more than once, this is not acceptable. 2726 if (FlagsVal == ~0U || (FlagsVal & Flag)) 2727 return MatchOperand_NoMatch; 2728 FlagsVal |= Flag; 2729 } 2730 } else // No match for special register. 2731 return MatchOperand_NoMatch; 2732 2733 // Special register without flags is NOT equivalent to "fc" flags. 2734 // NOTE: This is a divergence from gas' behavior. Uncommenting the following 2735 // two lines would enable gas compatibility at the expense of breaking 2736 // round-tripping. 2737 // 2738 // if (!FlagsVal) 2739 // FlagsVal = 0x9; 2740 2741 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) 2742 if (SpecReg == "spsr") 2743 FlagsVal |= 16; 2744 2745 Parser.Lex(); // Eat identifier token. 2746 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 2747 return MatchOperand_Success; 2748} 2749 2750ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2751parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op, 2752 int Low, int High) { 2753 const AsmToken &Tok = Parser.getTok(); 2754 if (Tok.isNot(AsmToken::Identifier)) { 2755 Error(Parser.getTok().getLoc(), Op + " operand expected."); 2756 return MatchOperand_ParseFail; 2757 } 2758 StringRef ShiftName = Tok.getString(); 2759 std::string LowerOp = LowercaseString(Op); 2760 std::string UpperOp = UppercaseString(Op); 2761 if (ShiftName != LowerOp && ShiftName != UpperOp) { 2762 Error(Parser.getTok().getLoc(), Op + " operand expected."); 2763 return MatchOperand_ParseFail; 2764 } 2765 Parser.Lex(); // Eat shift type token. 2766 2767 // There must be a '#' and a shift amount. 2768 if (Parser.getTok().isNot(AsmToken::Hash)) { 2769 Error(Parser.getTok().getLoc(), "'#' expected"); 2770 return MatchOperand_ParseFail; 2771 } 2772 Parser.Lex(); // Eat hash token. 2773 2774 const MCExpr *ShiftAmount; 2775 SMLoc Loc = Parser.getTok().getLoc(); 2776 if (getParser().ParseExpression(ShiftAmount)) { 2777 Error(Loc, "illegal expression"); 2778 return MatchOperand_ParseFail; 2779 } 2780 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 2781 if (!CE) { 2782 Error(Loc, "constant expression expected"); 2783 return MatchOperand_ParseFail; 2784 } 2785 int Val = CE->getValue(); 2786 if (Val < Low || Val > High) { 2787 Error(Loc, "immediate value out of range"); 2788 return MatchOperand_ParseFail; 2789 } 2790 2791 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc())); 2792 2793 return MatchOperand_Success; 2794} 2795 2796ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2797parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2798 const AsmToken &Tok = Parser.getTok(); 2799 SMLoc S = Tok.getLoc(); 2800 if (Tok.isNot(AsmToken::Identifier)) { 2801 Error(Tok.getLoc(), "'be' or 'le' operand expected"); 2802 return MatchOperand_ParseFail; 2803 } 2804 int Val = StringSwitch<int>(Tok.getString()) 2805 .Case("be", 1) 2806 .Case("le", 0) 2807 .Default(-1); 2808 Parser.Lex(); // Eat the token. 2809 2810 if (Val == -1) { 2811 Error(Tok.getLoc(), "'be' or 'le' operand expected"); 2812 return MatchOperand_ParseFail; 2813 } 2814 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val, 2815 getContext()), 2816 S, Parser.getTok().getLoc())); 2817 return MatchOperand_Success; 2818} 2819 2820/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT 2821/// instructions. Legal values are: 2822/// lsl #n 'n' in [0,31] 2823/// asr #n 'n' in [1,32] 2824/// n == 32 encoded as n == 0. 2825ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2826parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2827 const AsmToken &Tok = Parser.getTok(); 2828 SMLoc S = Tok.getLoc(); 2829 if (Tok.isNot(AsmToken::Identifier)) { 2830 Error(S, "shift operator 'asr' or 'lsl' expected"); 2831 return MatchOperand_ParseFail; 2832 } 2833 StringRef ShiftName = Tok.getString(); 2834 bool isASR; 2835 if (ShiftName == "lsl" || ShiftName == "LSL") 2836 isASR = false; 2837 else if (ShiftName == "asr" || ShiftName == "ASR") 2838 isASR = true; 2839 else { 2840 Error(S, "shift operator 'asr' or 'lsl' expected"); 2841 return MatchOperand_ParseFail; 2842 } 2843 Parser.Lex(); // Eat the operator. 2844 2845 // A '#' and a shift amount. 2846 if (Parser.getTok().isNot(AsmToken::Hash)) { 2847 Error(Parser.getTok().getLoc(), "'#' expected"); 2848 return MatchOperand_ParseFail; 2849 } 2850 Parser.Lex(); // Eat hash token. 2851 2852 const MCExpr *ShiftAmount; 2853 SMLoc E = Parser.getTok().getLoc(); 2854 if (getParser().ParseExpression(ShiftAmount)) { 2855 Error(E, "malformed shift expression"); 2856 return MatchOperand_ParseFail; 2857 } 2858 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 2859 if (!CE) { 2860 Error(E, "shift amount must be an immediate"); 2861 return MatchOperand_ParseFail; 2862 } 2863 2864 int64_t Val = CE->getValue(); 2865 if (isASR) { 2866 // Shift amount must be in [1,32] 2867 if (Val < 1 || Val > 32) { 2868 Error(E, "'asr' shift amount must be in range [1,32]"); 2869 return MatchOperand_ParseFail; 2870 } 2871 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode. 2872 if (isThumb() && Val == 32) { 2873 Error(E, "'asr #32' shift amount not allowed in Thumb mode"); 2874 return MatchOperand_ParseFail; 2875 } 2876 if (Val == 32) Val = 0; 2877 } else { 2878 // Shift amount must be in [1,32] 2879 if (Val < 0 || Val > 31) { 2880 Error(E, "'lsr' shift amount must be in range [0,31]"); 2881 return MatchOperand_ParseFail; 2882 } 2883 } 2884 2885 E = Parser.getTok().getLoc(); 2886 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E)); 2887 2888 return MatchOperand_Success; 2889} 2890 2891/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family 2892/// of instructions. Legal values are: 2893/// ror #n 'n' in {0, 8, 16, 24} 2894ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2895parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2896 const AsmToken &Tok = Parser.getTok(); 2897 SMLoc S = Tok.getLoc(); 2898 if (Tok.isNot(AsmToken::Identifier)) 2899 return MatchOperand_NoMatch; 2900 StringRef ShiftName = Tok.getString(); 2901 if (ShiftName != "ror" && ShiftName != "ROR") 2902 return MatchOperand_NoMatch; 2903 Parser.Lex(); // Eat the operator. 2904 2905 // A '#' and a rotate amount. 2906 if (Parser.getTok().isNot(AsmToken::Hash)) { 2907 Error(Parser.getTok().getLoc(), "'#' expected"); 2908 return MatchOperand_ParseFail; 2909 } 2910 Parser.Lex(); // Eat hash token. 2911 2912 const MCExpr *ShiftAmount; 2913 SMLoc E = Parser.getTok().getLoc(); 2914 if (getParser().ParseExpression(ShiftAmount)) { 2915 Error(E, "malformed rotate expression"); 2916 return MatchOperand_ParseFail; 2917 } 2918 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 2919 if (!CE) { 2920 Error(E, "rotate amount must be an immediate"); 2921 return MatchOperand_ParseFail; 2922 } 2923 2924 int64_t Val = CE->getValue(); 2925 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) 2926 // normally, zero is represented in asm by omitting the rotate operand 2927 // entirely. 2928 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { 2929 Error(E, "'ror' rotate amount must be 8, 16, or 24"); 2930 return MatchOperand_ParseFail; 2931 } 2932 2933 E = Parser.getTok().getLoc(); 2934 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E)); 2935 2936 return MatchOperand_Success; 2937} 2938 2939ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2940parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2941 SMLoc S = Parser.getTok().getLoc(); 2942 // The bitfield descriptor is really two operands, the LSB and the width. 2943 if (Parser.getTok().isNot(AsmToken::Hash)) { 2944 Error(Parser.getTok().getLoc(), "'#' expected"); 2945 return MatchOperand_ParseFail; 2946 } 2947 Parser.Lex(); // Eat hash token. 2948 2949 const MCExpr *LSBExpr; 2950 SMLoc E = Parser.getTok().getLoc(); 2951 if (getParser().ParseExpression(LSBExpr)) { 2952 Error(E, "malformed immediate expression"); 2953 return MatchOperand_ParseFail; 2954 } 2955 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr); 2956 if (!CE) { 2957 Error(E, "'lsb' operand must be an immediate"); 2958 return MatchOperand_ParseFail; 2959 } 2960 2961 int64_t LSB = CE->getValue(); 2962 // The LSB must be in the range [0,31] 2963 if (LSB < 0 || LSB > 31) { 2964 Error(E, "'lsb' operand must be in the range [0,31]"); 2965 return MatchOperand_ParseFail; 2966 } 2967 E = Parser.getTok().getLoc(); 2968 2969 // Expect another immediate operand. 2970 if (Parser.getTok().isNot(AsmToken::Comma)) { 2971 Error(Parser.getTok().getLoc(), "too few operands"); 2972 return MatchOperand_ParseFail; 2973 } 2974 Parser.Lex(); // Eat hash token. 2975 if (Parser.getTok().isNot(AsmToken::Hash)) { 2976 Error(Parser.getTok().getLoc(), "'#' expected"); 2977 return MatchOperand_ParseFail; 2978 } 2979 Parser.Lex(); // Eat hash token. 2980 2981 const MCExpr *WidthExpr; 2982 if (getParser().ParseExpression(WidthExpr)) { 2983 Error(E, "malformed immediate expression"); 2984 return MatchOperand_ParseFail; 2985 } 2986 CE = dyn_cast<MCConstantExpr>(WidthExpr); 2987 if (!CE) { 2988 Error(E, "'width' operand must be an immediate"); 2989 return MatchOperand_ParseFail; 2990 } 2991 2992 int64_t Width = CE->getValue(); 2993 // The LSB must be in the range [1,32-lsb] 2994 if (Width < 1 || Width > 32 - LSB) { 2995 Error(E, "'width' operand must be in the range [1,32-lsb]"); 2996 return MatchOperand_ParseFail; 2997 } 2998 E = Parser.getTok().getLoc(); 2999 3000 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E)); 3001 3002 return MatchOperand_Success; 3003} 3004 3005ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3006parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3007 // Check for a post-index addressing register operand. Specifically: 3008 // postidx_reg := '+' register {, shift} 3009 // | '-' register {, shift} 3010 // | register {, shift} 3011 3012 // This method must return MatchOperand_NoMatch without consuming any tokens 3013 // in the case where there is no match, as other alternatives take other 3014 // parse methods. 3015 AsmToken Tok = Parser.getTok(); 3016 SMLoc S = Tok.getLoc(); 3017 bool haveEaten = false; 3018 bool isAdd = true; 3019 int Reg = -1; 3020 if (Tok.is(AsmToken::Plus)) { 3021 Parser.Lex(); // Eat the '+' token. 3022 haveEaten = true; 3023 } else if (Tok.is(AsmToken::Minus)) { 3024 Parser.Lex(); // Eat the '-' token. 3025 isAdd = false; 3026 haveEaten = true; 3027 } 3028 if (Parser.getTok().is(AsmToken::Identifier)) 3029 Reg = tryParseRegister(); 3030 if (Reg == -1) { 3031 if (!haveEaten) 3032 return MatchOperand_NoMatch; 3033 Error(Parser.getTok().getLoc(), "register expected"); 3034 return MatchOperand_ParseFail; 3035 } 3036 SMLoc E = Parser.getTok().getLoc(); 3037 3038 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; 3039 unsigned ShiftImm = 0; 3040 if (Parser.getTok().is(AsmToken::Comma)) { 3041 Parser.Lex(); // Eat the ','. 3042 if (parseMemRegOffsetShift(ShiftTy, ShiftImm)) 3043 return MatchOperand_ParseFail; 3044 } 3045 3046 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, 3047 ShiftImm, S, E)); 3048 3049 return MatchOperand_Success; 3050} 3051 3052ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3053parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3054 // Check for a post-index addressing register operand. Specifically: 3055 // am3offset := '+' register 3056 // | '-' register 3057 // | register 3058 // | # imm 3059 // | # + imm 3060 // | # - imm 3061 3062 // This method must return MatchOperand_NoMatch without consuming any tokens 3063 // in the case where there is no match, as other alternatives take other 3064 // parse methods. 3065 AsmToken Tok = Parser.getTok(); 3066 SMLoc S = Tok.getLoc(); 3067 3068 // Do immediates first, as we always parse those if we have a '#'. 3069 if (Parser.getTok().is(AsmToken::Hash)) { 3070 Parser.Lex(); // Eat the '#'. 3071 // Explicitly look for a '-', as we need to encode negative zero 3072 // differently. 3073 bool isNegative = Parser.getTok().is(AsmToken::Minus); 3074 const MCExpr *Offset; 3075 if (getParser().ParseExpression(Offset)) 3076 return MatchOperand_ParseFail; 3077 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 3078 if (!CE) { 3079 Error(S, "constant expression expected"); 3080 return MatchOperand_ParseFail; 3081 } 3082 SMLoc E = Tok.getLoc(); 3083 // Negative zero is encoded as the flag value INT32_MIN. 3084 int32_t Val = CE->getValue(); 3085 if (isNegative && Val == 0) 3086 Val = INT32_MIN; 3087 3088 Operands.push_back( 3089 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E)); 3090 3091 return MatchOperand_Success; 3092 } 3093 3094 3095 bool haveEaten = false; 3096 bool isAdd = true; 3097 int Reg = -1; 3098 if (Tok.is(AsmToken::Plus)) { 3099 Parser.Lex(); // Eat the '+' token. 3100 haveEaten = true; 3101 } else if (Tok.is(AsmToken::Minus)) { 3102 Parser.Lex(); // Eat the '-' token. 3103 isAdd = false; 3104 haveEaten = true; 3105 } 3106 if (Parser.getTok().is(AsmToken::Identifier)) 3107 Reg = tryParseRegister(); 3108 if (Reg == -1) { 3109 if (!haveEaten) 3110 return MatchOperand_NoMatch; 3111 Error(Parser.getTok().getLoc(), "register expected"); 3112 return MatchOperand_ParseFail; 3113 } 3114 SMLoc E = Parser.getTok().getLoc(); 3115 3116 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, 3117 0, S, E)); 3118 3119 return MatchOperand_Success; 3120} 3121 3122/// cvtT2LdrdPre - Convert parsed operands to MCInst. 3123/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3124/// when they refer multiple MIOperands inside a single one. 3125bool ARMAsmParser:: 3126cvtT2LdrdPre(MCInst &Inst, unsigned Opcode, 3127 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3128 // Rt, Rt2 3129 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3130 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 3131 // Create a writeback register dummy placeholder. 3132 Inst.addOperand(MCOperand::CreateReg(0)); 3133 // addr 3134 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); 3135 // pred 3136 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3137 return true; 3138} 3139 3140/// cvtT2StrdPre - Convert parsed operands to MCInst. 3141/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3142/// when they refer multiple MIOperands inside a single one. 3143bool ARMAsmParser:: 3144cvtT2StrdPre(MCInst &Inst, unsigned Opcode, 3145 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3146 // Create a writeback register dummy placeholder. 3147 Inst.addOperand(MCOperand::CreateReg(0)); 3148 // Rt, Rt2 3149 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3150 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 3151 // addr 3152 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); 3153 // pred 3154 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3155 return true; 3156} 3157 3158/// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst. 3159/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3160/// when they refer multiple MIOperands inside a single one. 3161bool ARMAsmParser:: 3162cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 3163 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3164 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3165 3166 // Create a writeback register dummy placeholder. 3167 Inst.addOperand(MCOperand::CreateImm(0)); 3168 3169 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2); 3170 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3171 return true; 3172} 3173 3174/// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst. 3175/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3176/// when they refer multiple MIOperands inside a single one. 3177bool ARMAsmParser:: 3178cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 3179 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3180 // Create a writeback register dummy placeholder. 3181 Inst.addOperand(MCOperand::CreateImm(0)); 3182 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3183 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2); 3184 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3185 return true; 3186} 3187 3188/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 3189/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3190/// when they refer multiple MIOperands inside a single one. 3191bool ARMAsmParser:: 3192cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 3193 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3194 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3195 3196 // Create a writeback register dummy placeholder. 3197 Inst.addOperand(MCOperand::CreateImm(0)); 3198 3199 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 3200 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3201 return true; 3202} 3203 3204/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. 3205/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3206/// when they refer multiple MIOperands inside a single one. 3207bool ARMAsmParser:: 3208cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 3209 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3210 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3211 3212 // Create a writeback register dummy placeholder. 3213 Inst.addOperand(MCOperand::CreateImm(0)); 3214 3215 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); 3216 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3217 return true; 3218} 3219 3220 3221/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. 3222/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3223/// when they refer multiple MIOperands inside a single one. 3224bool ARMAsmParser:: 3225cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 3226 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3227 // Create a writeback register dummy placeholder. 3228 Inst.addOperand(MCOperand::CreateImm(0)); 3229 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3230 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); 3231 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3232 return true; 3233} 3234 3235/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 3236/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3237/// when they refer multiple MIOperands inside a single one. 3238bool ARMAsmParser:: 3239cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 3240 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3241 // Create a writeback register dummy placeholder. 3242 Inst.addOperand(MCOperand::CreateImm(0)); 3243 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3244 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 3245 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3246 return true; 3247} 3248 3249/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 3250/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3251/// when they refer multiple MIOperands inside a single one. 3252bool ARMAsmParser:: 3253cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 3254 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3255 // Create a writeback register dummy placeholder. 3256 Inst.addOperand(MCOperand::CreateImm(0)); 3257 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3258 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 3259 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3260 return true; 3261} 3262 3263/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst. 3264/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3265/// when they refer multiple MIOperands inside a single one. 3266bool ARMAsmParser:: 3267cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 3268 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3269 // Rt 3270 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3271 // Create a writeback register dummy placeholder. 3272 Inst.addOperand(MCOperand::CreateImm(0)); 3273 // addr 3274 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 3275 // offset 3276 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 3277 // pred 3278 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3279 return true; 3280} 3281 3282/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst. 3283/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3284/// when they refer multiple MIOperands inside a single one. 3285bool ARMAsmParser:: 3286cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 3287 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3288 // Rt 3289 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3290 // Create a writeback register dummy placeholder. 3291 Inst.addOperand(MCOperand::CreateImm(0)); 3292 // addr 3293 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 3294 // offset 3295 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 3296 // pred 3297 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3298 return true; 3299} 3300 3301/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst. 3302/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3303/// when they refer multiple MIOperands inside a single one. 3304bool ARMAsmParser:: 3305cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 3306 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3307 // Create a writeback register dummy placeholder. 3308 Inst.addOperand(MCOperand::CreateImm(0)); 3309 // Rt 3310 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3311 // addr 3312 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 3313 // offset 3314 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 3315 // pred 3316 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3317 return true; 3318} 3319 3320/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst. 3321/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3322/// when they refer multiple MIOperands inside a single one. 3323bool ARMAsmParser:: 3324cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 3325 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3326 // Create a writeback register dummy placeholder. 3327 Inst.addOperand(MCOperand::CreateImm(0)); 3328 // Rt 3329 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3330 // addr 3331 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 3332 // offset 3333 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 3334 // pred 3335 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3336 return true; 3337} 3338 3339/// cvtLdrdPre - Convert parsed operands to MCInst. 3340/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3341/// when they refer multiple MIOperands inside a single one. 3342bool ARMAsmParser:: 3343cvtLdrdPre(MCInst &Inst, unsigned Opcode, 3344 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3345 // Rt, Rt2 3346 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3347 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 3348 // Create a writeback register dummy placeholder. 3349 Inst.addOperand(MCOperand::CreateImm(0)); 3350 // addr 3351 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 3352 // pred 3353 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3354 return true; 3355} 3356 3357/// cvtStrdPre - Convert parsed operands to MCInst. 3358/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3359/// when they refer multiple MIOperands inside a single one. 3360bool ARMAsmParser:: 3361cvtStrdPre(MCInst &Inst, unsigned Opcode, 3362 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3363 // Create a writeback register dummy placeholder. 3364 Inst.addOperand(MCOperand::CreateImm(0)); 3365 // Rt, Rt2 3366 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3367 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 3368 // addr 3369 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 3370 // pred 3371 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3372 return true; 3373} 3374 3375/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 3376/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3377/// when they refer multiple MIOperands inside a single one. 3378bool ARMAsmParser:: 3379cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 3380 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3381 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3382 // Create a writeback register dummy placeholder. 3383 Inst.addOperand(MCOperand::CreateImm(0)); 3384 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 3385 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3386 return true; 3387} 3388 3389/// cvtThumbMultiple- Convert parsed operands to MCInst. 3390/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3391/// when they refer multiple MIOperands inside a single one. 3392bool ARMAsmParser:: 3393cvtThumbMultiply(MCInst &Inst, unsigned Opcode, 3394 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3395 // The second source operand must be the same register as the destination 3396 // operand. 3397 if (Operands.size() == 6 && 3398 (((ARMOperand*)Operands[3])->getReg() != 3399 ((ARMOperand*)Operands[5])->getReg()) && 3400 (((ARMOperand*)Operands[3])->getReg() != 3401 ((ARMOperand*)Operands[4])->getReg())) { 3402 Error(Operands[3]->getStartLoc(), 3403 "destination register must match source register"); 3404 return false; 3405 } 3406 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 3407 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1); 3408 ((ARMOperand*)Operands[4])->addRegOperands(Inst, 1); 3409 // If we have a three-operand form, use that, else the second source operand 3410 // is just the destination operand again. 3411 if (Operands.size() == 6) 3412 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); 3413 else 3414 Inst.addOperand(Inst.getOperand(0)); 3415 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2); 3416 3417 return true; 3418} 3419 3420bool ARMAsmParser:: 3421cvtVLDwbFixed(MCInst &Inst, unsigned Opcode, 3422 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3423 // Vd 3424 ((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1); 3425 // Create a writeback register dummy placeholder. 3426 Inst.addOperand(MCOperand::CreateImm(0)); 3427 // Vn 3428 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 3429 // pred 3430 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3431 return true; 3432} 3433 3434bool ARMAsmParser:: 3435cvtVLDwbRegister(MCInst &Inst, unsigned Opcode, 3436 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3437 // Vd 3438 ((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1); 3439 // Create a writeback register dummy placeholder. 3440 Inst.addOperand(MCOperand::CreateImm(0)); 3441 // Vn 3442 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 3443 // Vm 3444 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); 3445 // pred 3446 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3447 return true; 3448} 3449 3450bool ARMAsmParser:: 3451cvtVSTwbFixed(MCInst &Inst, unsigned Opcode, 3452 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3453 // Create a writeback register dummy placeholder. 3454 Inst.addOperand(MCOperand::CreateImm(0)); 3455 // Vn 3456 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 3457 // Vt 3458 ((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1); 3459 // pred 3460 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3461 return true; 3462} 3463 3464bool ARMAsmParser:: 3465cvtVSTwbRegister(MCInst &Inst, unsigned Opcode, 3466 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3467 // Create a writeback register dummy placeholder. 3468 Inst.addOperand(MCOperand::CreateImm(0)); 3469 // Vn 3470 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 3471 // Vm 3472 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); 3473 // Vt 3474 ((ARMOperand*)Operands[3])->addVecListTwoDOperands(Inst, 1); 3475 // pred 3476 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3477 return true; 3478} 3479 3480/// Parse an ARM memory expression, return false if successful else return true 3481/// or an error. The first token must be a '[' when called. 3482bool ARMAsmParser:: 3483parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3484 SMLoc S, E; 3485 assert(Parser.getTok().is(AsmToken::LBrac) && 3486 "Token is not a Left Bracket"); 3487 S = Parser.getTok().getLoc(); 3488 Parser.Lex(); // Eat left bracket token. 3489 3490 const AsmToken &BaseRegTok = Parser.getTok(); 3491 int BaseRegNum = tryParseRegister(); 3492 if (BaseRegNum == -1) 3493 return Error(BaseRegTok.getLoc(), "register expected"); 3494 3495 // The next token must either be a comma or a closing bracket. 3496 const AsmToken &Tok = Parser.getTok(); 3497 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac)) 3498 return Error(Tok.getLoc(), "malformed memory operand"); 3499 3500 if (Tok.is(AsmToken::RBrac)) { 3501 E = Tok.getLoc(); 3502 Parser.Lex(); // Eat right bracket token. 3503 3504 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift, 3505 0, 0, false, S, E)); 3506 3507 // If there's a pre-indexing writeback marker, '!', just add it as a token 3508 // operand. It's rather odd, but syntactically valid. 3509 if (Parser.getTok().is(AsmToken::Exclaim)) { 3510 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 3511 Parser.Lex(); // Eat the '!'. 3512 } 3513 3514 return false; 3515 } 3516 3517 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!"); 3518 Parser.Lex(); // Eat the comma. 3519 3520 // If we have a ':', it's an alignment specifier. 3521 if (Parser.getTok().is(AsmToken::Colon)) { 3522 Parser.Lex(); // Eat the ':'. 3523 E = Parser.getTok().getLoc(); 3524 3525 const MCExpr *Expr; 3526 if (getParser().ParseExpression(Expr)) 3527 return true; 3528 3529 // The expression has to be a constant. Memory references with relocations 3530 // don't come through here, as they use the <label> forms of the relevant 3531 // instructions. 3532 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 3533 if (!CE) 3534 return Error (E, "constant expression expected"); 3535 3536 unsigned Align = 0; 3537 switch (CE->getValue()) { 3538 default: 3539 return Error(E, "alignment specifier must be 64, 128, or 256 bits"); 3540 case 64: Align = 8; break; 3541 case 128: Align = 16; break; 3542 case 256: Align = 32; break; 3543 } 3544 3545 // Now we should have the closing ']' 3546 E = Parser.getTok().getLoc(); 3547 if (Parser.getTok().isNot(AsmToken::RBrac)) 3548 return Error(E, "']' expected"); 3549 Parser.Lex(); // Eat right bracket token. 3550 3551 // Don't worry about range checking the value here. That's handled by 3552 // the is*() predicates. 3553 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, 3554 ARM_AM::no_shift, 0, Align, 3555 false, S, E)); 3556 3557 // If there's a pre-indexing writeback marker, '!', just add it as a token 3558 // operand. 3559 if (Parser.getTok().is(AsmToken::Exclaim)) { 3560 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 3561 Parser.Lex(); // Eat the '!'. 3562 } 3563 3564 return false; 3565 } 3566 3567 // If we have a '#', it's an immediate offset, else assume it's a register 3568 // offset. 3569 if (Parser.getTok().is(AsmToken::Hash)) { 3570 Parser.Lex(); // Eat the '#'. 3571 E = Parser.getTok().getLoc(); 3572 3573 bool isNegative = getParser().getTok().is(AsmToken::Minus); 3574 const MCExpr *Offset; 3575 if (getParser().ParseExpression(Offset)) 3576 return true; 3577 3578 // The expression has to be a constant. Memory references with relocations 3579 // don't come through here, as they use the <label> forms of the relevant 3580 // instructions. 3581 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 3582 if (!CE) 3583 return Error (E, "constant expression expected"); 3584 3585 // If the constant was #-0, represent it as INT32_MIN. 3586 int32_t Val = CE->getValue(); 3587 if (isNegative && Val == 0) 3588 CE = MCConstantExpr::Create(INT32_MIN, getContext()); 3589 3590 // Now we should have the closing ']' 3591 E = Parser.getTok().getLoc(); 3592 if (Parser.getTok().isNot(AsmToken::RBrac)) 3593 return Error(E, "']' expected"); 3594 Parser.Lex(); // Eat right bracket token. 3595 3596 // Don't worry about range checking the value here. That's handled by 3597 // the is*() predicates. 3598 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0, 3599 ARM_AM::no_shift, 0, 0, 3600 false, S, E)); 3601 3602 // If there's a pre-indexing writeback marker, '!', just add it as a token 3603 // operand. 3604 if (Parser.getTok().is(AsmToken::Exclaim)) { 3605 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 3606 Parser.Lex(); // Eat the '!'. 3607 } 3608 3609 return false; 3610 } 3611 3612 // The register offset is optionally preceded by a '+' or '-' 3613 bool isNegative = false; 3614 if (Parser.getTok().is(AsmToken::Minus)) { 3615 isNegative = true; 3616 Parser.Lex(); // Eat the '-'. 3617 } else if (Parser.getTok().is(AsmToken::Plus)) { 3618 // Nothing to do. 3619 Parser.Lex(); // Eat the '+'. 3620 } 3621 3622 E = Parser.getTok().getLoc(); 3623 int OffsetRegNum = tryParseRegister(); 3624 if (OffsetRegNum == -1) 3625 return Error(E, "register expected"); 3626 3627 // If there's a shift operator, handle it. 3628 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift; 3629 unsigned ShiftImm = 0; 3630 if (Parser.getTok().is(AsmToken::Comma)) { 3631 Parser.Lex(); // Eat the ','. 3632 if (parseMemRegOffsetShift(ShiftType, ShiftImm)) 3633 return true; 3634 } 3635 3636 // Now we should have the closing ']' 3637 E = Parser.getTok().getLoc(); 3638 if (Parser.getTok().isNot(AsmToken::RBrac)) 3639 return Error(E, "']' expected"); 3640 Parser.Lex(); // Eat right bracket token. 3641 3642 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum, 3643 ShiftType, ShiftImm, 0, isNegative, 3644 S, E)); 3645 3646 // If there's a pre-indexing writeback marker, '!', just add it as a token 3647 // operand. 3648 if (Parser.getTok().is(AsmToken::Exclaim)) { 3649 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 3650 Parser.Lex(); // Eat the '!'. 3651 } 3652 3653 return false; 3654} 3655 3656/// parseMemRegOffsetShift - one of these two: 3657/// ( lsl | lsr | asr | ror ) , # shift_amount 3658/// rrx 3659/// return true if it parses a shift otherwise it returns false. 3660bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St, 3661 unsigned &Amount) { 3662 SMLoc Loc = Parser.getTok().getLoc(); 3663 const AsmToken &Tok = Parser.getTok(); 3664 if (Tok.isNot(AsmToken::Identifier)) 3665 return true; 3666 StringRef ShiftName = Tok.getString(); 3667 if (ShiftName == "lsl" || ShiftName == "LSL") 3668 St = ARM_AM::lsl; 3669 else if (ShiftName == "lsr" || ShiftName == "LSR") 3670 St = ARM_AM::lsr; 3671 else if (ShiftName == "asr" || ShiftName == "ASR") 3672 St = ARM_AM::asr; 3673 else if (ShiftName == "ror" || ShiftName == "ROR") 3674 St = ARM_AM::ror; 3675 else if (ShiftName == "rrx" || ShiftName == "RRX") 3676 St = ARM_AM::rrx; 3677 else 3678 return Error(Loc, "illegal shift operator"); 3679 Parser.Lex(); // Eat shift type token. 3680 3681 // rrx stands alone. 3682 Amount = 0; 3683 if (St != ARM_AM::rrx) { 3684 Loc = Parser.getTok().getLoc(); 3685 // A '#' and a shift amount. 3686 const AsmToken &HashTok = Parser.getTok(); 3687 if (HashTok.isNot(AsmToken::Hash)) 3688 return Error(HashTok.getLoc(), "'#' expected"); 3689 Parser.Lex(); // Eat hash token. 3690 3691 const MCExpr *Expr; 3692 if (getParser().ParseExpression(Expr)) 3693 return true; 3694 // Range check the immediate. 3695 // lsl, ror: 0 <= imm <= 31 3696 // lsr, asr: 0 <= imm <= 32 3697 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 3698 if (!CE) 3699 return Error(Loc, "shift amount must be an immediate"); 3700 int64_t Imm = CE->getValue(); 3701 if (Imm < 0 || 3702 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) || 3703 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32)) 3704 return Error(Loc, "immediate shift value out of range"); 3705 Amount = Imm; 3706 } 3707 3708 return false; 3709} 3710 3711/// parseFPImm - A floating point immediate expression operand. 3712ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3713parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3714 SMLoc S = Parser.getTok().getLoc(); 3715 3716 if (Parser.getTok().isNot(AsmToken::Hash)) 3717 return MatchOperand_NoMatch; 3718 3719 // Disambiguate the VMOV forms that can accept an FP immediate. 3720 // vmov.f32 <sreg>, #imm 3721 // vmov.f64 <dreg>, #imm 3722 // vmov.f32 <dreg>, #imm @ vector f32x2 3723 // vmov.f32 <qreg>, #imm @ vector f32x4 3724 // 3725 // There are also the NEON VMOV instructions which expect an 3726 // integer constant. Make sure we don't try to parse an FPImm 3727 // for these: 3728 // vmov.i{8|16|32|64} <dreg|qreg>, #imm 3729 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]); 3730 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" && 3731 TyOp->getToken() != ".f64")) 3732 return MatchOperand_NoMatch; 3733 3734 Parser.Lex(); // Eat the '#'. 3735 3736 // Handle negation, as that still comes through as a separate token. 3737 bool isNegative = false; 3738 if (Parser.getTok().is(AsmToken::Minus)) { 3739 isNegative = true; 3740 Parser.Lex(); 3741 } 3742 const AsmToken &Tok = Parser.getTok(); 3743 if (Tok.is(AsmToken::Real)) { 3744 APFloat RealVal(APFloat::IEEEdouble, Tok.getString()); 3745 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue(); 3746 // If we had a '-' in front, toggle the sign bit. 3747 IntVal ^= (uint64_t)isNegative << 63; 3748 int Val = ARM_AM::getFP64Imm(APInt(64, IntVal)); 3749 Parser.Lex(); // Eat the token. 3750 if (Val == -1) { 3751 TokError("floating point value out of range"); 3752 return MatchOperand_ParseFail; 3753 } 3754 Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext())); 3755 return MatchOperand_Success; 3756 } 3757 if (Tok.is(AsmToken::Integer)) { 3758 int64_t Val = Tok.getIntVal(); 3759 Parser.Lex(); // Eat the token. 3760 if (Val > 255 || Val < 0) { 3761 TokError("encoded floating point value out of range"); 3762 return MatchOperand_ParseFail; 3763 } 3764 Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext())); 3765 return MatchOperand_Success; 3766 } 3767 3768 TokError("invalid floating point immediate"); 3769 return MatchOperand_ParseFail; 3770} 3771/// Parse a arm instruction operand. For now this parses the operand regardless 3772/// of the mnemonic. 3773bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 3774 StringRef Mnemonic) { 3775 SMLoc S, E; 3776 3777 // Check if the current operand has a custom associated parser, if so, try to 3778 // custom parse the operand, or fallback to the general approach. 3779 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 3780 if (ResTy == MatchOperand_Success) 3781 return false; 3782 // If there wasn't a custom match, try the generic matcher below. Otherwise, 3783 // there was a match, but an error occurred, in which case, just return that 3784 // the operand parsing failed. 3785 if (ResTy == MatchOperand_ParseFail) 3786 return true; 3787 3788 switch (getLexer().getKind()) { 3789 default: 3790 Error(Parser.getTok().getLoc(), "unexpected token in operand"); 3791 return true; 3792 case AsmToken::Identifier: { 3793 // If this is VMRS, check for the apsr_nzcv operand. 3794 if (!tryParseRegisterWithWriteBack(Operands)) 3795 return false; 3796 int Res = tryParseShiftRegister(Operands); 3797 if (Res == 0) // success 3798 return false; 3799 else if (Res == -1) // irrecoverable error 3800 return true; 3801 if (Mnemonic == "vmrs" && Parser.getTok().getString() == "apsr_nzcv") { 3802 S = Parser.getTok().getLoc(); 3803 Parser.Lex(); 3804 Operands.push_back(ARMOperand::CreateToken("apsr_nzcv", S)); 3805 return false; 3806 } 3807 3808 // Fall though for the Identifier case that is not a register or a 3809 // special name. 3810 } 3811 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4) 3812 case AsmToken::Integer: // things like 1f and 2b as a branch targets 3813 case AsmToken::Dot: { // . as a branch target 3814 // This was not a register so parse other operands that start with an 3815 // identifier (like labels) as expressions and create them as immediates. 3816 const MCExpr *IdVal; 3817 S = Parser.getTok().getLoc(); 3818 if (getParser().ParseExpression(IdVal)) 3819 return true; 3820 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 3821 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); 3822 return false; 3823 } 3824 case AsmToken::LBrac: 3825 return parseMemory(Operands); 3826 case AsmToken::LCurly: 3827 return parseRegisterList(Operands); 3828 case AsmToken::Hash: { 3829 // #42 -> immediate. 3830 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate 3831 S = Parser.getTok().getLoc(); 3832 Parser.Lex(); 3833 bool isNegative = Parser.getTok().is(AsmToken::Minus); 3834 const MCExpr *ImmVal; 3835 if (getParser().ParseExpression(ImmVal)) 3836 return true; 3837 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal); 3838 if (CE) { 3839 int32_t Val = CE->getValue(); 3840 if (isNegative && Val == 0) 3841 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext()); 3842 } 3843 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 3844 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); 3845 return false; 3846 } 3847 case AsmToken::Colon: { 3848 // ":lower16:" and ":upper16:" expression prefixes 3849 // FIXME: Check it's an expression prefix, 3850 // e.g. (FOO - :lower16:BAR) isn't legal. 3851 ARMMCExpr::VariantKind RefKind; 3852 if (parsePrefix(RefKind)) 3853 return true; 3854 3855 const MCExpr *SubExprVal; 3856 if (getParser().ParseExpression(SubExprVal)) 3857 return true; 3858 3859 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal, 3860 getContext()); 3861 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 3862 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); 3863 return false; 3864 } 3865 } 3866} 3867 3868// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. 3869// :lower16: and :upper16:. 3870bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) { 3871 RefKind = ARMMCExpr::VK_ARM_None; 3872 3873 // :lower16: and :upper16: modifiers 3874 assert(getLexer().is(AsmToken::Colon) && "expected a :"); 3875 Parser.Lex(); // Eat ':' 3876 3877 if (getLexer().isNot(AsmToken::Identifier)) { 3878 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); 3879 return true; 3880 } 3881 3882 StringRef IDVal = Parser.getTok().getIdentifier(); 3883 if (IDVal == "lower16") { 3884 RefKind = ARMMCExpr::VK_ARM_LO16; 3885 } else if (IDVal == "upper16") { 3886 RefKind = ARMMCExpr::VK_ARM_HI16; 3887 } else { 3888 Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); 3889 return true; 3890 } 3891 Parser.Lex(); 3892 3893 if (getLexer().isNot(AsmToken::Colon)) { 3894 Error(Parser.getTok().getLoc(), "unexpected token after prefix"); 3895 return true; 3896 } 3897 Parser.Lex(); // Eat the last ':' 3898 return false; 3899} 3900 3901/// \brief Given a mnemonic, split out possible predication code and carry 3902/// setting letters to form a canonical mnemonic and flags. 3903// 3904// FIXME: Would be nice to autogen this. 3905// FIXME: This is a bit of a maze of special cases. 3906StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, 3907 unsigned &PredicationCode, 3908 bool &CarrySetting, 3909 unsigned &ProcessorIMod, 3910 StringRef &ITMask) { 3911 PredicationCode = ARMCC::AL; 3912 CarrySetting = false; 3913 ProcessorIMod = 0; 3914 3915 // Ignore some mnemonics we know aren't predicated forms. 3916 // 3917 // FIXME: Would be nice to autogen this. 3918 if ((Mnemonic == "movs" && isThumb()) || 3919 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" || 3920 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || 3921 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" || 3922 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" || 3923 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" || 3924 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || 3925 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal") 3926 return Mnemonic; 3927 3928 // First, split out any predication code. Ignore mnemonics we know aren't 3929 // predicated but do have a carry-set and so weren't caught above. 3930 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && 3931 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" && 3932 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" && 3933 Mnemonic != "sbcs" && Mnemonic != "rscs") { 3934 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2)) 3935 .Case("eq", ARMCC::EQ) 3936 .Case("ne", ARMCC::NE) 3937 .Case("hs", ARMCC::HS) 3938 .Case("cs", ARMCC::HS) 3939 .Case("lo", ARMCC::LO) 3940 .Case("cc", ARMCC::LO) 3941 .Case("mi", ARMCC::MI) 3942 .Case("pl", ARMCC::PL) 3943 .Case("vs", ARMCC::VS) 3944 .Case("vc", ARMCC::VC) 3945 .Case("hi", ARMCC::HI) 3946 .Case("ls", ARMCC::LS) 3947 .Case("ge", ARMCC::GE) 3948 .Case("lt", ARMCC::LT) 3949 .Case("gt", ARMCC::GT) 3950 .Case("le", ARMCC::LE) 3951 .Case("al", ARMCC::AL) 3952 .Default(~0U); 3953 if (CC != ~0U) { 3954 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); 3955 PredicationCode = CC; 3956 } 3957 } 3958 3959 // Next, determine if we have a carry setting bit. We explicitly ignore all 3960 // the instructions we know end in 's'. 3961 if (Mnemonic.endswith("s") && 3962 !(Mnemonic == "cps" || Mnemonic == "mls" || 3963 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" || 3964 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" || 3965 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" || 3966 Mnemonic == "vrsqrts" || Mnemonic == "srs" || 3967 (Mnemonic == "movs" && isThumb()))) { 3968 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); 3969 CarrySetting = true; 3970 } 3971 3972 // The "cps" instruction can have a interrupt mode operand which is glued into 3973 // the mnemonic. Check if this is the case, split it and parse the imod op 3974 if (Mnemonic.startswith("cps")) { 3975 // Split out any imod code. 3976 unsigned IMod = 3977 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2)) 3978 .Case("ie", ARM_PROC::IE) 3979 .Case("id", ARM_PROC::ID) 3980 .Default(~0U); 3981 if (IMod != ~0U) { 3982 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2); 3983 ProcessorIMod = IMod; 3984 } 3985 } 3986 3987 // The "it" instruction has the condition mask on the end of the mnemonic. 3988 if (Mnemonic.startswith("it")) { 3989 ITMask = Mnemonic.slice(2, Mnemonic.size()); 3990 Mnemonic = Mnemonic.slice(0, 2); 3991 } 3992 3993 return Mnemonic; 3994} 3995 3996/// \brief Given a canonical mnemonic, determine if the instruction ever allows 3997/// inclusion of carry set or predication code operands. 3998// 3999// FIXME: It would be nice to autogen this. 4000void ARMAsmParser:: 4001getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 4002 bool &CanAcceptPredicationCode) { 4003 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || 4004 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || 4005 Mnemonic == "add" || Mnemonic == "adc" || 4006 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" || 4007 Mnemonic == "orr" || Mnemonic == "mvn" || 4008 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || 4009 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" || 4010 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" || 4011 Mnemonic == "mla" || Mnemonic == "smlal" || 4012 Mnemonic == "umlal" || Mnemonic == "umull"))) { 4013 CanAcceptCarrySet = true; 4014 } else 4015 CanAcceptCarrySet = false; 4016 4017 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" || 4018 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" || 4019 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" || 4020 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" || 4021 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" || 4022 (Mnemonic == "clrex" && !isThumb()) || 4023 (Mnemonic == "nop" && isThumbOne()) || 4024 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" || 4025 Mnemonic == "ldc2" || Mnemonic == "ldc2l" || 4026 Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) || 4027 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) && 4028 !isThumb()) || 4029 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) { 4030 CanAcceptPredicationCode = false; 4031 } else 4032 CanAcceptPredicationCode = true; 4033 4034 if (isThumb()) { 4035 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" || 4036 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp") 4037 CanAcceptPredicationCode = false; 4038 } 4039} 4040 4041bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic, 4042 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4043 // FIXME: This is all horribly hacky. We really need a better way to deal 4044 // with optional operands like this in the matcher table. 4045 4046 // The 'mov' mnemonic is special. One variant has a cc_out operand, while 4047 // another does not. Specifically, the MOVW instruction does not. So we 4048 // special case it here and remove the defaulted (non-setting) cc_out 4049 // operand if that's the instruction we're trying to match. 4050 // 4051 // We do this as post-processing of the explicit operands rather than just 4052 // conditionally adding the cc_out in the first place because we need 4053 // to check the type of the parsed immediate operand. 4054 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() && 4055 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() && 4056 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() && 4057 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 4058 return true; 4059 4060 // Register-register 'add' for thumb does not have a cc_out operand 4061 // when there are only two register operands. 4062 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && 4063 static_cast<ARMOperand*>(Operands[3])->isReg() && 4064 static_cast<ARMOperand*>(Operands[4])->isReg() && 4065 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 4066 return true; 4067 // Register-register 'add' for thumb does not have a cc_out operand 4068 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do 4069 // have to check the immediate range here since Thumb2 has a variant 4070 // that can handle a different range and has a cc_out operand. 4071 if (((isThumb() && Mnemonic == "add") || 4072 (isThumbTwo() && Mnemonic == "sub")) && 4073 Operands.size() == 6 && 4074 static_cast<ARMOperand*>(Operands[3])->isReg() && 4075 static_cast<ARMOperand*>(Operands[4])->isReg() && 4076 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP && 4077 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4078 (static_cast<ARMOperand*>(Operands[5])->isReg() || 4079 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4())) 4080 return true; 4081 // For Thumb2, add/sub immediate does not have a cc_out operand for the 4082 // imm0_4095 variant. That's the least-preferred variant when 4083 // selecting via the generic "add" mnemonic, so to know that we 4084 // should remove the cc_out operand, we have to explicitly check that 4085 // it's not one of the other variants. Ugh. 4086 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") && 4087 Operands.size() == 6 && 4088 static_cast<ARMOperand*>(Operands[3])->isReg() && 4089 static_cast<ARMOperand*>(Operands[4])->isReg() && 4090 static_cast<ARMOperand*>(Operands[5])->isImm()) { 4091 // Nest conditions rather than one big 'if' statement for readability. 4092 // 4093 // If either register is a high reg, it's either one of the SP 4094 // variants (handled above) or a 32-bit encoding, so we just 4095 // check against T3. 4096 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 4097 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) && 4098 static_cast<ARMOperand*>(Operands[5])->isT2SOImm()) 4099 return false; 4100 // If both registers are low, we're in an IT block, and the immediate is 4101 // in range, we should use encoding T1 instead, which has a cc_out. 4102 if (inITBlock() && 4103 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) && 4104 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) && 4105 static_cast<ARMOperand*>(Operands[5])->isImm0_7()) 4106 return false; 4107 4108 // Otherwise, we use encoding T4, which does not have a cc_out 4109 // operand. 4110 return true; 4111 } 4112 4113 // The thumb2 multiply instruction doesn't have a CCOut register, so 4114 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to 4115 // use the 16-bit encoding or not. 4116 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 && 4117 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4118 static_cast<ARMOperand*>(Operands[3])->isReg() && 4119 static_cast<ARMOperand*>(Operands[4])->isReg() && 4120 static_cast<ARMOperand*>(Operands[5])->isReg() && 4121 // If the registers aren't low regs, the destination reg isn't the 4122 // same as one of the source regs, or the cc_out operand is zero 4123 // outside of an IT block, we have to use the 32-bit encoding, so 4124 // remove the cc_out operand. 4125 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 4126 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 4127 !inITBlock() || 4128 (static_cast<ARMOperand*>(Operands[3])->getReg() != 4129 static_cast<ARMOperand*>(Operands[5])->getReg() && 4130 static_cast<ARMOperand*>(Operands[3])->getReg() != 4131 static_cast<ARMOperand*>(Operands[4])->getReg()))) 4132 return true; 4133 4134 4135 4136 // Register-register 'add/sub' for thumb does not have a cc_out operand 4137 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also 4138 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't 4139 // right, this will result in better diagnostics (which operand is off) 4140 // anyway. 4141 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") && 4142 (Operands.size() == 5 || Operands.size() == 6) && 4143 static_cast<ARMOperand*>(Operands[3])->isReg() && 4144 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP && 4145 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 4146 return true; 4147 4148 return false; 4149} 4150 4151/// Parse an arm instruction mnemonic followed by its operands. 4152bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc, 4153 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4154 // Create the leading tokens for the mnemonic, split by '.' characters. 4155 size_t Start = 0, Next = Name.find('.'); 4156 StringRef Mnemonic = Name.slice(Start, Next); 4157 4158 // Split out the predication code and carry setting flag from the mnemonic. 4159 unsigned PredicationCode; 4160 unsigned ProcessorIMod; 4161 bool CarrySetting; 4162 StringRef ITMask; 4163 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting, 4164 ProcessorIMod, ITMask); 4165 4166 // In Thumb1, only the branch (B) instruction can be predicated. 4167 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") { 4168 Parser.EatToEndOfStatement(); 4169 return Error(NameLoc, "conditional execution not supported in Thumb1"); 4170 } 4171 4172 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); 4173 4174 // Handle the IT instruction ITMask. Convert it to a bitmask. This 4175 // is the mask as it will be for the IT encoding if the conditional 4176 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case 4177 // where the conditional bit0 is zero, the instruction post-processing 4178 // will adjust the mask accordingly. 4179 if (Mnemonic == "it") { 4180 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2); 4181 if (ITMask.size() > 3) { 4182 Parser.EatToEndOfStatement(); 4183 return Error(Loc, "too many conditions on IT instruction"); 4184 } 4185 unsigned Mask = 8; 4186 for (unsigned i = ITMask.size(); i != 0; --i) { 4187 char pos = ITMask[i - 1]; 4188 if (pos != 't' && pos != 'e') { 4189 Parser.EatToEndOfStatement(); 4190 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'"); 4191 } 4192 Mask >>= 1; 4193 if (ITMask[i - 1] == 't') 4194 Mask |= 8; 4195 } 4196 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); 4197 } 4198 4199 // FIXME: This is all a pretty gross hack. We should automatically handle 4200 // optional operands like this via tblgen. 4201 4202 // Next, add the CCOut and ConditionCode operands, if needed. 4203 // 4204 // For mnemonics which can ever incorporate a carry setting bit or predication 4205 // code, our matching model involves us always generating CCOut and 4206 // ConditionCode operands to match the mnemonic "as written" and then we let 4207 // the matcher deal with finding the right instruction or generating an 4208 // appropriate error. 4209 bool CanAcceptCarrySet, CanAcceptPredicationCode; 4210 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode); 4211 4212 // If we had a carry-set on an instruction that can't do that, issue an 4213 // error. 4214 if (!CanAcceptCarrySet && CarrySetting) { 4215 Parser.EatToEndOfStatement(); 4216 return Error(NameLoc, "instruction '" + Mnemonic + 4217 "' can not set flags, but 's' suffix specified"); 4218 } 4219 // If we had a predication code on an instruction that can't do that, issue an 4220 // error. 4221 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) { 4222 Parser.EatToEndOfStatement(); 4223 return Error(NameLoc, "instruction '" + Mnemonic + 4224 "' is not predicable, but condition code specified"); 4225 } 4226 4227 // Add the carry setting operand, if necessary. 4228 if (CanAcceptCarrySet) { 4229 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size()); 4230 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, 4231 Loc)); 4232 } 4233 4234 // Add the predication code operand, if necessary. 4235 if (CanAcceptPredicationCode) { 4236 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() + 4237 CarrySetting); 4238 Operands.push_back(ARMOperand::CreateCondCode( 4239 ARMCC::CondCodes(PredicationCode), Loc)); 4240 } 4241 4242 // Add the processor imod operand, if necessary. 4243 if (ProcessorIMod) { 4244 Operands.push_back(ARMOperand::CreateImm( 4245 MCConstantExpr::Create(ProcessorIMod, getContext()), 4246 NameLoc, NameLoc)); 4247 } 4248 4249 // Add the remaining tokens in the mnemonic. 4250 while (Next != StringRef::npos) { 4251 Start = Next; 4252 Next = Name.find('.', Start + 1); 4253 StringRef ExtraToken = Name.slice(Start, Next); 4254 4255 // For now, we're only parsing Thumb1 (for the most part), so 4256 // just ignore ".n" qualifiers. We'll use them to restrict 4257 // matching when we do Thumb2. 4258 if (ExtraToken != ".n") { 4259 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 4260 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc)); 4261 } 4262 } 4263 4264 // Read the remaining operands. 4265 if (getLexer().isNot(AsmToken::EndOfStatement)) { 4266 // Read the first operand. 4267 if (parseOperand(Operands, Mnemonic)) { 4268 Parser.EatToEndOfStatement(); 4269 return true; 4270 } 4271 4272 while (getLexer().is(AsmToken::Comma)) { 4273 Parser.Lex(); // Eat the comma. 4274 4275 // Parse and remember the operand. 4276 if (parseOperand(Operands, Mnemonic)) { 4277 Parser.EatToEndOfStatement(); 4278 return true; 4279 } 4280 } 4281 } 4282 4283 if (getLexer().isNot(AsmToken::EndOfStatement)) { 4284 SMLoc Loc = getLexer().getLoc(); 4285 Parser.EatToEndOfStatement(); 4286 return Error(Loc, "unexpected token in argument list"); 4287 } 4288 4289 Parser.Lex(); // Consume the EndOfStatement 4290 4291 // Some instructions, mostly Thumb, have forms for the same mnemonic that 4292 // do and don't have a cc_out optional-def operand. With some spot-checks 4293 // of the operand list, we can figure out which variant we're trying to 4294 // parse and adjust accordingly before actually matching. We shouldn't ever 4295 // try to remove a cc_out operand that was explicitly set on the the 4296 // mnemonic, of course (CarrySetting == true). Reason number #317 the 4297 // table driven matcher doesn't fit well with the ARM instruction set. 4298 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) { 4299 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 4300 Operands.erase(Operands.begin() + 1); 4301 delete Op; 4302 } 4303 4304 // ARM mode 'blx' need special handling, as the register operand version 4305 // is predicable, but the label operand version is not. So, we can't rely 4306 // on the Mnemonic based checking to correctly figure out when to put 4307 // a k_CondCode operand in the list. If we're trying to match the label 4308 // version, remove the k_CondCode operand here. 4309 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && 4310 static_cast<ARMOperand*>(Operands[2])->isImm()) { 4311 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 4312 Operands.erase(Operands.begin() + 1); 4313 delete Op; 4314 } 4315 4316 // The vector-compare-to-zero instructions have a literal token "#0" at 4317 // the end that comes to here as an immediate operand. Convert it to a 4318 // token to play nicely with the matcher. 4319 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" || 4320 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 && 4321 static_cast<ARMOperand*>(Operands[5])->isImm()) { 4322 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]); 4323 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 4324 if (CE && CE->getValue() == 0) { 4325 Operands.erase(Operands.begin() + 5); 4326 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 4327 delete Op; 4328 } 4329 } 4330 // VCMP{E} does the same thing, but with a different operand count. 4331 if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 && 4332 static_cast<ARMOperand*>(Operands[4])->isImm()) { 4333 ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]); 4334 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 4335 if (CE && CE->getValue() == 0) { 4336 Operands.erase(Operands.begin() + 4); 4337 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 4338 delete Op; 4339 } 4340 } 4341 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the 4342 // end. Convert it to a token here. 4343 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 && 4344 static_cast<ARMOperand*>(Operands[5])->isImm()) { 4345 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]); 4346 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 4347 if (CE && CE->getValue() == 0) { 4348 Operands.erase(Operands.begin() + 5); 4349 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 4350 delete Op; 4351 } 4352 } 4353 4354 return false; 4355} 4356 4357// Validate context-sensitive operand constraints. 4358 4359// return 'true' if register list contains non-low GPR registers, 4360// 'false' otherwise. If Reg is in the register list or is HiReg, set 4361// 'containsReg' to true. 4362static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, 4363 unsigned HiReg, bool &containsReg) { 4364 containsReg = false; 4365 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 4366 unsigned OpReg = Inst.getOperand(i).getReg(); 4367 if (OpReg == Reg) 4368 containsReg = true; 4369 // Anything other than a low register isn't legal here. 4370 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) 4371 return true; 4372 } 4373 return false; 4374} 4375 4376// Check if the specified regisgter is in the register list of the inst, 4377// starting at the indicated operand number. 4378static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) { 4379 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 4380 unsigned OpReg = Inst.getOperand(i).getReg(); 4381 if (OpReg == Reg) 4382 return true; 4383 } 4384 return false; 4385} 4386 4387// FIXME: We would really prefer to have MCInstrInfo (the wrapper around 4388// the ARMInsts array) instead. Getting that here requires awkward 4389// API changes, though. Better way? 4390namespace llvm { 4391extern const MCInstrDesc ARMInsts[]; 4392} 4393static const MCInstrDesc &getInstDesc(unsigned Opcode) { 4394 return ARMInsts[Opcode]; 4395} 4396 4397// FIXME: We would really like to be able to tablegen'erate this. 4398bool ARMAsmParser:: 4399validateInstruction(MCInst &Inst, 4400 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4401 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode()); 4402 SMLoc Loc = Operands[0]->getStartLoc(); 4403 // Check the IT block state first. 4404 // NOTE: In Thumb mode, the BKPT instruction has the interesting property of 4405 // being allowed in IT blocks, but not being predicable. It just always 4406 // executes. 4407 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT) { 4408 unsigned bit = 1; 4409 if (ITState.FirstCond) 4410 ITState.FirstCond = false; 4411 else 4412 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1; 4413 // The instruction must be predicable. 4414 if (!MCID.isPredicable()) 4415 return Error(Loc, "instructions in IT block must be predicable"); 4416 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm(); 4417 unsigned ITCond = bit ? ITState.Cond : 4418 ARMCC::getOppositeCondition(ITState.Cond); 4419 if (Cond != ITCond) { 4420 // Find the condition code Operand to get its SMLoc information. 4421 SMLoc CondLoc; 4422 for (unsigned i = 1; i < Operands.size(); ++i) 4423 if (static_cast<ARMOperand*>(Operands[i])->isCondCode()) 4424 CondLoc = Operands[i]->getStartLoc(); 4425 return Error(CondLoc, "incorrect condition in IT block; got '" + 4426 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) + 4427 "', but expected '" + 4428 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'"); 4429 } 4430 // Check for non-'al' condition codes outside of the IT block. 4431 } else if (isThumbTwo() && MCID.isPredicable() && 4432 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != 4433 ARMCC::AL && Inst.getOpcode() != ARM::tB && 4434 Inst.getOpcode() != ARM::t2B) 4435 return Error(Loc, "predicated instructions must be in IT block"); 4436 4437 switch (Inst.getOpcode()) { 4438 case ARM::LDRD: 4439 case ARM::LDRD_PRE: 4440 case ARM::LDRD_POST: 4441 case ARM::LDREXD: { 4442 // Rt2 must be Rt + 1. 4443 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg()); 4444 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 4445 if (Rt2 != Rt + 1) 4446 return Error(Operands[3]->getStartLoc(), 4447 "destination operands must be sequential"); 4448 return false; 4449 } 4450 case ARM::STRD: { 4451 // Rt2 must be Rt + 1. 4452 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg()); 4453 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 4454 if (Rt2 != Rt + 1) 4455 return Error(Operands[3]->getStartLoc(), 4456 "source operands must be sequential"); 4457 return false; 4458 } 4459 case ARM::STRD_PRE: 4460 case ARM::STRD_POST: 4461 case ARM::STREXD: { 4462 // Rt2 must be Rt + 1. 4463 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 4464 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg()); 4465 if (Rt2 != Rt + 1) 4466 return Error(Operands[3]->getStartLoc(), 4467 "source operands must be sequential"); 4468 return false; 4469 } 4470 case ARM::SBFX: 4471 case ARM::UBFX: { 4472 // width must be in range [1, 32-lsb] 4473 unsigned lsb = Inst.getOperand(2).getImm(); 4474 unsigned widthm1 = Inst.getOperand(3).getImm(); 4475 if (widthm1 >= 32 - lsb) 4476 return Error(Operands[5]->getStartLoc(), 4477 "bitfield width must be in range [1,32-lsb]"); 4478 return false; 4479 } 4480 case ARM::tLDMIA: { 4481 // If we're parsing Thumb2, the .w variant is available and handles 4482 // most cases that are normally illegal for a Thumb1 LDM 4483 // instruction. We'll make the transformation in processInstruction() 4484 // if necessary. 4485 // 4486 // Thumb LDM instructions are writeback iff the base register is not 4487 // in the register list. 4488 unsigned Rn = Inst.getOperand(0).getReg(); 4489 bool hasWritebackToken = 4490 (static_cast<ARMOperand*>(Operands[3])->isToken() && 4491 static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 4492 bool listContainsBase; 4493 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo()) 4494 return Error(Operands[3 + hasWritebackToken]->getStartLoc(), 4495 "registers must be in range r0-r7"); 4496 // If we should have writeback, then there should be a '!' token. 4497 if (!listContainsBase && !hasWritebackToken && !isThumbTwo()) 4498 return Error(Operands[2]->getStartLoc(), 4499 "writeback operator '!' expected"); 4500 // If we should not have writeback, there must not be a '!'. This is 4501 // true even for the 32-bit wide encodings. 4502 if (listContainsBase && hasWritebackToken) 4503 return Error(Operands[3]->getStartLoc(), 4504 "writeback operator '!' not allowed when base register " 4505 "in register list"); 4506 4507 break; 4508 } 4509 case ARM::t2LDMIA_UPD: { 4510 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) 4511 return Error(Operands[4]->getStartLoc(), 4512 "writeback operator '!' not allowed when base register " 4513 "in register list"); 4514 break; 4515 } 4516 case ARM::tPOP: { 4517 bool listContainsBase; 4518 if (checkLowRegisterList(Inst, 3, 0, ARM::PC, listContainsBase)) 4519 return Error(Operands[2]->getStartLoc(), 4520 "registers must be in range r0-r7 or pc"); 4521 break; 4522 } 4523 case ARM::tPUSH: { 4524 bool listContainsBase; 4525 if (checkLowRegisterList(Inst, 3, 0, ARM::LR, listContainsBase)) 4526 return Error(Operands[2]->getStartLoc(), 4527 "registers must be in range r0-r7 or lr"); 4528 break; 4529 } 4530 case ARM::tSTMIA_UPD: { 4531 bool listContainsBase; 4532 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo()) 4533 return Error(Operands[4]->getStartLoc(), 4534 "registers must be in range r0-r7"); 4535 break; 4536 } 4537 } 4538 4539 return false; 4540} 4541 4542void ARMAsmParser:: 4543processInstruction(MCInst &Inst, 4544 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4545 switch (Inst.getOpcode()) { 4546 case ARM::LDMIA_UPD: 4547 // If this is a load of a single register via a 'pop', then we should use 4548 // a post-indexed LDR instruction instead, per the ARM ARM. 4549 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" && 4550 Inst.getNumOperands() == 5) { 4551 MCInst TmpInst; 4552 TmpInst.setOpcode(ARM::LDR_POST_IMM); 4553 TmpInst.addOperand(Inst.getOperand(4)); // Rt 4554 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 4555 TmpInst.addOperand(Inst.getOperand(1)); // Rn 4556 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset 4557 TmpInst.addOperand(MCOperand::CreateImm(4)); 4558 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 4559 TmpInst.addOperand(Inst.getOperand(3)); 4560 Inst = TmpInst; 4561 } 4562 break; 4563 case ARM::STMDB_UPD: 4564 // If this is a store of a single register via a 'push', then we should use 4565 // a pre-indexed STR instruction instead, per the ARM ARM. 4566 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" && 4567 Inst.getNumOperands() == 5) { 4568 MCInst TmpInst; 4569 TmpInst.setOpcode(ARM::STR_PRE_IMM); 4570 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 4571 TmpInst.addOperand(Inst.getOperand(4)); // Rt 4572 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12 4573 TmpInst.addOperand(MCOperand::CreateImm(-4)); 4574 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 4575 TmpInst.addOperand(Inst.getOperand(3)); 4576 Inst = TmpInst; 4577 } 4578 break; 4579 case ARM::tADDi8: 4580 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 4581 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 4582 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 4583 // to encoding T1 if <Rd> is omitted." 4584 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) 4585 Inst.setOpcode(ARM::tADDi3); 4586 break; 4587 case ARM::tSUBi8: 4588 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 4589 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 4590 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 4591 // to encoding T1 if <Rd> is omitted." 4592 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) 4593 Inst.setOpcode(ARM::tSUBi3); 4594 break; 4595 case ARM::tB: 4596 // A Thumb conditional branch outside of an IT block is a tBcc. 4597 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) 4598 Inst.setOpcode(ARM::tBcc); 4599 break; 4600 case ARM::t2B: 4601 // A Thumb2 conditional branch outside of an IT block is a t2Bcc. 4602 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) 4603 Inst.setOpcode(ARM::t2Bcc); 4604 break; 4605 case ARM::t2Bcc: 4606 // If the conditional is AL or we're in an IT block, we really want t2B. 4607 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) 4608 Inst.setOpcode(ARM::t2B); 4609 break; 4610 case ARM::tBcc: 4611 // If the conditional is AL, we really want tB. 4612 if (Inst.getOperand(1).getImm() == ARMCC::AL) 4613 Inst.setOpcode(ARM::tB); 4614 break; 4615 case ARM::tLDMIA: { 4616 // If the register list contains any high registers, or if the writeback 4617 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding 4618 // instead if we're in Thumb2. Otherwise, this should have generated 4619 // an error in validateInstruction(). 4620 unsigned Rn = Inst.getOperand(0).getReg(); 4621 bool hasWritebackToken = 4622 (static_cast<ARMOperand*>(Operands[3])->isToken() && 4623 static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 4624 bool listContainsBase; 4625 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) || 4626 (!listContainsBase && !hasWritebackToken) || 4627 (listContainsBase && hasWritebackToken)) { 4628 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 4629 assert (isThumbTwo()); 4630 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); 4631 // If we're switching to the updating version, we need to insert 4632 // the writeback tied operand. 4633 if (hasWritebackToken) 4634 Inst.insert(Inst.begin(), 4635 MCOperand::CreateReg(Inst.getOperand(0).getReg())); 4636 } 4637 break; 4638 } 4639 case ARM::tSTMIA_UPD: { 4640 // If the register list contains any high registers, we need to use 4641 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 4642 // should have generated an error in validateInstruction(). 4643 unsigned Rn = Inst.getOperand(0).getReg(); 4644 bool listContainsBase; 4645 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) { 4646 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 4647 assert (isThumbTwo()); 4648 Inst.setOpcode(ARM::t2STMIA_UPD); 4649 } 4650 break; 4651 } 4652 case ARM::t2MOVi: { 4653 // If we can use the 16-bit encoding and the user didn't explicitly 4654 // request the 32-bit variant, transform it here. 4655 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 4656 Inst.getOperand(1).getImm() <= 255 && 4657 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL && 4658 Inst.getOperand(4).getReg() == ARM::CPSR) || 4659 (inITBlock() && Inst.getOperand(4).getReg() == 0)) && 4660 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 4661 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 4662 // The operands aren't in the same order for tMOVi8... 4663 MCInst TmpInst; 4664 TmpInst.setOpcode(ARM::tMOVi8); 4665 TmpInst.addOperand(Inst.getOperand(0)); 4666 TmpInst.addOperand(Inst.getOperand(4)); 4667 TmpInst.addOperand(Inst.getOperand(1)); 4668 TmpInst.addOperand(Inst.getOperand(2)); 4669 TmpInst.addOperand(Inst.getOperand(3)); 4670 Inst = TmpInst; 4671 } 4672 break; 4673 } 4674 case ARM::t2MOVr: { 4675 // If we can use the 16-bit encoding and the user didn't explicitly 4676 // request the 32-bit variant, transform it here. 4677 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 4678 isARMLowRegister(Inst.getOperand(1).getReg()) && 4679 Inst.getOperand(2).getImm() == ARMCC::AL && 4680 Inst.getOperand(4).getReg() == ARM::CPSR && 4681 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 4682 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 4683 // The operands aren't the same for tMOV[S]r... (no cc_out) 4684 MCInst TmpInst; 4685 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr); 4686 TmpInst.addOperand(Inst.getOperand(0)); 4687 TmpInst.addOperand(Inst.getOperand(1)); 4688 TmpInst.addOperand(Inst.getOperand(2)); 4689 TmpInst.addOperand(Inst.getOperand(3)); 4690 Inst = TmpInst; 4691 } 4692 break; 4693 } 4694 case ARM::t2SXTH: 4695 case ARM::t2SXTB: 4696 case ARM::t2UXTH: 4697 case ARM::t2UXTB: { 4698 // If we can use the 16-bit encoding and the user didn't explicitly 4699 // request the 32-bit variant, transform it here. 4700 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 4701 isARMLowRegister(Inst.getOperand(1).getReg()) && 4702 Inst.getOperand(2).getImm() == 0 && 4703 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 4704 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 4705 unsigned NewOpc; 4706 switch (Inst.getOpcode()) { 4707 default: llvm_unreachable("Illegal opcode!"); 4708 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; 4709 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; 4710 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; 4711 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break; 4712 } 4713 // The operands aren't the same for thumb1 (no rotate operand). 4714 MCInst TmpInst; 4715 TmpInst.setOpcode(NewOpc); 4716 TmpInst.addOperand(Inst.getOperand(0)); 4717 TmpInst.addOperand(Inst.getOperand(1)); 4718 TmpInst.addOperand(Inst.getOperand(3)); 4719 TmpInst.addOperand(Inst.getOperand(4)); 4720 Inst = TmpInst; 4721 } 4722 break; 4723 } 4724 case ARM::t2IT: { 4725 // The mask bits for all but the first condition are represented as 4726 // the low bit of the condition code value implies 't'. We currently 4727 // always have 1 implies 't', so XOR toggle the bits if the low bit 4728 // of the condition code is zero. The encoding also expects the low 4729 // bit of the condition to be encoded as bit 4 of the mask operand, 4730 // so mask that in if needed 4731 MCOperand &MO = Inst.getOperand(1); 4732 unsigned Mask = MO.getImm(); 4733 unsigned OrigMask = Mask; 4734 unsigned TZ = CountTrailingZeros_32(Mask); 4735 if ((Inst.getOperand(0).getImm() & 1) == 0) { 4736 assert(Mask && TZ <= 3 && "illegal IT mask value!"); 4737 for (unsigned i = 3; i != TZ; --i) 4738 Mask ^= 1 << i; 4739 } else 4740 Mask |= 0x10; 4741 MO.setImm(Mask); 4742 4743 // Set up the IT block state according to the IT instruction we just 4744 // matched. 4745 assert(!inITBlock() && "nested IT blocks?!"); 4746 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm()); 4747 ITState.Mask = OrigMask; // Use the original mask, not the updated one. 4748 ITState.CurPosition = 0; 4749 ITState.FirstCond = true; 4750 break; 4751 } 4752 } 4753} 4754 4755unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) { 4756 // 16-bit thumb arithmetic instructions either require or preclude the 'S' 4757 // suffix depending on whether they're in an IT block or not. 4758 unsigned Opc = Inst.getOpcode(); 4759 const MCInstrDesc &MCID = getInstDesc(Opc); 4760 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) { 4761 assert(MCID.hasOptionalDef() && 4762 "optionally flag setting instruction missing optional def operand"); 4763 assert(MCID.NumOperands == Inst.getNumOperands() && 4764 "operand count mismatch!"); 4765 // Find the optional-def operand (cc_out). 4766 unsigned OpNo; 4767 for (OpNo = 0; 4768 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands; 4769 ++OpNo) 4770 ; 4771 // If we're parsing Thumb1, reject it completely. 4772 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) 4773 return Match_MnemonicFail; 4774 // If we're parsing Thumb2, which form is legal depends on whether we're 4775 // in an IT block. 4776 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && 4777 !inITBlock()) 4778 return Match_RequiresITBlock; 4779 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && 4780 inITBlock()) 4781 return Match_RequiresNotITBlock; 4782 } 4783 // Some high-register supporting Thumb1 encodings only allow both registers 4784 // to be from r0-r7 when in Thumb2. 4785 else if (Opc == ARM::tADDhirr && isThumbOne() && 4786 isARMLowRegister(Inst.getOperand(1).getReg()) && 4787 isARMLowRegister(Inst.getOperand(2).getReg())) 4788 return Match_RequiresThumb2; 4789 // Others only require ARMv6 or later. 4790 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() && 4791 isARMLowRegister(Inst.getOperand(0).getReg()) && 4792 isARMLowRegister(Inst.getOperand(1).getReg())) 4793 return Match_RequiresV6; 4794 return Match_Success; 4795} 4796 4797bool ARMAsmParser:: 4798MatchAndEmitInstruction(SMLoc IDLoc, 4799 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 4800 MCStreamer &Out) { 4801 MCInst Inst; 4802 unsigned ErrorInfo; 4803 unsigned MatchResult; 4804 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo); 4805 switch (MatchResult) { 4806 default: break; 4807 case Match_Success: 4808 // Context sensitive operand constraints aren't handled by the matcher, 4809 // so check them here. 4810 if (validateInstruction(Inst, Operands)) { 4811 // Still progress the IT block, otherwise one wrong condition causes 4812 // nasty cascading errors. 4813 forwardITPosition(); 4814 return true; 4815 } 4816 4817 // Some instructions need post-processing to, for example, tweak which 4818 // encoding is selected. 4819 processInstruction(Inst, Operands); 4820 4821 // Only move forward at the very end so that everything in validate 4822 // and process gets a consistent answer about whether we're in an IT 4823 // block. 4824 forwardITPosition(); 4825 4826 Out.EmitInstruction(Inst); 4827 return false; 4828 case Match_MissingFeature: 4829 Error(IDLoc, "instruction requires a CPU feature not currently enabled"); 4830 return true; 4831 case Match_InvalidOperand: { 4832 SMLoc ErrorLoc = IDLoc; 4833 if (ErrorInfo != ~0U) { 4834 if (ErrorInfo >= Operands.size()) 4835 return Error(IDLoc, "too few operands for instruction"); 4836 4837 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 4838 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 4839 } 4840 4841 return Error(ErrorLoc, "invalid operand for instruction"); 4842 } 4843 case Match_MnemonicFail: 4844 return Error(IDLoc, "invalid instruction"); 4845 case Match_ConversionFail: 4846 // The converter function will have already emited a diagnostic. 4847 return true; 4848 case Match_RequiresNotITBlock: 4849 return Error(IDLoc, "flag setting instruction only valid outside IT block"); 4850 case Match_RequiresITBlock: 4851 return Error(IDLoc, "instruction only valid inside IT block"); 4852 case Match_RequiresV6: 4853 return Error(IDLoc, "instruction variant requires ARMv6 or later"); 4854 case Match_RequiresThumb2: 4855 return Error(IDLoc, "instruction variant requires Thumb2"); 4856 } 4857 4858 llvm_unreachable("Implement any new match types added!"); 4859 return true; 4860} 4861 4862/// parseDirective parses the arm specific directives 4863bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { 4864 StringRef IDVal = DirectiveID.getIdentifier(); 4865 if (IDVal == ".word") 4866 return parseDirectiveWord(4, DirectiveID.getLoc()); 4867 else if (IDVal == ".thumb") 4868 return parseDirectiveThumb(DirectiveID.getLoc()); 4869 else if (IDVal == ".thumb_func") 4870 return parseDirectiveThumbFunc(DirectiveID.getLoc()); 4871 else if (IDVal == ".code") 4872 return parseDirectiveCode(DirectiveID.getLoc()); 4873 else if (IDVal == ".syntax") 4874 return parseDirectiveSyntax(DirectiveID.getLoc()); 4875 return true; 4876} 4877 4878/// parseDirectiveWord 4879/// ::= .word [ expression (, expression)* ] 4880bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) { 4881 if (getLexer().isNot(AsmToken::EndOfStatement)) { 4882 for (;;) { 4883 const MCExpr *Value; 4884 if (getParser().ParseExpression(Value)) 4885 return true; 4886 4887 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/); 4888 4889 if (getLexer().is(AsmToken::EndOfStatement)) 4890 break; 4891 4892 // FIXME: Improve diagnostic. 4893 if (getLexer().isNot(AsmToken::Comma)) 4894 return Error(L, "unexpected token in directive"); 4895 Parser.Lex(); 4896 } 4897 } 4898 4899 Parser.Lex(); 4900 return false; 4901} 4902 4903/// parseDirectiveThumb 4904/// ::= .thumb 4905bool ARMAsmParser::parseDirectiveThumb(SMLoc L) { 4906 if (getLexer().isNot(AsmToken::EndOfStatement)) 4907 return Error(L, "unexpected token in directive"); 4908 Parser.Lex(); 4909 4910 // TODO: set thumb mode 4911 // TODO: tell the MC streamer the mode 4912 // getParser().getStreamer().Emit???(); 4913 return false; 4914} 4915 4916/// parseDirectiveThumbFunc 4917/// ::= .thumbfunc symbol_name 4918bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) { 4919 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo(); 4920 bool isMachO = MAI.hasSubsectionsViaSymbols(); 4921 StringRef Name; 4922 4923 // Darwin asm has function name after .thumb_func direction 4924 // ELF doesn't 4925 if (isMachO) { 4926 const AsmToken &Tok = Parser.getTok(); 4927 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) 4928 return Error(L, "unexpected token in .thumb_func directive"); 4929 Name = Tok.getString(); 4930 Parser.Lex(); // Consume the identifier token. 4931 } 4932 4933 if (getLexer().isNot(AsmToken::EndOfStatement)) 4934 return Error(L, "unexpected token in directive"); 4935 Parser.Lex(); 4936 4937 // FIXME: assuming function name will be the line following .thumb_func 4938 if (!isMachO) { 4939 Name = Parser.getTok().getString(); 4940 } 4941 4942 // Mark symbol as a thumb symbol. 4943 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name); 4944 getParser().getStreamer().EmitThumbFunc(Func); 4945 return false; 4946} 4947 4948/// parseDirectiveSyntax 4949/// ::= .syntax unified | divided 4950bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) { 4951 const AsmToken &Tok = Parser.getTok(); 4952 if (Tok.isNot(AsmToken::Identifier)) 4953 return Error(L, "unexpected token in .syntax directive"); 4954 StringRef Mode = Tok.getString(); 4955 if (Mode == "unified" || Mode == "UNIFIED") 4956 Parser.Lex(); 4957 else if (Mode == "divided" || Mode == "DIVIDED") 4958 return Error(L, "'.syntax divided' arm asssembly not supported"); 4959 else 4960 return Error(L, "unrecognized syntax mode in .syntax directive"); 4961 4962 if (getLexer().isNot(AsmToken::EndOfStatement)) 4963 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 4964 Parser.Lex(); 4965 4966 // TODO tell the MC streamer the mode 4967 // getParser().getStreamer().Emit???(); 4968 return false; 4969} 4970 4971/// parseDirectiveCode 4972/// ::= .code 16 | 32 4973bool ARMAsmParser::parseDirectiveCode(SMLoc L) { 4974 const AsmToken &Tok = Parser.getTok(); 4975 if (Tok.isNot(AsmToken::Integer)) 4976 return Error(L, "unexpected token in .code directive"); 4977 int64_t Val = Parser.getTok().getIntVal(); 4978 if (Val == 16) 4979 Parser.Lex(); 4980 else if (Val == 32) 4981 Parser.Lex(); 4982 else 4983 return Error(L, "invalid operand to .code directive"); 4984 4985 if (getLexer().isNot(AsmToken::EndOfStatement)) 4986 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 4987 Parser.Lex(); 4988 4989 if (Val == 16) { 4990 if (!isThumb()) 4991 SwitchMode(); 4992 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 4993 } else { 4994 if (isThumb()) 4995 SwitchMode(); 4996 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 4997 } 4998 4999 return false; 5000} 5001 5002extern "C" void LLVMInitializeARMAsmLexer(); 5003 5004/// Force static initialization. 5005extern "C" void LLVMInitializeARMAsmParser() { 5006 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget); 5007 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget); 5008 LLVMInitializeARMAsmLexer(); 5009} 5010 5011#define GET_REGISTER_MATCHER 5012#define GET_MATCHER_IMPLEMENTATION 5013#include "ARMGenAsmMatcher.inc" 5014