ARMAsmParser.cpp revision fd652df8b36a9d3e6b09ae2b9f7bcb07e88fdfaa
1//===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#include "MCTargetDesc/ARMBaseInfo.h" 11#include "MCTargetDesc/ARMAddressingModes.h" 12#include "MCTargetDesc/ARMMCExpr.h" 13#include "llvm/MC/MCParser/MCAsmLexer.h" 14#include "llvm/MC/MCParser/MCAsmParser.h" 15#include "llvm/MC/MCParser/MCParsedAsmOperand.h" 16#include "llvm/MC/MCAsmInfo.h" 17#include "llvm/MC/MCContext.h" 18#include "llvm/MC/MCStreamer.h" 19#include "llvm/MC/MCExpr.h" 20#include "llvm/MC/MCInst.h" 21#include "llvm/MC/MCInstrDesc.h" 22#include "llvm/MC/MCRegisterInfo.h" 23#include "llvm/MC/MCSubtargetInfo.h" 24#include "llvm/MC/MCTargetAsmParser.h" 25#include "llvm/Support/MathExtras.h" 26#include "llvm/Support/SourceMgr.h" 27#include "llvm/Support/TargetRegistry.h" 28#include "llvm/Support/raw_ostream.h" 29#include "llvm/ADT/BitVector.h" 30#include "llvm/ADT/OwningPtr.h" 31#include "llvm/ADT/STLExtras.h" 32#include "llvm/ADT/SmallVector.h" 33#include "llvm/ADT/StringSwitch.h" 34#include "llvm/ADT/Twine.h" 35 36using namespace llvm; 37 38namespace { 39 40class ARMOperand; 41 42enum VectorLaneTy { NoLanes, AllLanes, IndexedLane }; 43 44class ARMAsmParser : public MCTargetAsmParser { 45 MCSubtargetInfo &STI; 46 MCAsmParser &Parser; 47 const MCRegisterInfo *MRI; 48 49 // Map of register aliases registers via the .req directive. 50 StringMap<unsigned> RegisterReqs; 51 52 struct { 53 ARMCC::CondCodes Cond; // Condition for IT block. 54 unsigned Mask:4; // Condition mask for instructions. 55 // Starting at first 1 (from lsb). 56 // '1' condition as indicated in IT. 57 // '0' inverse of condition (else). 58 // Count of instructions in IT block is 59 // 4 - trailingzeroes(mask) 60 61 bool FirstCond; // Explicit flag for when we're parsing the 62 // First instruction in the IT block. It's 63 // implied in the mask, so needs special 64 // handling. 65 66 unsigned CurPosition; // Current position in parsing of IT 67 // block. In range [0,3]. Initialized 68 // according to count of instructions in block. 69 // ~0U if no active IT block. 70 } ITState; 71 bool inITBlock() { return ITState.CurPosition != ~0U;} 72 void forwardITPosition() { 73 if (!inITBlock()) return; 74 // Move to the next instruction in the IT block, if there is one. If not, 75 // mark the block as done. 76 unsigned TZ = CountTrailingZeros_32(ITState.Mask); 77 if (++ITState.CurPosition == 5 - TZ) 78 ITState.CurPosition = ~0U; // Done with the IT block after this. 79 } 80 81 82 MCAsmParser &getParser() const { return Parser; } 83 MCAsmLexer &getLexer() const { return Parser.getLexer(); } 84 85 bool Warning(SMLoc L, const Twine &Msg, 86 ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) { 87 return Parser.Warning(L, Msg, Ranges); 88 } 89 bool Error(SMLoc L, const Twine &Msg, 90 ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) { 91 return Parser.Error(L, Msg, Ranges); 92 } 93 94 int tryParseRegister(); 95 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &); 96 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &); 97 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &); 98 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &); 99 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic); 100 bool parsePrefix(ARMMCExpr::VariantKind &RefKind); 101 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, 102 unsigned &ShiftAmount); 103 bool parseDirectiveWord(unsigned Size, SMLoc L); 104 bool parseDirectiveThumb(SMLoc L); 105 bool parseDirectiveARM(SMLoc L); 106 bool parseDirectiveThumbFunc(SMLoc L); 107 bool parseDirectiveCode(SMLoc L); 108 bool parseDirectiveSyntax(SMLoc L); 109 bool parseDirectiveReq(StringRef Name, SMLoc L); 110 bool parseDirectiveUnreq(SMLoc L); 111 bool parseDirectiveArch(SMLoc L); 112 bool parseDirectiveEabiAttr(SMLoc L); 113 114 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode, 115 bool &CarrySetting, unsigned &ProcessorIMod, 116 StringRef &ITMask); 117 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 118 bool &CanAcceptPredicationCode); 119 120 bool isThumb() const { 121 // FIXME: Can tablegen auto-generate this? 122 return (STI.getFeatureBits() & ARM::ModeThumb) != 0; 123 } 124 bool isThumbOne() const { 125 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0; 126 } 127 bool isThumbTwo() const { 128 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2); 129 } 130 bool hasV6Ops() const { 131 return STI.getFeatureBits() & ARM::HasV6Ops; 132 } 133 bool hasV7Ops() const { 134 return STI.getFeatureBits() & ARM::HasV7Ops; 135 } 136 void SwitchMode() { 137 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); 138 setAvailableFeatures(FB); 139 } 140 bool isMClass() const { 141 return STI.getFeatureBits() & ARM::FeatureMClass; 142 } 143 144 /// @name Auto-generated Match Functions 145 /// { 146 147#define GET_ASSEMBLER_HEADER 148#include "ARMGenAsmMatcher.inc" 149 150 /// } 151 152 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&); 153 OperandMatchResultTy parseCoprocNumOperand( 154 SmallVectorImpl<MCParsedAsmOperand*>&); 155 OperandMatchResultTy parseCoprocRegOperand( 156 SmallVectorImpl<MCParsedAsmOperand*>&); 157 OperandMatchResultTy parseCoprocOptionOperand( 158 SmallVectorImpl<MCParsedAsmOperand*>&); 159 OperandMatchResultTy parseMemBarrierOptOperand( 160 SmallVectorImpl<MCParsedAsmOperand*>&); 161 OperandMatchResultTy parseProcIFlagsOperand( 162 SmallVectorImpl<MCParsedAsmOperand*>&); 163 OperandMatchResultTy parseMSRMaskOperand( 164 SmallVectorImpl<MCParsedAsmOperand*>&); 165 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O, 166 StringRef Op, int Low, int High); 167 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 168 return parsePKHImm(O, "lsl", 0, 31); 169 } 170 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) { 171 return parsePKHImm(O, "asr", 1, 32); 172 } 173 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&); 174 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&); 175 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&); 176 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&); 177 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&); 178 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&); 179 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&); 180 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&); 181 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index); 182 183 // Asm Match Converter Methods 184 bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode, 185 const SmallVectorImpl<MCParsedAsmOperand*> &); 186 bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode, 187 const SmallVectorImpl<MCParsedAsmOperand*> &); 188 bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 189 const SmallVectorImpl<MCParsedAsmOperand*> &); 190 bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 191 const SmallVectorImpl<MCParsedAsmOperand*> &); 192 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 193 const SmallVectorImpl<MCParsedAsmOperand*> &); 194 bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 195 const SmallVectorImpl<MCParsedAsmOperand*> &); 196 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 197 const SmallVectorImpl<MCParsedAsmOperand*> &); 198 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 199 const SmallVectorImpl<MCParsedAsmOperand*> &); 200 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 201 const SmallVectorImpl<MCParsedAsmOperand*> &); 202 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 203 const SmallVectorImpl<MCParsedAsmOperand*> &); 204 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 205 const SmallVectorImpl<MCParsedAsmOperand*> &); 206 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 207 const SmallVectorImpl<MCParsedAsmOperand*> &); 208 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 209 const SmallVectorImpl<MCParsedAsmOperand*> &); 210 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode, 211 const SmallVectorImpl<MCParsedAsmOperand*> &); 212 bool cvtStrdPre(MCInst &Inst, unsigned Opcode, 213 const SmallVectorImpl<MCParsedAsmOperand*> &); 214 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 215 const SmallVectorImpl<MCParsedAsmOperand*> &); 216 bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode, 217 const SmallVectorImpl<MCParsedAsmOperand*> &); 218 bool cvtVLDwbFixed(MCInst &Inst, unsigned Opcode, 219 const SmallVectorImpl<MCParsedAsmOperand*> &); 220 bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode, 221 const SmallVectorImpl<MCParsedAsmOperand*> &); 222 bool cvtVSTwbFixed(MCInst &Inst, unsigned Opcode, 223 const SmallVectorImpl<MCParsedAsmOperand*> &); 224 bool cvtVSTwbRegister(MCInst &Inst, unsigned Opcode, 225 const SmallVectorImpl<MCParsedAsmOperand*> &); 226 227 bool validateInstruction(MCInst &Inst, 228 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 229 bool processInstruction(MCInst &Inst, 230 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 231 bool shouldOmitCCOutOperand(StringRef Mnemonic, 232 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 233 234public: 235 enum ARMMatchResultTy { 236 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY, 237 Match_RequiresNotITBlock, 238 Match_RequiresV6, 239 Match_RequiresThumb2, 240#define GET_OPERAND_DIAGNOSTIC_TYPES 241#include "ARMGenAsmMatcher.inc" 242 243 }; 244 245 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser) 246 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) { 247 MCAsmParserExtension::Initialize(_Parser); 248 249 // Cache the MCRegisterInfo. 250 MRI = &getContext().getRegisterInfo(); 251 252 // Initialize the set of available features. 253 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 254 255 // Not in an ITBlock to start with. 256 ITState.CurPosition = ~0U; 257 } 258 259 // Implementation of the MCTargetAsmParser interface: 260 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); 261 bool ParseInstruction(StringRef Name, SMLoc NameLoc, 262 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 263 bool ParseDirective(AsmToken DirectiveID); 264 265 unsigned checkTargetMatchPredicate(MCInst &Inst); 266 267 bool MatchAndEmitInstruction(SMLoc IDLoc, 268 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 269 MCStreamer &Out); 270}; 271} // end anonymous namespace 272 273namespace { 274 275/// ARMOperand - Instances of this class represent a parsed ARM machine 276/// instruction. 277class ARMOperand : public MCParsedAsmOperand { 278 enum KindTy { 279 k_CondCode, 280 k_CCOut, 281 k_ITCondMask, 282 k_CoprocNum, 283 k_CoprocReg, 284 k_CoprocOption, 285 k_Immediate, 286 k_MemBarrierOpt, 287 k_Memory, 288 k_PostIndexRegister, 289 k_MSRMask, 290 k_ProcIFlags, 291 k_VectorIndex, 292 k_Register, 293 k_RegisterList, 294 k_DPRRegisterList, 295 k_SPRRegisterList, 296 k_VectorList, 297 k_VectorListAllLanes, 298 k_VectorListIndexed, 299 k_ShiftedRegister, 300 k_ShiftedImmediate, 301 k_ShifterImmediate, 302 k_RotateImmediate, 303 k_BitfieldDescriptor, 304 k_Token 305 } Kind; 306 307 SMLoc StartLoc, EndLoc; 308 SmallVector<unsigned, 8> Registers; 309 310 union { 311 struct { 312 ARMCC::CondCodes Val; 313 } CC; 314 315 struct { 316 unsigned Val; 317 } Cop; 318 319 struct { 320 unsigned Val; 321 } CoprocOption; 322 323 struct { 324 unsigned Mask:4; 325 } ITMask; 326 327 struct { 328 ARM_MB::MemBOpt Val; 329 } MBOpt; 330 331 struct { 332 ARM_PROC::IFlags Val; 333 } IFlags; 334 335 struct { 336 unsigned Val; 337 } MMask; 338 339 struct { 340 const char *Data; 341 unsigned Length; 342 } Tok; 343 344 struct { 345 unsigned RegNum; 346 } Reg; 347 348 // A vector register list is a sequential list of 1 to 4 registers. 349 struct { 350 unsigned RegNum; 351 unsigned Count; 352 unsigned LaneIndex; 353 bool isDoubleSpaced; 354 } VectorList; 355 356 struct { 357 unsigned Val; 358 } VectorIndex; 359 360 struct { 361 const MCExpr *Val; 362 } Imm; 363 364 /// Combined record for all forms of ARM address expressions. 365 struct { 366 unsigned BaseRegNum; 367 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset 368 // was specified. 369 const MCConstantExpr *OffsetImm; // Offset immediate value 370 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL 371 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg 372 unsigned ShiftImm; // shift for OffsetReg. 373 unsigned Alignment; // 0 = no alignment specified 374 // n = alignment in bytes (2, 4, 8, 16, or 32) 375 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit) 376 } Memory; 377 378 struct { 379 unsigned RegNum; 380 bool isAdd; 381 ARM_AM::ShiftOpc ShiftTy; 382 unsigned ShiftImm; 383 } PostIdxReg; 384 385 struct { 386 bool isASR; 387 unsigned Imm; 388 } ShifterImm; 389 struct { 390 ARM_AM::ShiftOpc ShiftTy; 391 unsigned SrcReg; 392 unsigned ShiftReg; 393 unsigned ShiftImm; 394 } RegShiftedReg; 395 struct { 396 ARM_AM::ShiftOpc ShiftTy; 397 unsigned SrcReg; 398 unsigned ShiftImm; 399 } RegShiftedImm; 400 struct { 401 unsigned Imm; 402 } RotImm; 403 struct { 404 unsigned LSB; 405 unsigned Width; 406 } Bitfield; 407 }; 408 409 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 410public: 411 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() { 412 Kind = o.Kind; 413 StartLoc = o.StartLoc; 414 EndLoc = o.EndLoc; 415 switch (Kind) { 416 case k_CondCode: 417 CC = o.CC; 418 break; 419 case k_ITCondMask: 420 ITMask = o.ITMask; 421 break; 422 case k_Token: 423 Tok = o.Tok; 424 break; 425 case k_CCOut: 426 case k_Register: 427 Reg = o.Reg; 428 break; 429 case k_RegisterList: 430 case k_DPRRegisterList: 431 case k_SPRRegisterList: 432 Registers = o.Registers; 433 break; 434 case k_VectorList: 435 case k_VectorListAllLanes: 436 case k_VectorListIndexed: 437 VectorList = o.VectorList; 438 break; 439 case k_CoprocNum: 440 case k_CoprocReg: 441 Cop = o.Cop; 442 break; 443 case k_CoprocOption: 444 CoprocOption = o.CoprocOption; 445 break; 446 case k_Immediate: 447 Imm = o.Imm; 448 break; 449 case k_MemBarrierOpt: 450 MBOpt = o.MBOpt; 451 break; 452 case k_Memory: 453 Memory = o.Memory; 454 break; 455 case k_PostIndexRegister: 456 PostIdxReg = o.PostIdxReg; 457 break; 458 case k_MSRMask: 459 MMask = o.MMask; 460 break; 461 case k_ProcIFlags: 462 IFlags = o.IFlags; 463 break; 464 case k_ShifterImmediate: 465 ShifterImm = o.ShifterImm; 466 break; 467 case k_ShiftedRegister: 468 RegShiftedReg = o.RegShiftedReg; 469 break; 470 case k_ShiftedImmediate: 471 RegShiftedImm = o.RegShiftedImm; 472 break; 473 case k_RotateImmediate: 474 RotImm = o.RotImm; 475 break; 476 case k_BitfieldDescriptor: 477 Bitfield = o.Bitfield; 478 break; 479 case k_VectorIndex: 480 VectorIndex = o.VectorIndex; 481 break; 482 } 483 } 484 485 /// getStartLoc - Get the location of the first token of this operand. 486 SMLoc getStartLoc() const { return StartLoc; } 487 /// getEndLoc - Get the location of the last token of this operand. 488 SMLoc getEndLoc() const { return EndLoc; } 489 490 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } 491 492 ARMCC::CondCodes getCondCode() const { 493 assert(Kind == k_CondCode && "Invalid access!"); 494 return CC.Val; 495 } 496 497 unsigned getCoproc() const { 498 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!"); 499 return Cop.Val; 500 } 501 502 StringRef getToken() const { 503 assert(Kind == k_Token && "Invalid access!"); 504 return StringRef(Tok.Data, Tok.Length); 505 } 506 507 unsigned getReg() const { 508 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!"); 509 return Reg.RegNum; 510 } 511 512 const SmallVectorImpl<unsigned> &getRegList() const { 513 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList || 514 Kind == k_SPRRegisterList) && "Invalid access!"); 515 return Registers; 516 } 517 518 const MCExpr *getImm() const { 519 assert(isImm() && "Invalid access!"); 520 return Imm.Val; 521 } 522 523 unsigned getVectorIndex() const { 524 assert(Kind == k_VectorIndex && "Invalid access!"); 525 return VectorIndex.Val; 526 } 527 528 ARM_MB::MemBOpt getMemBarrierOpt() const { 529 assert(Kind == k_MemBarrierOpt && "Invalid access!"); 530 return MBOpt.Val; 531 } 532 533 ARM_PROC::IFlags getProcIFlags() const { 534 assert(Kind == k_ProcIFlags && "Invalid access!"); 535 return IFlags.Val; 536 } 537 538 unsigned getMSRMask() const { 539 assert(Kind == k_MSRMask && "Invalid access!"); 540 return MMask.Val; 541 } 542 543 bool isCoprocNum() const { return Kind == k_CoprocNum; } 544 bool isCoprocReg() const { return Kind == k_CoprocReg; } 545 bool isCoprocOption() const { return Kind == k_CoprocOption; } 546 bool isCondCode() const { return Kind == k_CondCode; } 547 bool isCCOut() const { return Kind == k_CCOut; } 548 bool isITMask() const { return Kind == k_ITCondMask; } 549 bool isITCondCode() const { return Kind == k_CondCode; } 550 bool isImm() const { return Kind == k_Immediate; } 551 bool isFPImm() const { 552 if (!isImm()) return false; 553 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 554 if (!CE) return false; 555 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 556 return Val != -1; 557 } 558 bool isFBits16() const { 559 if (!isImm()) return false; 560 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 561 if (!CE) return false; 562 int64_t Value = CE->getValue(); 563 return Value >= 0 && Value <= 16; 564 } 565 bool isFBits32() const { 566 if (!isImm()) return false; 567 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 568 if (!CE) return false; 569 int64_t Value = CE->getValue(); 570 return Value >= 1 && Value <= 32; 571 } 572 bool isImm8s4() const { 573 if (!isImm()) return false; 574 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 575 if (!CE) return false; 576 int64_t Value = CE->getValue(); 577 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020; 578 } 579 bool isImm0_1020s4() const { 580 if (!isImm()) return false; 581 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 582 if (!CE) return false; 583 int64_t Value = CE->getValue(); 584 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020; 585 } 586 bool isImm0_508s4() const { 587 if (!isImm()) return false; 588 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 589 if (!CE) return false; 590 int64_t Value = CE->getValue(); 591 return ((Value & 3) == 0) && Value >= 0 && Value <= 508; 592 } 593 bool isImm0_508s4Neg() const { 594 if (!isImm()) return false; 595 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 596 if (!CE) return false; 597 int64_t Value = -CE->getValue(); 598 // explicitly exclude zero. we want that to use the normal 0_508 version. 599 return ((Value & 3) == 0) && Value > 0 && Value <= 508; 600 } 601 bool isImm0_255() const { 602 if (!isImm()) return false; 603 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 604 if (!CE) return false; 605 int64_t Value = CE->getValue(); 606 return Value >= 0 && Value < 256; 607 } 608 bool isImm0_4095() const { 609 if (!isImm()) return false; 610 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 611 if (!CE) return false; 612 int64_t Value = CE->getValue(); 613 return Value >= 0 && Value < 4096; 614 } 615 bool isImm0_4095Neg() const { 616 if (!isImm()) return false; 617 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 618 if (!CE) return false; 619 int64_t Value = -CE->getValue(); 620 return Value > 0 && Value < 4096; 621 } 622 bool isImm0_1() const { 623 if (!isImm()) return false; 624 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 625 if (!CE) return false; 626 int64_t Value = CE->getValue(); 627 return Value >= 0 && Value < 2; 628 } 629 bool isImm0_3() const { 630 if (!isImm()) return false; 631 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 632 if (!CE) return false; 633 int64_t Value = CE->getValue(); 634 return Value >= 0 && Value < 4; 635 } 636 bool isImm0_7() const { 637 if (!isImm()) return false; 638 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 639 if (!CE) return false; 640 int64_t Value = CE->getValue(); 641 return Value >= 0 && Value < 8; 642 } 643 bool isImm0_15() const { 644 if (!isImm()) return false; 645 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 646 if (!CE) return false; 647 int64_t Value = CE->getValue(); 648 return Value >= 0 && Value < 16; 649 } 650 bool isImm0_31() const { 651 if (!isImm()) return false; 652 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 653 if (!CE) return false; 654 int64_t Value = CE->getValue(); 655 return Value >= 0 && Value < 32; 656 } 657 bool isImm0_63() const { 658 if (!isImm()) return false; 659 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 660 if (!CE) return false; 661 int64_t Value = CE->getValue(); 662 return Value >= 0 && Value < 64; 663 } 664 bool isImm8() const { 665 if (!isImm()) return false; 666 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 667 if (!CE) return false; 668 int64_t Value = CE->getValue(); 669 return Value == 8; 670 } 671 bool isImm16() const { 672 if (!isImm()) return false; 673 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 674 if (!CE) return false; 675 int64_t Value = CE->getValue(); 676 return Value == 16; 677 } 678 bool isImm32() const { 679 if (!isImm()) return false; 680 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 681 if (!CE) return false; 682 int64_t Value = CE->getValue(); 683 return Value == 32; 684 } 685 bool isShrImm8() const { 686 if (!isImm()) return false; 687 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 688 if (!CE) return false; 689 int64_t Value = CE->getValue(); 690 return Value > 0 && Value <= 8; 691 } 692 bool isShrImm16() const { 693 if (!isImm()) return false; 694 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 695 if (!CE) return false; 696 int64_t Value = CE->getValue(); 697 return Value > 0 && Value <= 16; 698 } 699 bool isShrImm32() const { 700 if (!isImm()) return false; 701 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 702 if (!CE) return false; 703 int64_t Value = CE->getValue(); 704 return Value > 0 && Value <= 32; 705 } 706 bool isShrImm64() const { 707 if (!isImm()) return false; 708 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 709 if (!CE) return false; 710 int64_t Value = CE->getValue(); 711 return Value > 0 && Value <= 64; 712 } 713 bool isImm1_7() const { 714 if (!isImm()) return false; 715 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 716 if (!CE) return false; 717 int64_t Value = CE->getValue(); 718 return Value > 0 && Value < 8; 719 } 720 bool isImm1_15() const { 721 if (!isImm()) return false; 722 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 723 if (!CE) return false; 724 int64_t Value = CE->getValue(); 725 return Value > 0 && Value < 16; 726 } 727 bool isImm1_31() const { 728 if (!isImm()) return false; 729 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 730 if (!CE) return false; 731 int64_t Value = CE->getValue(); 732 return Value > 0 && Value < 32; 733 } 734 bool isImm1_16() const { 735 if (!isImm()) return false; 736 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 737 if (!CE) return false; 738 int64_t Value = CE->getValue(); 739 return Value > 0 && Value < 17; 740 } 741 bool isImm1_32() const { 742 if (!isImm()) return false; 743 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 744 if (!CE) return false; 745 int64_t Value = CE->getValue(); 746 return Value > 0 && Value < 33; 747 } 748 bool isImm0_32() const { 749 if (!isImm()) return false; 750 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 751 if (!CE) return false; 752 int64_t Value = CE->getValue(); 753 return Value >= 0 && Value < 33; 754 } 755 bool isImm0_65535() const { 756 if (!isImm()) return false; 757 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 758 if (!CE) return false; 759 int64_t Value = CE->getValue(); 760 return Value >= 0 && Value < 65536; 761 } 762 bool isImm0_65535Expr() const { 763 if (!isImm()) return false; 764 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 765 // If it's not a constant expression, it'll generate a fixup and be 766 // handled later. 767 if (!CE) return true; 768 int64_t Value = CE->getValue(); 769 return Value >= 0 && Value < 65536; 770 } 771 bool isImm24bit() const { 772 if (!isImm()) return false; 773 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 774 if (!CE) return false; 775 int64_t Value = CE->getValue(); 776 return Value >= 0 && Value <= 0xffffff; 777 } 778 bool isImmThumbSR() const { 779 if (!isImm()) return false; 780 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 781 if (!CE) return false; 782 int64_t Value = CE->getValue(); 783 return Value > 0 && Value < 33; 784 } 785 bool isPKHLSLImm() const { 786 if (!isImm()) return false; 787 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 788 if (!CE) return false; 789 int64_t Value = CE->getValue(); 790 return Value >= 0 && Value < 32; 791 } 792 bool isPKHASRImm() const { 793 if (!isImm()) return false; 794 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 795 if (!CE) return false; 796 int64_t Value = CE->getValue(); 797 return Value > 0 && Value <= 32; 798 } 799 bool isAdrLabel() const { 800 // If we have an immediate that's not a constant, treat it as a label 801 // reference needing a fixup. If it is a constant, but it can't fit 802 // into shift immediate encoding, we reject it. 803 if (isImm() && !isa<MCConstantExpr>(getImm())) return true; 804 else return (isARMSOImm() || isARMSOImmNeg()); 805 } 806 bool isARMSOImm() const { 807 if (!isImm()) return false; 808 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 809 if (!CE) return false; 810 int64_t Value = CE->getValue(); 811 return ARM_AM::getSOImmVal(Value) != -1; 812 } 813 bool isARMSOImmNot() const { 814 if (!isImm()) return false; 815 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 816 if (!CE) return false; 817 int64_t Value = CE->getValue(); 818 return ARM_AM::getSOImmVal(~Value) != -1; 819 } 820 bool isARMSOImmNeg() const { 821 if (!isImm()) return false; 822 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 823 if (!CE) return false; 824 int64_t Value = CE->getValue(); 825 // Only use this when not representable as a plain so_imm. 826 return ARM_AM::getSOImmVal(Value) == -1 && 827 ARM_AM::getSOImmVal(-Value) != -1; 828 } 829 bool isT2SOImm() const { 830 if (!isImm()) return false; 831 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 832 if (!CE) return false; 833 int64_t Value = CE->getValue(); 834 return ARM_AM::getT2SOImmVal(Value) != -1; 835 } 836 bool isT2SOImmNot() const { 837 if (!isImm()) return false; 838 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 839 if (!CE) return false; 840 int64_t Value = CE->getValue(); 841 return ARM_AM::getT2SOImmVal(~Value) != -1; 842 } 843 bool isT2SOImmNeg() const { 844 if (!isImm()) return false; 845 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 846 if (!CE) return false; 847 int64_t Value = CE->getValue(); 848 // Only use this when not representable as a plain so_imm. 849 return ARM_AM::getT2SOImmVal(Value) == -1 && 850 ARM_AM::getT2SOImmVal(-Value) != -1; 851 } 852 bool isSetEndImm() const { 853 if (!isImm()) return false; 854 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 855 if (!CE) return false; 856 int64_t Value = CE->getValue(); 857 return Value == 1 || Value == 0; 858 } 859 bool isReg() const { return Kind == k_Register; } 860 bool isRegList() const { return Kind == k_RegisterList; } 861 bool isDPRRegList() const { return Kind == k_DPRRegisterList; } 862 bool isSPRRegList() const { return Kind == k_SPRRegisterList; } 863 bool isToken() const { return Kind == k_Token; } 864 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; } 865 bool isMemory() const { return Kind == k_Memory; } 866 bool isShifterImm() const { return Kind == k_ShifterImmediate; } 867 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; } 868 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; } 869 bool isRotImm() const { return Kind == k_RotateImmediate; } 870 bool isBitfield() const { return Kind == k_BitfieldDescriptor; } 871 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; } 872 bool isPostIdxReg() const { 873 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift; 874 } 875 bool isMemNoOffset(bool alignOK = false) const { 876 if (!isMemory()) 877 return false; 878 // No offset of any kind. 879 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 && 880 (alignOK || Memory.Alignment == 0); 881 } 882 bool isMemPCRelImm12() const { 883 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 884 return false; 885 // Base register must be PC. 886 if (Memory.BaseRegNum != ARM::PC) 887 return false; 888 // Immediate offset in range [-4095, 4095]. 889 if (!Memory.OffsetImm) return true; 890 int64_t Val = Memory.OffsetImm->getValue(); 891 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 892 } 893 bool isAlignedMemory() const { 894 return isMemNoOffset(true); 895 } 896 bool isAddrMode2() const { 897 if (!isMemory() || Memory.Alignment != 0) return false; 898 // Check for register offset. 899 if (Memory.OffsetRegNum) return true; 900 // Immediate offset in range [-4095, 4095]. 901 if (!Memory.OffsetImm) return true; 902 int64_t Val = Memory.OffsetImm->getValue(); 903 return Val > -4096 && Val < 4096; 904 } 905 bool isAM2OffsetImm() const { 906 if (!isImm()) return false; 907 // Immediate offset in range [-4095, 4095]. 908 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 909 if (!CE) return false; 910 int64_t Val = CE->getValue(); 911 return Val > -4096 && Val < 4096; 912 } 913 bool isAddrMode3() const { 914 // If we have an immediate that's not a constant, treat it as a label 915 // reference needing a fixup. If it is a constant, it's something else 916 // and we reject it. 917 if (isImm() && !isa<MCConstantExpr>(getImm())) 918 return true; 919 if (!isMemory() || Memory.Alignment != 0) return false; 920 // No shifts are legal for AM3. 921 if (Memory.ShiftType != ARM_AM::no_shift) return false; 922 // Check for register offset. 923 if (Memory.OffsetRegNum) return true; 924 // Immediate offset in range [-255, 255]. 925 if (!Memory.OffsetImm) return true; 926 int64_t Val = Memory.OffsetImm->getValue(); 927 // The #-0 offset is encoded as INT32_MIN, and we have to check 928 // for this too. 929 return (Val > -256 && Val < 256) || Val == INT32_MIN; 930 } 931 bool isAM3Offset() const { 932 if (Kind != k_Immediate && Kind != k_PostIndexRegister) 933 return false; 934 if (Kind == k_PostIndexRegister) 935 return PostIdxReg.ShiftTy == ARM_AM::no_shift; 936 // Immediate offset in range [-255, 255]. 937 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 938 if (!CE) return false; 939 int64_t Val = CE->getValue(); 940 // Special case, #-0 is INT32_MIN. 941 return (Val > -256 && Val < 256) || Val == INT32_MIN; 942 } 943 bool isAddrMode5() const { 944 // If we have an immediate that's not a constant, treat it as a label 945 // reference needing a fixup. If it is a constant, it's something else 946 // and we reject it. 947 if (isImm() && !isa<MCConstantExpr>(getImm())) 948 return true; 949 if (!isMemory() || Memory.Alignment != 0) return false; 950 // Check for register offset. 951 if (Memory.OffsetRegNum) return false; 952 // Immediate offset in range [-1020, 1020] and a multiple of 4. 953 if (!Memory.OffsetImm) return true; 954 int64_t Val = Memory.OffsetImm->getValue(); 955 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) || 956 Val == INT32_MIN; 957 } 958 bool isMemTBB() const { 959 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 960 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 961 return false; 962 return true; 963 } 964 bool isMemTBH() const { 965 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 966 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || 967 Memory.Alignment != 0 ) 968 return false; 969 return true; 970 } 971 bool isMemRegOffset() const { 972 if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0) 973 return false; 974 return true; 975 } 976 bool isT2MemRegOffset() const { 977 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 978 Memory.Alignment != 0) 979 return false; 980 // Only lsl #{0, 1, 2, 3} allowed. 981 if (Memory.ShiftType == ARM_AM::no_shift) 982 return true; 983 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) 984 return false; 985 return true; 986 } 987 bool isMemThumbRR() const { 988 // Thumb reg+reg addressing is simple. Just two registers, a base and 989 // an offset. No shifts, negations or any other complicating factors. 990 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative || 991 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) 992 return false; 993 return isARMLowRegister(Memory.BaseRegNum) && 994 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); 995 } 996 bool isMemThumbRIs4() const { 997 if (!isMemory() || Memory.OffsetRegNum != 0 || 998 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 999 return false; 1000 // Immediate offset, multiple of 4 in range [0, 124]. 1001 if (!Memory.OffsetImm) return true; 1002 int64_t Val = Memory.OffsetImm->getValue(); 1003 return Val >= 0 && Val <= 124 && (Val % 4) == 0; 1004 } 1005 bool isMemThumbRIs2() const { 1006 if (!isMemory() || Memory.OffsetRegNum != 0 || 1007 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1008 return false; 1009 // Immediate offset, multiple of 4 in range [0, 62]. 1010 if (!Memory.OffsetImm) return true; 1011 int64_t Val = Memory.OffsetImm->getValue(); 1012 return Val >= 0 && Val <= 62 && (Val % 2) == 0; 1013 } 1014 bool isMemThumbRIs1() const { 1015 if (!isMemory() || Memory.OffsetRegNum != 0 || 1016 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) 1017 return false; 1018 // Immediate offset in range [0, 31]. 1019 if (!Memory.OffsetImm) return true; 1020 int64_t Val = Memory.OffsetImm->getValue(); 1021 return Val >= 0 && Val <= 31; 1022 } 1023 bool isMemThumbSPI() const { 1024 if (!isMemory() || Memory.OffsetRegNum != 0 || 1025 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) 1026 return false; 1027 // Immediate offset, multiple of 4 in range [0, 1020]. 1028 if (!Memory.OffsetImm) return true; 1029 int64_t Val = Memory.OffsetImm->getValue(); 1030 return Val >= 0 && Val <= 1020 && (Val % 4) == 0; 1031 } 1032 bool isMemImm8s4Offset() const { 1033 // If we have an immediate that's not a constant, treat it as a label 1034 // reference needing a fixup. If it is a constant, it's something else 1035 // and we reject it. 1036 if (isImm() && !isa<MCConstantExpr>(getImm())) 1037 return true; 1038 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1039 return false; 1040 // Immediate offset a multiple of 4 in range [-1020, 1020]. 1041 if (!Memory.OffsetImm) return true; 1042 int64_t Val = Memory.OffsetImm->getValue(); 1043 // Special case, #-0 is INT32_MIN. 1044 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN; 1045 } 1046 bool isMemImm0_1020s4Offset() const { 1047 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1048 return false; 1049 // Immediate offset a multiple of 4 in range [0, 1020]. 1050 if (!Memory.OffsetImm) return true; 1051 int64_t Val = Memory.OffsetImm->getValue(); 1052 return Val >= 0 && Val <= 1020 && (Val & 3) == 0; 1053 } 1054 bool isMemImm8Offset() const { 1055 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1056 return false; 1057 // Base reg of PC isn't allowed for these encodings. 1058 if (Memory.BaseRegNum == ARM::PC) return false; 1059 // Immediate offset in range [-255, 255]. 1060 if (!Memory.OffsetImm) return true; 1061 int64_t Val = Memory.OffsetImm->getValue(); 1062 return (Val == INT32_MIN) || (Val > -256 && Val < 256); 1063 } 1064 bool isMemPosImm8Offset() const { 1065 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1066 return false; 1067 // Immediate offset in range [0, 255]. 1068 if (!Memory.OffsetImm) return true; 1069 int64_t Val = Memory.OffsetImm->getValue(); 1070 return Val >= 0 && Val < 256; 1071 } 1072 bool isMemNegImm8Offset() const { 1073 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1074 return false; 1075 // Base reg of PC isn't allowed for these encodings. 1076 if (Memory.BaseRegNum == ARM::PC) return false; 1077 // Immediate offset in range [-255, -1]. 1078 if (!Memory.OffsetImm) return false; 1079 int64_t Val = Memory.OffsetImm->getValue(); 1080 return (Val == INT32_MIN) || (Val > -256 && Val < 0); 1081 } 1082 bool isMemUImm12Offset() const { 1083 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1084 return false; 1085 // Immediate offset in range [0, 4095]. 1086 if (!Memory.OffsetImm) return true; 1087 int64_t Val = Memory.OffsetImm->getValue(); 1088 return (Val >= 0 && Val < 4096); 1089 } 1090 bool isMemImm12Offset() const { 1091 // If we have an immediate that's not a constant, treat it as a label 1092 // reference needing a fixup. If it is a constant, it's something else 1093 // and we reject it. 1094 if (isImm() && !isa<MCConstantExpr>(getImm())) 1095 return true; 1096 1097 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) 1098 return false; 1099 // Immediate offset in range [-4095, 4095]. 1100 if (!Memory.OffsetImm) return true; 1101 int64_t Val = Memory.OffsetImm->getValue(); 1102 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN); 1103 } 1104 bool isPostIdxImm8() const { 1105 if (!isImm()) return false; 1106 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1107 if (!CE) return false; 1108 int64_t Val = CE->getValue(); 1109 return (Val > -256 && Val < 256) || (Val == INT32_MIN); 1110 } 1111 bool isPostIdxImm8s4() const { 1112 if (!isImm()) return false; 1113 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1114 if (!CE) return false; 1115 int64_t Val = CE->getValue(); 1116 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) || 1117 (Val == INT32_MIN); 1118 } 1119 1120 bool isMSRMask() const { return Kind == k_MSRMask; } 1121 bool isProcIFlags() const { return Kind == k_ProcIFlags; } 1122 1123 // NEON operands. 1124 bool isSingleSpacedVectorList() const { 1125 return Kind == k_VectorList && !VectorList.isDoubleSpaced; 1126 } 1127 bool isDoubleSpacedVectorList() const { 1128 return Kind == k_VectorList && VectorList.isDoubleSpaced; 1129 } 1130 bool isVecListOneD() const { 1131 if (!isSingleSpacedVectorList()) return false; 1132 return VectorList.Count == 1; 1133 } 1134 1135 bool isVecListDPair() const { 1136 if (!isSingleSpacedVectorList()) return false; 1137 return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1138 .contains(VectorList.RegNum)); 1139 } 1140 1141 bool isVecListThreeD() const { 1142 if (!isSingleSpacedVectorList()) return false; 1143 return VectorList.Count == 3; 1144 } 1145 1146 bool isVecListFourD() const { 1147 if (!isSingleSpacedVectorList()) return false; 1148 return VectorList.Count == 4; 1149 } 1150 1151 bool isVecListDPairSpaced() const { 1152 if (isSingleSpacedVectorList()) return false; 1153 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] 1154 .contains(VectorList.RegNum)); 1155 } 1156 1157 bool isVecListThreeQ() const { 1158 if (!isDoubleSpacedVectorList()) return false; 1159 return VectorList.Count == 3; 1160 } 1161 1162 bool isVecListFourQ() const { 1163 if (!isDoubleSpacedVectorList()) return false; 1164 return VectorList.Count == 4; 1165 } 1166 1167 bool isSingleSpacedVectorAllLanes() const { 1168 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced; 1169 } 1170 bool isDoubleSpacedVectorAllLanes() const { 1171 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced; 1172 } 1173 bool isVecListOneDAllLanes() const { 1174 if (!isSingleSpacedVectorAllLanes()) return false; 1175 return VectorList.Count == 1; 1176 } 1177 1178 bool isVecListDPairAllLanes() const { 1179 if (!isSingleSpacedVectorAllLanes()) return false; 1180 return (ARMMCRegisterClasses[ARM::DPairRegClassID] 1181 .contains(VectorList.RegNum)); 1182 } 1183 1184 bool isVecListDPairSpacedAllLanes() const { 1185 if (!isDoubleSpacedVectorAllLanes()) return false; 1186 return VectorList.Count == 2; 1187 } 1188 1189 bool isVecListThreeDAllLanes() const { 1190 if (!isSingleSpacedVectorAllLanes()) return false; 1191 return VectorList.Count == 3; 1192 } 1193 1194 bool isVecListThreeQAllLanes() const { 1195 if (!isDoubleSpacedVectorAllLanes()) return false; 1196 return VectorList.Count == 3; 1197 } 1198 1199 bool isVecListFourDAllLanes() const { 1200 if (!isSingleSpacedVectorAllLanes()) return false; 1201 return VectorList.Count == 4; 1202 } 1203 1204 bool isVecListFourQAllLanes() const { 1205 if (!isDoubleSpacedVectorAllLanes()) return false; 1206 return VectorList.Count == 4; 1207 } 1208 1209 bool isSingleSpacedVectorIndexed() const { 1210 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced; 1211 } 1212 bool isDoubleSpacedVectorIndexed() const { 1213 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced; 1214 } 1215 bool isVecListOneDByteIndexed() const { 1216 if (!isSingleSpacedVectorIndexed()) return false; 1217 return VectorList.Count == 1 && VectorList.LaneIndex <= 7; 1218 } 1219 1220 bool isVecListOneDHWordIndexed() const { 1221 if (!isSingleSpacedVectorIndexed()) return false; 1222 return VectorList.Count == 1 && VectorList.LaneIndex <= 3; 1223 } 1224 1225 bool isVecListOneDWordIndexed() const { 1226 if (!isSingleSpacedVectorIndexed()) return false; 1227 return VectorList.Count == 1 && VectorList.LaneIndex <= 1; 1228 } 1229 1230 bool isVecListTwoDByteIndexed() const { 1231 if (!isSingleSpacedVectorIndexed()) return false; 1232 return VectorList.Count == 2 && VectorList.LaneIndex <= 7; 1233 } 1234 1235 bool isVecListTwoDHWordIndexed() const { 1236 if (!isSingleSpacedVectorIndexed()) return false; 1237 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1238 } 1239 1240 bool isVecListTwoQWordIndexed() const { 1241 if (!isDoubleSpacedVectorIndexed()) return false; 1242 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1243 } 1244 1245 bool isVecListTwoQHWordIndexed() const { 1246 if (!isDoubleSpacedVectorIndexed()) return false; 1247 return VectorList.Count == 2 && VectorList.LaneIndex <= 3; 1248 } 1249 1250 bool isVecListTwoDWordIndexed() const { 1251 if (!isSingleSpacedVectorIndexed()) return false; 1252 return VectorList.Count == 2 && VectorList.LaneIndex <= 1; 1253 } 1254 1255 bool isVecListThreeDByteIndexed() const { 1256 if (!isSingleSpacedVectorIndexed()) return false; 1257 return VectorList.Count == 3 && VectorList.LaneIndex <= 7; 1258 } 1259 1260 bool isVecListThreeDHWordIndexed() const { 1261 if (!isSingleSpacedVectorIndexed()) return false; 1262 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 1263 } 1264 1265 bool isVecListThreeQWordIndexed() const { 1266 if (!isDoubleSpacedVectorIndexed()) return false; 1267 return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 1268 } 1269 1270 bool isVecListThreeQHWordIndexed() const { 1271 if (!isDoubleSpacedVectorIndexed()) return false; 1272 return VectorList.Count == 3 && VectorList.LaneIndex <= 3; 1273 } 1274 1275 bool isVecListThreeDWordIndexed() const { 1276 if (!isSingleSpacedVectorIndexed()) return false; 1277 return VectorList.Count == 3 && VectorList.LaneIndex <= 1; 1278 } 1279 1280 bool isVecListFourDByteIndexed() const { 1281 if (!isSingleSpacedVectorIndexed()) return false; 1282 return VectorList.Count == 4 && VectorList.LaneIndex <= 7; 1283 } 1284 1285 bool isVecListFourDHWordIndexed() const { 1286 if (!isSingleSpacedVectorIndexed()) return false; 1287 return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1288 } 1289 1290 bool isVecListFourQWordIndexed() const { 1291 if (!isDoubleSpacedVectorIndexed()) return false; 1292 return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1293 } 1294 1295 bool isVecListFourQHWordIndexed() const { 1296 if (!isDoubleSpacedVectorIndexed()) return false; 1297 return VectorList.Count == 4 && VectorList.LaneIndex <= 3; 1298 } 1299 1300 bool isVecListFourDWordIndexed() const { 1301 if (!isSingleSpacedVectorIndexed()) return false; 1302 return VectorList.Count == 4 && VectorList.LaneIndex <= 1; 1303 } 1304 1305 bool isVectorIndex8() const { 1306 if (Kind != k_VectorIndex) return false; 1307 return VectorIndex.Val < 8; 1308 } 1309 bool isVectorIndex16() const { 1310 if (Kind != k_VectorIndex) return false; 1311 return VectorIndex.Val < 4; 1312 } 1313 bool isVectorIndex32() const { 1314 if (Kind != k_VectorIndex) return false; 1315 return VectorIndex.Val < 2; 1316 } 1317 1318 bool isNEONi8splat() const { 1319 if (!isImm()) return false; 1320 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1321 // Must be a constant. 1322 if (!CE) return false; 1323 int64_t Value = CE->getValue(); 1324 // i8 value splatted across 8 bytes. The immediate is just the 8 byte 1325 // value. 1326 return Value >= 0 && Value < 256; 1327 } 1328 1329 bool isNEONi16splat() const { 1330 if (!isImm()) return false; 1331 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1332 // Must be a constant. 1333 if (!CE) return false; 1334 int64_t Value = CE->getValue(); 1335 // i16 value in the range [0,255] or [0x0100, 0xff00] 1336 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00); 1337 } 1338 1339 bool isNEONi32splat() const { 1340 if (!isImm()) return false; 1341 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1342 // Must be a constant. 1343 if (!CE) return false; 1344 int64_t Value = CE->getValue(); 1345 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X. 1346 return (Value >= 0 && Value < 256) || 1347 (Value >= 0x0100 && Value <= 0xff00) || 1348 (Value >= 0x010000 && Value <= 0xff0000) || 1349 (Value >= 0x01000000 && Value <= 0xff000000); 1350 } 1351 1352 bool isNEONi32vmov() const { 1353 if (!isImm()) return false; 1354 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1355 // Must be a constant. 1356 if (!CE) return false; 1357 int64_t Value = CE->getValue(); 1358 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1359 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1360 return (Value >= 0 && Value < 256) || 1361 (Value >= 0x0100 && Value <= 0xff00) || 1362 (Value >= 0x010000 && Value <= 0xff0000) || 1363 (Value >= 0x01000000 && Value <= 0xff000000) || 1364 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1365 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1366 } 1367 bool isNEONi32vmovNeg() const { 1368 if (!isImm()) return false; 1369 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1370 // Must be a constant. 1371 if (!CE) return false; 1372 int64_t Value = ~CE->getValue(); 1373 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, 1374 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. 1375 return (Value >= 0 && Value < 256) || 1376 (Value >= 0x0100 && Value <= 0xff00) || 1377 (Value >= 0x010000 && Value <= 0xff0000) || 1378 (Value >= 0x01000000 && Value <= 0xff000000) || 1379 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) || 1380 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff); 1381 } 1382 1383 bool isNEONi64splat() const { 1384 if (!isImm()) return false; 1385 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1386 // Must be a constant. 1387 if (!CE) return false; 1388 uint64_t Value = CE->getValue(); 1389 // i64 value with each byte being either 0 or 0xff. 1390 for (unsigned i = 0; i < 8; ++i) 1391 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false; 1392 return true; 1393 } 1394 1395 void addExpr(MCInst &Inst, const MCExpr *Expr) const { 1396 // Add as immediates when possible. Null MCExpr = 0. 1397 if (Expr == 0) 1398 Inst.addOperand(MCOperand::CreateImm(0)); 1399 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) 1400 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1401 else 1402 Inst.addOperand(MCOperand::CreateExpr(Expr)); 1403 } 1404 1405 void addCondCodeOperands(MCInst &Inst, unsigned N) const { 1406 assert(N == 2 && "Invalid number of operands!"); 1407 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 1408 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; 1409 Inst.addOperand(MCOperand::CreateReg(RegNum)); 1410 } 1411 1412 void addCoprocNumOperands(MCInst &Inst, unsigned N) const { 1413 assert(N == 1 && "Invalid number of operands!"); 1414 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1415 } 1416 1417 void addCoprocRegOperands(MCInst &Inst, unsigned N) const { 1418 assert(N == 1 && "Invalid number of operands!"); 1419 Inst.addOperand(MCOperand::CreateImm(getCoproc())); 1420 } 1421 1422 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const { 1423 assert(N == 1 && "Invalid number of operands!"); 1424 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val)); 1425 } 1426 1427 void addITMaskOperands(MCInst &Inst, unsigned N) const { 1428 assert(N == 1 && "Invalid number of operands!"); 1429 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask)); 1430 } 1431 1432 void addITCondCodeOperands(MCInst &Inst, unsigned N) const { 1433 assert(N == 1 && "Invalid number of operands!"); 1434 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode()))); 1435 } 1436 1437 void addCCOutOperands(MCInst &Inst, unsigned N) const { 1438 assert(N == 1 && "Invalid number of operands!"); 1439 Inst.addOperand(MCOperand::CreateReg(getReg())); 1440 } 1441 1442 void addRegOperands(MCInst &Inst, unsigned N) const { 1443 assert(N == 1 && "Invalid number of operands!"); 1444 Inst.addOperand(MCOperand::CreateReg(getReg())); 1445 } 1446 1447 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { 1448 assert(N == 3 && "Invalid number of operands!"); 1449 assert(isRegShiftedReg() && 1450 "addRegShiftedRegOperands() on non RegShiftedReg!"); 1451 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); 1452 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); 1453 Inst.addOperand(MCOperand::CreateImm( 1454 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); 1455 } 1456 1457 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { 1458 assert(N == 2 && "Invalid number of operands!"); 1459 assert(isRegShiftedImm() && 1460 "addRegShiftedImmOperands() on non RegShiftedImm!"); 1461 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); 1462 // Shift of #32 is encoded as 0 where permitted 1463 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); 1464 Inst.addOperand(MCOperand::CreateImm( 1465 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); 1466 } 1467 1468 void addShifterImmOperands(MCInst &Inst, unsigned N) const { 1469 assert(N == 1 && "Invalid number of operands!"); 1470 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) | 1471 ShifterImm.Imm)); 1472 } 1473 1474 void addRegListOperands(MCInst &Inst, unsigned N) const { 1475 assert(N == 1 && "Invalid number of operands!"); 1476 const SmallVectorImpl<unsigned> &RegList = getRegList(); 1477 for (SmallVectorImpl<unsigned>::const_iterator 1478 I = RegList.begin(), E = RegList.end(); I != E; ++I) 1479 Inst.addOperand(MCOperand::CreateReg(*I)); 1480 } 1481 1482 void addDPRRegListOperands(MCInst &Inst, unsigned N) const { 1483 addRegListOperands(Inst, N); 1484 } 1485 1486 void addSPRRegListOperands(MCInst &Inst, unsigned N) const { 1487 addRegListOperands(Inst, N); 1488 } 1489 1490 void addRotImmOperands(MCInst &Inst, unsigned N) const { 1491 assert(N == 1 && "Invalid number of operands!"); 1492 // Encoded as val>>3. The printer handles display as 8, 16, 24. 1493 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3)); 1494 } 1495 1496 void addBitfieldOperands(MCInst &Inst, unsigned N) const { 1497 assert(N == 1 && "Invalid number of operands!"); 1498 // Munge the lsb/width into a bitfield mask. 1499 unsigned lsb = Bitfield.LSB; 1500 unsigned width = Bitfield.Width; 1501 // Make a 32-bit mask w/ the referenced bits clear and all other bits set. 1502 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> 1503 (32 - (lsb + width))); 1504 Inst.addOperand(MCOperand::CreateImm(Mask)); 1505 } 1506 1507 void addImmOperands(MCInst &Inst, unsigned N) const { 1508 assert(N == 1 && "Invalid number of operands!"); 1509 addExpr(Inst, getImm()); 1510 } 1511 1512 void addFBits16Operands(MCInst &Inst, unsigned N) const { 1513 assert(N == 1 && "Invalid number of operands!"); 1514 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1515 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue())); 1516 } 1517 1518 void addFBits32Operands(MCInst &Inst, unsigned N) const { 1519 assert(N == 1 && "Invalid number of operands!"); 1520 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1521 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue())); 1522 } 1523 1524 void addFPImmOperands(MCInst &Inst, unsigned N) const { 1525 assert(N == 1 && "Invalid number of operands!"); 1526 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1527 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 1528 Inst.addOperand(MCOperand::CreateImm(Val)); 1529 } 1530 1531 void addImm8s4Operands(MCInst &Inst, unsigned N) const { 1532 assert(N == 1 && "Invalid number of operands!"); 1533 // FIXME: We really want to scale the value here, but the LDRD/STRD 1534 // instruction don't encode operands that way yet. 1535 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1536 Inst.addOperand(MCOperand::CreateImm(CE->getValue())); 1537 } 1538 1539 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { 1540 assert(N == 1 && "Invalid number of operands!"); 1541 // The immediate is scaled by four in the encoding and is stored 1542 // in the MCInst as such. Lop off the low two bits here. 1543 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1544 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 1545 } 1546 1547 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const { 1548 assert(N == 1 && "Invalid number of operands!"); 1549 // The immediate is scaled by four in the encoding and is stored 1550 // in the MCInst as such. Lop off the low two bits here. 1551 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1552 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4))); 1553 } 1554 1555 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { 1556 assert(N == 1 && "Invalid number of operands!"); 1557 // The immediate is scaled by four in the encoding and is stored 1558 // in the MCInst as such. Lop off the low two bits here. 1559 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1560 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4)); 1561 } 1562 1563 void addImm1_16Operands(MCInst &Inst, unsigned N) const { 1564 assert(N == 1 && "Invalid number of operands!"); 1565 // The constant encodes as the immediate-1, and we store in the instruction 1566 // the bits as encoded, so subtract off one here. 1567 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1568 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1569 } 1570 1571 void addImm1_32Operands(MCInst &Inst, unsigned N) const { 1572 assert(N == 1 && "Invalid number of operands!"); 1573 // The constant encodes as the immediate-1, and we store in the instruction 1574 // the bits as encoded, so subtract off one here. 1575 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1576 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1)); 1577 } 1578 1579 void addImmThumbSROperands(MCInst &Inst, unsigned N) const { 1580 assert(N == 1 && "Invalid number of operands!"); 1581 // The constant encodes as the immediate, except for 32, which encodes as 1582 // zero. 1583 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1584 unsigned Imm = CE->getValue(); 1585 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm))); 1586 } 1587 1588 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { 1589 assert(N == 1 && "Invalid number of operands!"); 1590 // An ASR value of 32 encodes as 0, so that's how we want to add it to 1591 // the instruction as well. 1592 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1593 int Val = CE->getValue(); 1594 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val)); 1595 } 1596 1597 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const { 1598 assert(N == 1 && "Invalid number of operands!"); 1599 // The operand is actually a t2_so_imm, but we have its bitwise 1600 // negation in the assembly source, so twiddle it here. 1601 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1602 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1603 } 1604 1605 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const { 1606 assert(N == 1 && "Invalid number of operands!"); 1607 // The operand is actually a t2_so_imm, but we have its 1608 // negation in the assembly source, so twiddle it here. 1609 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1610 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1611 } 1612 1613 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const { 1614 assert(N == 1 && "Invalid number of operands!"); 1615 // The operand is actually an imm0_4095, but we have its 1616 // negation in the assembly source, so twiddle it here. 1617 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1618 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1619 } 1620 1621 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const { 1622 assert(N == 1 && "Invalid number of operands!"); 1623 // The operand is actually a so_imm, but we have its bitwise 1624 // negation in the assembly source, so twiddle it here. 1625 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1626 Inst.addOperand(MCOperand::CreateImm(~CE->getValue())); 1627 } 1628 1629 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const { 1630 assert(N == 1 && "Invalid number of operands!"); 1631 // The operand is actually a so_imm, but we have its 1632 // negation in the assembly source, so twiddle it here. 1633 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1634 Inst.addOperand(MCOperand::CreateImm(-CE->getValue())); 1635 } 1636 1637 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { 1638 assert(N == 1 && "Invalid number of operands!"); 1639 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt()))); 1640 } 1641 1642 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { 1643 assert(N == 1 && "Invalid number of operands!"); 1644 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1645 } 1646 1647 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const { 1648 assert(N == 1 && "Invalid number of operands!"); 1649 int32_t Imm = Memory.OffsetImm->getValue(); 1650 // FIXME: Handle #-0 1651 if (Imm == INT32_MIN) Imm = 0; 1652 Inst.addOperand(MCOperand::CreateImm(Imm)); 1653 } 1654 1655 void addAdrLabelOperands(MCInst &Inst, unsigned N) const { 1656 assert(N == 1 && "Invalid number of operands!"); 1657 assert(isImm() && "Not an immediate!"); 1658 1659 // If we have an immediate that's not a constant, treat it as a label 1660 // reference needing a fixup. 1661 if (!isa<MCConstantExpr>(getImm())) { 1662 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1663 return; 1664 } 1665 1666 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1667 int Val = CE->getValue(); 1668 Inst.addOperand(MCOperand::CreateImm(Val)); 1669 } 1670 1671 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const { 1672 assert(N == 2 && "Invalid number of operands!"); 1673 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1674 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment)); 1675 } 1676 1677 void addAddrMode2Operands(MCInst &Inst, unsigned N) const { 1678 assert(N == 3 && "Invalid number of operands!"); 1679 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1680 if (!Memory.OffsetRegNum) { 1681 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1682 // Special case for #-0 1683 if (Val == INT32_MIN) Val = 0; 1684 if (Val < 0) Val = -Val; 1685 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1686 } else { 1687 // For register offset, we encode the shift type and negation flag 1688 // here. 1689 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 1690 Memory.ShiftImm, Memory.ShiftType); 1691 } 1692 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1693 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1694 Inst.addOperand(MCOperand::CreateImm(Val)); 1695 } 1696 1697 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { 1698 assert(N == 2 && "Invalid number of operands!"); 1699 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1700 assert(CE && "non-constant AM2OffsetImm operand!"); 1701 int32_t Val = CE->getValue(); 1702 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1703 // Special case for #-0 1704 if (Val == INT32_MIN) Val = 0; 1705 if (Val < 0) Val = -Val; 1706 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); 1707 Inst.addOperand(MCOperand::CreateReg(0)); 1708 Inst.addOperand(MCOperand::CreateImm(Val)); 1709 } 1710 1711 void addAddrMode3Operands(MCInst &Inst, unsigned N) const { 1712 assert(N == 3 && "Invalid number of operands!"); 1713 // If we have an immediate that's not a constant, treat it as a label 1714 // reference needing a fixup. If it is a constant, it's something else 1715 // and we reject it. 1716 if (isImm()) { 1717 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1718 Inst.addOperand(MCOperand::CreateReg(0)); 1719 Inst.addOperand(MCOperand::CreateImm(0)); 1720 return; 1721 } 1722 1723 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1724 if (!Memory.OffsetRegNum) { 1725 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1726 // Special case for #-0 1727 if (Val == INT32_MIN) Val = 0; 1728 if (Val < 0) Val = -Val; 1729 Val = ARM_AM::getAM3Opc(AddSub, Val); 1730 } else { 1731 // For register offset, we encode the shift type and negation flag 1732 // here. 1733 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0); 1734 } 1735 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1736 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1737 Inst.addOperand(MCOperand::CreateImm(Val)); 1738 } 1739 1740 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { 1741 assert(N == 2 && "Invalid number of operands!"); 1742 if (Kind == k_PostIndexRegister) { 1743 int32_t Val = 1744 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); 1745 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1746 Inst.addOperand(MCOperand::CreateImm(Val)); 1747 return; 1748 } 1749 1750 // Constant offset. 1751 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm()); 1752 int32_t Val = CE->getValue(); 1753 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1754 // Special case for #-0 1755 if (Val == INT32_MIN) Val = 0; 1756 if (Val < 0) Val = -Val; 1757 Val = ARM_AM::getAM3Opc(AddSub, Val); 1758 Inst.addOperand(MCOperand::CreateReg(0)); 1759 Inst.addOperand(MCOperand::CreateImm(Val)); 1760 } 1761 1762 void addAddrMode5Operands(MCInst &Inst, unsigned N) const { 1763 assert(N == 2 && "Invalid number of operands!"); 1764 // If we have an immediate that's not a constant, treat it as a label 1765 // reference needing a fixup. If it is a constant, it's something else 1766 // and we reject it. 1767 if (isImm()) { 1768 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1769 Inst.addOperand(MCOperand::CreateImm(0)); 1770 return; 1771 } 1772 1773 // The lower two bits are always zero and as such are not encoded. 1774 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 1775 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; 1776 // Special case for #-0 1777 if (Val == INT32_MIN) Val = 0; 1778 if (Val < 0) Val = -Val; 1779 Val = ARM_AM::getAM5Opc(AddSub, Val); 1780 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1781 Inst.addOperand(MCOperand::CreateImm(Val)); 1782 } 1783 1784 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const { 1785 assert(N == 2 && "Invalid number of operands!"); 1786 // If we have an immediate that's not a constant, treat it as a label 1787 // reference needing a fixup. If it is a constant, it's something else 1788 // and we reject it. 1789 if (isImm()) { 1790 Inst.addOperand(MCOperand::CreateExpr(getImm())); 1791 Inst.addOperand(MCOperand::CreateImm(0)); 1792 return; 1793 } 1794 1795 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1796 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1797 Inst.addOperand(MCOperand::CreateImm(Val)); 1798 } 1799 1800 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const { 1801 assert(N == 2 && "Invalid number of operands!"); 1802 // The lower two bits are always zero and as such are not encoded. 1803 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; 1804 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1805 Inst.addOperand(MCOperand::CreateImm(Val)); 1806 } 1807 1808 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1809 assert(N == 2 && "Invalid number of operands!"); 1810 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1811 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1812 Inst.addOperand(MCOperand::CreateImm(Val)); 1813 } 1814 1815 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1816 addMemImm8OffsetOperands(Inst, N); 1817 } 1818 1819 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const { 1820 addMemImm8OffsetOperands(Inst, N); 1821 } 1822 1823 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { 1824 assert(N == 2 && "Invalid number of operands!"); 1825 // If this is an immediate, it's a label reference. 1826 if (isImm()) { 1827 addExpr(Inst, getImm()); 1828 Inst.addOperand(MCOperand::CreateImm(0)); 1829 return; 1830 } 1831 1832 // Otherwise, it's a normal memory reg+offset. 1833 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1834 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1835 Inst.addOperand(MCOperand::CreateImm(Val)); 1836 } 1837 1838 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { 1839 assert(N == 2 && "Invalid number of operands!"); 1840 // If this is an immediate, it's a label reference. 1841 if (isImm()) { 1842 addExpr(Inst, getImm()); 1843 Inst.addOperand(MCOperand::CreateImm(0)); 1844 return; 1845 } 1846 1847 // Otherwise, it's a normal memory reg+offset. 1848 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; 1849 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1850 Inst.addOperand(MCOperand::CreateImm(Val)); 1851 } 1852 1853 void addMemTBBOperands(MCInst &Inst, unsigned N) const { 1854 assert(N == 2 && "Invalid number of operands!"); 1855 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1856 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1857 } 1858 1859 void addMemTBHOperands(MCInst &Inst, unsigned N) const { 1860 assert(N == 2 && "Invalid number of operands!"); 1861 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1862 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1863 } 1864 1865 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { 1866 assert(N == 3 && "Invalid number of operands!"); 1867 unsigned Val = 1868 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 1869 Memory.ShiftImm, Memory.ShiftType); 1870 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1871 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1872 Inst.addOperand(MCOperand::CreateImm(Val)); 1873 } 1874 1875 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { 1876 assert(N == 3 && "Invalid number of operands!"); 1877 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1878 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1879 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm)); 1880 } 1881 1882 void addMemThumbRROperands(MCInst &Inst, unsigned N) const { 1883 assert(N == 2 && "Invalid number of operands!"); 1884 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1885 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum)); 1886 } 1887 1888 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const { 1889 assert(N == 2 && "Invalid number of operands!"); 1890 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 1891 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1892 Inst.addOperand(MCOperand::CreateImm(Val)); 1893 } 1894 1895 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const { 1896 assert(N == 2 && "Invalid number of operands!"); 1897 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0; 1898 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1899 Inst.addOperand(MCOperand::CreateImm(Val)); 1900 } 1901 1902 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { 1903 assert(N == 2 && "Invalid number of operands!"); 1904 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0; 1905 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1906 Inst.addOperand(MCOperand::CreateImm(Val)); 1907 } 1908 1909 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { 1910 assert(N == 2 && "Invalid number of operands!"); 1911 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; 1912 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1913 Inst.addOperand(MCOperand::CreateImm(Val)); 1914 } 1915 1916 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { 1917 assert(N == 1 && "Invalid number of operands!"); 1918 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1919 assert(CE && "non-constant post-idx-imm8 operand!"); 1920 int Imm = CE->getValue(); 1921 bool isAdd = Imm >= 0; 1922 if (Imm == INT32_MIN) Imm = 0; 1923 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; 1924 Inst.addOperand(MCOperand::CreateImm(Imm)); 1925 } 1926 1927 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const { 1928 assert(N == 1 && "Invalid number of operands!"); 1929 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1930 assert(CE && "non-constant post-idx-imm8s4 operand!"); 1931 int Imm = CE->getValue(); 1932 bool isAdd = Imm >= 0; 1933 if (Imm == INT32_MIN) Imm = 0; 1934 // Immediate is scaled by 4. 1935 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; 1936 Inst.addOperand(MCOperand::CreateImm(Imm)); 1937 } 1938 1939 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { 1940 assert(N == 2 && "Invalid number of operands!"); 1941 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1942 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd)); 1943 } 1944 1945 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { 1946 assert(N == 2 && "Invalid number of operands!"); 1947 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); 1948 // The sign, shift type, and shift amount are encoded in a single operand 1949 // using the AM2 encoding helpers. 1950 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; 1951 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, 1952 PostIdxReg.ShiftTy); 1953 Inst.addOperand(MCOperand::CreateImm(Imm)); 1954 } 1955 1956 void addMSRMaskOperands(MCInst &Inst, unsigned N) const { 1957 assert(N == 1 && "Invalid number of operands!"); 1958 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask()))); 1959 } 1960 1961 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { 1962 assert(N == 1 && "Invalid number of operands!"); 1963 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags()))); 1964 } 1965 1966 void addVecListOperands(MCInst &Inst, unsigned N) const { 1967 assert(N == 1 && "Invalid number of operands!"); 1968 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 1969 } 1970 1971 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const { 1972 assert(N == 2 && "Invalid number of operands!"); 1973 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum)); 1974 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex)); 1975 } 1976 1977 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const { 1978 assert(N == 1 && "Invalid number of operands!"); 1979 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1980 } 1981 1982 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const { 1983 assert(N == 1 && "Invalid number of operands!"); 1984 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1985 } 1986 1987 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const { 1988 assert(N == 1 && "Invalid number of operands!"); 1989 Inst.addOperand(MCOperand::CreateImm(getVectorIndex())); 1990 } 1991 1992 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const { 1993 assert(N == 1 && "Invalid number of operands!"); 1994 // The immediate encodes the type of constant as well as the value. 1995 // Mask in that this is an i8 splat. 1996 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 1997 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00)); 1998 } 1999 2000 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const { 2001 assert(N == 1 && "Invalid number of operands!"); 2002 // The immediate encodes the type of constant as well as the value. 2003 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2004 unsigned Value = CE->getValue(); 2005 if (Value >= 256) 2006 Value = (Value >> 8) | 0xa00; 2007 else 2008 Value |= 0x800; 2009 Inst.addOperand(MCOperand::CreateImm(Value)); 2010 } 2011 2012 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const { 2013 assert(N == 1 && "Invalid number of operands!"); 2014 // The immediate encodes the type of constant as well as the value. 2015 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2016 unsigned Value = CE->getValue(); 2017 if (Value >= 256 && Value <= 0xff00) 2018 Value = (Value >> 8) | 0x200; 2019 else if (Value > 0xffff && Value <= 0xff0000) 2020 Value = (Value >> 16) | 0x400; 2021 else if (Value > 0xffffff) 2022 Value = (Value >> 24) | 0x600; 2023 Inst.addOperand(MCOperand::CreateImm(Value)); 2024 } 2025 2026 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const { 2027 assert(N == 1 && "Invalid number of operands!"); 2028 // The immediate encodes the type of constant as well as the value. 2029 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2030 unsigned Value = CE->getValue(); 2031 if (Value >= 256 && Value <= 0xffff) 2032 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 2033 else if (Value > 0xffff && Value <= 0xffffff) 2034 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 2035 else if (Value > 0xffffff) 2036 Value = (Value >> 24) | 0x600; 2037 Inst.addOperand(MCOperand::CreateImm(Value)); 2038 } 2039 2040 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const { 2041 assert(N == 1 && "Invalid number of operands!"); 2042 // The immediate encodes the type of constant as well as the value. 2043 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2044 unsigned Value = ~CE->getValue(); 2045 if (Value >= 256 && Value <= 0xffff) 2046 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); 2047 else if (Value > 0xffff && Value <= 0xffffff) 2048 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); 2049 else if (Value > 0xffffff) 2050 Value = (Value >> 24) | 0x600; 2051 Inst.addOperand(MCOperand::CreateImm(Value)); 2052 } 2053 2054 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const { 2055 assert(N == 1 && "Invalid number of operands!"); 2056 // The immediate encodes the type of constant as well as the value. 2057 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); 2058 uint64_t Value = CE->getValue(); 2059 unsigned Imm = 0; 2060 for (unsigned i = 0; i < 8; ++i, Value >>= 8) { 2061 Imm |= (Value & 1) << i; 2062 } 2063 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00)); 2064 } 2065 2066 virtual void print(raw_ostream &OS) const; 2067 2068 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) { 2069 ARMOperand *Op = new ARMOperand(k_ITCondMask); 2070 Op->ITMask.Mask = Mask; 2071 Op->StartLoc = S; 2072 Op->EndLoc = S; 2073 return Op; 2074 } 2075 2076 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) { 2077 ARMOperand *Op = new ARMOperand(k_CondCode); 2078 Op->CC.Val = CC; 2079 Op->StartLoc = S; 2080 Op->EndLoc = S; 2081 return Op; 2082 } 2083 2084 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) { 2085 ARMOperand *Op = new ARMOperand(k_CoprocNum); 2086 Op->Cop.Val = CopVal; 2087 Op->StartLoc = S; 2088 Op->EndLoc = S; 2089 return Op; 2090 } 2091 2092 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) { 2093 ARMOperand *Op = new ARMOperand(k_CoprocReg); 2094 Op->Cop.Val = CopVal; 2095 Op->StartLoc = S; 2096 Op->EndLoc = S; 2097 return Op; 2098 } 2099 2100 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) { 2101 ARMOperand *Op = new ARMOperand(k_CoprocOption); 2102 Op->Cop.Val = Val; 2103 Op->StartLoc = S; 2104 Op->EndLoc = E; 2105 return Op; 2106 } 2107 2108 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) { 2109 ARMOperand *Op = new ARMOperand(k_CCOut); 2110 Op->Reg.RegNum = RegNum; 2111 Op->StartLoc = S; 2112 Op->EndLoc = S; 2113 return Op; 2114 } 2115 2116 static ARMOperand *CreateToken(StringRef Str, SMLoc S) { 2117 ARMOperand *Op = new ARMOperand(k_Token); 2118 Op->Tok.Data = Str.data(); 2119 Op->Tok.Length = Str.size(); 2120 Op->StartLoc = S; 2121 Op->EndLoc = S; 2122 return Op; 2123 } 2124 2125 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { 2126 ARMOperand *Op = new ARMOperand(k_Register); 2127 Op->Reg.RegNum = RegNum; 2128 Op->StartLoc = S; 2129 Op->EndLoc = E; 2130 return Op; 2131 } 2132 2133 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, 2134 unsigned SrcReg, 2135 unsigned ShiftReg, 2136 unsigned ShiftImm, 2137 SMLoc S, SMLoc E) { 2138 ARMOperand *Op = new ARMOperand(k_ShiftedRegister); 2139 Op->RegShiftedReg.ShiftTy = ShTy; 2140 Op->RegShiftedReg.SrcReg = SrcReg; 2141 Op->RegShiftedReg.ShiftReg = ShiftReg; 2142 Op->RegShiftedReg.ShiftImm = ShiftImm; 2143 Op->StartLoc = S; 2144 Op->EndLoc = E; 2145 return Op; 2146 } 2147 2148 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, 2149 unsigned SrcReg, 2150 unsigned ShiftImm, 2151 SMLoc S, SMLoc E) { 2152 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate); 2153 Op->RegShiftedImm.ShiftTy = ShTy; 2154 Op->RegShiftedImm.SrcReg = SrcReg; 2155 Op->RegShiftedImm.ShiftImm = ShiftImm; 2156 Op->StartLoc = S; 2157 Op->EndLoc = E; 2158 return Op; 2159 } 2160 2161 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm, 2162 SMLoc S, SMLoc E) { 2163 ARMOperand *Op = new ARMOperand(k_ShifterImmediate); 2164 Op->ShifterImm.isASR = isASR; 2165 Op->ShifterImm.Imm = Imm; 2166 Op->StartLoc = S; 2167 Op->EndLoc = E; 2168 return Op; 2169 } 2170 2171 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) { 2172 ARMOperand *Op = new ARMOperand(k_RotateImmediate); 2173 Op->RotImm.Imm = Imm; 2174 Op->StartLoc = S; 2175 Op->EndLoc = E; 2176 return Op; 2177 } 2178 2179 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width, 2180 SMLoc S, SMLoc E) { 2181 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor); 2182 Op->Bitfield.LSB = LSB; 2183 Op->Bitfield.Width = Width; 2184 Op->StartLoc = S; 2185 Op->EndLoc = E; 2186 return Op; 2187 } 2188 2189 static ARMOperand * 2190 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs, 2191 SMLoc StartLoc, SMLoc EndLoc) { 2192 KindTy Kind = k_RegisterList; 2193 2194 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first)) 2195 Kind = k_DPRRegisterList; 2196 else if (ARMMCRegisterClasses[ARM::SPRRegClassID]. 2197 contains(Regs.front().first)) 2198 Kind = k_SPRRegisterList; 2199 2200 ARMOperand *Op = new ARMOperand(Kind); 2201 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator 2202 I = Regs.begin(), E = Regs.end(); I != E; ++I) 2203 Op->Registers.push_back(I->first); 2204 array_pod_sort(Op->Registers.begin(), Op->Registers.end()); 2205 Op->StartLoc = StartLoc; 2206 Op->EndLoc = EndLoc; 2207 return Op; 2208 } 2209 2210 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count, 2211 bool isDoubleSpaced, SMLoc S, SMLoc E) { 2212 ARMOperand *Op = new ARMOperand(k_VectorList); 2213 Op->VectorList.RegNum = RegNum; 2214 Op->VectorList.Count = Count; 2215 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2216 Op->StartLoc = S; 2217 Op->EndLoc = E; 2218 return Op; 2219 } 2220 2221 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count, 2222 bool isDoubleSpaced, 2223 SMLoc S, SMLoc E) { 2224 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes); 2225 Op->VectorList.RegNum = RegNum; 2226 Op->VectorList.Count = Count; 2227 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2228 Op->StartLoc = S; 2229 Op->EndLoc = E; 2230 return Op; 2231 } 2232 2233 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count, 2234 unsigned Index, 2235 bool isDoubleSpaced, 2236 SMLoc S, SMLoc E) { 2237 ARMOperand *Op = new ARMOperand(k_VectorListIndexed); 2238 Op->VectorList.RegNum = RegNum; 2239 Op->VectorList.Count = Count; 2240 Op->VectorList.LaneIndex = Index; 2241 Op->VectorList.isDoubleSpaced = isDoubleSpaced; 2242 Op->StartLoc = S; 2243 Op->EndLoc = E; 2244 return Op; 2245 } 2246 2247 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, 2248 MCContext &Ctx) { 2249 ARMOperand *Op = new ARMOperand(k_VectorIndex); 2250 Op->VectorIndex.Val = Idx; 2251 Op->StartLoc = S; 2252 Op->EndLoc = E; 2253 return Op; 2254 } 2255 2256 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { 2257 ARMOperand *Op = new ARMOperand(k_Immediate); 2258 Op->Imm.Val = Val; 2259 Op->StartLoc = S; 2260 Op->EndLoc = E; 2261 return Op; 2262 } 2263 2264 static ARMOperand *CreateMem(unsigned BaseRegNum, 2265 const MCConstantExpr *OffsetImm, 2266 unsigned OffsetRegNum, 2267 ARM_AM::ShiftOpc ShiftType, 2268 unsigned ShiftImm, 2269 unsigned Alignment, 2270 bool isNegative, 2271 SMLoc S, SMLoc E) { 2272 ARMOperand *Op = new ARMOperand(k_Memory); 2273 Op->Memory.BaseRegNum = BaseRegNum; 2274 Op->Memory.OffsetImm = OffsetImm; 2275 Op->Memory.OffsetRegNum = OffsetRegNum; 2276 Op->Memory.ShiftType = ShiftType; 2277 Op->Memory.ShiftImm = ShiftImm; 2278 Op->Memory.Alignment = Alignment; 2279 Op->Memory.isNegative = isNegative; 2280 Op->StartLoc = S; 2281 Op->EndLoc = E; 2282 return Op; 2283 } 2284 2285 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd, 2286 ARM_AM::ShiftOpc ShiftTy, 2287 unsigned ShiftImm, 2288 SMLoc S, SMLoc E) { 2289 ARMOperand *Op = new ARMOperand(k_PostIndexRegister); 2290 Op->PostIdxReg.RegNum = RegNum; 2291 Op->PostIdxReg.isAdd = isAdd; 2292 Op->PostIdxReg.ShiftTy = ShiftTy; 2293 Op->PostIdxReg.ShiftImm = ShiftImm; 2294 Op->StartLoc = S; 2295 Op->EndLoc = E; 2296 return Op; 2297 } 2298 2299 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) { 2300 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt); 2301 Op->MBOpt.Val = Opt; 2302 Op->StartLoc = S; 2303 Op->EndLoc = S; 2304 return Op; 2305 } 2306 2307 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) { 2308 ARMOperand *Op = new ARMOperand(k_ProcIFlags); 2309 Op->IFlags.Val = IFlags; 2310 Op->StartLoc = S; 2311 Op->EndLoc = S; 2312 return Op; 2313 } 2314 2315 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) { 2316 ARMOperand *Op = new ARMOperand(k_MSRMask); 2317 Op->MMask.Val = MMask; 2318 Op->StartLoc = S; 2319 Op->EndLoc = S; 2320 return Op; 2321 } 2322}; 2323 2324} // end anonymous namespace. 2325 2326void ARMOperand::print(raw_ostream &OS) const { 2327 switch (Kind) { 2328 case k_CondCode: 2329 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; 2330 break; 2331 case k_CCOut: 2332 OS << "<ccout " << getReg() << ">"; 2333 break; 2334 case k_ITCondMask: { 2335 static const char *const MaskStr[] = { 2336 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)", 2337 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)" 2338 }; 2339 assert((ITMask.Mask & 0xf) == ITMask.Mask); 2340 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">"; 2341 break; 2342 } 2343 case k_CoprocNum: 2344 OS << "<coprocessor number: " << getCoproc() << ">"; 2345 break; 2346 case k_CoprocReg: 2347 OS << "<coprocessor register: " << getCoproc() << ">"; 2348 break; 2349 case k_CoprocOption: 2350 OS << "<coprocessor option: " << CoprocOption.Val << ">"; 2351 break; 2352 case k_MSRMask: 2353 OS << "<mask: " << getMSRMask() << ">"; 2354 break; 2355 case k_Immediate: 2356 getImm()->print(OS); 2357 break; 2358 case k_MemBarrierOpt: 2359 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">"; 2360 break; 2361 case k_Memory: 2362 OS << "<memory " 2363 << " base:" << Memory.BaseRegNum; 2364 OS << ">"; 2365 break; 2366 case k_PostIndexRegister: 2367 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") 2368 << PostIdxReg.RegNum; 2369 if (PostIdxReg.ShiftTy != ARM_AM::no_shift) 2370 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " 2371 << PostIdxReg.ShiftImm; 2372 OS << ">"; 2373 break; 2374 case k_ProcIFlags: { 2375 OS << "<ARM_PROC::"; 2376 unsigned IFlags = getProcIFlags(); 2377 for (int i=2; i >= 0; --i) 2378 if (IFlags & (1 << i)) 2379 OS << ARM_PROC::IFlagsToString(1 << i); 2380 OS << ">"; 2381 break; 2382 } 2383 case k_Register: 2384 OS << "<register " << getReg() << ">"; 2385 break; 2386 case k_ShifterImmediate: 2387 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl") 2388 << " #" << ShifterImm.Imm << ">"; 2389 break; 2390 case k_ShiftedRegister: 2391 OS << "<so_reg_reg " 2392 << RegShiftedReg.SrcReg << " " 2393 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) 2394 << " " << RegShiftedReg.ShiftReg << ">"; 2395 break; 2396 case k_ShiftedImmediate: 2397 OS << "<so_reg_imm " 2398 << RegShiftedImm.SrcReg << " " 2399 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) 2400 << " #" << RegShiftedImm.ShiftImm << ">"; 2401 break; 2402 case k_RotateImmediate: 2403 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">"; 2404 break; 2405 case k_BitfieldDescriptor: 2406 OS << "<bitfield " << "lsb: " << Bitfield.LSB 2407 << ", width: " << Bitfield.Width << ">"; 2408 break; 2409 case k_RegisterList: 2410 case k_DPRRegisterList: 2411 case k_SPRRegisterList: { 2412 OS << "<register_list "; 2413 2414 const SmallVectorImpl<unsigned> &RegList = getRegList(); 2415 for (SmallVectorImpl<unsigned>::const_iterator 2416 I = RegList.begin(), E = RegList.end(); I != E; ) { 2417 OS << *I; 2418 if (++I < E) OS << ", "; 2419 } 2420 2421 OS << ">"; 2422 break; 2423 } 2424 case k_VectorList: 2425 OS << "<vector_list " << VectorList.Count << " * " 2426 << VectorList.RegNum << ">"; 2427 break; 2428 case k_VectorListAllLanes: 2429 OS << "<vector_list(all lanes) " << VectorList.Count << " * " 2430 << VectorList.RegNum << ">"; 2431 break; 2432 case k_VectorListIndexed: 2433 OS << "<vector_list(lane " << VectorList.LaneIndex << ") " 2434 << VectorList.Count << " * " << VectorList.RegNum << ">"; 2435 break; 2436 case k_Token: 2437 OS << "'" << getToken() << "'"; 2438 break; 2439 case k_VectorIndex: 2440 OS << "<vectorindex " << getVectorIndex() << ">"; 2441 break; 2442 } 2443} 2444 2445/// @name Auto-generated Match Functions 2446/// { 2447 2448static unsigned MatchRegisterName(StringRef Name); 2449 2450/// } 2451 2452bool ARMAsmParser::ParseRegister(unsigned &RegNo, 2453 SMLoc &StartLoc, SMLoc &EndLoc) { 2454 StartLoc = Parser.getTok().getLoc(); 2455 RegNo = tryParseRegister(); 2456 EndLoc = Parser.getTok().getLoc(); 2457 2458 return (RegNo == (unsigned)-1); 2459} 2460 2461/// Try to parse a register name. The token must be an Identifier when called, 2462/// and if it is a register name the token is eaten and the register number is 2463/// returned. Otherwise return -1. 2464/// 2465int ARMAsmParser::tryParseRegister() { 2466 const AsmToken &Tok = Parser.getTok(); 2467 if (Tok.isNot(AsmToken::Identifier)) return -1; 2468 2469 std::string lowerCase = Tok.getString().lower(); 2470 unsigned RegNum = MatchRegisterName(lowerCase); 2471 if (!RegNum) { 2472 RegNum = StringSwitch<unsigned>(lowerCase) 2473 .Case("r13", ARM::SP) 2474 .Case("r14", ARM::LR) 2475 .Case("r15", ARM::PC) 2476 .Case("ip", ARM::R12) 2477 // Additional register name aliases for 'gas' compatibility. 2478 .Case("a1", ARM::R0) 2479 .Case("a2", ARM::R1) 2480 .Case("a3", ARM::R2) 2481 .Case("a4", ARM::R3) 2482 .Case("v1", ARM::R4) 2483 .Case("v2", ARM::R5) 2484 .Case("v3", ARM::R6) 2485 .Case("v4", ARM::R7) 2486 .Case("v5", ARM::R8) 2487 .Case("v6", ARM::R9) 2488 .Case("v7", ARM::R10) 2489 .Case("v8", ARM::R11) 2490 .Case("sb", ARM::R9) 2491 .Case("sl", ARM::R10) 2492 .Case("fp", ARM::R11) 2493 .Default(0); 2494 } 2495 if (!RegNum) { 2496 // Check for aliases registered via .req. Canonicalize to lower case. 2497 // That's more consistent since register names are case insensitive, and 2498 // it's how the original entry was passed in from MC/MCParser/AsmParser. 2499 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase); 2500 // If no match, return failure. 2501 if (Entry == RegisterReqs.end()) 2502 return -1; 2503 Parser.Lex(); // Eat identifier token. 2504 return Entry->getValue(); 2505 } 2506 2507 Parser.Lex(); // Eat identifier token. 2508 2509 return RegNum; 2510} 2511 2512// Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0. 2513// If a recoverable error occurs, return 1. If an irrecoverable error 2514// occurs, return -1. An irrecoverable error is one where tokens have been 2515// consumed in the process of trying to parse the shifter (i.e., when it is 2516// indeed a shifter operand, but malformed). 2517int ARMAsmParser::tryParseShiftRegister( 2518 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2519 SMLoc S = Parser.getTok().getLoc(); 2520 const AsmToken &Tok = Parser.getTok(); 2521 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 2522 2523 std::string lowerCase = Tok.getString().lower(); 2524 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase) 2525 .Case("asl", ARM_AM::lsl) 2526 .Case("lsl", ARM_AM::lsl) 2527 .Case("lsr", ARM_AM::lsr) 2528 .Case("asr", ARM_AM::asr) 2529 .Case("ror", ARM_AM::ror) 2530 .Case("rrx", ARM_AM::rrx) 2531 .Default(ARM_AM::no_shift); 2532 2533 if (ShiftTy == ARM_AM::no_shift) 2534 return 1; 2535 2536 Parser.Lex(); // Eat the operator. 2537 2538 // The source register for the shift has already been added to the 2539 // operand list, so we need to pop it off and combine it into the shifted 2540 // register operand instead. 2541 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val()); 2542 if (!PrevOp->isReg()) 2543 return Error(PrevOp->getStartLoc(), "shift must be of a register"); 2544 int SrcReg = PrevOp->getReg(); 2545 int64_t Imm = 0; 2546 int ShiftReg = 0; 2547 if (ShiftTy == ARM_AM::rrx) { 2548 // RRX Doesn't have an explicit shift amount. The encoder expects 2549 // the shift register to be the same as the source register. Seems odd, 2550 // but OK. 2551 ShiftReg = SrcReg; 2552 } else { 2553 // Figure out if this is shifted by a constant or a register (for non-RRX). 2554 if (Parser.getTok().is(AsmToken::Hash) || 2555 Parser.getTok().is(AsmToken::Dollar)) { 2556 Parser.Lex(); // Eat hash. 2557 SMLoc ImmLoc = Parser.getTok().getLoc(); 2558 const MCExpr *ShiftExpr = 0; 2559 if (getParser().ParseExpression(ShiftExpr)) { 2560 Error(ImmLoc, "invalid immediate shift value"); 2561 return -1; 2562 } 2563 // The expression must be evaluatable as an immediate. 2564 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr); 2565 if (!CE) { 2566 Error(ImmLoc, "invalid immediate shift value"); 2567 return -1; 2568 } 2569 // Range check the immediate. 2570 // lsl, ror: 0 <= imm <= 31 2571 // lsr, asr: 0 <= imm <= 32 2572 Imm = CE->getValue(); 2573 if (Imm < 0 || 2574 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || 2575 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { 2576 Error(ImmLoc, "immediate shift value out of range"); 2577 return -1; 2578 } 2579 // shift by zero is a nop. Always send it through as lsl. 2580 // ('as' compatibility) 2581 if (Imm == 0) 2582 ShiftTy = ARM_AM::lsl; 2583 } else if (Parser.getTok().is(AsmToken::Identifier)) { 2584 ShiftReg = tryParseRegister(); 2585 SMLoc L = Parser.getTok().getLoc(); 2586 if (ShiftReg == -1) { 2587 Error (L, "expected immediate or register in shift operand"); 2588 return -1; 2589 } 2590 } else { 2591 Error (Parser.getTok().getLoc(), 2592 "expected immediate or register in shift operand"); 2593 return -1; 2594 } 2595 } 2596 2597 if (ShiftReg && ShiftTy != ARM_AM::rrx) 2598 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, 2599 ShiftReg, Imm, 2600 S, Parser.getTok().getLoc())); 2601 else 2602 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, 2603 S, Parser.getTok().getLoc())); 2604 2605 return 0; 2606} 2607 2608 2609/// Try to parse a register name. The token must be an Identifier when called. 2610/// If it's a register, an AsmOperand is created. Another AsmOperand is created 2611/// if there is a "writeback". 'true' if it's not a register. 2612/// 2613/// TODO this is likely to change to allow different register types and or to 2614/// parse for a specific register type. 2615bool ARMAsmParser:: 2616tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2617 SMLoc S = Parser.getTok().getLoc(); 2618 int RegNo = tryParseRegister(); 2619 if (RegNo == -1) 2620 return true; 2621 2622 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc())); 2623 2624 const AsmToken &ExclaimTok = Parser.getTok(); 2625 if (ExclaimTok.is(AsmToken::Exclaim)) { 2626 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), 2627 ExclaimTok.getLoc())); 2628 Parser.Lex(); // Eat exclaim token 2629 return false; 2630 } 2631 2632 // Also check for an index operand. This is only legal for vector registers, 2633 // but that'll get caught OK in operand matching, so we don't need to 2634 // explicitly filter everything else out here. 2635 if (Parser.getTok().is(AsmToken::LBrac)) { 2636 SMLoc SIdx = Parser.getTok().getLoc(); 2637 Parser.Lex(); // Eat left bracket token. 2638 2639 const MCExpr *ImmVal; 2640 if (getParser().ParseExpression(ImmVal)) 2641 return true; 2642 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal); 2643 if (!MCE) 2644 return TokError("immediate value expected for vector index"); 2645 2646 SMLoc E = Parser.getTok().getLoc(); 2647 if (Parser.getTok().isNot(AsmToken::RBrac)) 2648 return Error(E, "']' expected"); 2649 2650 Parser.Lex(); // Eat right bracket token. 2651 2652 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), 2653 SIdx, E, 2654 getContext())); 2655 } 2656 2657 return false; 2658} 2659 2660/// MatchCoprocessorOperandName - Try to parse an coprocessor related 2661/// instruction with a symbolic operand name. Example: "p1", "p7", "c3", 2662/// "c5", ... 2663static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { 2664 // Use the same layout as the tablegen'erated register name matcher. Ugly, 2665 // but efficient. 2666 switch (Name.size()) { 2667 default: return -1; 2668 case 2: 2669 if (Name[0] != CoprocOp) 2670 return -1; 2671 switch (Name[1]) { 2672 default: return -1; 2673 case '0': return 0; 2674 case '1': return 1; 2675 case '2': return 2; 2676 case '3': return 3; 2677 case '4': return 4; 2678 case '5': return 5; 2679 case '6': return 6; 2680 case '7': return 7; 2681 case '8': return 8; 2682 case '9': return 9; 2683 } 2684 case 3: 2685 if (Name[0] != CoprocOp || Name[1] != '1') 2686 return -1; 2687 switch (Name[2]) { 2688 default: return -1; 2689 case '0': return 10; 2690 case '1': return 11; 2691 case '2': return 12; 2692 case '3': return 13; 2693 case '4': return 14; 2694 case '5': return 15; 2695 } 2696 } 2697} 2698 2699/// parseITCondCode - Try to parse a condition code for an IT instruction. 2700ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2701parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2702 SMLoc S = Parser.getTok().getLoc(); 2703 const AsmToken &Tok = Parser.getTok(); 2704 if (!Tok.is(AsmToken::Identifier)) 2705 return MatchOperand_NoMatch; 2706 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower()) 2707 .Case("eq", ARMCC::EQ) 2708 .Case("ne", ARMCC::NE) 2709 .Case("hs", ARMCC::HS) 2710 .Case("cs", ARMCC::HS) 2711 .Case("lo", ARMCC::LO) 2712 .Case("cc", ARMCC::LO) 2713 .Case("mi", ARMCC::MI) 2714 .Case("pl", ARMCC::PL) 2715 .Case("vs", ARMCC::VS) 2716 .Case("vc", ARMCC::VC) 2717 .Case("hi", ARMCC::HI) 2718 .Case("ls", ARMCC::LS) 2719 .Case("ge", ARMCC::GE) 2720 .Case("lt", ARMCC::LT) 2721 .Case("gt", ARMCC::GT) 2722 .Case("le", ARMCC::LE) 2723 .Case("al", ARMCC::AL) 2724 .Default(~0U); 2725 if (CC == ~0U) 2726 return MatchOperand_NoMatch; 2727 Parser.Lex(); // Eat the token. 2728 2729 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); 2730 2731 return MatchOperand_Success; 2732} 2733 2734/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The 2735/// token must be an Identifier when called, and if it is a coprocessor 2736/// number, the token is eaten and the operand is added to the operand list. 2737ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2738parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2739 SMLoc S = Parser.getTok().getLoc(); 2740 const AsmToken &Tok = Parser.getTok(); 2741 if (Tok.isNot(AsmToken::Identifier)) 2742 return MatchOperand_NoMatch; 2743 2744 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p'); 2745 if (Num == -1) 2746 return MatchOperand_NoMatch; 2747 2748 Parser.Lex(); // Eat identifier token. 2749 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); 2750 return MatchOperand_Success; 2751} 2752 2753/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The 2754/// token must be an Identifier when called, and if it is a coprocessor 2755/// number, the token is eaten and the operand is added to the operand list. 2756ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2757parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2758 SMLoc S = Parser.getTok().getLoc(); 2759 const AsmToken &Tok = Parser.getTok(); 2760 if (Tok.isNot(AsmToken::Identifier)) 2761 return MatchOperand_NoMatch; 2762 2763 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c'); 2764 if (Reg == -1) 2765 return MatchOperand_NoMatch; 2766 2767 Parser.Lex(); // Eat identifier token. 2768 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); 2769 return MatchOperand_Success; 2770} 2771 2772/// parseCoprocOptionOperand - Try to parse an coprocessor option operand. 2773/// coproc_option : '{' imm0_255 '}' 2774ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2775parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2776 SMLoc S = Parser.getTok().getLoc(); 2777 2778 // If this isn't a '{', this isn't a coprocessor immediate operand. 2779 if (Parser.getTok().isNot(AsmToken::LCurly)) 2780 return MatchOperand_NoMatch; 2781 Parser.Lex(); // Eat the '{' 2782 2783 const MCExpr *Expr; 2784 SMLoc Loc = Parser.getTok().getLoc(); 2785 if (getParser().ParseExpression(Expr)) { 2786 Error(Loc, "illegal expression"); 2787 return MatchOperand_ParseFail; 2788 } 2789 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 2790 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) { 2791 Error(Loc, "coprocessor option must be an immediate in range [0, 255]"); 2792 return MatchOperand_ParseFail; 2793 } 2794 int Val = CE->getValue(); 2795 2796 // Check for and consume the closing '}' 2797 if (Parser.getTok().isNot(AsmToken::RCurly)) 2798 return MatchOperand_ParseFail; 2799 SMLoc E = Parser.getTok().getLoc(); 2800 Parser.Lex(); // Eat the '}' 2801 2802 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); 2803 return MatchOperand_Success; 2804} 2805 2806// For register list parsing, we need to map from raw GPR register numbering 2807// to the enumeration values. The enumeration values aren't sorted by 2808// register number due to our using "sp", "lr" and "pc" as canonical names. 2809static unsigned getNextRegister(unsigned Reg) { 2810 // If this is a GPR, we need to do it manually, otherwise we can rely 2811 // on the sort ordering of the enumeration since the other reg-classes 2812 // are sane. 2813 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2814 return Reg + 1; 2815 switch(Reg) { 2816 default: llvm_unreachable("Invalid GPR number!"); 2817 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; 2818 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; 2819 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; 2820 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; 2821 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; 2822 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; 2823 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; 2824 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; 2825 } 2826} 2827 2828// Return the low-subreg of a given Q register. 2829static unsigned getDRegFromQReg(unsigned QReg) { 2830 switch (QReg) { 2831 default: llvm_unreachable("expected a Q register!"); 2832 case ARM::Q0: return ARM::D0; 2833 case ARM::Q1: return ARM::D2; 2834 case ARM::Q2: return ARM::D4; 2835 case ARM::Q3: return ARM::D6; 2836 case ARM::Q4: return ARM::D8; 2837 case ARM::Q5: return ARM::D10; 2838 case ARM::Q6: return ARM::D12; 2839 case ARM::Q7: return ARM::D14; 2840 case ARM::Q8: return ARM::D16; 2841 case ARM::Q9: return ARM::D18; 2842 case ARM::Q10: return ARM::D20; 2843 case ARM::Q11: return ARM::D22; 2844 case ARM::Q12: return ARM::D24; 2845 case ARM::Q13: return ARM::D26; 2846 case ARM::Q14: return ARM::D28; 2847 case ARM::Q15: return ARM::D30; 2848 } 2849} 2850 2851/// Parse a register list. 2852bool ARMAsmParser:: 2853parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 2854 assert(Parser.getTok().is(AsmToken::LCurly) && 2855 "Token is not a Left Curly Brace"); 2856 SMLoc S = Parser.getTok().getLoc(); 2857 Parser.Lex(); // Eat '{' token. 2858 SMLoc RegLoc = Parser.getTok().getLoc(); 2859 2860 // Check the first register in the list to see what register class 2861 // this is a list of. 2862 int Reg = tryParseRegister(); 2863 if (Reg == -1) 2864 return Error(RegLoc, "register expected"); 2865 2866 // The reglist instructions have at most 16 registers, so reserve 2867 // space for that many. 2868 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers; 2869 2870 // Allow Q regs and just interpret them as the two D sub-registers. 2871 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 2872 Reg = getDRegFromQReg(Reg); 2873 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2874 ++Reg; 2875 } 2876 const MCRegisterClass *RC; 2877 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2878 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; 2879 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) 2880 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; 2881 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) 2882 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; 2883 else 2884 return Error(RegLoc, "invalid register in register list"); 2885 2886 // Store the register. 2887 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2888 2889 // This starts immediately after the first register token in the list, 2890 // so we can see either a comma or a minus (range separator) as a legal 2891 // next token. 2892 while (Parser.getTok().is(AsmToken::Comma) || 2893 Parser.getTok().is(AsmToken::Minus)) { 2894 if (Parser.getTok().is(AsmToken::Minus)) { 2895 Parser.Lex(); // Eat the minus. 2896 SMLoc EndLoc = Parser.getTok().getLoc(); 2897 int EndReg = tryParseRegister(); 2898 if (EndReg == -1) 2899 return Error(EndLoc, "register expected"); 2900 // Allow Q regs and just interpret them as the two D sub-registers. 2901 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 2902 EndReg = getDRegFromQReg(EndReg) + 1; 2903 // If the register is the same as the start reg, there's nothing 2904 // more to do. 2905 if (Reg == EndReg) 2906 continue; 2907 // The register must be in the same register class as the first. 2908 if (!RC->contains(EndReg)) 2909 return Error(EndLoc, "invalid register in register list"); 2910 // Ranges must go from low to high. 2911 if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg)) 2912 return Error(EndLoc, "bad range in register list"); 2913 2914 // Add all the registers in the range to the register list. 2915 while (Reg != EndReg) { 2916 Reg = getNextRegister(Reg); 2917 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2918 } 2919 continue; 2920 } 2921 Parser.Lex(); // Eat the comma. 2922 RegLoc = Parser.getTok().getLoc(); 2923 int OldReg = Reg; 2924 const AsmToken RegTok = Parser.getTok(); 2925 Reg = tryParseRegister(); 2926 if (Reg == -1) 2927 return Error(RegLoc, "register expected"); 2928 // Allow Q regs and just interpret them as the two D sub-registers. 2929 bool isQReg = false; 2930 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 2931 Reg = getDRegFromQReg(Reg); 2932 isQReg = true; 2933 } 2934 // The register must be in the same register class as the first. 2935 if (!RC->contains(Reg)) 2936 return Error(RegLoc, "invalid register in register list"); 2937 // List must be monotonically increasing. 2938 if (getARMRegisterNumbering(Reg) < getARMRegisterNumbering(OldReg)) { 2939 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 2940 Warning(RegLoc, "register list not in ascending order"); 2941 else 2942 return Error(RegLoc, "register list not in ascending order"); 2943 } 2944 if (getARMRegisterNumbering(Reg) == getARMRegisterNumbering(OldReg)) { 2945 Warning(RegLoc, "duplicated register (" + RegTok.getString() + 2946 ") in register list"); 2947 continue; 2948 } 2949 // VFP register lists must also be contiguous. 2950 // It's OK to use the enumeration values directly here rather, as the 2951 // VFP register classes have the enum sorted properly. 2952 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && 2953 Reg != OldReg + 1) 2954 return Error(RegLoc, "non-contiguous register range"); 2955 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc)); 2956 if (isQReg) 2957 Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc)); 2958 } 2959 2960 SMLoc E = Parser.getTok().getLoc(); 2961 if (Parser.getTok().isNot(AsmToken::RCurly)) 2962 return Error(E, "'}' expected"); 2963 Parser.Lex(); // Eat '}' token. 2964 2965 // Push the register list operand. 2966 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); 2967 2968 // The ARM system instruction variants for LDM/STM have a '^' token here. 2969 if (Parser.getTok().is(AsmToken::Caret)) { 2970 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc())); 2971 Parser.Lex(); // Eat '^' token. 2972 } 2973 2974 return false; 2975} 2976 2977// Helper function to parse the lane index for vector lists. 2978ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 2979parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index) { 2980 Index = 0; // Always return a defined index value. 2981 if (Parser.getTok().is(AsmToken::LBrac)) { 2982 Parser.Lex(); // Eat the '['. 2983 if (Parser.getTok().is(AsmToken::RBrac)) { 2984 // "Dn[]" is the 'all lanes' syntax. 2985 LaneKind = AllLanes; 2986 Parser.Lex(); // Eat the ']'. 2987 return MatchOperand_Success; 2988 } 2989 2990 // There's an optional '#' token here. Normally there wouldn't be, but 2991 // inline assemble puts one in, and it's friendly to accept that. 2992 if (Parser.getTok().is(AsmToken::Hash)) 2993 Parser.Lex(); // Eat the '#' 2994 2995 const MCExpr *LaneIndex; 2996 SMLoc Loc = Parser.getTok().getLoc(); 2997 if (getParser().ParseExpression(LaneIndex)) { 2998 Error(Loc, "illegal expression"); 2999 return MatchOperand_ParseFail; 3000 } 3001 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex); 3002 if (!CE) { 3003 Error(Loc, "lane index must be empty or an integer"); 3004 return MatchOperand_ParseFail; 3005 } 3006 if (Parser.getTok().isNot(AsmToken::RBrac)) { 3007 Error(Parser.getTok().getLoc(), "']' expected"); 3008 return MatchOperand_ParseFail; 3009 } 3010 Parser.Lex(); // Eat the ']'. 3011 int64_t Val = CE->getValue(); 3012 3013 // FIXME: Make this range check context sensitive for .8, .16, .32. 3014 if (Val < 0 || Val > 7) { 3015 Error(Parser.getTok().getLoc(), "lane index out of range"); 3016 return MatchOperand_ParseFail; 3017 } 3018 Index = Val; 3019 LaneKind = IndexedLane; 3020 return MatchOperand_Success; 3021 } 3022 LaneKind = NoLanes; 3023 return MatchOperand_Success; 3024} 3025 3026// parse a vector register list 3027ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3028parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3029 VectorLaneTy LaneKind; 3030 unsigned LaneIndex; 3031 SMLoc S = Parser.getTok().getLoc(); 3032 // As an extension (to match gas), support a plain D register or Q register 3033 // (without encosing curly braces) as a single or double entry list, 3034 // respectively. 3035 if (Parser.getTok().is(AsmToken::Identifier)) { 3036 int Reg = tryParseRegister(); 3037 if (Reg == -1) 3038 return MatchOperand_NoMatch; 3039 SMLoc E = Parser.getTok().getLoc(); 3040 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { 3041 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex); 3042 if (Res != MatchOperand_Success) 3043 return Res; 3044 switch (LaneKind) { 3045 case NoLanes: 3046 E = Parser.getTok().getLoc(); 3047 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E)); 3048 break; 3049 case AllLanes: 3050 E = Parser.getTok().getLoc(); 3051 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, 3052 S, E)); 3053 break; 3054 case IndexedLane: 3055 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, 3056 LaneIndex, 3057 false, S, E)); 3058 break; 3059 } 3060 return MatchOperand_Success; 3061 } 3062 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3063 Reg = getDRegFromQReg(Reg); 3064 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex); 3065 if (Res != MatchOperand_Success) 3066 return Res; 3067 switch (LaneKind) { 3068 case NoLanes: 3069 E = Parser.getTok().getLoc(); 3070 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3071 &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3072 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); 3073 break; 3074 case AllLanes: 3075 E = Parser.getTok().getLoc(); 3076 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, 3077 &ARMMCRegisterClasses[ARM::DPairRegClassID]); 3078 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, 3079 S, E)); 3080 break; 3081 case IndexedLane: 3082 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, 3083 LaneIndex, 3084 false, S, E)); 3085 break; 3086 } 3087 return MatchOperand_Success; 3088 } 3089 Error(S, "vector register expected"); 3090 return MatchOperand_ParseFail; 3091 } 3092 3093 if (Parser.getTok().isNot(AsmToken::LCurly)) 3094 return MatchOperand_NoMatch; 3095 3096 Parser.Lex(); // Eat '{' token. 3097 SMLoc RegLoc = Parser.getTok().getLoc(); 3098 3099 int Reg = tryParseRegister(); 3100 if (Reg == -1) { 3101 Error(RegLoc, "register expected"); 3102 return MatchOperand_ParseFail; 3103 } 3104 unsigned Count = 1; 3105 int Spacing = 0; 3106 unsigned FirstReg = Reg; 3107 // The list is of D registers, but we also allow Q regs and just interpret 3108 // them as the two D sub-registers. 3109 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3110 FirstReg = Reg = getDRegFromQReg(Reg); 3111 Spacing = 1; // double-spacing requires explicit D registers, otherwise 3112 // it's ambiguous with four-register single spaced. 3113 ++Reg; 3114 ++Count; 3115 } 3116 if (parseVectorLane(LaneKind, LaneIndex) != MatchOperand_Success) 3117 return MatchOperand_ParseFail; 3118 3119 while (Parser.getTok().is(AsmToken::Comma) || 3120 Parser.getTok().is(AsmToken::Minus)) { 3121 if (Parser.getTok().is(AsmToken::Minus)) { 3122 if (!Spacing) 3123 Spacing = 1; // Register range implies a single spaced list. 3124 else if (Spacing == 2) { 3125 Error(Parser.getTok().getLoc(), 3126 "sequential registers in double spaced list"); 3127 return MatchOperand_ParseFail; 3128 } 3129 Parser.Lex(); // Eat the minus. 3130 SMLoc EndLoc = Parser.getTok().getLoc(); 3131 int EndReg = tryParseRegister(); 3132 if (EndReg == -1) { 3133 Error(EndLoc, "register expected"); 3134 return MatchOperand_ParseFail; 3135 } 3136 // Allow Q regs and just interpret them as the two D sub-registers. 3137 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) 3138 EndReg = getDRegFromQReg(EndReg) + 1; 3139 // If the register is the same as the start reg, there's nothing 3140 // more to do. 3141 if (Reg == EndReg) 3142 continue; 3143 // The register must be in the same register class as the first. 3144 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) { 3145 Error(EndLoc, "invalid register in register list"); 3146 return MatchOperand_ParseFail; 3147 } 3148 // Ranges must go from low to high. 3149 if (Reg > EndReg) { 3150 Error(EndLoc, "bad range in register list"); 3151 return MatchOperand_ParseFail; 3152 } 3153 // Parse the lane specifier if present. 3154 VectorLaneTy NextLaneKind; 3155 unsigned NextLaneIndex; 3156 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success) 3157 return MatchOperand_ParseFail; 3158 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3159 Error(EndLoc, "mismatched lane index in register list"); 3160 return MatchOperand_ParseFail; 3161 } 3162 EndLoc = Parser.getTok().getLoc(); 3163 3164 // Add all the registers in the range to the register list. 3165 Count += EndReg - Reg; 3166 Reg = EndReg; 3167 continue; 3168 } 3169 Parser.Lex(); // Eat the comma. 3170 RegLoc = Parser.getTok().getLoc(); 3171 int OldReg = Reg; 3172 Reg = tryParseRegister(); 3173 if (Reg == -1) { 3174 Error(RegLoc, "register expected"); 3175 return MatchOperand_ParseFail; 3176 } 3177 // vector register lists must be contiguous. 3178 // It's OK to use the enumeration values directly here rather, as the 3179 // VFP register classes have the enum sorted properly. 3180 // 3181 // The list is of D registers, but we also allow Q regs and just interpret 3182 // them as the two D sub-registers. 3183 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { 3184 if (!Spacing) 3185 Spacing = 1; // Register range implies a single spaced list. 3186 else if (Spacing == 2) { 3187 Error(RegLoc, 3188 "invalid register in double-spaced list (must be 'D' register')"); 3189 return MatchOperand_ParseFail; 3190 } 3191 Reg = getDRegFromQReg(Reg); 3192 if (Reg != OldReg + 1) { 3193 Error(RegLoc, "non-contiguous register range"); 3194 return MatchOperand_ParseFail; 3195 } 3196 ++Reg; 3197 Count += 2; 3198 // Parse the lane specifier if present. 3199 VectorLaneTy NextLaneKind; 3200 unsigned NextLaneIndex; 3201 SMLoc EndLoc = Parser.getTok().getLoc(); 3202 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success) 3203 return MatchOperand_ParseFail; 3204 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3205 Error(EndLoc, "mismatched lane index in register list"); 3206 return MatchOperand_ParseFail; 3207 } 3208 continue; 3209 } 3210 // Normal D register. 3211 // Figure out the register spacing (single or double) of the list if 3212 // we don't know it already. 3213 if (!Spacing) 3214 Spacing = 1 + (Reg == OldReg + 2); 3215 3216 // Just check that it's contiguous and keep going. 3217 if (Reg != OldReg + Spacing) { 3218 Error(RegLoc, "non-contiguous register range"); 3219 return MatchOperand_ParseFail; 3220 } 3221 ++Count; 3222 // Parse the lane specifier if present. 3223 VectorLaneTy NextLaneKind; 3224 unsigned NextLaneIndex; 3225 SMLoc EndLoc = Parser.getTok().getLoc(); 3226 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success) 3227 return MatchOperand_ParseFail; 3228 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { 3229 Error(EndLoc, "mismatched lane index in register list"); 3230 return MatchOperand_ParseFail; 3231 } 3232 } 3233 3234 SMLoc E = Parser.getTok().getLoc(); 3235 if (Parser.getTok().isNot(AsmToken::RCurly)) { 3236 Error(E, "'}' expected"); 3237 return MatchOperand_ParseFail; 3238 } 3239 Parser.Lex(); // Eat '}' token. 3240 3241 switch (LaneKind) { 3242 case NoLanes: 3243 // Two-register operands have been converted to the 3244 // composite register classes. 3245 if (Count == 2) { 3246 const MCRegisterClass *RC = (Spacing == 1) ? 3247 &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3248 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3249 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3250 } 3251 3252 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, 3253 (Spacing == 2), S, E)); 3254 break; 3255 case AllLanes: 3256 // Two-register operands have been converted to the 3257 // composite register classes. 3258 if (Count == 2) { 3259 const MCRegisterClass *RC = (Spacing == 1) ? 3260 &ARMMCRegisterClasses[ARM::DPairRegClassID] : 3261 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; 3262 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); 3263 } 3264 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count, 3265 (Spacing == 2), 3266 S, E)); 3267 break; 3268 case IndexedLane: 3269 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, 3270 LaneIndex, 3271 (Spacing == 2), 3272 S, E)); 3273 break; 3274 } 3275 return MatchOperand_Success; 3276} 3277 3278/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. 3279ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3280parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3281 SMLoc S = Parser.getTok().getLoc(); 3282 const AsmToken &Tok = Parser.getTok(); 3283 unsigned Opt; 3284 3285 if (Tok.is(AsmToken::Identifier)) { 3286 StringRef OptStr = Tok.getString(); 3287 3288 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower()) 3289 .Case("sy", ARM_MB::SY) 3290 .Case("st", ARM_MB::ST) 3291 .Case("sh", ARM_MB::ISH) 3292 .Case("ish", ARM_MB::ISH) 3293 .Case("shst", ARM_MB::ISHST) 3294 .Case("ishst", ARM_MB::ISHST) 3295 .Case("nsh", ARM_MB::NSH) 3296 .Case("un", ARM_MB::NSH) 3297 .Case("nshst", ARM_MB::NSHST) 3298 .Case("unst", ARM_MB::NSHST) 3299 .Case("osh", ARM_MB::OSH) 3300 .Case("oshst", ARM_MB::OSHST) 3301 .Default(~0U); 3302 3303 if (Opt == ~0U) 3304 return MatchOperand_NoMatch; 3305 3306 Parser.Lex(); // Eat identifier token. 3307 } else if (Tok.is(AsmToken::Hash) || 3308 Tok.is(AsmToken::Dollar) || 3309 Tok.is(AsmToken::Integer)) { 3310 if (Parser.getTok().isNot(AsmToken::Integer)) 3311 Parser.Lex(); // Eat the '#'. 3312 SMLoc Loc = Parser.getTok().getLoc(); 3313 3314 const MCExpr *MemBarrierID; 3315 if (getParser().ParseExpression(MemBarrierID)) { 3316 Error(Loc, "illegal expression"); 3317 return MatchOperand_ParseFail; 3318 } 3319 3320 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID); 3321 if (!CE) { 3322 Error(Loc, "constant expression expected"); 3323 return MatchOperand_ParseFail; 3324 } 3325 3326 int Val = CE->getValue(); 3327 if (Val & ~0xf) { 3328 Error(Loc, "immediate value out of range"); 3329 return MatchOperand_ParseFail; 3330 } 3331 3332 Opt = ARM_MB::RESERVED_0 + Val; 3333 } else 3334 return MatchOperand_ParseFail; 3335 3336 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); 3337 return MatchOperand_Success; 3338} 3339 3340/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. 3341ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3342parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3343 SMLoc S = Parser.getTok().getLoc(); 3344 const AsmToken &Tok = Parser.getTok(); 3345 if (!Tok.is(AsmToken::Identifier)) 3346 return MatchOperand_NoMatch; 3347 StringRef IFlagsStr = Tok.getString(); 3348 3349 // An iflags string of "none" is interpreted to mean that none of the AIF 3350 // bits are set. Not a terribly useful instruction, but a valid encoding. 3351 unsigned IFlags = 0; 3352 if (IFlagsStr != "none") { 3353 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { 3354 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1)) 3355 .Case("a", ARM_PROC::A) 3356 .Case("i", ARM_PROC::I) 3357 .Case("f", ARM_PROC::F) 3358 .Default(~0U); 3359 3360 // If some specific iflag is already set, it means that some letter is 3361 // present more than once, this is not acceptable. 3362 if (Flag == ~0U || (IFlags & Flag)) 3363 return MatchOperand_NoMatch; 3364 3365 IFlags |= Flag; 3366 } 3367 } 3368 3369 Parser.Lex(); // Eat identifier token. 3370 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); 3371 return MatchOperand_Success; 3372} 3373 3374/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. 3375ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3376parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3377 SMLoc S = Parser.getTok().getLoc(); 3378 const AsmToken &Tok = Parser.getTok(); 3379 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); 3380 StringRef Mask = Tok.getString(); 3381 3382 if (isMClass()) { 3383 // See ARMv6-M 10.1.1 3384 std::string Name = Mask.lower(); 3385 unsigned FlagsVal = StringSwitch<unsigned>(Name) 3386 // Note: in the documentation: 3387 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias 3388 // for MSR APSR_nzcvq. 3389 // but we do make it an alias here. This is so to get the "mask encoding" 3390 // bits correct on MSR APSR writes. 3391 // 3392 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers 3393 // should really only be allowed when writing a special register. Note 3394 // they get dropped in the MRS instruction reading a special register as 3395 // the SYSm field is only 8 bits. 3396 // 3397 // FIXME: the _g and _nzcvqg versions are only allowed if the processor 3398 // includes the DSP extension but that is not checked. 3399 .Case("apsr", 0x800) 3400 .Case("apsr_nzcvq", 0x800) 3401 .Case("apsr_g", 0x400) 3402 .Case("apsr_nzcvqg", 0xc00) 3403 .Case("iapsr", 0x801) 3404 .Case("iapsr_nzcvq", 0x801) 3405 .Case("iapsr_g", 0x401) 3406 .Case("iapsr_nzcvqg", 0xc01) 3407 .Case("eapsr", 0x802) 3408 .Case("eapsr_nzcvq", 0x802) 3409 .Case("eapsr_g", 0x402) 3410 .Case("eapsr_nzcvqg", 0xc02) 3411 .Case("xpsr", 0x803) 3412 .Case("xpsr_nzcvq", 0x803) 3413 .Case("xpsr_g", 0x403) 3414 .Case("xpsr_nzcvqg", 0xc03) 3415 .Case("ipsr", 0x805) 3416 .Case("epsr", 0x806) 3417 .Case("iepsr", 0x807) 3418 .Case("msp", 0x808) 3419 .Case("psp", 0x809) 3420 .Case("primask", 0x810) 3421 .Case("basepri", 0x811) 3422 .Case("basepri_max", 0x812) 3423 .Case("faultmask", 0x813) 3424 .Case("control", 0x814) 3425 .Default(~0U); 3426 3427 if (FlagsVal == ~0U) 3428 return MatchOperand_NoMatch; 3429 3430 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813) 3431 // basepri, basepri_max and faultmask only valid for V7m. 3432 return MatchOperand_NoMatch; 3433 3434 Parser.Lex(); // Eat identifier token. 3435 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3436 return MatchOperand_Success; 3437 } 3438 3439 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" 3440 size_t Start = 0, Next = Mask.find('_'); 3441 StringRef Flags = ""; 3442 std::string SpecReg = Mask.slice(Start, Next).lower(); 3443 if (Next != StringRef::npos) 3444 Flags = Mask.slice(Next+1, Mask.size()); 3445 3446 // FlagsVal contains the complete mask: 3447 // 3-0: Mask 3448 // 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3449 unsigned FlagsVal = 0; 3450 3451 if (SpecReg == "apsr") { 3452 FlagsVal = StringSwitch<unsigned>(Flags) 3453 .Case("nzcvq", 0x8) // same as CPSR_f 3454 .Case("g", 0x4) // same as CPSR_s 3455 .Case("nzcvqg", 0xc) // same as CPSR_fs 3456 .Default(~0U); 3457 3458 if (FlagsVal == ~0U) { 3459 if (!Flags.empty()) 3460 return MatchOperand_NoMatch; 3461 else 3462 FlagsVal = 8; // No flag 3463 } 3464 } else if (SpecReg == "cpsr" || SpecReg == "spsr") { 3465 // cpsr_all is an alias for cpsr_fc, as is plain cpsr. 3466 if (Flags == "all" || Flags == "") 3467 Flags = "fc"; 3468 for (int i = 0, e = Flags.size(); i != e; ++i) { 3469 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1)) 3470 .Case("c", 1) 3471 .Case("x", 2) 3472 .Case("s", 4) 3473 .Case("f", 8) 3474 .Default(~0U); 3475 3476 // If some specific flag is already set, it means that some letter is 3477 // present more than once, this is not acceptable. 3478 if (FlagsVal == ~0U || (FlagsVal & Flag)) 3479 return MatchOperand_NoMatch; 3480 FlagsVal |= Flag; 3481 } 3482 } else // No match for special register. 3483 return MatchOperand_NoMatch; 3484 3485 // Special register without flags is NOT equivalent to "fc" flags. 3486 // NOTE: This is a divergence from gas' behavior. Uncommenting the following 3487 // two lines would enable gas compatibility at the expense of breaking 3488 // round-tripping. 3489 // 3490 // if (!FlagsVal) 3491 // FlagsVal = 0x9; 3492 3493 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) 3494 if (SpecReg == "spsr") 3495 FlagsVal |= 16; 3496 3497 Parser.Lex(); // Eat identifier token. 3498 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); 3499 return MatchOperand_Success; 3500} 3501 3502ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3503parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op, 3504 int Low, int High) { 3505 const AsmToken &Tok = Parser.getTok(); 3506 if (Tok.isNot(AsmToken::Identifier)) { 3507 Error(Parser.getTok().getLoc(), Op + " operand expected."); 3508 return MatchOperand_ParseFail; 3509 } 3510 StringRef ShiftName = Tok.getString(); 3511 std::string LowerOp = Op.lower(); 3512 std::string UpperOp = Op.upper(); 3513 if (ShiftName != LowerOp && ShiftName != UpperOp) { 3514 Error(Parser.getTok().getLoc(), Op + " operand expected."); 3515 return MatchOperand_ParseFail; 3516 } 3517 Parser.Lex(); // Eat shift type token. 3518 3519 // There must be a '#' and a shift amount. 3520 if (Parser.getTok().isNot(AsmToken::Hash) && 3521 Parser.getTok().isNot(AsmToken::Dollar)) { 3522 Error(Parser.getTok().getLoc(), "'#' expected"); 3523 return MatchOperand_ParseFail; 3524 } 3525 Parser.Lex(); // Eat hash token. 3526 3527 const MCExpr *ShiftAmount; 3528 SMLoc Loc = Parser.getTok().getLoc(); 3529 if (getParser().ParseExpression(ShiftAmount)) { 3530 Error(Loc, "illegal expression"); 3531 return MatchOperand_ParseFail; 3532 } 3533 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3534 if (!CE) { 3535 Error(Loc, "constant expression expected"); 3536 return MatchOperand_ParseFail; 3537 } 3538 int Val = CE->getValue(); 3539 if (Val < Low || Val > High) { 3540 Error(Loc, "immediate value out of range"); 3541 return MatchOperand_ParseFail; 3542 } 3543 3544 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc())); 3545 3546 return MatchOperand_Success; 3547} 3548 3549ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3550parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3551 const AsmToken &Tok = Parser.getTok(); 3552 SMLoc S = Tok.getLoc(); 3553 if (Tok.isNot(AsmToken::Identifier)) { 3554 Error(Tok.getLoc(), "'be' or 'le' operand expected"); 3555 return MatchOperand_ParseFail; 3556 } 3557 int Val = StringSwitch<int>(Tok.getString()) 3558 .Case("be", 1) 3559 .Case("le", 0) 3560 .Default(-1); 3561 Parser.Lex(); // Eat the token. 3562 3563 if (Val == -1) { 3564 Error(Tok.getLoc(), "'be' or 'le' operand expected"); 3565 return MatchOperand_ParseFail; 3566 } 3567 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val, 3568 getContext()), 3569 S, Parser.getTok().getLoc())); 3570 return MatchOperand_Success; 3571} 3572 3573/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT 3574/// instructions. Legal values are: 3575/// lsl #n 'n' in [0,31] 3576/// asr #n 'n' in [1,32] 3577/// n == 32 encoded as n == 0. 3578ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3579parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3580 const AsmToken &Tok = Parser.getTok(); 3581 SMLoc S = Tok.getLoc(); 3582 if (Tok.isNot(AsmToken::Identifier)) { 3583 Error(S, "shift operator 'asr' or 'lsl' expected"); 3584 return MatchOperand_ParseFail; 3585 } 3586 StringRef ShiftName = Tok.getString(); 3587 bool isASR; 3588 if (ShiftName == "lsl" || ShiftName == "LSL") 3589 isASR = false; 3590 else if (ShiftName == "asr" || ShiftName == "ASR") 3591 isASR = true; 3592 else { 3593 Error(S, "shift operator 'asr' or 'lsl' expected"); 3594 return MatchOperand_ParseFail; 3595 } 3596 Parser.Lex(); // Eat the operator. 3597 3598 // A '#' and a shift amount. 3599 if (Parser.getTok().isNot(AsmToken::Hash) && 3600 Parser.getTok().isNot(AsmToken::Dollar)) { 3601 Error(Parser.getTok().getLoc(), "'#' expected"); 3602 return MatchOperand_ParseFail; 3603 } 3604 Parser.Lex(); // Eat hash token. 3605 3606 const MCExpr *ShiftAmount; 3607 SMLoc E = Parser.getTok().getLoc(); 3608 if (getParser().ParseExpression(ShiftAmount)) { 3609 Error(E, "malformed shift expression"); 3610 return MatchOperand_ParseFail; 3611 } 3612 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3613 if (!CE) { 3614 Error(E, "shift amount must be an immediate"); 3615 return MatchOperand_ParseFail; 3616 } 3617 3618 int64_t Val = CE->getValue(); 3619 if (isASR) { 3620 // Shift amount must be in [1,32] 3621 if (Val < 1 || Val > 32) { 3622 Error(E, "'asr' shift amount must be in range [1,32]"); 3623 return MatchOperand_ParseFail; 3624 } 3625 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode. 3626 if (isThumb() && Val == 32) { 3627 Error(E, "'asr #32' shift amount not allowed in Thumb mode"); 3628 return MatchOperand_ParseFail; 3629 } 3630 if (Val == 32) Val = 0; 3631 } else { 3632 // Shift amount must be in [1,32] 3633 if (Val < 0 || Val > 31) { 3634 Error(E, "'lsr' shift amount must be in range [0,31]"); 3635 return MatchOperand_ParseFail; 3636 } 3637 } 3638 3639 E = Parser.getTok().getLoc(); 3640 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E)); 3641 3642 return MatchOperand_Success; 3643} 3644 3645/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family 3646/// of instructions. Legal values are: 3647/// ror #n 'n' in {0, 8, 16, 24} 3648ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3649parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3650 const AsmToken &Tok = Parser.getTok(); 3651 SMLoc S = Tok.getLoc(); 3652 if (Tok.isNot(AsmToken::Identifier)) 3653 return MatchOperand_NoMatch; 3654 StringRef ShiftName = Tok.getString(); 3655 if (ShiftName != "ror" && ShiftName != "ROR") 3656 return MatchOperand_NoMatch; 3657 Parser.Lex(); // Eat the operator. 3658 3659 // A '#' and a rotate amount. 3660 if (Parser.getTok().isNot(AsmToken::Hash) && 3661 Parser.getTok().isNot(AsmToken::Dollar)) { 3662 Error(Parser.getTok().getLoc(), "'#' expected"); 3663 return MatchOperand_ParseFail; 3664 } 3665 Parser.Lex(); // Eat hash token. 3666 3667 const MCExpr *ShiftAmount; 3668 SMLoc E = Parser.getTok().getLoc(); 3669 if (getParser().ParseExpression(ShiftAmount)) { 3670 Error(E, "malformed rotate expression"); 3671 return MatchOperand_ParseFail; 3672 } 3673 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); 3674 if (!CE) { 3675 Error(E, "rotate amount must be an immediate"); 3676 return MatchOperand_ParseFail; 3677 } 3678 3679 int64_t Val = CE->getValue(); 3680 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) 3681 // normally, zero is represented in asm by omitting the rotate operand 3682 // entirely. 3683 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { 3684 Error(E, "'ror' rotate amount must be 8, 16, or 24"); 3685 return MatchOperand_ParseFail; 3686 } 3687 3688 E = Parser.getTok().getLoc(); 3689 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E)); 3690 3691 return MatchOperand_Success; 3692} 3693 3694ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3695parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3696 SMLoc S = Parser.getTok().getLoc(); 3697 // The bitfield descriptor is really two operands, the LSB and the width. 3698 if (Parser.getTok().isNot(AsmToken::Hash) && 3699 Parser.getTok().isNot(AsmToken::Dollar)) { 3700 Error(Parser.getTok().getLoc(), "'#' expected"); 3701 return MatchOperand_ParseFail; 3702 } 3703 Parser.Lex(); // Eat hash token. 3704 3705 const MCExpr *LSBExpr; 3706 SMLoc E = Parser.getTok().getLoc(); 3707 if (getParser().ParseExpression(LSBExpr)) { 3708 Error(E, "malformed immediate expression"); 3709 return MatchOperand_ParseFail; 3710 } 3711 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr); 3712 if (!CE) { 3713 Error(E, "'lsb' operand must be an immediate"); 3714 return MatchOperand_ParseFail; 3715 } 3716 3717 int64_t LSB = CE->getValue(); 3718 // The LSB must be in the range [0,31] 3719 if (LSB < 0 || LSB > 31) { 3720 Error(E, "'lsb' operand must be in the range [0,31]"); 3721 return MatchOperand_ParseFail; 3722 } 3723 E = Parser.getTok().getLoc(); 3724 3725 // Expect another immediate operand. 3726 if (Parser.getTok().isNot(AsmToken::Comma)) { 3727 Error(Parser.getTok().getLoc(), "too few operands"); 3728 return MatchOperand_ParseFail; 3729 } 3730 Parser.Lex(); // Eat hash token. 3731 if (Parser.getTok().isNot(AsmToken::Hash) && 3732 Parser.getTok().isNot(AsmToken::Dollar)) { 3733 Error(Parser.getTok().getLoc(), "'#' expected"); 3734 return MatchOperand_ParseFail; 3735 } 3736 Parser.Lex(); // Eat hash token. 3737 3738 const MCExpr *WidthExpr; 3739 if (getParser().ParseExpression(WidthExpr)) { 3740 Error(E, "malformed immediate expression"); 3741 return MatchOperand_ParseFail; 3742 } 3743 CE = dyn_cast<MCConstantExpr>(WidthExpr); 3744 if (!CE) { 3745 Error(E, "'width' operand must be an immediate"); 3746 return MatchOperand_ParseFail; 3747 } 3748 3749 int64_t Width = CE->getValue(); 3750 // The LSB must be in the range [1,32-lsb] 3751 if (Width < 1 || Width > 32 - LSB) { 3752 Error(E, "'width' operand must be in the range [1,32-lsb]"); 3753 return MatchOperand_ParseFail; 3754 } 3755 E = Parser.getTok().getLoc(); 3756 3757 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E)); 3758 3759 return MatchOperand_Success; 3760} 3761 3762ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3763parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3764 // Check for a post-index addressing register operand. Specifically: 3765 // postidx_reg := '+' register {, shift} 3766 // | '-' register {, shift} 3767 // | register {, shift} 3768 3769 // This method must return MatchOperand_NoMatch without consuming any tokens 3770 // in the case where there is no match, as other alternatives take other 3771 // parse methods. 3772 AsmToken Tok = Parser.getTok(); 3773 SMLoc S = Tok.getLoc(); 3774 bool haveEaten = false; 3775 bool isAdd = true; 3776 int Reg = -1; 3777 if (Tok.is(AsmToken::Plus)) { 3778 Parser.Lex(); // Eat the '+' token. 3779 haveEaten = true; 3780 } else if (Tok.is(AsmToken::Minus)) { 3781 Parser.Lex(); // Eat the '-' token. 3782 isAdd = false; 3783 haveEaten = true; 3784 } 3785 if (Parser.getTok().is(AsmToken::Identifier)) 3786 Reg = tryParseRegister(); 3787 if (Reg == -1) { 3788 if (!haveEaten) 3789 return MatchOperand_NoMatch; 3790 Error(Parser.getTok().getLoc(), "register expected"); 3791 return MatchOperand_ParseFail; 3792 } 3793 SMLoc E = Parser.getTok().getLoc(); 3794 3795 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; 3796 unsigned ShiftImm = 0; 3797 if (Parser.getTok().is(AsmToken::Comma)) { 3798 Parser.Lex(); // Eat the ','. 3799 if (parseMemRegOffsetShift(ShiftTy, ShiftImm)) 3800 return MatchOperand_ParseFail; 3801 } 3802 3803 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, 3804 ShiftImm, S, E)); 3805 3806 return MatchOperand_Success; 3807} 3808 3809ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 3810parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3811 // Check for a post-index addressing register operand. Specifically: 3812 // am3offset := '+' register 3813 // | '-' register 3814 // | register 3815 // | # imm 3816 // | # + imm 3817 // | # - imm 3818 3819 // This method must return MatchOperand_NoMatch without consuming any tokens 3820 // in the case where there is no match, as other alternatives take other 3821 // parse methods. 3822 AsmToken Tok = Parser.getTok(); 3823 SMLoc S = Tok.getLoc(); 3824 3825 // Do immediates first, as we always parse those if we have a '#'. 3826 if (Parser.getTok().is(AsmToken::Hash) || 3827 Parser.getTok().is(AsmToken::Dollar)) { 3828 Parser.Lex(); // Eat the '#'. 3829 // Explicitly look for a '-', as we need to encode negative zero 3830 // differently. 3831 bool isNegative = Parser.getTok().is(AsmToken::Minus); 3832 const MCExpr *Offset; 3833 if (getParser().ParseExpression(Offset)) 3834 return MatchOperand_ParseFail; 3835 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 3836 if (!CE) { 3837 Error(S, "constant expression expected"); 3838 return MatchOperand_ParseFail; 3839 } 3840 SMLoc E = Tok.getLoc(); 3841 // Negative zero is encoded as the flag value INT32_MIN. 3842 int32_t Val = CE->getValue(); 3843 if (isNegative && Val == 0) 3844 Val = INT32_MIN; 3845 3846 Operands.push_back( 3847 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E)); 3848 3849 return MatchOperand_Success; 3850 } 3851 3852 3853 bool haveEaten = false; 3854 bool isAdd = true; 3855 int Reg = -1; 3856 if (Tok.is(AsmToken::Plus)) { 3857 Parser.Lex(); // Eat the '+' token. 3858 haveEaten = true; 3859 } else if (Tok.is(AsmToken::Minus)) { 3860 Parser.Lex(); // Eat the '-' token. 3861 isAdd = false; 3862 haveEaten = true; 3863 } 3864 if (Parser.getTok().is(AsmToken::Identifier)) 3865 Reg = tryParseRegister(); 3866 if (Reg == -1) { 3867 if (!haveEaten) 3868 return MatchOperand_NoMatch; 3869 Error(Parser.getTok().getLoc(), "register expected"); 3870 return MatchOperand_ParseFail; 3871 } 3872 SMLoc E = Parser.getTok().getLoc(); 3873 3874 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, 3875 0, S, E)); 3876 3877 return MatchOperand_Success; 3878} 3879 3880/// cvtT2LdrdPre - Convert parsed operands to MCInst. 3881/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3882/// when they refer multiple MIOperands inside a single one. 3883bool ARMAsmParser:: 3884cvtT2LdrdPre(MCInst &Inst, unsigned Opcode, 3885 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3886 // Rt, Rt2 3887 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3888 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 3889 // Create a writeback register dummy placeholder. 3890 Inst.addOperand(MCOperand::CreateReg(0)); 3891 // addr 3892 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); 3893 // pred 3894 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3895 return true; 3896} 3897 3898/// cvtT2StrdPre - Convert parsed operands to MCInst. 3899/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3900/// when they refer multiple MIOperands inside a single one. 3901bool ARMAsmParser:: 3902cvtT2StrdPre(MCInst &Inst, unsigned Opcode, 3903 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3904 // Create a writeback register dummy placeholder. 3905 Inst.addOperand(MCOperand::CreateReg(0)); 3906 // Rt, Rt2 3907 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3908 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 3909 // addr 3910 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2); 3911 // pred 3912 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3913 return true; 3914} 3915 3916/// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst. 3917/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3918/// when they refer multiple MIOperands inside a single one. 3919bool ARMAsmParser:: 3920cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 3921 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3922 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3923 3924 // Create a writeback register dummy placeholder. 3925 Inst.addOperand(MCOperand::CreateImm(0)); 3926 3927 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2); 3928 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3929 return true; 3930} 3931 3932/// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst. 3933/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3934/// when they refer multiple MIOperands inside a single one. 3935bool ARMAsmParser:: 3936cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode, 3937 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3938 // Create a writeback register dummy placeholder. 3939 Inst.addOperand(MCOperand::CreateImm(0)); 3940 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3941 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2); 3942 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3943 return true; 3944} 3945 3946/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 3947/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3948/// when they refer multiple MIOperands inside a single one. 3949bool ARMAsmParser:: 3950cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 3951 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3952 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3953 3954 // Create a writeback register dummy placeholder. 3955 Inst.addOperand(MCOperand::CreateImm(0)); 3956 3957 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 3958 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3959 return true; 3960} 3961 3962/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. 3963/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3964/// when they refer multiple MIOperands inside a single one. 3965bool ARMAsmParser:: 3966cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 3967 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3968 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3969 3970 // Create a writeback register dummy placeholder. 3971 Inst.addOperand(MCOperand::CreateImm(0)); 3972 3973 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); 3974 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3975 return true; 3976} 3977 3978 3979/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst. 3980/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3981/// when they refer multiple MIOperands inside a single one. 3982bool ARMAsmParser:: 3983cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode, 3984 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3985 // Create a writeback register dummy placeholder. 3986 Inst.addOperand(MCOperand::CreateImm(0)); 3987 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 3988 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2); 3989 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 3990 return true; 3991} 3992 3993/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst. 3994/// Needed here because the Asm Gen Matcher can't handle properly tied operands 3995/// when they refer multiple MIOperands inside a single one. 3996bool ARMAsmParser:: 3997cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode, 3998 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 3999 // Create a writeback register dummy placeholder. 4000 Inst.addOperand(MCOperand::CreateImm(0)); 4001 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4002 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3); 4003 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4004 return true; 4005} 4006 4007/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 4008/// Needed here because the Asm Gen Matcher can't handle properly tied operands 4009/// when they refer multiple MIOperands inside a single one. 4010bool ARMAsmParser:: 4011cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 4012 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4013 // Create a writeback register dummy placeholder. 4014 Inst.addOperand(MCOperand::CreateImm(0)); 4015 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4016 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 4017 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4018 return true; 4019} 4020 4021/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst. 4022/// Needed here because the Asm Gen Matcher can't handle properly tied operands 4023/// when they refer multiple MIOperands inside a single one. 4024bool ARMAsmParser:: 4025cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 4026 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4027 // Rt 4028 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4029 // Create a writeback register dummy placeholder. 4030 Inst.addOperand(MCOperand::CreateImm(0)); 4031 // addr 4032 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 4033 // offset 4034 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 4035 // pred 4036 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4037 return true; 4038} 4039 4040/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst. 4041/// Needed here because the Asm Gen Matcher can't handle properly tied operands 4042/// when they refer multiple MIOperands inside a single one. 4043bool ARMAsmParser:: 4044cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 4045 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4046 // Rt 4047 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4048 // Create a writeback register dummy placeholder. 4049 Inst.addOperand(MCOperand::CreateImm(0)); 4050 // addr 4051 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 4052 // offset 4053 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 4054 // pred 4055 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4056 return true; 4057} 4058 4059/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst. 4060/// Needed here because the Asm Gen Matcher can't handle properly tied operands 4061/// when they refer multiple MIOperands inside a single one. 4062bool ARMAsmParser:: 4063cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode, 4064 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4065 // Create a writeback register dummy placeholder. 4066 Inst.addOperand(MCOperand::CreateImm(0)); 4067 // Rt 4068 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4069 // addr 4070 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 4071 // offset 4072 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1); 4073 // pred 4074 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4075 return true; 4076} 4077 4078/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst. 4079/// Needed here because the Asm Gen Matcher can't handle properly tied operands 4080/// when they refer multiple MIOperands inside a single one. 4081bool ARMAsmParser:: 4082cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode, 4083 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4084 // Create a writeback register dummy placeholder. 4085 Inst.addOperand(MCOperand::CreateImm(0)); 4086 // Rt 4087 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4088 // addr 4089 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1); 4090 // offset 4091 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2); 4092 // pred 4093 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4094 return true; 4095} 4096 4097/// cvtLdrdPre - Convert parsed operands to MCInst. 4098/// Needed here because the Asm Gen Matcher can't handle properly tied operands 4099/// when they refer multiple MIOperands inside a single one. 4100bool ARMAsmParser:: 4101cvtLdrdPre(MCInst &Inst, unsigned Opcode, 4102 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4103 // Rt, Rt2 4104 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4105 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 4106 // Create a writeback register dummy placeholder. 4107 Inst.addOperand(MCOperand::CreateImm(0)); 4108 // addr 4109 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 4110 // pred 4111 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4112 return true; 4113} 4114 4115/// cvtStrdPre - Convert parsed operands to MCInst. 4116/// Needed here because the Asm Gen Matcher can't handle properly tied operands 4117/// when they refer multiple MIOperands inside a single one. 4118bool ARMAsmParser:: 4119cvtStrdPre(MCInst &Inst, unsigned Opcode, 4120 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4121 // Create a writeback register dummy placeholder. 4122 Inst.addOperand(MCOperand::CreateImm(0)); 4123 // Rt, Rt2 4124 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4125 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 4126 // addr 4127 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3); 4128 // pred 4129 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4130 return true; 4131} 4132 4133/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst. 4134/// Needed here because the Asm Gen Matcher can't handle properly tied operands 4135/// when they refer multiple MIOperands inside a single one. 4136bool ARMAsmParser:: 4137cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode, 4138 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4139 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1); 4140 // Create a writeback register dummy placeholder. 4141 Inst.addOperand(MCOperand::CreateImm(0)); 4142 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3); 4143 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4144 return true; 4145} 4146 4147/// cvtThumbMultiple- Convert parsed operands to MCInst. 4148/// Needed here because the Asm Gen Matcher can't handle properly tied operands 4149/// when they refer multiple MIOperands inside a single one. 4150bool ARMAsmParser:: 4151cvtThumbMultiply(MCInst &Inst, unsigned Opcode, 4152 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4153 // The second source operand must be the same register as the destination 4154 // operand. 4155 if (Operands.size() == 6 && 4156 (((ARMOperand*)Operands[3])->getReg() != 4157 ((ARMOperand*)Operands[5])->getReg()) && 4158 (((ARMOperand*)Operands[3])->getReg() != 4159 ((ARMOperand*)Operands[4])->getReg())) { 4160 Error(Operands[3]->getStartLoc(), 4161 "destination register must match source register"); 4162 return false; 4163 } 4164 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1); 4165 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1); 4166 // If we have a three-operand form, make sure to set Rn to be the operand 4167 // that isn't the same as Rd. 4168 unsigned RegOp = 4; 4169 if (Operands.size() == 6 && 4170 ((ARMOperand*)Operands[4])->getReg() == 4171 ((ARMOperand*)Operands[3])->getReg()) 4172 RegOp = 5; 4173 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1); 4174 Inst.addOperand(Inst.getOperand(0)); 4175 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2); 4176 4177 return true; 4178} 4179 4180bool ARMAsmParser:: 4181cvtVLDwbFixed(MCInst &Inst, unsigned Opcode, 4182 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4183 // Vd 4184 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 4185 // Create a writeback register dummy placeholder. 4186 Inst.addOperand(MCOperand::CreateImm(0)); 4187 // Vn 4188 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 4189 // pred 4190 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4191 return true; 4192} 4193 4194bool ARMAsmParser:: 4195cvtVLDwbRegister(MCInst &Inst, unsigned Opcode, 4196 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4197 // Vd 4198 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 4199 // Create a writeback register dummy placeholder. 4200 Inst.addOperand(MCOperand::CreateImm(0)); 4201 // Vn 4202 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 4203 // Vm 4204 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); 4205 // pred 4206 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4207 return true; 4208} 4209 4210bool ARMAsmParser:: 4211cvtVSTwbFixed(MCInst &Inst, unsigned Opcode, 4212 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4213 // Create a writeback register dummy placeholder. 4214 Inst.addOperand(MCOperand::CreateImm(0)); 4215 // Vn 4216 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 4217 // Vt 4218 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 4219 // pred 4220 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4221 return true; 4222} 4223 4224bool ARMAsmParser:: 4225cvtVSTwbRegister(MCInst &Inst, unsigned Opcode, 4226 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4227 // Create a writeback register dummy placeholder. 4228 Inst.addOperand(MCOperand::CreateImm(0)); 4229 // Vn 4230 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2); 4231 // Vm 4232 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1); 4233 // Vt 4234 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1); 4235 // pred 4236 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2); 4237 return true; 4238} 4239 4240/// Parse an ARM memory expression, return false if successful else return true 4241/// or an error. The first token must be a '[' when called. 4242bool ARMAsmParser:: 4243parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4244 SMLoc S, E; 4245 assert(Parser.getTok().is(AsmToken::LBrac) && 4246 "Token is not a Left Bracket"); 4247 S = Parser.getTok().getLoc(); 4248 Parser.Lex(); // Eat left bracket token. 4249 4250 const AsmToken &BaseRegTok = Parser.getTok(); 4251 int BaseRegNum = tryParseRegister(); 4252 if (BaseRegNum == -1) 4253 return Error(BaseRegTok.getLoc(), "register expected"); 4254 4255 // The next token must either be a comma or a closing bracket. 4256 const AsmToken &Tok = Parser.getTok(); 4257 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac)) 4258 return Error(Tok.getLoc(), "malformed memory operand"); 4259 4260 if (Tok.is(AsmToken::RBrac)) { 4261 E = Tok.getLoc(); 4262 Parser.Lex(); // Eat right bracket token. 4263 4264 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift, 4265 0, 0, false, S, E)); 4266 4267 // If there's a pre-indexing writeback marker, '!', just add it as a token 4268 // operand. It's rather odd, but syntactically valid. 4269 if (Parser.getTok().is(AsmToken::Exclaim)) { 4270 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4271 Parser.Lex(); // Eat the '!'. 4272 } 4273 4274 return false; 4275 } 4276 4277 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!"); 4278 Parser.Lex(); // Eat the comma. 4279 4280 // If we have a ':', it's an alignment specifier. 4281 if (Parser.getTok().is(AsmToken::Colon)) { 4282 Parser.Lex(); // Eat the ':'. 4283 E = Parser.getTok().getLoc(); 4284 4285 const MCExpr *Expr; 4286 if (getParser().ParseExpression(Expr)) 4287 return true; 4288 4289 // The expression has to be a constant. Memory references with relocations 4290 // don't come through here, as they use the <label> forms of the relevant 4291 // instructions. 4292 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 4293 if (!CE) 4294 return Error (E, "constant expression expected"); 4295 4296 unsigned Align = 0; 4297 switch (CE->getValue()) { 4298 default: 4299 return Error(E, 4300 "alignment specifier must be 16, 32, 64, 128, or 256 bits"); 4301 case 16: Align = 2; break; 4302 case 32: Align = 4; break; 4303 case 64: Align = 8; break; 4304 case 128: Align = 16; break; 4305 case 256: Align = 32; break; 4306 } 4307 4308 // Now we should have the closing ']' 4309 E = Parser.getTok().getLoc(); 4310 if (Parser.getTok().isNot(AsmToken::RBrac)) 4311 return Error(E, "']' expected"); 4312 Parser.Lex(); // Eat right bracket token. 4313 4314 // Don't worry about range checking the value here. That's handled by 4315 // the is*() predicates. 4316 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, 4317 ARM_AM::no_shift, 0, Align, 4318 false, S, E)); 4319 4320 // If there's a pre-indexing writeback marker, '!', just add it as a token 4321 // operand. 4322 if (Parser.getTok().is(AsmToken::Exclaim)) { 4323 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4324 Parser.Lex(); // Eat the '!'. 4325 } 4326 4327 return false; 4328 } 4329 4330 // If we have a '#', it's an immediate offset, else assume it's a register 4331 // offset. Be friendly and also accept a plain integer (without a leading 4332 // hash) for gas compatibility. 4333 if (Parser.getTok().is(AsmToken::Hash) || 4334 Parser.getTok().is(AsmToken::Dollar) || 4335 Parser.getTok().is(AsmToken::Integer)) { 4336 if (Parser.getTok().isNot(AsmToken::Integer)) 4337 Parser.Lex(); // Eat the '#'. 4338 E = Parser.getTok().getLoc(); 4339 4340 bool isNegative = getParser().getTok().is(AsmToken::Minus); 4341 const MCExpr *Offset; 4342 if (getParser().ParseExpression(Offset)) 4343 return true; 4344 4345 // The expression has to be a constant. Memory references with relocations 4346 // don't come through here, as they use the <label> forms of the relevant 4347 // instructions. 4348 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset); 4349 if (!CE) 4350 return Error (E, "constant expression expected"); 4351 4352 // If the constant was #-0, represent it as INT32_MIN. 4353 int32_t Val = CE->getValue(); 4354 if (isNegative && Val == 0) 4355 CE = MCConstantExpr::Create(INT32_MIN, getContext()); 4356 4357 // Now we should have the closing ']' 4358 E = Parser.getTok().getLoc(); 4359 if (Parser.getTok().isNot(AsmToken::RBrac)) 4360 return Error(E, "']' expected"); 4361 Parser.Lex(); // Eat right bracket token. 4362 4363 // Don't worry about range checking the value here. That's handled by 4364 // the is*() predicates. 4365 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0, 4366 ARM_AM::no_shift, 0, 0, 4367 false, S, E)); 4368 4369 // If there's a pre-indexing writeback marker, '!', just add it as a token 4370 // operand. 4371 if (Parser.getTok().is(AsmToken::Exclaim)) { 4372 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4373 Parser.Lex(); // Eat the '!'. 4374 } 4375 4376 return false; 4377 } 4378 4379 // The register offset is optionally preceded by a '+' or '-' 4380 bool isNegative = false; 4381 if (Parser.getTok().is(AsmToken::Minus)) { 4382 isNegative = true; 4383 Parser.Lex(); // Eat the '-'. 4384 } else if (Parser.getTok().is(AsmToken::Plus)) { 4385 // Nothing to do. 4386 Parser.Lex(); // Eat the '+'. 4387 } 4388 4389 E = Parser.getTok().getLoc(); 4390 int OffsetRegNum = tryParseRegister(); 4391 if (OffsetRegNum == -1) 4392 return Error(E, "register expected"); 4393 4394 // If there's a shift operator, handle it. 4395 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift; 4396 unsigned ShiftImm = 0; 4397 if (Parser.getTok().is(AsmToken::Comma)) { 4398 Parser.Lex(); // Eat the ','. 4399 if (parseMemRegOffsetShift(ShiftType, ShiftImm)) 4400 return true; 4401 } 4402 4403 // Now we should have the closing ']' 4404 E = Parser.getTok().getLoc(); 4405 if (Parser.getTok().isNot(AsmToken::RBrac)) 4406 return Error(E, "']' expected"); 4407 Parser.Lex(); // Eat right bracket token. 4408 4409 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum, 4410 ShiftType, ShiftImm, 0, isNegative, 4411 S, E)); 4412 4413 // If there's a pre-indexing writeback marker, '!', just add it as a token 4414 // operand. 4415 if (Parser.getTok().is(AsmToken::Exclaim)) { 4416 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); 4417 Parser.Lex(); // Eat the '!'. 4418 } 4419 4420 return false; 4421} 4422 4423/// parseMemRegOffsetShift - one of these two: 4424/// ( lsl | lsr | asr | ror ) , # shift_amount 4425/// rrx 4426/// return true if it parses a shift otherwise it returns false. 4427bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St, 4428 unsigned &Amount) { 4429 SMLoc Loc = Parser.getTok().getLoc(); 4430 const AsmToken &Tok = Parser.getTok(); 4431 if (Tok.isNot(AsmToken::Identifier)) 4432 return true; 4433 StringRef ShiftName = Tok.getString(); 4434 if (ShiftName == "lsl" || ShiftName == "LSL" || 4435 ShiftName == "asl" || ShiftName == "ASL") 4436 St = ARM_AM::lsl; 4437 else if (ShiftName == "lsr" || ShiftName == "LSR") 4438 St = ARM_AM::lsr; 4439 else if (ShiftName == "asr" || ShiftName == "ASR") 4440 St = ARM_AM::asr; 4441 else if (ShiftName == "ror" || ShiftName == "ROR") 4442 St = ARM_AM::ror; 4443 else if (ShiftName == "rrx" || ShiftName == "RRX") 4444 St = ARM_AM::rrx; 4445 else 4446 return Error(Loc, "illegal shift operator"); 4447 Parser.Lex(); // Eat shift type token. 4448 4449 // rrx stands alone. 4450 Amount = 0; 4451 if (St != ARM_AM::rrx) { 4452 Loc = Parser.getTok().getLoc(); 4453 // A '#' and a shift amount. 4454 const AsmToken &HashTok = Parser.getTok(); 4455 if (HashTok.isNot(AsmToken::Hash) && 4456 HashTok.isNot(AsmToken::Dollar)) 4457 return Error(HashTok.getLoc(), "'#' expected"); 4458 Parser.Lex(); // Eat hash token. 4459 4460 const MCExpr *Expr; 4461 if (getParser().ParseExpression(Expr)) 4462 return true; 4463 // Range check the immediate. 4464 // lsl, ror: 0 <= imm <= 31 4465 // lsr, asr: 0 <= imm <= 32 4466 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr); 4467 if (!CE) 4468 return Error(Loc, "shift amount must be an immediate"); 4469 int64_t Imm = CE->getValue(); 4470 if (Imm < 0 || 4471 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) || 4472 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32)) 4473 return Error(Loc, "immediate shift value out of range"); 4474 Amount = Imm; 4475 } 4476 4477 return false; 4478} 4479 4480/// parseFPImm - A floating point immediate expression operand. 4481ARMAsmParser::OperandMatchResultTy ARMAsmParser:: 4482parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4483 // Anything that can accept a floating point constant as an operand 4484 // needs to go through here, as the regular ParseExpression is 4485 // integer only. 4486 // 4487 // This routine still creates a generic Immediate operand, containing 4488 // a bitcast of the 64-bit floating point value. The various operands 4489 // that accept floats can check whether the value is valid for them 4490 // via the standard is*() predicates. 4491 4492 SMLoc S = Parser.getTok().getLoc(); 4493 4494 if (Parser.getTok().isNot(AsmToken::Hash) && 4495 Parser.getTok().isNot(AsmToken::Dollar)) 4496 return MatchOperand_NoMatch; 4497 4498 // Disambiguate the VMOV forms that can accept an FP immediate. 4499 // vmov.f32 <sreg>, #imm 4500 // vmov.f64 <dreg>, #imm 4501 // vmov.f32 <dreg>, #imm @ vector f32x2 4502 // vmov.f32 <qreg>, #imm @ vector f32x4 4503 // 4504 // There are also the NEON VMOV instructions which expect an 4505 // integer constant. Make sure we don't try to parse an FPImm 4506 // for these: 4507 // vmov.i{8|16|32|64} <dreg|qreg>, #imm 4508 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]); 4509 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" && 4510 TyOp->getToken() != ".f64")) 4511 return MatchOperand_NoMatch; 4512 4513 Parser.Lex(); // Eat the '#'. 4514 4515 // Handle negation, as that still comes through as a separate token. 4516 bool isNegative = false; 4517 if (Parser.getTok().is(AsmToken::Minus)) { 4518 isNegative = true; 4519 Parser.Lex(); 4520 } 4521 const AsmToken &Tok = Parser.getTok(); 4522 SMLoc Loc = Tok.getLoc(); 4523 if (Tok.is(AsmToken::Real)) { 4524 APFloat RealVal(APFloat::IEEEsingle, Tok.getString()); 4525 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue(); 4526 // If we had a '-' in front, toggle the sign bit. 4527 IntVal ^= (uint64_t)isNegative << 31; 4528 Parser.Lex(); // Eat the token. 4529 Operands.push_back(ARMOperand::CreateImm( 4530 MCConstantExpr::Create(IntVal, getContext()), 4531 S, Parser.getTok().getLoc())); 4532 return MatchOperand_Success; 4533 } 4534 // Also handle plain integers. Instructions which allow floating point 4535 // immediates also allow a raw encoded 8-bit value. 4536 if (Tok.is(AsmToken::Integer)) { 4537 int64_t Val = Tok.getIntVal(); 4538 Parser.Lex(); // Eat the token. 4539 if (Val > 255 || Val < 0) { 4540 Error(Loc, "encoded floating point value out of range"); 4541 return MatchOperand_ParseFail; 4542 } 4543 double RealVal = ARM_AM::getFPImmFloat(Val); 4544 Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue(); 4545 Operands.push_back(ARMOperand::CreateImm( 4546 MCConstantExpr::Create(Val, getContext()), S, 4547 Parser.getTok().getLoc())); 4548 return MatchOperand_Success; 4549 } 4550 4551 Error(Loc, "invalid floating point immediate"); 4552 return MatchOperand_ParseFail; 4553} 4554 4555/// Parse a arm instruction operand. For now this parses the operand regardless 4556/// of the mnemonic. 4557bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands, 4558 StringRef Mnemonic) { 4559 SMLoc S, E; 4560 4561 // Check if the current operand has a custom associated parser, if so, try to 4562 // custom parse the operand, or fallback to the general approach. 4563 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 4564 if (ResTy == MatchOperand_Success) 4565 return false; 4566 // If there wasn't a custom match, try the generic matcher below. Otherwise, 4567 // there was a match, but an error occurred, in which case, just return that 4568 // the operand parsing failed. 4569 if (ResTy == MatchOperand_ParseFail) 4570 return true; 4571 4572 switch (getLexer().getKind()) { 4573 default: 4574 Error(Parser.getTok().getLoc(), "unexpected token in operand"); 4575 return true; 4576 case AsmToken::Identifier: { 4577 if (!tryParseRegisterWithWriteBack(Operands)) 4578 return false; 4579 int Res = tryParseShiftRegister(Operands); 4580 if (Res == 0) // success 4581 return false; 4582 else if (Res == -1) // irrecoverable error 4583 return true; 4584 // If this is VMRS, check for the apsr_nzcv operand. 4585 if (Mnemonic == "vmrs" && 4586 Parser.getTok().getString().equals_lower("apsr_nzcv")) { 4587 S = Parser.getTok().getLoc(); 4588 Parser.Lex(); 4589 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S)); 4590 return false; 4591 } 4592 4593 // Fall though for the Identifier case that is not a register or a 4594 // special name. 4595 } 4596 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4) 4597 case AsmToken::Integer: // things like 1f and 2b as a branch targets 4598 case AsmToken::String: // quoted label names. 4599 case AsmToken::Dot: { // . as a branch target 4600 // This was not a register so parse other operands that start with an 4601 // identifier (like labels) as expressions and create them as immediates. 4602 const MCExpr *IdVal; 4603 S = Parser.getTok().getLoc(); 4604 if (getParser().ParseExpression(IdVal)) 4605 return true; 4606 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4607 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E)); 4608 return false; 4609 } 4610 case AsmToken::LBrac: 4611 return parseMemory(Operands); 4612 case AsmToken::LCurly: 4613 return parseRegisterList(Operands); 4614 case AsmToken::Dollar: 4615 case AsmToken::Hash: { 4616 // #42 -> immediate. 4617 S = Parser.getTok().getLoc(); 4618 Parser.Lex(); 4619 4620 if (Parser.getTok().isNot(AsmToken::Colon)) { 4621 bool isNegative = Parser.getTok().is(AsmToken::Minus); 4622 const MCExpr *ImmVal; 4623 if (getParser().ParseExpression(ImmVal)) 4624 return true; 4625 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal); 4626 if (CE) { 4627 int32_t Val = CE->getValue(); 4628 if (isNegative && Val == 0) 4629 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext()); 4630 } 4631 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4632 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); 4633 return false; 4634 } 4635 // w/ a ':' after the '#', it's just like a plain ':'. 4636 // FALLTHROUGH 4637 } 4638 case AsmToken::Colon: { 4639 // ":lower16:" and ":upper16:" expression prefixes 4640 // FIXME: Check it's an expression prefix, 4641 // e.g. (FOO - :lower16:BAR) isn't legal. 4642 ARMMCExpr::VariantKind RefKind; 4643 if (parsePrefix(RefKind)) 4644 return true; 4645 4646 const MCExpr *SubExprVal; 4647 if (getParser().ParseExpression(SubExprVal)) 4648 return true; 4649 4650 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal, 4651 getContext()); 4652 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 4653 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); 4654 return false; 4655 } 4656 } 4657} 4658 4659// parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. 4660// :lower16: and :upper16:. 4661bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) { 4662 RefKind = ARMMCExpr::VK_ARM_None; 4663 4664 // :lower16: and :upper16: modifiers 4665 assert(getLexer().is(AsmToken::Colon) && "expected a :"); 4666 Parser.Lex(); // Eat ':' 4667 4668 if (getLexer().isNot(AsmToken::Identifier)) { 4669 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); 4670 return true; 4671 } 4672 4673 StringRef IDVal = Parser.getTok().getIdentifier(); 4674 if (IDVal == "lower16") { 4675 RefKind = ARMMCExpr::VK_ARM_LO16; 4676 } else if (IDVal == "upper16") { 4677 RefKind = ARMMCExpr::VK_ARM_HI16; 4678 } else { 4679 Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); 4680 return true; 4681 } 4682 Parser.Lex(); 4683 4684 if (getLexer().isNot(AsmToken::Colon)) { 4685 Error(Parser.getTok().getLoc(), "unexpected token after prefix"); 4686 return true; 4687 } 4688 Parser.Lex(); // Eat the last ':' 4689 return false; 4690} 4691 4692/// \brief Given a mnemonic, split out possible predication code and carry 4693/// setting letters to form a canonical mnemonic and flags. 4694// 4695// FIXME: Would be nice to autogen this. 4696// FIXME: This is a bit of a maze of special cases. 4697StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, 4698 unsigned &PredicationCode, 4699 bool &CarrySetting, 4700 unsigned &ProcessorIMod, 4701 StringRef &ITMask) { 4702 PredicationCode = ARMCC::AL; 4703 CarrySetting = false; 4704 ProcessorIMod = 0; 4705 4706 // Ignore some mnemonics we know aren't predicated forms. 4707 // 4708 // FIXME: Would be nice to autogen this. 4709 if ((Mnemonic == "movs" && isThumb()) || 4710 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" || 4711 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || 4712 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" || 4713 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" || 4714 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" || 4715 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || 4716 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" || 4717 Mnemonic == "fmuls") 4718 return Mnemonic; 4719 4720 // First, split out any predication code. Ignore mnemonics we know aren't 4721 // predicated but do have a carry-set and so weren't caught above. 4722 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" && 4723 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" && 4724 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" && 4725 Mnemonic != "sbcs" && Mnemonic != "rscs") { 4726 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2)) 4727 .Case("eq", ARMCC::EQ) 4728 .Case("ne", ARMCC::NE) 4729 .Case("hs", ARMCC::HS) 4730 .Case("cs", ARMCC::HS) 4731 .Case("lo", ARMCC::LO) 4732 .Case("cc", ARMCC::LO) 4733 .Case("mi", ARMCC::MI) 4734 .Case("pl", ARMCC::PL) 4735 .Case("vs", ARMCC::VS) 4736 .Case("vc", ARMCC::VC) 4737 .Case("hi", ARMCC::HI) 4738 .Case("ls", ARMCC::LS) 4739 .Case("ge", ARMCC::GE) 4740 .Case("lt", ARMCC::LT) 4741 .Case("gt", ARMCC::GT) 4742 .Case("le", ARMCC::LE) 4743 .Case("al", ARMCC::AL) 4744 .Default(~0U); 4745 if (CC != ~0U) { 4746 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); 4747 PredicationCode = CC; 4748 } 4749 } 4750 4751 // Next, determine if we have a carry setting bit. We explicitly ignore all 4752 // the instructions we know end in 's'. 4753 if (Mnemonic.endswith("s") && 4754 !(Mnemonic == "cps" || Mnemonic == "mls" || 4755 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" || 4756 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" || 4757 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" || 4758 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" || 4759 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" || 4760 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" || 4761 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" || 4762 Mnemonic == "vfms" || Mnemonic == "vfnms" || 4763 (Mnemonic == "movs" && isThumb()))) { 4764 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); 4765 CarrySetting = true; 4766 } 4767 4768 // The "cps" instruction can have a interrupt mode operand which is glued into 4769 // the mnemonic. Check if this is the case, split it and parse the imod op 4770 if (Mnemonic.startswith("cps")) { 4771 // Split out any imod code. 4772 unsigned IMod = 4773 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2)) 4774 .Case("ie", ARM_PROC::IE) 4775 .Case("id", ARM_PROC::ID) 4776 .Default(~0U); 4777 if (IMod != ~0U) { 4778 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2); 4779 ProcessorIMod = IMod; 4780 } 4781 } 4782 4783 // The "it" instruction has the condition mask on the end of the mnemonic. 4784 if (Mnemonic.startswith("it")) { 4785 ITMask = Mnemonic.slice(2, Mnemonic.size()); 4786 Mnemonic = Mnemonic.slice(0, 2); 4787 } 4788 4789 return Mnemonic; 4790} 4791 4792/// \brief Given a canonical mnemonic, determine if the instruction ever allows 4793/// inclusion of carry set or predication code operands. 4794// 4795// FIXME: It would be nice to autogen this. 4796void ARMAsmParser:: 4797getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, 4798 bool &CanAcceptPredicationCode) { 4799 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || 4800 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || 4801 Mnemonic == "add" || Mnemonic == "adc" || 4802 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" || 4803 Mnemonic == "orr" || Mnemonic == "mvn" || 4804 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || 4805 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" || 4806 Mnemonic == "vfm" || Mnemonic == "vfnm" || 4807 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" || 4808 Mnemonic == "mla" || Mnemonic == "smlal" || 4809 Mnemonic == "umlal" || Mnemonic == "umull"))) { 4810 CanAcceptCarrySet = true; 4811 } else 4812 CanAcceptCarrySet = false; 4813 4814 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" || 4815 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" || 4816 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" || 4817 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" || 4818 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" || 4819 (Mnemonic == "clrex" && !isThumb()) || 4820 (Mnemonic == "nop" && isThumbOne()) || 4821 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" || 4822 Mnemonic == "ldc2" || Mnemonic == "ldc2l" || 4823 Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) || 4824 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) && 4825 !isThumb()) || 4826 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) { 4827 CanAcceptPredicationCode = false; 4828 } else 4829 CanAcceptPredicationCode = true; 4830 4831 if (isThumb()) { 4832 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" || 4833 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp") 4834 CanAcceptPredicationCode = false; 4835 } 4836} 4837 4838bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic, 4839 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4840 // FIXME: This is all horribly hacky. We really need a better way to deal 4841 // with optional operands like this in the matcher table. 4842 4843 // The 'mov' mnemonic is special. One variant has a cc_out operand, while 4844 // another does not. Specifically, the MOVW instruction does not. So we 4845 // special case it here and remove the defaulted (non-setting) cc_out 4846 // operand if that's the instruction we're trying to match. 4847 // 4848 // We do this as post-processing of the explicit operands rather than just 4849 // conditionally adding the cc_out in the first place because we need 4850 // to check the type of the parsed immediate operand. 4851 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() && 4852 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() && 4853 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() && 4854 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 4855 return true; 4856 4857 // Register-register 'add' for thumb does not have a cc_out operand 4858 // when there are only two register operands. 4859 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 && 4860 static_cast<ARMOperand*>(Operands[3])->isReg() && 4861 static_cast<ARMOperand*>(Operands[4])->isReg() && 4862 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) 4863 return true; 4864 // Register-register 'add' for thumb does not have a cc_out operand 4865 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do 4866 // have to check the immediate range here since Thumb2 has a variant 4867 // that can handle a different range and has a cc_out operand. 4868 if (((isThumb() && Mnemonic == "add") || 4869 (isThumbTwo() && Mnemonic == "sub")) && 4870 Operands.size() == 6 && 4871 static_cast<ARMOperand*>(Operands[3])->isReg() && 4872 static_cast<ARMOperand*>(Operands[4])->isReg() && 4873 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP && 4874 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4875 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) || 4876 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4())) 4877 return true; 4878 // For Thumb2, add/sub immediate does not have a cc_out operand for the 4879 // imm0_4095 variant. That's the least-preferred variant when 4880 // selecting via the generic "add" mnemonic, so to know that we 4881 // should remove the cc_out operand, we have to explicitly check that 4882 // it's not one of the other variants. Ugh. 4883 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") && 4884 Operands.size() == 6 && 4885 static_cast<ARMOperand*>(Operands[3])->isReg() && 4886 static_cast<ARMOperand*>(Operands[4])->isReg() && 4887 static_cast<ARMOperand*>(Operands[5])->isImm()) { 4888 // Nest conditions rather than one big 'if' statement for readability. 4889 // 4890 // If either register is a high reg, it's either one of the SP 4891 // variants (handled above) or a 32-bit encoding, so we just 4892 // check against T3. If the second register is the PC, this is an 4893 // alternate form of ADR, which uses encoding T4, so check for that too. 4894 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 4895 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) && 4896 static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC && 4897 static_cast<ARMOperand*>(Operands[5])->isT2SOImm()) 4898 return false; 4899 // If both registers are low, we're in an IT block, and the immediate is 4900 // in range, we should use encoding T1 instead, which has a cc_out. 4901 if (inITBlock() && 4902 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) && 4903 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) && 4904 static_cast<ARMOperand*>(Operands[5])->isImm0_7()) 4905 return false; 4906 4907 // Otherwise, we use encoding T4, which does not have a cc_out 4908 // operand. 4909 return true; 4910 } 4911 4912 // The thumb2 multiply instruction doesn't have a CCOut register, so 4913 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to 4914 // use the 16-bit encoding or not. 4915 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 && 4916 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4917 static_cast<ARMOperand*>(Operands[3])->isReg() && 4918 static_cast<ARMOperand*>(Operands[4])->isReg() && 4919 static_cast<ARMOperand*>(Operands[5])->isReg() && 4920 // If the registers aren't low regs, the destination reg isn't the 4921 // same as one of the source regs, or the cc_out operand is zero 4922 // outside of an IT block, we have to use the 32-bit encoding, so 4923 // remove the cc_out operand. 4924 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 4925 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 4926 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) || 4927 !inITBlock() || 4928 (static_cast<ARMOperand*>(Operands[3])->getReg() != 4929 static_cast<ARMOperand*>(Operands[5])->getReg() && 4930 static_cast<ARMOperand*>(Operands[3])->getReg() != 4931 static_cast<ARMOperand*>(Operands[4])->getReg()))) 4932 return true; 4933 4934 // Also check the 'mul' syntax variant that doesn't specify an explicit 4935 // destination register. 4936 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 && 4937 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4938 static_cast<ARMOperand*>(Operands[3])->isReg() && 4939 static_cast<ARMOperand*>(Operands[4])->isReg() && 4940 // If the registers aren't low regs or the cc_out operand is zero 4941 // outside of an IT block, we have to use the 32-bit encoding, so 4942 // remove the cc_out operand. 4943 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) || 4944 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) || 4945 !inITBlock())) 4946 return true; 4947 4948 4949 4950 // Register-register 'add/sub' for thumb does not have a cc_out operand 4951 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also 4952 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't 4953 // right, this will result in better diagnostics (which operand is off) 4954 // anyway. 4955 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") && 4956 (Operands.size() == 5 || Operands.size() == 6) && 4957 static_cast<ARMOperand*>(Operands[3])->isReg() && 4958 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP && 4959 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 && 4960 (static_cast<ARMOperand*>(Operands[4])->isImm() || 4961 (Operands.size() == 6 && 4962 static_cast<ARMOperand*>(Operands[5])->isImm()))) 4963 return true; 4964 4965 return false; 4966} 4967 4968static bool isDataTypeToken(StringRef Tok) { 4969 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" || 4970 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" || 4971 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" || 4972 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" || 4973 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" || 4974 Tok == ".f" || Tok == ".d"; 4975} 4976 4977// FIXME: This bit should probably be handled via an explicit match class 4978// in the .td files that matches the suffix instead of having it be 4979// a literal string token the way it is now. 4980static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) { 4981 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm"); 4982} 4983 4984static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features); 4985/// Parse an arm instruction mnemonic followed by its operands. 4986bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc, 4987 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 4988 // Apply mnemonic aliases before doing anything else, as the destination 4989 // mnemnonic may include suffices and we want to handle them normally. 4990 // The generic tblgen'erated code does this later, at the start of 4991 // MatchInstructionImpl(), but that's too late for aliases that include 4992 // any sort of suffix. 4993 unsigned AvailableFeatures = getAvailableFeatures(); 4994 applyMnemonicAliases(Name, AvailableFeatures); 4995 4996 // First check for the ARM-specific .req directive. 4997 if (Parser.getTok().is(AsmToken::Identifier) && 4998 Parser.getTok().getIdentifier() == ".req") { 4999 parseDirectiveReq(Name, NameLoc); 5000 // We always return 'error' for this, as we're done with this 5001 // statement and don't need to match the 'instruction." 5002 return true; 5003 } 5004 5005 // Create the leading tokens for the mnemonic, split by '.' characters. 5006 size_t Start = 0, Next = Name.find('.'); 5007 StringRef Mnemonic = Name.slice(Start, Next); 5008 5009 // Split out the predication code and carry setting flag from the mnemonic. 5010 unsigned PredicationCode; 5011 unsigned ProcessorIMod; 5012 bool CarrySetting; 5013 StringRef ITMask; 5014 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting, 5015 ProcessorIMod, ITMask); 5016 5017 // In Thumb1, only the branch (B) instruction can be predicated. 5018 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") { 5019 Parser.EatToEndOfStatement(); 5020 return Error(NameLoc, "conditional execution not supported in Thumb1"); 5021 } 5022 5023 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc)); 5024 5025 // Handle the IT instruction ITMask. Convert it to a bitmask. This 5026 // is the mask as it will be for the IT encoding if the conditional 5027 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case 5028 // where the conditional bit0 is zero, the instruction post-processing 5029 // will adjust the mask accordingly. 5030 if (Mnemonic == "it") { 5031 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2); 5032 if (ITMask.size() > 3) { 5033 Parser.EatToEndOfStatement(); 5034 return Error(Loc, "too many conditions on IT instruction"); 5035 } 5036 unsigned Mask = 8; 5037 for (unsigned i = ITMask.size(); i != 0; --i) { 5038 char pos = ITMask[i - 1]; 5039 if (pos != 't' && pos != 'e') { 5040 Parser.EatToEndOfStatement(); 5041 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'"); 5042 } 5043 Mask >>= 1; 5044 if (ITMask[i - 1] == 't') 5045 Mask |= 8; 5046 } 5047 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc)); 5048 } 5049 5050 // FIXME: This is all a pretty gross hack. We should automatically handle 5051 // optional operands like this via tblgen. 5052 5053 // Next, add the CCOut and ConditionCode operands, if needed. 5054 // 5055 // For mnemonics which can ever incorporate a carry setting bit or predication 5056 // code, our matching model involves us always generating CCOut and 5057 // ConditionCode operands to match the mnemonic "as written" and then we let 5058 // the matcher deal with finding the right instruction or generating an 5059 // appropriate error. 5060 bool CanAcceptCarrySet, CanAcceptPredicationCode; 5061 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode); 5062 5063 // If we had a carry-set on an instruction that can't do that, issue an 5064 // error. 5065 if (!CanAcceptCarrySet && CarrySetting) { 5066 Parser.EatToEndOfStatement(); 5067 return Error(NameLoc, "instruction '" + Mnemonic + 5068 "' can not set flags, but 's' suffix specified"); 5069 } 5070 // If we had a predication code on an instruction that can't do that, issue an 5071 // error. 5072 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) { 5073 Parser.EatToEndOfStatement(); 5074 return Error(NameLoc, "instruction '" + Mnemonic + 5075 "' is not predicable, but condition code specified"); 5076 } 5077 5078 // Add the carry setting operand, if necessary. 5079 if (CanAcceptCarrySet) { 5080 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size()); 5081 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, 5082 Loc)); 5083 } 5084 5085 // Add the predication code operand, if necessary. 5086 if (CanAcceptPredicationCode) { 5087 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() + 5088 CarrySetting); 5089 Operands.push_back(ARMOperand::CreateCondCode( 5090 ARMCC::CondCodes(PredicationCode), Loc)); 5091 } 5092 5093 // Add the processor imod operand, if necessary. 5094 if (ProcessorIMod) { 5095 Operands.push_back(ARMOperand::CreateImm( 5096 MCConstantExpr::Create(ProcessorIMod, getContext()), 5097 NameLoc, NameLoc)); 5098 } 5099 5100 // Add the remaining tokens in the mnemonic. 5101 while (Next != StringRef::npos) { 5102 Start = Next; 5103 Next = Name.find('.', Start + 1); 5104 StringRef ExtraToken = Name.slice(Start, Next); 5105 5106 // Some NEON instructions have an optional datatype suffix that is 5107 // completely ignored. Check for that. 5108 if (isDataTypeToken(ExtraToken) && 5109 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken)) 5110 continue; 5111 5112 if (ExtraToken != ".n") { 5113 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start); 5114 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc)); 5115 } 5116 } 5117 5118 // Read the remaining operands. 5119 if (getLexer().isNot(AsmToken::EndOfStatement)) { 5120 // Read the first operand. 5121 if (parseOperand(Operands, Mnemonic)) { 5122 Parser.EatToEndOfStatement(); 5123 return true; 5124 } 5125 5126 while (getLexer().is(AsmToken::Comma)) { 5127 Parser.Lex(); // Eat the comma. 5128 5129 // Parse and remember the operand. 5130 if (parseOperand(Operands, Mnemonic)) { 5131 Parser.EatToEndOfStatement(); 5132 return true; 5133 } 5134 } 5135 } 5136 5137 if (getLexer().isNot(AsmToken::EndOfStatement)) { 5138 SMLoc Loc = getLexer().getLoc(); 5139 Parser.EatToEndOfStatement(); 5140 return Error(Loc, "unexpected token in argument list"); 5141 } 5142 5143 Parser.Lex(); // Consume the EndOfStatement 5144 5145 // Some instructions, mostly Thumb, have forms for the same mnemonic that 5146 // do and don't have a cc_out optional-def operand. With some spot-checks 5147 // of the operand list, we can figure out which variant we're trying to 5148 // parse and adjust accordingly before actually matching. We shouldn't ever 5149 // try to remove a cc_out operand that was explicitly set on the the 5150 // mnemonic, of course (CarrySetting == true). Reason number #317 the 5151 // table driven matcher doesn't fit well with the ARM instruction set. 5152 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) { 5153 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 5154 Operands.erase(Operands.begin() + 1); 5155 delete Op; 5156 } 5157 5158 // ARM mode 'blx' need special handling, as the register operand version 5159 // is predicable, but the label operand version is not. So, we can't rely 5160 // on the Mnemonic based checking to correctly figure out when to put 5161 // a k_CondCode operand in the list. If we're trying to match the label 5162 // version, remove the k_CondCode operand here. 5163 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 && 5164 static_cast<ARMOperand*>(Operands[2])->isImm()) { 5165 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]); 5166 Operands.erase(Operands.begin() + 1); 5167 delete Op; 5168 } 5169 5170 // The vector-compare-to-zero instructions have a literal token "#0" at 5171 // the end that comes to here as an immediate operand. Convert it to a 5172 // token to play nicely with the matcher. 5173 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" || 5174 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 && 5175 static_cast<ARMOperand*>(Operands[5])->isImm()) { 5176 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]); 5177 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 5178 if (CE && CE->getValue() == 0) { 5179 Operands.erase(Operands.begin() + 5); 5180 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 5181 delete Op; 5182 } 5183 } 5184 // VCMP{E} does the same thing, but with a different operand count. 5185 if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 && 5186 static_cast<ARMOperand*>(Operands[4])->isImm()) { 5187 ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]); 5188 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 5189 if (CE && CE->getValue() == 0) { 5190 Operands.erase(Operands.begin() + 4); 5191 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 5192 delete Op; 5193 } 5194 } 5195 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the 5196 // end. Convert it to a token here. Take care not to convert those 5197 // that should hit the Thumb2 encoding. 5198 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 && 5199 static_cast<ARMOperand*>(Operands[3])->isReg() && 5200 static_cast<ARMOperand*>(Operands[4])->isReg() && 5201 static_cast<ARMOperand*>(Operands[5])->isImm()) { 5202 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]); 5203 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()); 5204 if (CE && CE->getValue() == 0 && 5205 (isThumbOne() || 5206 // The cc_out operand matches the IT block. 5207 ((inITBlock() != CarrySetting) && 5208 // Neither register operand is a high register. 5209 (isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) && 5210 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()))))){ 5211 Operands.erase(Operands.begin() + 5); 5212 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc())); 5213 delete Op; 5214 } 5215 } 5216 5217 return false; 5218} 5219 5220// Validate context-sensitive operand constraints. 5221 5222// return 'true' if register list contains non-low GPR registers, 5223// 'false' otherwise. If Reg is in the register list or is HiReg, set 5224// 'containsReg' to true. 5225static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg, 5226 unsigned HiReg, bool &containsReg) { 5227 containsReg = false; 5228 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 5229 unsigned OpReg = Inst.getOperand(i).getReg(); 5230 if (OpReg == Reg) 5231 containsReg = true; 5232 // Anything other than a low register isn't legal here. 5233 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) 5234 return true; 5235 } 5236 return false; 5237} 5238 5239// Check if the specified regisgter is in the register list of the inst, 5240// starting at the indicated operand number. 5241static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) { 5242 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) { 5243 unsigned OpReg = Inst.getOperand(i).getReg(); 5244 if (OpReg == Reg) 5245 return true; 5246 } 5247 return false; 5248} 5249 5250// FIXME: We would really prefer to have MCInstrInfo (the wrapper around 5251// the ARMInsts array) instead. Getting that here requires awkward 5252// API changes, though. Better way? 5253namespace llvm { 5254extern const MCInstrDesc ARMInsts[]; 5255} 5256static const MCInstrDesc &getInstDesc(unsigned Opcode) { 5257 return ARMInsts[Opcode]; 5258} 5259 5260// FIXME: We would really like to be able to tablegen'erate this. 5261bool ARMAsmParser:: 5262validateInstruction(MCInst &Inst, 5263 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 5264 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode()); 5265 SMLoc Loc = Operands[0]->getStartLoc(); 5266 // Check the IT block state first. 5267 // NOTE: BKPT instruction has the interesting property of being 5268 // allowed in IT blocks, but not being predicable. It just always 5269 // executes. 5270 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT && 5271 Inst.getOpcode() != ARM::BKPT) { 5272 unsigned bit = 1; 5273 if (ITState.FirstCond) 5274 ITState.FirstCond = false; 5275 else 5276 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1; 5277 // The instruction must be predicable. 5278 if (!MCID.isPredicable()) 5279 return Error(Loc, "instructions in IT block must be predicable"); 5280 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm(); 5281 unsigned ITCond = bit ? ITState.Cond : 5282 ARMCC::getOppositeCondition(ITState.Cond); 5283 if (Cond != ITCond) { 5284 // Find the condition code Operand to get its SMLoc information. 5285 SMLoc CondLoc; 5286 for (unsigned i = 1; i < Operands.size(); ++i) 5287 if (static_cast<ARMOperand*>(Operands[i])->isCondCode()) 5288 CondLoc = Operands[i]->getStartLoc(); 5289 return Error(CondLoc, "incorrect condition in IT block; got '" + 5290 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) + 5291 "', but expected '" + 5292 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'"); 5293 } 5294 // Check for non-'al' condition codes outside of the IT block. 5295 } else if (isThumbTwo() && MCID.isPredicable() && 5296 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != 5297 ARMCC::AL && Inst.getOpcode() != ARM::tB && 5298 Inst.getOpcode() != ARM::t2B) 5299 return Error(Loc, "predicated instructions must be in IT block"); 5300 5301 switch (Inst.getOpcode()) { 5302 case ARM::LDRD: 5303 case ARM::LDRD_PRE: 5304 case ARM::LDRD_POST: 5305 case ARM::LDREXD: { 5306 // Rt2 must be Rt + 1. 5307 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg()); 5308 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 5309 if (Rt2 != Rt + 1) 5310 return Error(Operands[3]->getStartLoc(), 5311 "destination operands must be sequential"); 5312 return false; 5313 } 5314 case ARM::STRD: { 5315 // Rt2 must be Rt + 1. 5316 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg()); 5317 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 5318 if (Rt2 != Rt + 1) 5319 return Error(Operands[3]->getStartLoc(), 5320 "source operands must be sequential"); 5321 return false; 5322 } 5323 case ARM::STRD_PRE: 5324 case ARM::STRD_POST: 5325 case ARM::STREXD: { 5326 // Rt2 must be Rt + 1. 5327 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg()); 5328 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg()); 5329 if (Rt2 != Rt + 1) 5330 return Error(Operands[3]->getStartLoc(), 5331 "source operands must be sequential"); 5332 return false; 5333 } 5334 case ARM::SBFX: 5335 case ARM::UBFX: { 5336 // width must be in range [1, 32-lsb] 5337 unsigned lsb = Inst.getOperand(2).getImm(); 5338 unsigned widthm1 = Inst.getOperand(3).getImm(); 5339 if (widthm1 >= 32 - lsb) 5340 return Error(Operands[5]->getStartLoc(), 5341 "bitfield width must be in range [1,32-lsb]"); 5342 return false; 5343 } 5344 case ARM::tLDMIA: { 5345 // If we're parsing Thumb2, the .w variant is available and handles 5346 // most cases that are normally illegal for a Thumb1 LDM 5347 // instruction. We'll make the transformation in processInstruction() 5348 // if necessary. 5349 // 5350 // Thumb LDM instructions are writeback iff the base register is not 5351 // in the register list. 5352 unsigned Rn = Inst.getOperand(0).getReg(); 5353 bool hasWritebackToken = 5354 (static_cast<ARMOperand*>(Operands[3])->isToken() && 5355 static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 5356 bool listContainsBase; 5357 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo()) 5358 return Error(Operands[3 + hasWritebackToken]->getStartLoc(), 5359 "registers must be in range r0-r7"); 5360 // If we should have writeback, then there should be a '!' token. 5361 if (!listContainsBase && !hasWritebackToken && !isThumbTwo()) 5362 return Error(Operands[2]->getStartLoc(), 5363 "writeback operator '!' expected"); 5364 // If we should not have writeback, there must not be a '!'. This is 5365 // true even for the 32-bit wide encodings. 5366 if (listContainsBase && hasWritebackToken) 5367 return Error(Operands[3]->getStartLoc(), 5368 "writeback operator '!' not allowed when base register " 5369 "in register list"); 5370 5371 break; 5372 } 5373 case ARM::t2LDMIA_UPD: { 5374 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg())) 5375 return Error(Operands[4]->getStartLoc(), 5376 "writeback operator '!' not allowed when base register " 5377 "in register list"); 5378 break; 5379 } 5380 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2, 5381 // so only issue a diagnostic for thumb1. The instructions will be 5382 // switched to the t2 encodings in processInstruction() if necessary. 5383 case ARM::tPOP: { 5384 bool listContainsBase; 5385 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) && 5386 !isThumbTwo()) 5387 return Error(Operands[2]->getStartLoc(), 5388 "registers must be in range r0-r7 or pc"); 5389 break; 5390 } 5391 case ARM::tPUSH: { 5392 bool listContainsBase; 5393 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) && 5394 !isThumbTwo()) 5395 return Error(Operands[2]->getStartLoc(), 5396 "registers must be in range r0-r7 or lr"); 5397 break; 5398 } 5399 case ARM::tSTMIA_UPD: { 5400 bool listContainsBase; 5401 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo()) 5402 return Error(Operands[4]->getStartLoc(), 5403 "registers must be in range r0-r7"); 5404 break; 5405 } 5406 case ARM::tADDrSP: { 5407 // If the non-SP source operand and the destination operand are not the 5408 // same, we need thumb2 (for the wide encoding), or we have an error. 5409 if (!isThumbTwo() && 5410 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 5411 return Error(Operands[4]->getStartLoc(), 5412 "source register must be the same as destination"); 5413 } 5414 break; 5415 } 5416 } 5417 5418 return false; 5419} 5420 5421static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) { 5422 switch(Opc) { 5423 default: llvm_unreachable("unexpected opcode!"); 5424 // VST1LN 5425 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 5426 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 5427 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 5428 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD; 5429 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD; 5430 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD; 5431 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8; 5432 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16; 5433 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32; 5434 5435 // VST2LN 5436 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 5437 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 5438 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 5439 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 5440 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 5441 5442 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD; 5443 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD; 5444 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD; 5445 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD; 5446 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD; 5447 5448 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8; 5449 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16; 5450 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32; 5451 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16; 5452 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32; 5453 5454 // VST3LN 5455 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 5456 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 5457 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 5458 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD; 5459 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 5460 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD; 5461 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD; 5462 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD; 5463 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD; 5464 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD; 5465 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8; 5466 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16; 5467 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32; 5468 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16; 5469 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32; 5470 5471 // VST3 5472 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 5473 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 5474 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 5475 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 5476 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 5477 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 5478 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD; 5479 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD; 5480 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD; 5481 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD; 5482 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD; 5483 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD; 5484 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8; 5485 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16; 5486 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32; 5487 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8; 5488 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16; 5489 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32; 5490 5491 // VST4LN 5492 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 5493 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 5494 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 5495 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD; 5496 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 5497 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD; 5498 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD; 5499 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD; 5500 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD; 5501 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD; 5502 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8; 5503 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16; 5504 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32; 5505 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16; 5506 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32; 5507 5508 // VST4 5509 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 5510 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 5511 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 5512 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 5513 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 5514 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 5515 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD; 5516 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD; 5517 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD; 5518 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD; 5519 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD; 5520 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD; 5521 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8; 5522 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16; 5523 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32; 5524 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8; 5525 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16; 5526 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32; 5527 } 5528} 5529 5530static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) { 5531 switch(Opc) { 5532 default: llvm_unreachable("unexpected opcode!"); 5533 // VLD1LN 5534 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 5535 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 5536 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 5537 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD; 5538 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD; 5539 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD; 5540 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8; 5541 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16; 5542 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32; 5543 5544 // VLD2LN 5545 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 5546 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 5547 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 5548 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD; 5549 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 5550 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD; 5551 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD; 5552 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD; 5553 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD; 5554 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD; 5555 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8; 5556 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16; 5557 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32; 5558 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16; 5559 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32; 5560 5561 // VLD3DUP 5562 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 5563 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 5564 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 5565 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD; 5566 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD; 5567 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 5568 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD; 5569 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD; 5570 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD; 5571 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD; 5572 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD; 5573 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD; 5574 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8; 5575 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16; 5576 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32; 5577 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8; 5578 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16; 5579 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32; 5580 5581 // VLD3LN 5582 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 5583 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 5584 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 5585 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD; 5586 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 5587 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD; 5588 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD; 5589 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD; 5590 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD; 5591 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD; 5592 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8; 5593 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16; 5594 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32; 5595 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16; 5596 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32; 5597 5598 // VLD3 5599 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 5600 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 5601 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 5602 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 5603 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 5604 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 5605 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD; 5606 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD; 5607 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD; 5608 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD; 5609 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD; 5610 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD; 5611 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8; 5612 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16; 5613 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32; 5614 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8; 5615 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16; 5616 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32; 5617 5618 // VLD4LN 5619 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 5620 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 5621 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 5622 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD; 5623 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 5624 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD; 5625 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD; 5626 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD; 5627 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD; 5628 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD; 5629 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8; 5630 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16; 5631 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32; 5632 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16; 5633 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32; 5634 5635 // VLD4DUP 5636 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 5637 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 5638 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 5639 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD; 5640 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD; 5641 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 5642 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD; 5643 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD; 5644 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD; 5645 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD; 5646 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD; 5647 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD; 5648 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8; 5649 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16; 5650 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32; 5651 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8; 5652 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16; 5653 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32; 5654 5655 // VLD4 5656 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 5657 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 5658 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 5659 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 5660 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 5661 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 5662 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD; 5663 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD; 5664 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD; 5665 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD; 5666 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD; 5667 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD; 5668 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8; 5669 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16; 5670 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32; 5671 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8; 5672 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16; 5673 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32; 5674 } 5675} 5676 5677bool ARMAsmParser:: 5678processInstruction(MCInst &Inst, 5679 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 5680 switch (Inst.getOpcode()) { 5681 // Aliases for alternate PC+imm syntax of LDR instructions. 5682 case ARM::t2LDRpcrel: 5683 Inst.setOpcode(ARM::t2LDRpci); 5684 return true; 5685 case ARM::t2LDRBpcrel: 5686 Inst.setOpcode(ARM::t2LDRBpci); 5687 return true; 5688 case ARM::t2LDRHpcrel: 5689 Inst.setOpcode(ARM::t2LDRHpci); 5690 return true; 5691 case ARM::t2LDRSBpcrel: 5692 Inst.setOpcode(ARM::t2LDRSBpci); 5693 return true; 5694 case ARM::t2LDRSHpcrel: 5695 Inst.setOpcode(ARM::t2LDRSHpci); 5696 return true; 5697 // Handle NEON VST complex aliases. 5698 case ARM::VST1LNdWB_register_Asm_8: 5699 case ARM::VST1LNdWB_register_Asm_16: 5700 case ARM::VST1LNdWB_register_Asm_32: { 5701 MCInst TmpInst; 5702 // Shuffle the operands around so the lane index operand is in the 5703 // right place. 5704 unsigned Spacing; 5705 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5706 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5707 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5708 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5709 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5710 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5711 TmpInst.addOperand(Inst.getOperand(1)); // lane 5712 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5713 TmpInst.addOperand(Inst.getOperand(6)); 5714 Inst = TmpInst; 5715 return true; 5716 } 5717 5718 case ARM::VST2LNdWB_register_Asm_8: 5719 case ARM::VST2LNdWB_register_Asm_16: 5720 case ARM::VST2LNdWB_register_Asm_32: 5721 case ARM::VST2LNqWB_register_Asm_16: 5722 case ARM::VST2LNqWB_register_Asm_32: { 5723 MCInst TmpInst; 5724 // Shuffle the operands around so the lane index operand is in the 5725 // right place. 5726 unsigned Spacing; 5727 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5728 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5729 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5730 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5731 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5732 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5733 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5734 Spacing)); 5735 TmpInst.addOperand(Inst.getOperand(1)); // lane 5736 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5737 TmpInst.addOperand(Inst.getOperand(6)); 5738 Inst = TmpInst; 5739 return true; 5740 } 5741 5742 case ARM::VST3LNdWB_register_Asm_8: 5743 case ARM::VST3LNdWB_register_Asm_16: 5744 case ARM::VST3LNdWB_register_Asm_32: 5745 case ARM::VST3LNqWB_register_Asm_16: 5746 case ARM::VST3LNqWB_register_Asm_32: { 5747 MCInst TmpInst; 5748 // Shuffle the operands around so the lane index operand is in the 5749 // right place. 5750 unsigned Spacing; 5751 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5752 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5753 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5754 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5755 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5756 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5757 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5758 Spacing)); 5759 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5760 Spacing * 2)); 5761 TmpInst.addOperand(Inst.getOperand(1)); // lane 5762 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5763 TmpInst.addOperand(Inst.getOperand(6)); 5764 Inst = TmpInst; 5765 return true; 5766 } 5767 5768 case ARM::VST4LNdWB_register_Asm_8: 5769 case ARM::VST4LNdWB_register_Asm_16: 5770 case ARM::VST4LNdWB_register_Asm_32: 5771 case ARM::VST4LNqWB_register_Asm_16: 5772 case ARM::VST4LNqWB_register_Asm_32: { 5773 MCInst TmpInst; 5774 // Shuffle the operands around so the lane index operand is in the 5775 // right place. 5776 unsigned Spacing; 5777 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5778 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5779 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5780 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5781 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5782 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5783 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5784 Spacing)); 5785 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5786 Spacing * 2)); 5787 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5788 Spacing * 3)); 5789 TmpInst.addOperand(Inst.getOperand(1)); // lane 5790 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 5791 TmpInst.addOperand(Inst.getOperand(6)); 5792 Inst = TmpInst; 5793 return true; 5794 } 5795 5796 case ARM::VST1LNdWB_fixed_Asm_8: 5797 case ARM::VST1LNdWB_fixed_Asm_16: 5798 case ARM::VST1LNdWB_fixed_Asm_32: { 5799 MCInst TmpInst; 5800 // Shuffle the operands around so the lane index operand is in the 5801 // right place. 5802 unsigned Spacing; 5803 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5804 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5805 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5806 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5807 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 5808 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5809 TmpInst.addOperand(Inst.getOperand(1)); // lane 5810 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5811 TmpInst.addOperand(Inst.getOperand(5)); 5812 Inst = TmpInst; 5813 return true; 5814 } 5815 5816 case ARM::VST2LNdWB_fixed_Asm_8: 5817 case ARM::VST2LNdWB_fixed_Asm_16: 5818 case ARM::VST2LNdWB_fixed_Asm_32: 5819 case ARM::VST2LNqWB_fixed_Asm_16: 5820 case ARM::VST2LNqWB_fixed_Asm_32: { 5821 MCInst TmpInst; 5822 // Shuffle the operands around so the lane index operand is in the 5823 // right place. 5824 unsigned Spacing; 5825 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5826 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5827 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5828 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5829 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 5830 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5831 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5832 Spacing)); 5833 TmpInst.addOperand(Inst.getOperand(1)); // lane 5834 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5835 TmpInst.addOperand(Inst.getOperand(5)); 5836 Inst = TmpInst; 5837 return true; 5838 } 5839 5840 case ARM::VST3LNdWB_fixed_Asm_8: 5841 case ARM::VST3LNdWB_fixed_Asm_16: 5842 case ARM::VST3LNdWB_fixed_Asm_32: 5843 case ARM::VST3LNqWB_fixed_Asm_16: 5844 case ARM::VST3LNqWB_fixed_Asm_32: { 5845 MCInst TmpInst; 5846 // Shuffle the operands around so the lane index operand is in the 5847 // right place. 5848 unsigned Spacing; 5849 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5850 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5851 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5852 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5853 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 5854 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5855 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5856 Spacing)); 5857 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5858 Spacing * 2)); 5859 TmpInst.addOperand(Inst.getOperand(1)); // lane 5860 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5861 TmpInst.addOperand(Inst.getOperand(5)); 5862 Inst = TmpInst; 5863 return true; 5864 } 5865 5866 case ARM::VST4LNdWB_fixed_Asm_8: 5867 case ARM::VST4LNdWB_fixed_Asm_16: 5868 case ARM::VST4LNdWB_fixed_Asm_32: 5869 case ARM::VST4LNqWB_fixed_Asm_16: 5870 case ARM::VST4LNqWB_fixed_Asm_32: { 5871 MCInst TmpInst; 5872 // Shuffle the operands around so the lane index operand is in the 5873 // right place. 5874 unsigned Spacing; 5875 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5876 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5877 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5878 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5879 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 5880 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5881 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5882 Spacing)); 5883 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5884 Spacing * 2)); 5885 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5886 Spacing * 3)); 5887 TmpInst.addOperand(Inst.getOperand(1)); // lane 5888 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5889 TmpInst.addOperand(Inst.getOperand(5)); 5890 Inst = TmpInst; 5891 return true; 5892 } 5893 5894 case ARM::VST1LNdAsm_8: 5895 case ARM::VST1LNdAsm_16: 5896 case ARM::VST1LNdAsm_32: { 5897 MCInst TmpInst; 5898 // Shuffle the operands around so the lane index operand is in the 5899 // right place. 5900 unsigned Spacing; 5901 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5902 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5903 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5904 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5905 TmpInst.addOperand(Inst.getOperand(1)); // lane 5906 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5907 TmpInst.addOperand(Inst.getOperand(5)); 5908 Inst = TmpInst; 5909 return true; 5910 } 5911 5912 case ARM::VST2LNdAsm_8: 5913 case ARM::VST2LNdAsm_16: 5914 case ARM::VST2LNdAsm_32: 5915 case ARM::VST2LNqAsm_16: 5916 case ARM::VST2LNqAsm_32: { 5917 MCInst TmpInst; 5918 // Shuffle the operands around so the lane index operand is in the 5919 // right place. 5920 unsigned Spacing; 5921 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5922 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5923 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5924 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5925 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5926 Spacing)); 5927 TmpInst.addOperand(Inst.getOperand(1)); // lane 5928 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5929 TmpInst.addOperand(Inst.getOperand(5)); 5930 Inst = TmpInst; 5931 return true; 5932 } 5933 5934 case ARM::VST3LNdAsm_8: 5935 case ARM::VST3LNdAsm_16: 5936 case ARM::VST3LNdAsm_32: 5937 case ARM::VST3LNqAsm_16: 5938 case ARM::VST3LNqAsm_32: { 5939 MCInst TmpInst; 5940 // Shuffle the operands around so the lane index operand is in the 5941 // right place. 5942 unsigned Spacing; 5943 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5944 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5945 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5946 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5947 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5948 Spacing)); 5949 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5950 Spacing * 2)); 5951 TmpInst.addOperand(Inst.getOperand(1)); // lane 5952 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5953 TmpInst.addOperand(Inst.getOperand(5)); 5954 Inst = TmpInst; 5955 return true; 5956 } 5957 5958 case ARM::VST4LNdAsm_8: 5959 case ARM::VST4LNdAsm_16: 5960 case ARM::VST4LNdAsm_32: 5961 case ARM::VST4LNqAsm_16: 5962 case ARM::VST4LNqAsm_32: { 5963 MCInst TmpInst; 5964 // Shuffle the operands around so the lane index operand is in the 5965 // right place. 5966 unsigned Spacing; 5967 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 5968 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5969 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5970 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5971 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5972 Spacing)); 5973 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5974 Spacing * 2)); 5975 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 5976 Spacing * 3)); 5977 TmpInst.addOperand(Inst.getOperand(1)); // lane 5978 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 5979 TmpInst.addOperand(Inst.getOperand(5)); 5980 Inst = TmpInst; 5981 return true; 5982 } 5983 5984 // Handle NEON VLD complex aliases. 5985 case ARM::VLD1LNdWB_register_Asm_8: 5986 case ARM::VLD1LNdWB_register_Asm_16: 5987 case ARM::VLD1LNdWB_register_Asm_32: { 5988 MCInst TmpInst; 5989 // Shuffle the operands around so the lane index operand is in the 5990 // right place. 5991 unsigned Spacing; 5992 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 5993 TmpInst.addOperand(Inst.getOperand(0)); // Vd 5994 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 5995 TmpInst.addOperand(Inst.getOperand(2)); // Rn 5996 TmpInst.addOperand(Inst.getOperand(3)); // alignment 5997 TmpInst.addOperand(Inst.getOperand(4)); // Rm 5998 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 5999 TmpInst.addOperand(Inst.getOperand(1)); // lane 6000 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6001 TmpInst.addOperand(Inst.getOperand(6)); 6002 Inst = TmpInst; 6003 return true; 6004 } 6005 6006 case ARM::VLD2LNdWB_register_Asm_8: 6007 case ARM::VLD2LNdWB_register_Asm_16: 6008 case ARM::VLD2LNdWB_register_Asm_32: 6009 case ARM::VLD2LNqWB_register_Asm_16: 6010 case ARM::VLD2LNqWB_register_Asm_32: { 6011 MCInst TmpInst; 6012 // Shuffle the operands around so the lane index operand is in the 6013 // right place. 6014 unsigned Spacing; 6015 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6016 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6017 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6018 Spacing)); 6019 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6020 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6021 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6022 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6023 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6024 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6025 Spacing)); 6026 TmpInst.addOperand(Inst.getOperand(1)); // lane 6027 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6028 TmpInst.addOperand(Inst.getOperand(6)); 6029 Inst = TmpInst; 6030 return true; 6031 } 6032 6033 case ARM::VLD3LNdWB_register_Asm_8: 6034 case ARM::VLD3LNdWB_register_Asm_16: 6035 case ARM::VLD3LNdWB_register_Asm_32: 6036 case ARM::VLD3LNqWB_register_Asm_16: 6037 case ARM::VLD3LNqWB_register_Asm_32: { 6038 MCInst TmpInst; 6039 // Shuffle the operands around so the lane index operand is in the 6040 // right place. 6041 unsigned Spacing; 6042 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6043 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6044 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6045 Spacing)); 6046 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6047 Spacing * 2)); 6048 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6049 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6050 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6051 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6052 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6053 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6054 Spacing)); 6055 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6056 Spacing * 2)); 6057 TmpInst.addOperand(Inst.getOperand(1)); // lane 6058 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6059 TmpInst.addOperand(Inst.getOperand(6)); 6060 Inst = TmpInst; 6061 return true; 6062 } 6063 6064 case ARM::VLD4LNdWB_register_Asm_8: 6065 case ARM::VLD4LNdWB_register_Asm_16: 6066 case ARM::VLD4LNdWB_register_Asm_32: 6067 case ARM::VLD4LNqWB_register_Asm_16: 6068 case ARM::VLD4LNqWB_register_Asm_32: { 6069 MCInst TmpInst; 6070 // Shuffle the operands around so the lane index operand is in the 6071 // right place. 6072 unsigned Spacing; 6073 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6074 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6075 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6076 Spacing)); 6077 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6078 Spacing * 2)); 6079 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6080 Spacing * 3)); 6081 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6082 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6083 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6084 TmpInst.addOperand(Inst.getOperand(4)); // Rm 6085 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6086 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6087 Spacing)); 6088 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6089 Spacing * 2)); 6090 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6091 Spacing * 3)); 6092 TmpInst.addOperand(Inst.getOperand(1)); // lane 6093 TmpInst.addOperand(Inst.getOperand(5)); // CondCode 6094 TmpInst.addOperand(Inst.getOperand(6)); 6095 Inst = TmpInst; 6096 return true; 6097 } 6098 6099 case ARM::VLD1LNdWB_fixed_Asm_8: 6100 case ARM::VLD1LNdWB_fixed_Asm_16: 6101 case ARM::VLD1LNdWB_fixed_Asm_32: { 6102 MCInst TmpInst; 6103 // Shuffle the operands around so the lane index operand is in the 6104 // right place. 6105 unsigned Spacing; 6106 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6107 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6108 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6109 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6110 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6111 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6112 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6113 TmpInst.addOperand(Inst.getOperand(1)); // lane 6114 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6115 TmpInst.addOperand(Inst.getOperand(5)); 6116 Inst = TmpInst; 6117 return true; 6118 } 6119 6120 case ARM::VLD2LNdWB_fixed_Asm_8: 6121 case ARM::VLD2LNdWB_fixed_Asm_16: 6122 case ARM::VLD2LNdWB_fixed_Asm_32: 6123 case ARM::VLD2LNqWB_fixed_Asm_16: 6124 case ARM::VLD2LNqWB_fixed_Asm_32: { 6125 MCInst TmpInst; 6126 // Shuffle the operands around so the lane index operand is in the 6127 // right place. 6128 unsigned Spacing; 6129 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6130 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6131 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6132 Spacing)); 6133 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6134 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6135 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6136 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6137 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6138 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6139 Spacing)); 6140 TmpInst.addOperand(Inst.getOperand(1)); // lane 6141 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6142 TmpInst.addOperand(Inst.getOperand(5)); 6143 Inst = TmpInst; 6144 return true; 6145 } 6146 6147 case ARM::VLD3LNdWB_fixed_Asm_8: 6148 case ARM::VLD3LNdWB_fixed_Asm_16: 6149 case ARM::VLD3LNdWB_fixed_Asm_32: 6150 case ARM::VLD3LNqWB_fixed_Asm_16: 6151 case ARM::VLD3LNqWB_fixed_Asm_32: { 6152 MCInst TmpInst; 6153 // Shuffle the operands around so the lane index operand is in the 6154 // right place. 6155 unsigned Spacing; 6156 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6157 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6158 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6159 Spacing)); 6160 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6161 Spacing * 2)); 6162 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6163 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6164 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6165 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6166 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6167 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6168 Spacing)); 6169 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6170 Spacing * 2)); 6171 TmpInst.addOperand(Inst.getOperand(1)); // lane 6172 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6173 TmpInst.addOperand(Inst.getOperand(5)); 6174 Inst = TmpInst; 6175 return true; 6176 } 6177 6178 case ARM::VLD4LNdWB_fixed_Asm_8: 6179 case ARM::VLD4LNdWB_fixed_Asm_16: 6180 case ARM::VLD4LNdWB_fixed_Asm_32: 6181 case ARM::VLD4LNqWB_fixed_Asm_16: 6182 case ARM::VLD4LNqWB_fixed_Asm_32: { 6183 MCInst TmpInst; 6184 // Shuffle the operands around so the lane index operand is in the 6185 // right place. 6186 unsigned Spacing; 6187 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6188 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6189 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6190 Spacing)); 6191 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6192 Spacing * 2)); 6193 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6194 Spacing * 3)); 6195 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb 6196 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6197 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6198 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6199 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6200 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6201 Spacing)); 6202 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6203 Spacing * 2)); 6204 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6205 Spacing * 3)); 6206 TmpInst.addOperand(Inst.getOperand(1)); // lane 6207 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6208 TmpInst.addOperand(Inst.getOperand(5)); 6209 Inst = TmpInst; 6210 return true; 6211 } 6212 6213 case ARM::VLD1LNdAsm_8: 6214 case ARM::VLD1LNdAsm_16: 6215 case ARM::VLD1LNdAsm_32: { 6216 MCInst TmpInst; 6217 // Shuffle the operands around so the lane index operand is in the 6218 // right place. 6219 unsigned Spacing; 6220 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6221 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6222 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6223 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6224 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6225 TmpInst.addOperand(Inst.getOperand(1)); // lane 6226 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6227 TmpInst.addOperand(Inst.getOperand(5)); 6228 Inst = TmpInst; 6229 return true; 6230 } 6231 6232 case ARM::VLD2LNdAsm_8: 6233 case ARM::VLD2LNdAsm_16: 6234 case ARM::VLD2LNdAsm_32: 6235 case ARM::VLD2LNqAsm_16: 6236 case ARM::VLD2LNqAsm_32: { 6237 MCInst TmpInst; 6238 // Shuffle the operands around so the lane index operand is in the 6239 // right place. 6240 unsigned Spacing; 6241 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6242 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6243 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6244 Spacing)); 6245 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6246 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6247 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6248 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6249 Spacing)); 6250 TmpInst.addOperand(Inst.getOperand(1)); // lane 6251 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6252 TmpInst.addOperand(Inst.getOperand(5)); 6253 Inst = TmpInst; 6254 return true; 6255 } 6256 6257 case ARM::VLD3LNdAsm_8: 6258 case ARM::VLD3LNdAsm_16: 6259 case ARM::VLD3LNdAsm_32: 6260 case ARM::VLD3LNqAsm_16: 6261 case ARM::VLD3LNqAsm_32: { 6262 MCInst TmpInst; 6263 // Shuffle the operands around so the lane index operand is in the 6264 // right place. 6265 unsigned Spacing; 6266 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6267 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6268 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6269 Spacing)); 6270 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6271 Spacing * 2)); 6272 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6273 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6274 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6275 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6276 Spacing)); 6277 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6278 Spacing * 2)); 6279 TmpInst.addOperand(Inst.getOperand(1)); // lane 6280 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6281 TmpInst.addOperand(Inst.getOperand(5)); 6282 Inst = TmpInst; 6283 return true; 6284 } 6285 6286 case ARM::VLD4LNdAsm_8: 6287 case ARM::VLD4LNdAsm_16: 6288 case ARM::VLD4LNdAsm_32: 6289 case ARM::VLD4LNqAsm_16: 6290 case ARM::VLD4LNqAsm_32: { 6291 MCInst TmpInst; 6292 // Shuffle the operands around so the lane index operand is in the 6293 // right place. 6294 unsigned Spacing; 6295 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6296 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6297 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6298 Spacing)); 6299 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6300 Spacing * 2)); 6301 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6302 Spacing * 3)); 6303 TmpInst.addOperand(Inst.getOperand(2)); // Rn 6304 TmpInst.addOperand(Inst.getOperand(3)); // alignment 6305 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd) 6306 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6307 Spacing)); 6308 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6309 Spacing * 2)); 6310 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6311 Spacing * 3)); 6312 TmpInst.addOperand(Inst.getOperand(1)); // lane 6313 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6314 TmpInst.addOperand(Inst.getOperand(5)); 6315 Inst = TmpInst; 6316 return true; 6317 } 6318 6319 // VLD3DUP single 3-element structure to all lanes instructions. 6320 case ARM::VLD3DUPdAsm_8: 6321 case ARM::VLD3DUPdAsm_16: 6322 case ARM::VLD3DUPdAsm_32: 6323 case ARM::VLD3DUPqAsm_8: 6324 case ARM::VLD3DUPqAsm_16: 6325 case ARM::VLD3DUPqAsm_32: { 6326 MCInst TmpInst; 6327 unsigned Spacing; 6328 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6329 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6330 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6331 Spacing)); 6332 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6333 Spacing * 2)); 6334 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6335 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6336 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6337 TmpInst.addOperand(Inst.getOperand(4)); 6338 Inst = TmpInst; 6339 return true; 6340 } 6341 6342 case ARM::VLD3DUPdWB_fixed_Asm_8: 6343 case ARM::VLD3DUPdWB_fixed_Asm_16: 6344 case ARM::VLD3DUPdWB_fixed_Asm_32: 6345 case ARM::VLD3DUPqWB_fixed_Asm_8: 6346 case ARM::VLD3DUPqWB_fixed_Asm_16: 6347 case ARM::VLD3DUPqWB_fixed_Asm_32: { 6348 MCInst TmpInst; 6349 unsigned Spacing; 6350 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6351 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6352 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6353 Spacing)); 6354 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6355 Spacing * 2)); 6356 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6357 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6358 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6359 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6360 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6361 TmpInst.addOperand(Inst.getOperand(4)); 6362 Inst = TmpInst; 6363 return true; 6364 } 6365 6366 case ARM::VLD3DUPdWB_register_Asm_8: 6367 case ARM::VLD3DUPdWB_register_Asm_16: 6368 case ARM::VLD3DUPdWB_register_Asm_32: 6369 case ARM::VLD3DUPqWB_register_Asm_8: 6370 case ARM::VLD3DUPqWB_register_Asm_16: 6371 case ARM::VLD3DUPqWB_register_Asm_32: { 6372 MCInst TmpInst; 6373 unsigned Spacing; 6374 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6375 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6376 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6377 Spacing)); 6378 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6379 Spacing * 2)); 6380 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6381 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6382 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6383 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6384 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6385 TmpInst.addOperand(Inst.getOperand(5)); 6386 Inst = TmpInst; 6387 return true; 6388 } 6389 6390 // VLD3 multiple 3-element structure instructions. 6391 case ARM::VLD3dAsm_8: 6392 case ARM::VLD3dAsm_16: 6393 case ARM::VLD3dAsm_32: 6394 case ARM::VLD3qAsm_8: 6395 case ARM::VLD3qAsm_16: 6396 case ARM::VLD3qAsm_32: { 6397 MCInst TmpInst; 6398 unsigned Spacing; 6399 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6400 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6401 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6402 Spacing)); 6403 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6404 Spacing * 2)); 6405 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6406 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6407 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6408 TmpInst.addOperand(Inst.getOperand(4)); 6409 Inst = TmpInst; 6410 return true; 6411 } 6412 6413 case ARM::VLD3dWB_fixed_Asm_8: 6414 case ARM::VLD3dWB_fixed_Asm_16: 6415 case ARM::VLD3dWB_fixed_Asm_32: 6416 case ARM::VLD3qWB_fixed_Asm_8: 6417 case ARM::VLD3qWB_fixed_Asm_16: 6418 case ARM::VLD3qWB_fixed_Asm_32: { 6419 MCInst TmpInst; 6420 unsigned Spacing; 6421 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6422 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6423 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6424 Spacing)); 6425 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6426 Spacing * 2)); 6427 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6428 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6429 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6430 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6431 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6432 TmpInst.addOperand(Inst.getOperand(4)); 6433 Inst = TmpInst; 6434 return true; 6435 } 6436 6437 case ARM::VLD3dWB_register_Asm_8: 6438 case ARM::VLD3dWB_register_Asm_16: 6439 case ARM::VLD3dWB_register_Asm_32: 6440 case ARM::VLD3qWB_register_Asm_8: 6441 case ARM::VLD3qWB_register_Asm_16: 6442 case ARM::VLD3qWB_register_Asm_32: { 6443 MCInst TmpInst; 6444 unsigned Spacing; 6445 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6446 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6447 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6448 Spacing)); 6449 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6450 Spacing * 2)); 6451 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6452 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6453 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6454 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6455 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6456 TmpInst.addOperand(Inst.getOperand(5)); 6457 Inst = TmpInst; 6458 return true; 6459 } 6460 6461 // VLD4DUP single 3-element structure to all lanes instructions. 6462 case ARM::VLD4DUPdAsm_8: 6463 case ARM::VLD4DUPdAsm_16: 6464 case ARM::VLD4DUPdAsm_32: 6465 case ARM::VLD4DUPqAsm_8: 6466 case ARM::VLD4DUPqAsm_16: 6467 case ARM::VLD4DUPqAsm_32: { 6468 MCInst TmpInst; 6469 unsigned Spacing; 6470 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6471 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6472 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6473 Spacing)); 6474 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6475 Spacing * 2)); 6476 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6477 Spacing * 3)); 6478 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6479 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6480 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6481 TmpInst.addOperand(Inst.getOperand(4)); 6482 Inst = TmpInst; 6483 return true; 6484 } 6485 6486 case ARM::VLD4DUPdWB_fixed_Asm_8: 6487 case ARM::VLD4DUPdWB_fixed_Asm_16: 6488 case ARM::VLD4DUPdWB_fixed_Asm_32: 6489 case ARM::VLD4DUPqWB_fixed_Asm_8: 6490 case ARM::VLD4DUPqWB_fixed_Asm_16: 6491 case ARM::VLD4DUPqWB_fixed_Asm_32: { 6492 MCInst TmpInst; 6493 unsigned Spacing; 6494 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6495 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6496 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6497 Spacing)); 6498 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6499 Spacing * 2)); 6500 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6501 Spacing * 3)); 6502 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6503 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6504 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6505 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6506 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6507 TmpInst.addOperand(Inst.getOperand(4)); 6508 Inst = TmpInst; 6509 return true; 6510 } 6511 6512 case ARM::VLD4DUPdWB_register_Asm_8: 6513 case ARM::VLD4DUPdWB_register_Asm_16: 6514 case ARM::VLD4DUPdWB_register_Asm_32: 6515 case ARM::VLD4DUPqWB_register_Asm_8: 6516 case ARM::VLD4DUPqWB_register_Asm_16: 6517 case ARM::VLD4DUPqWB_register_Asm_32: { 6518 MCInst TmpInst; 6519 unsigned Spacing; 6520 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6521 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6522 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6523 Spacing)); 6524 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6525 Spacing * 2)); 6526 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6527 Spacing * 3)); 6528 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6529 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6530 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6531 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6532 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6533 TmpInst.addOperand(Inst.getOperand(5)); 6534 Inst = TmpInst; 6535 return true; 6536 } 6537 6538 // VLD4 multiple 4-element structure instructions. 6539 case ARM::VLD4dAsm_8: 6540 case ARM::VLD4dAsm_16: 6541 case ARM::VLD4dAsm_32: 6542 case ARM::VLD4qAsm_8: 6543 case ARM::VLD4qAsm_16: 6544 case ARM::VLD4qAsm_32: { 6545 MCInst TmpInst; 6546 unsigned Spacing; 6547 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6548 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6549 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6550 Spacing)); 6551 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6552 Spacing * 2)); 6553 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6554 Spacing * 3)); 6555 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6556 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6557 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6558 TmpInst.addOperand(Inst.getOperand(4)); 6559 Inst = TmpInst; 6560 return true; 6561 } 6562 6563 case ARM::VLD4dWB_fixed_Asm_8: 6564 case ARM::VLD4dWB_fixed_Asm_16: 6565 case ARM::VLD4dWB_fixed_Asm_32: 6566 case ARM::VLD4qWB_fixed_Asm_8: 6567 case ARM::VLD4qWB_fixed_Asm_16: 6568 case ARM::VLD4qWB_fixed_Asm_32: { 6569 MCInst TmpInst; 6570 unsigned Spacing; 6571 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6572 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6573 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6574 Spacing)); 6575 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6576 Spacing * 2)); 6577 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6578 Spacing * 3)); 6579 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6580 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6581 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6582 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6583 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6584 TmpInst.addOperand(Inst.getOperand(4)); 6585 Inst = TmpInst; 6586 return true; 6587 } 6588 6589 case ARM::VLD4dWB_register_Asm_8: 6590 case ARM::VLD4dWB_register_Asm_16: 6591 case ARM::VLD4dWB_register_Asm_32: 6592 case ARM::VLD4qWB_register_Asm_8: 6593 case ARM::VLD4qWB_register_Asm_16: 6594 case ARM::VLD4qWB_register_Asm_32: { 6595 MCInst TmpInst; 6596 unsigned Spacing; 6597 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing)); 6598 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6599 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6600 Spacing)); 6601 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6602 Spacing * 2)); 6603 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6604 Spacing * 3)); 6605 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6606 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6607 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6608 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6609 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6610 TmpInst.addOperand(Inst.getOperand(5)); 6611 Inst = TmpInst; 6612 return true; 6613 } 6614 6615 // VST3 multiple 3-element structure instructions. 6616 case ARM::VST3dAsm_8: 6617 case ARM::VST3dAsm_16: 6618 case ARM::VST3dAsm_32: 6619 case ARM::VST3qAsm_8: 6620 case ARM::VST3qAsm_16: 6621 case ARM::VST3qAsm_32: { 6622 MCInst TmpInst; 6623 unsigned Spacing; 6624 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6625 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6626 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6627 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6628 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6629 Spacing)); 6630 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6631 Spacing * 2)); 6632 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6633 TmpInst.addOperand(Inst.getOperand(4)); 6634 Inst = TmpInst; 6635 return true; 6636 } 6637 6638 case ARM::VST3dWB_fixed_Asm_8: 6639 case ARM::VST3dWB_fixed_Asm_16: 6640 case ARM::VST3dWB_fixed_Asm_32: 6641 case ARM::VST3qWB_fixed_Asm_8: 6642 case ARM::VST3qWB_fixed_Asm_16: 6643 case ARM::VST3qWB_fixed_Asm_32: { 6644 MCInst TmpInst; 6645 unsigned Spacing; 6646 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6647 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6648 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6649 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6650 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6651 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6652 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6653 Spacing)); 6654 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6655 Spacing * 2)); 6656 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6657 TmpInst.addOperand(Inst.getOperand(4)); 6658 Inst = TmpInst; 6659 return true; 6660 } 6661 6662 case ARM::VST3dWB_register_Asm_8: 6663 case ARM::VST3dWB_register_Asm_16: 6664 case ARM::VST3dWB_register_Asm_32: 6665 case ARM::VST3qWB_register_Asm_8: 6666 case ARM::VST3qWB_register_Asm_16: 6667 case ARM::VST3qWB_register_Asm_32: { 6668 MCInst TmpInst; 6669 unsigned Spacing; 6670 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6671 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6672 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6673 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6674 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6675 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6676 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6677 Spacing)); 6678 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6679 Spacing * 2)); 6680 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6681 TmpInst.addOperand(Inst.getOperand(5)); 6682 Inst = TmpInst; 6683 return true; 6684 } 6685 6686 // VST4 multiple 3-element structure instructions. 6687 case ARM::VST4dAsm_8: 6688 case ARM::VST4dAsm_16: 6689 case ARM::VST4dAsm_32: 6690 case ARM::VST4qAsm_8: 6691 case ARM::VST4qAsm_16: 6692 case ARM::VST4qAsm_32: { 6693 MCInst TmpInst; 6694 unsigned Spacing; 6695 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6696 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6697 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6698 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6699 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6700 Spacing)); 6701 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6702 Spacing * 2)); 6703 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6704 Spacing * 3)); 6705 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6706 TmpInst.addOperand(Inst.getOperand(4)); 6707 Inst = TmpInst; 6708 return true; 6709 } 6710 6711 case ARM::VST4dWB_fixed_Asm_8: 6712 case ARM::VST4dWB_fixed_Asm_16: 6713 case ARM::VST4dWB_fixed_Asm_32: 6714 case ARM::VST4qWB_fixed_Asm_8: 6715 case ARM::VST4qWB_fixed_Asm_16: 6716 case ARM::VST4qWB_fixed_Asm_32: { 6717 MCInst TmpInst; 6718 unsigned Spacing; 6719 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6720 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6721 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6722 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6723 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm 6724 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6725 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6726 Spacing)); 6727 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6728 Spacing * 2)); 6729 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6730 Spacing * 3)); 6731 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6732 TmpInst.addOperand(Inst.getOperand(4)); 6733 Inst = TmpInst; 6734 return true; 6735 } 6736 6737 case ARM::VST4dWB_register_Asm_8: 6738 case ARM::VST4dWB_register_Asm_16: 6739 case ARM::VST4dWB_register_Asm_32: 6740 case ARM::VST4qWB_register_Asm_8: 6741 case ARM::VST4qWB_register_Asm_16: 6742 case ARM::VST4qWB_register_Asm_32: { 6743 MCInst TmpInst; 6744 unsigned Spacing; 6745 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing)); 6746 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6747 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn 6748 TmpInst.addOperand(Inst.getOperand(2)); // alignment 6749 TmpInst.addOperand(Inst.getOperand(3)); // Rm 6750 TmpInst.addOperand(Inst.getOperand(0)); // Vd 6751 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6752 Spacing)); 6753 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6754 Spacing * 2)); 6755 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() + 6756 Spacing * 3)); 6757 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6758 TmpInst.addOperand(Inst.getOperand(5)); 6759 Inst = TmpInst; 6760 return true; 6761 } 6762 6763 // Handle encoding choice for the shift-immediate instructions. 6764 case ARM::t2LSLri: 6765 case ARM::t2LSRri: 6766 case ARM::t2ASRri: { 6767 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 6768 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 6769 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && 6770 !(static_cast<ARMOperand*>(Operands[3])->isToken() && 6771 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) { 6772 unsigned NewOpc; 6773 switch (Inst.getOpcode()) { 6774 default: llvm_unreachable("unexpected opcode"); 6775 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break; 6776 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break; 6777 case ARM::t2ASRri: NewOpc = ARM::tASRri; break; 6778 } 6779 // The Thumb1 operands aren't in the same order. Awesome, eh? 6780 MCInst TmpInst; 6781 TmpInst.setOpcode(NewOpc); 6782 TmpInst.addOperand(Inst.getOperand(0)); 6783 TmpInst.addOperand(Inst.getOperand(5)); 6784 TmpInst.addOperand(Inst.getOperand(1)); 6785 TmpInst.addOperand(Inst.getOperand(2)); 6786 TmpInst.addOperand(Inst.getOperand(3)); 6787 TmpInst.addOperand(Inst.getOperand(4)); 6788 Inst = TmpInst; 6789 return true; 6790 } 6791 return false; 6792 } 6793 6794 // Handle the Thumb2 mode MOV complex aliases. 6795 case ARM::t2MOVsr: 6796 case ARM::t2MOVSsr: { 6797 // Which instruction to expand to depends on the CCOut operand and 6798 // whether we're in an IT block if the register operands are low 6799 // registers. 6800 bool isNarrow = false; 6801 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 6802 isARMLowRegister(Inst.getOperand(1).getReg()) && 6803 isARMLowRegister(Inst.getOperand(2).getReg()) && 6804 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 6805 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr)) 6806 isNarrow = true; 6807 MCInst TmpInst; 6808 unsigned newOpc; 6809 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) { 6810 default: llvm_unreachable("unexpected opcode!"); 6811 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break; 6812 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break; 6813 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break; 6814 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break; 6815 } 6816 TmpInst.setOpcode(newOpc); 6817 TmpInst.addOperand(Inst.getOperand(0)); // Rd 6818 if (isNarrow) 6819 TmpInst.addOperand(MCOperand::CreateReg( 6820 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 6821 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6822 TmpInst.addOperand(Inst.getOperand(2)); // Rm 6823 TmpInst.addOperand(Inst.getOperand(4)); // CondCode 6824 TmpInst.addOperand(Inst.getOperand(5)); 6825 if (!isNarrow) 6826 TmpInst.addOperand(MCOperand::CreateReg( 6827 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); 6828 Inst = TmpInst; 6829 return true; 6830 } 6831 case ARM::t2MOVsi: 6832 case ARM::t2MOVSsi: { 6833 // Which instruction to expand to depends on the CCOut operand and 6834 // whether we're in an IT block if the register operands are low 6835 // registers. 6836 bool isNarrow = false; 6837 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 6838 isARMLowRegister(Inst.getOperand(1).getReg()) && 6839 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi)) 6840 isNarrow = true; 6841 MCInst TmpInst; 6842 unsigned newOpc; 6843 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) { 6844 default: llvm_unreachable("unexpected opcode!"); 6845 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break; 6846 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break; 6847 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break; 6848 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break; 6849 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break; 6850 } 6851 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()); 6852 if (Amount == 32) Amount = 0; 6853 TmpInst.setOpcode(newOpc); 6854 TmpInst.addOperand(Inst.getOperand(0)); // Rd 6855 if (isNarrow) 6856 TmpInst.addOperand(MCOperand::CreateReg( 6857 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 6858 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6859 if (newOpc != ARM::t2RRX) 6860 TmpInst.addOperand(MCOperand::CreateImm(Amount)); 6861 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6862 TmpInst.addOperand(Inst.getOperand(4)); 6863 if (!isNarrow) 6864 TmpInst.addOperand(MCOperand::CreateReg( 6865 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); 6866 Inst = TmpInst; 6867 return true; 6868 } 6869 // Handle the ARM mode MOV complex aliases. 6870 case ARM::ASRr: 6871 case ARM::LSRr: 6872 case ARM::LSLr: 6873 case ARM::RORr: { 6874 ARM_AM::ShiftOpc ShiftTy; 6875 switch(Inst.getOpcode()) { 6876 default: llvm_unreachable("unexpected opcode!"); 6877 case ARM::ASRr: ShiftTy = ARM_AM::asr; break; 6878 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break; 6879 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break; 6880 case ARM::RORr: ShiftTy = ARM_AM::ror; break; 6881 } 6882 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0); 6883 MCInst TmpInst; 6884 TmpInst.setOpcode(ARM::MOVsr); 6885 TmpInst.addOperand(Inst.getOperand(0)); // Rd 6886 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6887 TmpInst.addOperand(Inst.getOperand(2)); // Rm 6888 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 6889 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6890 TmpInst.addOperand(Inst.getOperand(4)); 6891 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 6892 Inst = TmpInst; 6893 return true; 6894 } 6895 case ARM::ASRi: 6896 case ARM::LSRi: 6897 case ARM::LSLi: 6898 case ARM::RORi: { 6899 ARM_AM::ShiftOpc ShiftTy; 6900 switch(Inst.getOpcode()) { 6901 default: llvm_unreachable("unexpected opcode!"); 6902 case ARM::ASRi: ShiftTy = ARM_AM::asr; break; 6903 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break; 6904 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break; 6905 case ARM::RORi: ShiftTy = ARM_AM::ror; break; 6906 } 6907 // A shift by zero is a plain MOVr, not a MOVsi. 6908 unsigned Amt = Inst.getOperand(2).getImm(); 6909 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi; 6910 // A shift by 32 should be encoded as 0 when permitted 6911 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr)) 6912 Amt = 0; 6913 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt); 6914 MCInst TmpInst; 6915 TmpInst.setOpcode(Opc); 6916 TmpInst.addOperand(Inst.getOperand(0)); // Rd 6917 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6918 if (Opc == ARM::MOVsi) 6919 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 6920 TmpInst.addOperand(Inst.getOperand(3)); // CondCode 6921 TmpInst.addOperand(Inst.getOperand(4)); 6922 TmpInst.addOperand(Inst.getOperand(5)); // cc_out 6923 Inst = TmpInst; 6924 return true; 6925 } 6926 case ARM::RRXi: { 6927 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0); 6928 MCInst TmpInst; 6929 TmpInst.setOpcode(ARM::MOVsi); 6930 TmpInst.addOperand(Inst.getOperand(0)); // Rd 6931 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6932 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty 6933 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 6934 TmpInst.addOperand(Inst.getOperand(3)); 6935 TmpInst.addOperand(Inst.getOperand(4)); // cc_out 6936 Inst = TmpInst; 6937 return true; 6938 } 6939 case ARM::t2LDMIA_UPD: { 6940 // If this is a load of a single register, then we should use 6941 // a post-indexed LDR instruction instead, per the ARM ARM. 6942 if (Inst.getNumOperands() != 5) 6943 return false; 6944 MCInst TmpInst; 6945 TmpInst.setOpcode(ARM::t2LDR_POST); 6946 TmpInst.addOperand(Inst.getOperand(4)); // Rt 6947 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 6948 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6949 TmpInst.addOperand(MCOperand::CreateImm(4)); 6950 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 6951 TmpInst.addOperand(Inst.getOperand(3)); 6952 Inst = TmpInst; 6953 return true; 6954 } 6955 case ARM::t2STMDB_UPD: { 6956 // If this is a store of a single register, then we should use 6957 // a pre-indexed STR instruction instead, per the ARM ARM. 6958 if (Inst.getNumOperands() != 5) 6959 return false; 6960 MCInst TmpInst; 6961 TmpInst.setOpcode(ARM::t2STR_PRE); 6962 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 6963 TmpInst.addOperand(Inst.getOperand(4)); // Rt 6964 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6965 TmpInst.addOperand(MCOperand::CreateImm(-4)); 6966 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 6967 TmpInst.addOperand(Inst.getOperand(3)); 6968 Inst = TmpInst; 6969 return true; 6970 } 6971 case ARM::LDMIA_UPD: 6972 // If this is a load of a single register via a 'pop', then we should use 6973 // a post-indexed LDR instruction instead, per the ARM ARM. 6974 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" && 6975 Inst.getNumOperands() == 5) { 6976 MCInst TmpInst; 6977 TmpInst.setOpcode(ARM::LDR_POST_IMM); 6978 TmpInst.addOperand(Inst.getOperand(4)); // Rt 6979 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 6980 TmpInst.addOperand(Inst.getOperand(1)); // Rn 6981 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset 6982 TmpInst.addOperand(MCOperand::CreateImm(4)); 6983 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 6984 TmpInst.addOperand(Inst.getOperand(3)); 6985 Inst = TmpInst; 6986 return true; 6987 } 6988 break; 6989 case ARM::STMDB_UPD: 6990 // If this is a store of a single register via a 'push', then we should use 6991 // a pre-indexed STR instruction instead, per the ARM ARM. 6992 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" && 6993 Inst.getNumOperands() == 5) { 6994 MCInst TmpInst; 6995 TmpInst.setOpcode(ARM::STR_PRE_IMM); 6996 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb 6997 TmpInst.addOperand(Inst.getOperand(4)); // Rt 6998 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12 6999 TmpInst.addOperand(MCOperand::CreateImm(-4)); 7000 TmpInst.addOperand(Inst.getOperand(2)); // CondCode 7001 TmpInst.addOperand(Inst.getOperand(3)); 7002 Inst = TmpInst; 7003 } 7004 break; 7005 case ARM::t2ADDri12: 7006 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add" 7007 // mnemonic was used (not "addw"), encoding T3 is preferred. 7008 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" || 7009 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 7010 break; 7011 Inst.setOpcode(ARM::t2ADDri); 7012 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 7013 break; 7014 case ARM::t2SUBri12: 7015 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub" 7016 // mnemonic was used (not "subw"), encoding T3 is preferred. 7017 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" || 7018 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1) 7019 break; 7020 Inst.setOpcode(ARM::t2SUBri); 7021 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 7022 break; 7023 case ARM::tADDi8: 7024 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 7025 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 7026 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 7027 // to encoding T1 if <Rd> is omitted." 7028 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 7029 Inst.setOpcode(ARM::tADDi3); 7030 return true; 7031 } 7032 break; 7033 case ARM::tSUBi8: 7034 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was 7035 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred 7036 // to encoding T2 if <Rd> is specified and encoding T2 is preferred 7037 // to encoding T1 if <Rd> is omitted." 7038 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) { 7039 Inst.setOpcode(ARM::tSUBi3); 7040 return true; 7041 } 7042 break; 7043 case ARM::t2ADDri: 7044 case ARM::t2SUBri: { 7045 // If the destination and first source operand are the same, and 7046 // the flags are compatible with the current IT status, use encoding T2 7047 // instead of T3. For compatibility with the system 'as'. Make sure the 7048 // wide encoding wasn't explicit. 7049 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 7050 !isARMLowRegister(Inst.getOperand(0).getReg()) || 7051 (unsigned)Inst.getOperand(2).getImm() > 255 || 7052 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) || 7053 (inITBlock() && Inst.getOperand(5).getReg() != 0)) || 7054 (static_cast<ARMOperand*>(Operands[3])->isToken() && 7055 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) 7056 break; 7057 MCInst TmpInst; 7058 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ? 7059 ARM::tADDi8 : ARM::tSUBi8); 7060 TmpInst.addOperand(Inst.getOperand(0)); 7061 TmpInst.addOperand(Inst.getOperand(5)); 7062 TmpInst.addOperand(Inst.getOperand(0)); 7063 TmpInst.addOperand(Inst.getOperand(2)); 7064 TmpInst.addOperand(Inst.getOperand(3)); 7065 TmpInst.addOperand(Inst.getOperand(4)); 7066 Inst = TmpInst; 7067 return true; 7068 } 7069 case ARM::t2ADDrr: { 7070 // If the destination and first source operand are the same, and 7071 // there's no setting of the flags, use encoding T2 instead of T3. 7072 // Note that this is only for ADD, not SUB. This mirrors the system 7073 // 'as' behaviour. Make sure the wide encoding wasn't explicit. 7074 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() || 7075 Inst.getOperand(5).getReg() != 0 || 7076 (static_cast<ARMOperand*>(Operands[3])->isToken() && 7077 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) 7078 break; 7079 MCInst TmpInst; 7080 TmpInst.setOpcode(ARM::tADDhirr); 7081 TmpInst.addOperand(Inst.getOperand(0)); 7082 TmpInst.addOperand(Inst.getOperand(0)); 7083 TmpInst.addOperand(Inst.getOperand(2)); 7084 TmpInst.addOperand(Inst.getOperand(3)); 7085 TmpInst.addOperand(Inst.getOperand(4)); 7086 Inst = TmpInst; 7087 return true; 7088 } 7089 case ARM::tADDrSP: { 7090 // If the non-SP source operand and the destination operand are not the 7091 // same, we need to use the 32-bit encoding if it's available. 7092 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) { 7093 Inst.setOpcode(ARM::t2ADDrr); 7094 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out 7095 return true; 7096 } 7097 break; 7098 } 7099 case ARM::tB: 7100 // A Thumb conditional branch outside of an IT block is a tBcc. 7101 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) { 7102 Inst.setOpcode(ARM::tBcc); 7103 return true; 7104 } 7105 break; 7106 case ARM::t2B: 7107 // A Thumb2 conditional branch outside of an IT block is a t2Bcc. 7108 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){ 7109 Inst.setOpcode(ARM::t2Bcc); 7110 return true; 7111 } 7112 break; 7113 case ARM::t2Bcc: 7114 // If the conditional is AL or we're in an IT block, we really want t2B. 7115 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) { 7116 Inst.setOpcode(ARM::t2B); 7117 return true; 7118 } 7119 break; 7120 case ARM::tBcc: 7121 // If the conditional is AL, we really want tB. 7122 if (Inst.getOperand(1).getImm() == ARMCC::AL) { 7123 Inst.setOpcode(ARM::tB); 7124 return true; 7125 } 7126 break; 7127 case ARM::tLDMIA: { 7128 // If the register list contains any high registers, or if the writeback 7129 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding 7130 // instead if we're in Thumb2. Otherwise, this should have generated 7131 // an error in validateInstruction(). 7132 unsigned Rn = Inst.getOperand(0).getReg(); 7133 bool hasWritebackToken = 7134 (static_cast<ARMOperand*>(Operands[3])->isToken() && 7135 static_cast<ARMOperand*>(Operands[3])->getToken() == "!"); 7136 bool listContainsBase; 7137 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) || 7138 (!listContainsBase && !hasWritebackToken) || 7139 (listContainsBase && hasWritebackToken)) { 7140 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 7141 assert (isThumbTwo()); 7142 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA); 7143 // If we're switching to the updating version, we need to insert 7144 // the writeback tied operand. 7145 if (hasWritebackToken) 7146 Inst.insert(Inst.begin(), 7147 MCOperand::CreateReg(Inst.getOperand(0).getReg())); 7148 return true; 7149 } 7150 break; 7151 } 7152 case ARM::tSTMIA_UPD: { 7153 // If the register list contains any high registers, we need to use 7154 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 7155 // should have generated an error in validateInstruction(). 7156 unsigned Rn = Inst.getOperand(0).getReg(); 7157 bool listContainsBase; 7158 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) { 7159 // 16-bit encoding isn't sufficient. Switch to the 32-bit version. 7160 assert (isThumbTwo()); 7161 Inst.setOpcode(ARM::t2STMIA_UPD); 7162 return true; 7163 } 7164 break; 7165 } 7166 case ARM::tPOP: { 7167 bool listContainsBase; 7168 // If the register list contains any high registers, we need to use 7169 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this 7170 // should have generated an error in validateInstruction(). 7171 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase)) 7172 return false; 7173 assert (isThumbTwo()); 7174 Inst.setOpcode(ARM::t2LDMIA_UPD); 7175 // Add the base register and writeback operands. 7176 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7177 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7178 return true; 7179 } 7180 case ARM::tPUSH: { 7181 bool listContainsBase; 7182 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase)) 7183 return false; 7184 assert (isThumbTwo()); 7185 Inst.setOpcode(ARM::t2STMDB_UPD); 7186 // Add the base register and writeback operands. 7187 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7188 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP)); 7189 return true; 7190 } 7191 case ARM::t2MOVi: { 7192 // If we can use the 16-bit encoding and the user didn't explicitly 7193 // request the 32-bit variant, transform it here. 7194 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7195 (unsigned)Inst.getOperand(1).getImm() <= 255 && 7196 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL && 7197 Inst.getOperand(4).getReg() == ARM::CPSR) || 7198 (inITBlock() && Inst.getOperand(4).getReg() == 0)) && 7199 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 7200 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 7201 // The operands aren't in the same order for tMOVi8... 7202 MCInst TmpInst; 7203 TmpInst.setOpcode(ARM::tMOVi8); 7204 TmpInst.addOperand(Inst.getOperand(0)); 7205 TmpInst.addOperand(Inst.getOperand(4)); 7206 TmpInst.addOperand(Inst.getOperand(1)); 7207 TmpInst.addOperand(Inst.getOperand(2)); 7208 TmpInst.addOperand(Inst.getOperand(3)); 7209 Inst = TmpInst; 7210 return true; 7211 } 7212 break; 7213 } 7214 case ARM::t2MOVr: { 7215 // If we can use the 16-bit encoding and the user didn't explicitly 7216 // request the 32-bit variant, transform it here. 7217 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7218 isARMLowRegister(Inst.getOperand(1).getReg()) && 7219 Inst.getOperand(2).getImm() == ARMCC::AL && 7220 Inst.getOperand(4).getReg() == ARM::CPSR && 7221 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 7222 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 7223 // The operands aren't the same for tMOV[S]r... (no cc_out) 7224 MCInst TmpInst; 7225 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr); 7226 TmpInst.addOperand(Inst.getOperand(0)); 7227 TmpInst.addOperand(Inst.getOperand(1)); 7228 TmpInst.addOperand(Inst.getOperand(2)); 7229 TmpInst.addOperand(Inst.getOperand(3)); 7230 Inst = TmpInst; 7231 return true; 7232 } 7233 break; 7234 } 7235 case ARM::t2SXTH: 7236 case ARM::t2SXTB: 7237 case ARM::t2UXTH: 7238 case ARM::t2UXTB: { 7239 // If we can use the 16-bit encoding and the user didn't explicitly 7240 // request the 32-bit variant, transform it here. 7241 if (isARMLowRegister(Inst.getOperand(0).getReg()) && 7242 isARMLowRegister(Inst.getOperand(1).getReg()) && 7243 Inst.getOperand(2).getImm() == 0 && 7244 (!static_cast<ARMOperand*>(Operands[2])->isToken() || 7245 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) { 7246 unsigned NewOpc; 7247 switch (Inst.getOpcode()) { 7248 default: llvm_unreachable("Illegal opcode!"); 7249 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; 7250 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; 7251 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; 7252 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break; 7253 } 7254 // The operands aren't the same for thumb1 (no rotate operand). 7255 MCInst TmpInst; 7256 TmpInst.setOpcode(NewOpc); 7257 TmpInst.addOperand(Inst.getOperand(0)); 7258 TmpInst.addOperand(Inst.getOperand(1)); 7259 TmpInst.addOperand(Inst.getOperand(3)); 7260 TmpInst.addOperand(Inst.getOperand(4)); 7261 Inst = TmpInst; 7262 return true; 7263 } 7264 break; 7265 } 7266 case ARM::MOVsi: { 7267 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm()); 7268 // rrx shifts and asr/lsr of #32 is encoded as 0 7269 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr) 7270 return false; 7271 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) { 7272 // Shifting by zero is accepted as a vanilla 'MOVr' 7273 MCInst TmpInst; 7274 TmpInst.setOpcode(ARM::MOVr); 7275 TmpInst.addOperand(Inst.getOperand(0)); 7276 TmpInst.addOperand(Inst.getOperand(1)); 7277 TmpInst.addOperand(Inst.getOperand(3)); 7278 TmpInst.addOperand(Inst.getOperand(4)); 7279 TmpInst.addOperand(Inst.getOperand(5)); 7280 Inst = TmpInst; 7281 return true; 7282 } 7283 return false; 7284 } 7285 case ARM::ANDrsi: 7286 case ARM::ORRrsi: 7287 case ARM::EORrsi: 7288 case ARM::BICrsi: 7289 case ARM::SUBrsi: 7290 case ARM::ADDrsi: { 7291 unsigned newOpc; 7292 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm()); 7293 if (SOpc == ARM_AM::rrx) return false; 7294 switch (Inst.getOpcode()) { 7295 default: llvm_unreachable("unexpected opcode!"); 7296 case ARM::ANDrsi: newOpc = ARM::ANDrr; break; 7297 case ARM::ORRrsi: newOpc = ARM::ORRrr; break; 7298 case ARM::EORrsi: newOpc = ARM::EORrr; break; 7299 case ARM::BICrsi: newOpc = ARM::BICrr; break; 7300 case ARM::SUBrsi: newOpc = ARM::SUBrr; break; 7301 case ARM::ADDrsi: newOpc = ARM::ADDrr; break; 7302 } 7303 // If the shift is by zero, use the non-shifted instruction definition. 7304 // The exception is for right shifts, where 0 == 32 7305 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 && 7306 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) { 7307 MCInst TmpInst; 7308 TmpInst.setOpcode(newOpc); 7309 TmpInst.addOperand(Inst.getOperand(0)); 7310 TmpInst.addOperand(Inst.getOperand(1)); 7311 TmpInst.addOperand(Inst.getOperand(2)); 7312 TmpInst.addOperand(Inst.getOperand(4)); 7313 TmpInst.addOperand(Inst.getOperand(5)); 7314 TmpInst.addOperand(Inst.getOperand(6)); 7315 Inst = TmpInst; 7316 return true; 7317 } 7318 return false; 7319 } 7320 case ARM::ITasm: 7321 case ARM::t2IT: { 7322 // The mask bits for all but the first condition are represented as 7323 // the low bit of the condition code value implies 't'. We currently 7324 // always have 1 implies 't', so XOR toggle the bits if the low bit 7325 // of the condition code is zero. 7326 MCOperand &MO = Inst.getOperand(1); 7327 unsigned Mask = MO.getImm(); 7328 unsigned OrigMask = Mask; 7329 unsigned TZ = CountTrailingZeros_32(Mask); 7330 if ((Inst.getOperand(0).getImm() & 1) == 0) { 7331 assert(Mask && TZ <= 3 && "illegal IT mask value!"); 7332 for (unsigned i = 3; i != TZ; --i) 7333 Mask ^= 1 << i; 7334 } 7335 MO.setImm(Mask); 7336 7337 // Set up the IT block state according to the IT instruction we just 7338 // matched. 7339 assert(!inITBlock() && "nested IT blocks?!"); 7340 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm()); 7341 ITState.Mask = OrigMask; // Use the original mask, not the updated one. 7342 ITState.CurPosition = 0; 7343 ITState.FirstCond = true; 7344 break; 7345 } 7346 case ARM::t2LSLrr: 7347 case ARM::t2LSRrr: 7348 case ARM::t2ASRrr: 7349 case ARM::t2SBCrr: 7350 case ARM::t2RORrr: 7351 case ARM::t2BICrr: 7352 { 7353 // Assemblers should use the narrow encodings of these instructions when permissible. 7354 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 7355 isARMLowRegister(Inst.getOperand(2).getReg())) && 7356 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() && 7357 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) || 7358 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) && 7359 (!static_cast<ARMOperand*>(Operands[3])->isToken() || 7360 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) { 7361 unsigned NewOpc; 7362 switch (Inst.getOpcode()) { 7363 default: llvm_unreachable("unexpected opcode"); 7364 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break; 7365 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break; 7366 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break; 7367 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break; 7368 case ARM::t2RORrr: NewOpc = ARM::tROR; break; 7369 case ARM::t2BICrr: NewOpc = ARM::tBIC; break; 7370 } 7371 MCInst TmpInst; 7372 TmpInst.setOpcode(NewOpc); 7373 TmpInst.addOperand(Inst.getOperand(0)); 7374 TmpInst.addOperand(Inst.getOperand(5)); 7375 TmpInst.addOperand(Inst.getOperand(1)); 7376 TmpInst.addOperand(Inst.getOperand(2)); 7377 TmpInst.addOperand(Inst.getOperand(3)); 7378 TmpInst.addOperand(Inst.getOperand(4)); 7379 Inst = TmpInst; 7380 return true; 7381 } 7382 return false; 7383 } 7384 case ARM::t2ANDrr: 7385 case ARM::t2EORrr: 7386 case ARM::t2ADCrr: 7387 case ARM::t2ORRrr: 7388 { 7389 // Assemblers should use the narrow encodings of these instructions when permissible. 7390 // These instructions are special in that they are commutable, so shorter encodings 7391 // are available more often. 7392 if ((isARMLowRegister(Inst.getOperand(1).getReg()) && 7393 isARMLowRegister(Inst.getOperand(2).getReg())) && 7394 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() || 7395 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) && 7396 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) || 7397 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) && 7398 (!static_cast<ARMOperand*>(Operands[3])->isToken() || 7399 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) { 7400 unsigned NewOpc; 7401 switch (Inst.getOpcode()) { 7402 default: llvm_unreachable("unexpected opcode"); 7403 case ARM::t2ADCrr: NewOpc = ARM::tADC; break; 7404 case ARM::t2ANDrr: NewOpc = ARM::tAND; break; 7405 case ARM::t2EORrr: NewOpc = ARM::tEOR; break; 7406 case ARM::t2ORRrr: NewOpc = ARM::tORR; break; 7407 } 7408 MCInst TmpInst; 7409 TmpInst.setOpcode(NewOpc); 7410 TmpInst.addOperand(Inst.getOperand(0)); 7411 TmpInst.addOperand(Inst.getOperand(5)); 7412 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) { 7413 TmpInst.addOperand(Inst.getOperand(1)); 7414 TmpInst.addOperand(Inst.getOperand(2)); 7415 } else { 7416 TmpInst.addOperand(Inst.getOperand(2)); 7417 TmpInst.addOperand(Inst.getOperand(1)); 7418 } 7419 TmpInst.addOperand(Inst.getOperand(3)); 7420 TmpInst.addOperand(Inst.getOperand(4)); 7421 Inst = TmpInst; 7422 return true; 7423 } 7424 return false; 7425 } 7426 } 7427 return false; 7428} 7429 7430unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) { 7431 // 16-bit thumb arithmetic instructions either require or preclude the 'S' 7432 // suffix depending on whether they're in an IT block or not. 7433 unsigned Opc = Inst.getOpcode(); 7434 const MCInstrDesc &MCID = getInstDesc(Opc); 7435 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) { 7436 assert(MCID.hasOptionalDef() && 7437 "optionally flag setting instruction missing optional def operand"); 7438 assert(MCID.NumOperands == Inst.getNumOperands() && 7439 "operand count mismatch!"); 7440 // Find the optional-def operand (cc_out). 7441 unsigned OpNo; 7442 for (OpNo = 0; 7443 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands; 7444 ++OpNo) 7445 ; 7446 // If we're parsing Thumb1, reject it completely. 7447 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) 7448 return Match_MnemonicFail; 7449 // If we're parsing Thumb2, which form is legal depends on whether we're 7450 // in an IT block. 7451 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && 7452 !inITBlock()) 7453 return Match_RequiresITBlock; 7454 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && 7455 inITBlock()) 7456 return Match_RequiresNotITBlock; 7457 } 7458 // Some high-register supporting Thumb1 encodings only allow both registers 7459 // to be from r0-r7 when in Thumb2. 7460 else if (Opc == ARM::tADDhirr && isThumbOne() && 7461 isARMLowRegister(Inst.getOperand(1).getReg()) && 7462 isARMLowRegister(Inst.getOperand(2).getReg())) 7463 return Match_RequiresThumb2; 7464 // Others only require ARMv6 or later. 7465 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() && 7466 isARMLowRegister(Inst.getOperand(0).getReg()) && 7467 isARMLowRegister(Inst.getOperand(1).getReg())) 7468 return Match_RequiresV6; 7469 return Match_Success; 7470} 7471 7472static const char *getSubtargetFeatureName(unsigned Val); 7473bool ARMAsmParser:: 7474MatchAndEmitInstruction(SMLoc IDLoc, 7475 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 7476 MCStreamer &Out) { 7477 MCInst Inst; 7478 unsigned ErrorInfo; 7479 unsigned MatchResult; 7480 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo); 7481 switch (MatchResult) { 7482 default: break; 7483 case Match_Success: 7484 // Context sensitive operand constraints aren't handled by the matcher, 7485 // so check them here. 7486 if (validateInstruction(Inst, Operands)) { 7487 // Still progress the IT block, otherwise one wrong condition causes 7488 // nasty cascading errors. 7489 forwardITPosition(); 7490 return true; 7491 } 7492 7493 // Some instructions need post-processing to, for example, tweak which 7494 // encoding is selected. Loop on it while changes happen so the 7495 // individual transformations can chain off each other. E.g., 7496 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8) 7497 while (processInstruction(Inst, Operands)) 7498 ; 7499 7500 // Only move forward at the very end so that everything in validate 7501 // and process gets a consistent answer about whether we're in an IT 7502 // block. 7503 forwardITPosition(); 7504 7505 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and 7506 // doesn't actually encode. 7507 if (Inst.getOpcode() == ARM::ITasm) 7508 return false; 7509 7510 Inst.setLoc(IDLoc); 7511 Out.EmitInstruction(Inst); 7512 return false; 7513 case Match_MissingFeature: { 7514 assert(ErrorInfo && "Unknown missing feature!"); 7515 // Special case the error message for the very common case where only 7516 // a single subtarget feature is missing (Thumb vs. ARM, e.g.). 7517 std::string Msg = "instruction requires:"; 7518 unsigned Mask = 1; 7519 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) { 7520 if (ErrorInfo & Mask) { 7521 Msg += " "; 7522 Msg += getSubtargetFeatureName(ErrorInfo & Mask); 7523 } 7524 Mask <<= 1; 7525 } 7526 return Error(IDLoc, Msg); 7527 } 7528 case Match_InvalidOperand: { 7529 SMLoc ErrorLoc = IDLoc; 7530 if (ErrorInfo != ~0U) { 7531 if (ErrorInfo >= Operands.size()) 7532 return Error(IDLoc, "too few operands for instruction"); 7533 7534 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 7535 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 7536 } 7537 7538 return Error(ErrorLoc, "invalid operand for instruction"); 7539 } 7540 case Match_MnemonicFail: 7541 return Error(IDLoc, "invalid instruction", 7542 ((ARMOperand*)Operands[0])->getLocRange()); 7543 case Match_ConversionFail: 7544 // The converter function will have already emitted a diagnostic. 7545 return true; 7546 case Match_RequiresNotITBlock: 7547 return Error(IDLoc, "flag setting instruction only valid outside IT block"); 7548 case Match_RequiresITBlock: 7549 return Error(IDLoc, "instruction only valid inside IT block"); 7550 case Match_RequiresV6: 7551 return Error(IDLoc, "instruction variant requires ARMv6 or later"); 7552 case Match_RequiresThumb2: 7553 return Error(IDLoc, "instruction variant requires Thumb2"); 7554 case Match_ImmRange0_15: { 7555 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc(); 7556 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 7557 return Error(ErrorLoc, "immediate operand must be in the range [0,15]"); 7558 } 7559 } 7560 7561 llvm_unreachable("Implement any new match types added!"); 7562} 7563 7564/// parseDirective parses the arm specific directives 7565bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) { 7566 StringRef IDVal = DirectiveID.getIdentifier(); 7567 if (IDVal == ".word") 7568 return parseDirectiveWord(4, DirectiveID.getLoc()); 7569 else if (IDVal == ".thumb") 7570 return parseDirectiveThumb(DirectiveID.getLoc()); 7571 else if (IDVal == ".arm") 7572 return parseDirectiveARM(DirectiveID.getLoc()); 7573 else if (IDVal == ".thumb_func") 7574 return parseDirectiveThumbFunc(DirectiveID.getLoc()); 7575 else if (IDVal == ".code") 7576 return parseDirectiveCode(DirectiveID.getLoc()); 7577 else if (IDVal == ".syntax") 7578 return parseDirectiveSyntax(DirectiveID.getLoc()); 7579 else if (IDVal == ".unreq") 7580 return parseDirectiveUnreq(DirectiveID.getLoc()); 7581 else if (IDVal == ".arch") 7582 return parseDirectiveArch(DirectiveID.getLoc()); 7583 else if (IDVal == ".eabi_attribute") 7584 return parseDirectiveEabiAttr(DirectiveID.getLoc()); 7585 return true; 7586} 7587 7588/// parseDirectiveWord 7589/// ::= .word [ expression (, expression)* ] 7590bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) { 7591 if (getLexer().isNot(AsmToken::EndOfStatement)) { 7592 for (;;) { 7593 const MCExpr *Value; 7594 if (getParser().ParseExpression(Value)) 7595 return true; 7596 7597 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/); 7598 7599 if (getLexer().is(AsmToken::EndOfStatement)) 7600 break; 7601 7602 // FIXME: Improve diagnostic. 7603 if (getLexer().isNot(AsmToken::Comma)) 7604 return Error(L, "unexpected token in directive"); 7605 Parser.Lex(); 7606 } 7607 } 7608 7609 Parser.Lex(); 7610 return false; 7611} 7612 7613/// parseDirectiveThumb 7614/// ::= .thumb 7615bool ARMAsmParser::parseDirectiveThumb(SMLoc L) { 7616 if (getLexer().isNot(AsmToken::EndOfStatement)) 7617 return Error(L, "unexpected token in directive"); 7618 Parser.Lex(); 7619 7620 if (!isThumb()) 7621 SwitchMode(); 7622 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 7623 return false; 7624} 7625 7626/// parseDirectiveARM 7627/// ::= .arm 7628bool ARMAsmParser::parseDirectiveARM(SMLoc L) { 7629 if (getLexer().isNot(AsmToken::EndOfStatement)) 7630 return Error(L, "unexpected token in directive"); 7631 Parser.Lex(); 7632 7633 if (isThumb()) 7634 SwitchMode(); 7635 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 7636 return false; 7637} 7638 7639/// parseDirectiveThumbFunc 7640/// ::= .thumbfunc symbol_name 7641bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) { 7642 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo(); 7643 bool isMachO = MAI.hasSubsectionsViaSymbols(); 7644 StringRef Name; 7645 bool needFuncName = true; 7646 7647 // Darwin asm has (optionally) function name after .thumb_func direction 7648 // ELF doesn't 7649 if (isMachO) { 7650 const AsmToken &Tok = Parser.getTok(); 7651 if (Tok.isNot(AsmToken::EndOfStatement)) { 7652 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) 7653 return Error(L, "unexpected token in .thumb_func directive"); 7654 Name = Tok.getIdentifier(); 7655 Parser.Lex(); // Consume the identifier token. 7656 needFuncName = false; 7657 } 7658 } 7659 7660 if (getLexer().isNot(AsmToken::EndOfStatement)) 7661 return Error(L, "unexpected token in directive"); 7662 7663 // Eat the end of statement and any blank lines that follow. 7664 while (getLexer().is(AsmToken::EndOfStatement)) 7665 Parser.Lex(); 7666 7667 // FIXME: assuming function name will be the line following .thumb_func 7668 // We really should be checking the next symbol definition even if there's 7669 // stuff in between. 7670 if (needFuncName) { 7671 Name = Parser.getTok().getIdentifier(); 7672 } 7673 7674 // Mark symbol as a thumb symbol. 7675 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name); 7676 getParser().getStreamer().EmitThumbFunc(Func); 7677 return false; 7678} 7679 7680/// parseDirectiveSyntax 7681/// ::= .syntax unified | divided 7682bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) { 7683 const AsmToken &Tok = Parser.getTok(); 7684 if (Tok.isNot(AsmToken::Identifier)) 7685 return Error(L, "unexpected token in .syntax directive"); 7686 StringRef Mode = Tok.getString(); 7687 if (Mode == "unified" || Mode == "UNIFIED") 7688 Parser.Lex(); 7689 else if (Mode == "divided" || Mode == "DIVIDED") 7690 return Error(L, "'.syntax divided' arm asssembly not supported"); 7691 else 7692 return Error(L, "unrecognized syntax mode in .syntax directive"); 7693 7694 if (getLexer().isNot(AsmToken::EndOfStatement)) 7695 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 7696 Parser.Lex(); 7697 7698 // TODO tell the MC streamer the mode 7699 // getParser().getStreamer().Emit???(); 7700 return false; 7701} 7702 7703/// parseDirectiveCode 7704/// ::= .code 16 | 32 7705bool ARMAsmParser::parseDirectiveCode(SMLoc L) { 7706 const AsmToken &Tok = Parser.getTok(); 7707 if (Tok.isNot(AsmToken::Integer)) 7708 return Error(L, "unexpected token in .code directive"); 7709 int64_t Val = Parser.getTok().getIntVal(); 7710 if (Val == 16) 7711 Parser.Lex(); 7712 else if (Val == 32) 7713 Parser.Lex(); 7714 else 7715 return Error(L, "invalid operand to .code directive"); 7716 7717 if (getLexer().isNot(AsmToken::EndOfStatement)) 7718 return Error(Parser.getTok().getLoc(), "unexpected token in directive"); 7719 Parser.Lex(); 7720 7721 if (Val == 16) { 7722 if (!isThumb()) 7723 SwitchMode(); 7724 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); 7725 } else { 7726 if (isThumb()) 7727 SwitchMode(); 7728 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); 7729 } 7730 7731 return false; 7732} 7733 7734/// parseDirectiveReq 7735/// ::= name .req registername 7736bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) { 7737 Parser.Lex(); // Eat the '.req' token. 7738 unsigned Reg; 7739 SMLoc SRegLoc, ERegLoc; 7740 if (ParseRegister(Reg, SRegLoc, ERegLoc)) { 7741 Parser.EatToEndOfStatement(); 7742 return Error(SRegLoc, "register name expected"); 7743 } 7744 7745 // Shouldn't be anything else. 7746 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { 7747 Parser.EatToEndOfStatement(); 7748 return Error(Parser.getTok().getLoc(), 7749 "unexpected input in .req directive."); 7750 } 7751 7752 Parser.Lex(); // Consume the EndOfStatement 7753 7754 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) 7755 return Error(SRegLoc, "redefinition of '" + Name + 7756 "' does not match original."); 7757 7758 return false; 7759} 7760 7761/// parseDirectiveUneq 7762/// ::= .unreq registername 7763bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) { 7764 if (Parser.getTok().isNot(AsmToken::Identifier)) { 7765 Parser.EatToEndOfStatement(); 7766 return Error(L, "unexpected input in .unreq directive."); 7767 } 7768 RegisterReqs.erase(Parser.getTok().getIdentifier()); 7769 Parser.Lex(); // Eat the identifier. 7770 return false; 7771} 7772 7773/// parseDirectiveArch 7774/// ::= .arch token 7775bool ARMAsmParser::parseDirectiveArch(SMLoc L) { 7776 return true; 7777} 7778 7779/// parseDirectiveEabiAttr 7780/// ::= .eabi_attribute int, int 7781bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) { 7782 return true; 7783} 7784 7785extern "C" void LLVMInitializeARMAsmLexer(); 7786 7787/// Force static initialization. 7788extern "C" void LLVMInitializeARMAsmParser() { 7789 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget); 7790 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget); 7791 LLVMInitializeARMAsmLexer(); 7792} 7793 7794#define GET_REGISTER_MATCHER 7795#define GET_SUBTARGET_FEATURE_NAME 7796#define GET_MATCHER_IMPLEMENTATION 7797#include "ARMGenAsmMatcher.inc" 7798