Thumb1InstrInfo.cpp revision 34dcc6fadca0a1117cdbd0e9b35c991a55b6e556 
1//===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Thumb-1 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Thumb1InstrInfo.h"
15#include "ARM.h"
16#include "ARMGenInstrInfo.inc"
17#include "ARMMachineFunctionInfo.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/CodeGen/MachineMemOperand.h"
21#include "llvm/CodeGen/PseudoSourceValue.h"
22#include "llvm/ADT/SmallVector.h"
23#include "Thumb1InstrInfo.h"
24
25using namespace llvm;
26
27Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
28  : ARMBaseInstrInfo(STI), RI(*this, STI) {
29}
30
31unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
32  return 0;
33}
34
35bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
36                                   MachineBasicBlock::iterator I,
37                                   unsigned DestReg, unsigned SrcReg,
38                                   const TargetRegisterClass *DestRC,
39                                   const TargetRegisterClass *SrcRC,
40                                   DebugLoc DL) const {
41  if (DestRC == ARM::GPRRegisterClass) {
42    if (SrcRC == ARM::GPRRegisterClass) {
43      BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
44      return true;
45    } else if (SrcRC == ARM::tGPRRegisterClass) {
46      BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
47      return true;
48    }
49  } else if (DestRC == ARM::tGPRRegisterClass) {
50    if (SrcRC == ARM::GPRRegisterClass) {
51      BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
52      return true;
53    } else if (SrcRC == ARM::tGPRRegisterClass) {
54      BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
55      return true;
56    }
57  }
58
59  return false;
60}
61
62bool Thumb1InstrInfo::
63canFoldMemoryOperand(const MachineInstr *MI,
64                     const SmallVectorImpl<unsigned> &Ops) const {
65  if (Ops.size() != 1) return false;
66
67  unsigned OpNum = Ops[0];
68  unsigned Opc = MI->getOpcode();
69  switch (Opc) {
70  default: break;
71  case ARM::tMOVr:
72  case ARM::tMOVtgpr2gpr:
73  case ARM::tMOVgpr2tgpr:
74  case ARM::tMOVgpr2gpr: {
75    if (OpNum == 0) { // move -> store
76      unsigned SrcReg = MI->getOperand(1).getReg();
77      if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
78          !isARMLowRegister(SrcReg))
79        // tSpill cannot take a high register operand.
80        return false;
81    } else {          // move -> load
82      unsigned DstReg = MI->getOperand(0).getReg();
83      if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
84          !isARMLowRegister(DstReg))
85        // tRestore cannot target a high register operand.
86        return false;
87    }
88    return true;
89  }
90  }
91
92  return false;
93}
94
95void Thumb1InstrInfo::
96storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
97                    unsigned SrcReg, bool isKill, int FI,
98                    const TargetRegisterClass *RC,
99                    const TargetRegisterInfo *TRI) const {
100  assert((RC == ARM::tGPRRegisterClass ||
101          (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
102           isARMLowRegister(SrcReg))) && "Unknown regclass!");
103
104  if (RC == ARM::tGPRRegisterClass ||
105      (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
106       isARMLowRegister(SrcReg))) {
107    DebugLoc DL;
108    if (I != MBB.end()) DL = I->getDebugLoc();
109
110    MachineFunction &MF = *MBB.getParent();
111    MachineFrameInfo &MFI = *MF.getFrameInfo();
112    MachineMemOperand *MMO =
113      MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
114                              MachineMemOperand::MOStore, 0,
115                              MFI.getObjectSize(FI),
116                              MFI.getObjectAlignment(FI));
117    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
118                   .addReg(SrcReg, getKillRegState(isKill))
119                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
120  }
121}
122
123void Thumb1InstrInfo::
124loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
125                     unsigned DestReg, int FI,
126                     const TargetRegisterClass *RC,
127                     const TargetRegisterInfo *TRI) const {
128  assert((RC == ARM::tGPRRegisterClass ||
129          (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
130           isARMLowRegister(DestReg))) && "Unknown regclass!");
131
132  if (RC == ARM::tGPRRegisterClass ||
133      (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
134       isARMLowRegister(DestReg))) {
135    DebugLoc DL;
136    if (I != MBB.end()) DL = I->getDebugLoc();
137
138    MachineFunction &MF = *MBB.getParent();
139    MachineFrameInfo &MFI = *MF.getFrameInfo();
140    MachineMemOperand *MMO =
141      MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
142                              MachineMemOperand::MOLoad, 0,
143                              MFI.getObjectSize(FI),
144                              MFI.getObjectAlignment(FI));
145    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
146                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
147  }
148}
149
150bool Thumb1InstrInfo::
151spillCalleeSavedRegisters(MachineBasicBlock &MBB,
152                          MachineBasicBlock::iterator MI,
153                          const std::vector<CalleeSavedInfo> &CSI) const {
154  if (CSI.empty())
155    return false;
156
157  DebugLoc DL;
158  if (MI != MBB.end()) DL = MI->getDebugLoc();
159
160  MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
161  AddDefaultPred(MIB);
162  for (unsigned i = CSI.size(); i != 0; --i) {
163    unsigned Reg = CSI[i-1].getReg();
164    // Add the callee-saved register as live-in. It's killed at the spill.
165    MBB.addLiveIn(Reg);
166    MIB.addReg(Reg, RegState::Kill);
167  }
168  return true;
169}
170
171bool Thumb1InstrInfo::
172restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
173                            MachineBasicBlock::iterator MI,
174                            const std::vector<CalleeSavedInfo> &CSI) const {
175  MachineFunction &MF = *MBB.getParent();
176  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
177  if (CSI.empty())
178    return false;
179
180  bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
181  DebugLoc DL = MI->getDebugLoc();
182  MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM::tPOP));
183  AddDefaultPred(MIB);
184
185  bool NumRegs = false;
186  for (unsigned i = CSI.size(); i != 0; --i) {
187    unsigned Reg = CSI[i-1].getReg();
188    if (Reg == ARM::LR) {
189      // Special epilogue for vararg functions. See emitEpilogue
190      if (isVarArg)
191        continue;
192      Reg = ARM::PC;
193      (*MIB).setDesc(get(ARM::tPOP_RET));
194      MI = MBB.erase(MI);
195    }
196    MIB.addReg(Reg, getDefRegState(true));
197    NumRegs = true;
198  }
199
200  // It's illegal to emit pop instruction without operands.
201  if (NumRegs)
202    MBB.insert(MI, &*MIB);
203  else
204    MF.DeleteMachineInstr(MIB);
205
206  return true;
207}
208
209MachineInstr *Thumb1InstrInfo::
210foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
211                      const SmallVectorImpl<unsigned> &Ops, int FI) const {
212  if (Ops.size() != 1) return NULL;
213
214  unsigned OpNum = Ops[0];
215  unsigned Opc = MI->getOpcode();
216  MachineInstr *NewMI = NULL;
217  switch (Opc) {
218  default: break;
219  case ARM::tMOVr:
220  case ARM::tMOVtgpr2gpr:
221  case ARM::tMOVgpr2tgpr:
222  case ARM::tMOVgpr2gpr: {
223    if (OpNum == 0) { // move -> store
224      unsigned SrcReg = MI->getOperand(1).getReg();
225      bool isKill = MI->getOperand(1).isKill();
226      if (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
227          !isARMLowRegister(SrcReg))
228        // tSpill cannot take a high register operand.
229        break;
230      NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
231                             .addReg(SrcReg, getKillRegState(isKill))
232                             .addFrameIndex(FI).addImm(0));
233    } else {          // move -> load
234      unsigned DstReg = MI->getOperand(0).getReg();
235      if (TargetRegisterInfo::isPhysicalRegister(DstReg) &&
236          !isARMLowRegister(DstReg))
237        // tRestore cannot target a high register operand.
238        break;
239      bool isDead = MI->getOperand(0).isDead();
240      NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
241                             .addReg(DstReg,
242                                     RegState::Define | getDeadRegState(isDead))
243                             .addFrameIndex(FI).addImm(0));
244    }
245    break;
246  }
247  }
248
249  return NewMI;
250}
251