Thumb1InstrInfo.cpp revision 978e0dfe46e481bfb1281e683aa308329e879e95 
1//===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information ----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Thumb-1 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Thumb1InstrInfo.h"
15#include "ARM.h"
16#include "ARMMachineFunctionInfo.h"
17#include "llvm/CodeGen/MachineFrameInfo.h"
18#include "llvm/CodeGen/MachineInstrBuilder.h"
19#include "llvm/CodeGen/MachineRegisterInfo.h"
20#include "llvm/CodeGen/MachineMemOperand.h"
21#include "llvm/ADT/SmallVector.h"
22#include "Thumb1InstrInfo.h"
23
24using namespace llvm;
25
26Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
27  : ARMBaseInstrInfo(STI), RI(*this, STI) {
28}
29
30unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
31  return 0;
32}
33
34void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
35                                  MachineBasicBlock::iterator I, DebugLoc DL,
36                                  unsigned DestReg, unsigned SrcReg,
37                                  bool KillSrc) const {
38  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
39    .addReg(SrcReg, getKillRegState(KillSrc)));
40  assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
41         "Thumb1 can only copy GPR registers");
42}
43
44void Thumb1InstrInfo::
45storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
46                    unsigned SrcReg, bool isKill, int FI,
47                    const TargetRegisterClass *RC,
48                    const TargetRegisterInfo *TRI) const {
49  assert((RC == ARM::tGPRRegisterClass ||
50          (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
51           isARMLowRegister(SrcReg))) && "Unknown regclass!");
52
53  if (RC == ARM::tGPRRegisterClass ||
54      (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
55       isARMLowRegister(SrcReg))) {
56    DebugLoc DL;
57    if (I != MBB.end()) DL = I->getDebugLoc();
58
59    MachineFunction &MF = *MBB.getParent();
60    MachineFrameInfo &MFI = *MF.getFrameInfo();
61    MachineMemOperand *MMO =
62      MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
63                              MachineMemOperand::MOStore,
64                              MFI.getObjectSize(FI),
65                              MFI.getObjectAlignment(FI));
66    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSTRspi))
67                   .addReg(SrcReg, getKillRegState(isKill))
68                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
69  }
70}
71
72void Thumb1InstrInfo::
73loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
74                     unsigned DestReg, int FI,
75                     const TargetRegisterClass *RC,
76                     const TargetRegisterInfo *TRI) const {
77  assert((RC == ARM::tGPRRegisterClass ||
78          (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
79           isARMLowRegister(DestReg))) && "Unknown regclass!");
80
81  if (RC == ARM::tGPRRegisterClass ||
82      (TargetRegisterInfo::isPhysicalRegister(DestReg) &&
83       isARMLowRegister(DestReg))) {
84    DebugLoc DL;
85    if (I != MBB.end()) DL = I->getDebugLoc();
86
87    MachineFunction &MF = *MBB.getParent();
88    MachineFrameInfo &MFI = *MF.getFrameInfo();
89    MachineMemOperand *MMO =
90      MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
91                              MachineMemOperand::MOLoad,
92                              MFI.getObjectSize(FI),
93                              MFI.getObjectAlignment(FI));
94    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
95                   .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
96  }
97}
98