Thumb1InstrInfo.cpp revision d90183d25dcbc0eabde56319fed4e8d6ace2e6eb 
1//===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Thumb-1 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMInstrInfo.h"
15#include "ARM.h"
16#include "ARMGenInstrInfo.inc"
17#include "ARMMachineFunctionInfo.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineInstrBuilder.h"
20#include "llvm/ADT/SmallVector.h"
21#include "Thumb1InstrInfo.h"
22
23using namespace llvm;
24
25Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI) : RI(*this, STI) {
26}
27
28unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
29  return 0;
30}
31
32bool
33Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
34  if (MBB.empty()) return false;
35
36  switch (MBB.back().getOpcode()) {
37  case ARM::tBX_RET:
38  case ARM::tBX_RET_vararg:
39  case ARM::tPOP_RET:
40  case ARM::tB:
41  case ARM::tBR_JTr:
42    return true;
43  default:
44    break;
45  }
46
47  return false;
48}
49
50bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
51                                   MachineBasicBlock::iterator I,
52                                   unsigned DestReg, unsigned SrcReg,
53                                   const TargetRegisterClass *DestRC,
54                                   const TargetRegisterClass *SrcRC) const {
55  DebugLoc DL = DebugLoc::getUnknownLoc();
56  if (I != MBB.end()) DL = I->getDebugLoc();
57
58  if (DestRC == ARM::GPRRegisterClass) {
59    if (SrcRC == ARM::GPRRegisterClass) {
60      BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
61      return true;
62    } else if (SrcRC == ARM::tGPRRegisterClass) {
63      BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
64      return true;
65    }
66  } else if (DestRC == ARM::tGPRRegisterClass) {
67    if (SrcRC == ARM::GPRRegisterClass) {
68      BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
69      return true;
70    } else if (SrcRC == ARM::tGPRRegisterClass) {
71      BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
72      return true;
73    }
74  }
75
76  return false;
77}
78
79bool Thumb1InstrInfo::
80canFoldMemoryOperand(const MachineInstr *MI,
81                     const SmallVectorImpl<unsigned> &Ops) const {
82  if (Ops.size() != 1) return false;
83
84  unsigned OpNum = Ops[0];
85  unsigned Opc = MI->getOpcode();
86  switch (Opc) {
87  default: break;
88  case ARM::tMOVr:
89  case ARM::tMOVtgpr2gpr:
90  case ARM::tMOVgpr2tgpr:
91  case ARM::tMOVgpr2gpr: {
92    if (OpNum == 0) { // move -> store
93      unsigned SrcReg = MI->getOperand(1).getReg();
94      if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
95        // tSpill cannot take a high register operand.
96        return false;
97    } else {          // move -> load
98      unsigned DstReg = MI->getOperand(0).getReg();
99      if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
100        // tRestore cannot target a high register operand.
101        return false;
102    }
103    return true;
104  }
105  }
106
107  return false;
108}
109
110void Thumb1InstrInfo::
111storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
112                    unsigned SrcReg, bool isKill, int FI,
113                    const TargetRegisterClass *RC) const {
114  DebugLoc DL = DebugLoc::getUnknownLoc();
115  if (I != MBB.end()) DL = I->getDebugLoc();
116
117  assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
118
119  if (RC == ARM::tGPRRegisterClass) {
120    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
121                   .addReg(SrcReg, getKillRegState(isKill))
122                   .addFrameIndex(FI).addImm(0));
123  }
124}
125
126void Thumb1InstrInfo::
127loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
128                     unsigned DestReg, int FI,
129                     const TargetRegisterClass *RC) const {
130  DebugLoc DL = DebugLoc::getUnknownLoc();
131  if (I != MBB.end()) DL = I->getDebugLoc();
132
133  assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
134
135  if (RC == ARM::tGPRRegisterClass) {
136    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
137                   .addFrameIndex(FI).addImm(0));
138  }
139}
140
141bool Thumb1InstrInfo::
142spillCalleeSavedRegisters(MachineBasicBlock &MBB,
143                          MachineBasicBlock::iterator MI,
144                          const std::vector<CalleeSavedInfo> &CSI) const {
145  if (CSI.empty())
146    return false;
147
148  DebugLoc DL = DebugLoc::getUnknownLoc();
149  if (MI != MBB.end()) DL = MI->getDebugLoc();
150
151  MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
152  for (unsigned i = CSI.size(); i != 0; --i) {
153    unsigned Reg = CSI[i-1].getReg();
154    // Add the callee-saved register as live-in. It's killed at the spill.
155    MBB.addLiveIn(Reg);
156    MIB.addReg(Reg, RegState::Kill);
157  }
158  return true;
159}
160
161bool Thumb1InstrInfo::
162restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
163                            MachineBasicBlock::iterator MI,
164                            const std::vector<CalleeSavedInfo> &CSI) const {
165  MachineFunction &MF = *MBB.getParent();
166  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
167  if (CSI.empty())
168    return false;
169
170  bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
171  MachineInstr *PopMI = MF.CreateMachineInstr(get(ARM::tPOP),MI->getDebugLoc());
172  for (unsigned i = CSI.size(); i != 0; --i) {
173    unsigned Reg = CSI[i-1].getReg();
174    if (Reg == ARM::LR) {
175      // Special epilogue for vararg functions. See emitEpilogue
176      if (isVarArg)
177        continue;
178      Reg = ARM::PC;
179      PopMI->setDesc(get(ARM::tPOP_RET));
180      MI = MBB.erase(MI);
181    }
182    PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
183  }
184
185  // It's illegal to emit pop instruction without operands.
186  if (PopMI->getNumOperands() > 0)
187    MBB.insert(MI, PopMI);
188
189  return true;
190}
191
192MachineInstr *Thumb1InstrInfo::
193foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
194                      const SmallVectorImpl<unsigned> &Ops, int FI) const {
195  if (Ops.size() != 1) return NULL;
196
197  unsigned OpNum = Ops[0];
198  unsigned Opc = MI->getOpcode();
199  MachineInstr *NewMI = NULL;
200  switch (Opc) {
201  default: break;
202  case ARM::tMOVr:
203  case ARM::tMOVtgpr2gpr:
204  case ARM::tMOVgpr2tgpr:
205  case ARM::tMOVgpr2gpr: {
206    if (OpNum == 0) { // move -> store
207      unsigned SrcReg = MI->getOperand(1).getReg();
208      bool isKill = MI->getOperand(1).isKill();
209      if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
210        // tSpill cannot take a high register operand.
211        break;
212      NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
213                             .addReg(SrcReg, getKillRegState(isKill))
214                             .addFrameIndex(FI).addImm(0));
215    } else {          // move -> load
216      unsigned DstReg = MI->getOperand(0).getReg();
217      if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
218        // tRestore cannot target a high register operand.
219        break;
220      bool isDead = MI->getOperand(0).isDead();
221      NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
222                             .addReg(DstReg,
223                                     RegState::Define | getDeadRegState(isDead))
224                             .addFrameIndex(FI).addImm(0));
225    }
226    break;
227  }
228  }
229
230  return NewMI;
231}
232