PPCISelLowering.h revision 1efa40f6a4b561cf8f80fe018684236010645cd0
1//===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that PPC uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 16#define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 17 18#include "llvm/Target/TargetLowering.h" 19#include "llvm/CodeGen/SelectionDAG.h" 20#include "PPC.h" 21 22namespace llvm { 23 namespace PPCISD { 24 enum NodeType { 25 // Start the numbering where the builting ops and target ops leave off. 26 FIRST_NUMBER = ISD::BUILTIN_OP_END+PPC::INSTRUCTION_LIST_END, 27 28 /// FSEL - Traditional three-operand fsel node. 29 /// 30 FSEL, 31 32 /// FCFID - The FCFID instruction, taking an f64 operand and producing 33 /// and f64 value containing the FP representation of the integer that 34 /// was temporarily in the f64 operand. 35 FCFID, 36 37 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64 38 /// operand, producing an f64 value containing the integer representation 39 /// of that FP value. 40 FCTIDZ, FCTIWZ, 41 42 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking 43 // three v4f32 operands and producing a v4f32 result. 44 VMADDFP, VNMSUBFP, 45 46 /// Hi/Lo - These represent the high and low 16-bit parts of a global 47 /// address respectively. These nodes have two operands, the first of 48 /// which must be a TargetGlobalAddress, and the second of which must be a 49 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C', 50 /// though these are usually folded into other nodes. 51 Hi, Lo, 52 53 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr 54 /// at function entry, used for PIC code. 55 GlobalBaseReg, 56 57 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit 58 /// shift amounts. These nodes are generated by the multi-precision shift 59 /// code. 60 SRL, SRA, SHL, 61 62 /// CALL - A function call. 63 CALL, 64 65 /// Return with a flag operand, matched by 'blr' 66 RET_FLAG, 67 }; 68 } 69 70 class PPCTargetLowering : public TargetLowering { 71 int VarArgsFrameIndex; // FrameIndex for start of varargs area. 72 int ReturnAddrIndex; // FrameIndex for return slot. 73 public: 74 PPCTargetLowering(TargetMachine &TM); 75 76 /// getTargetNodeName() - This method returns the name of a target specific 77 /// DAG node. 78 virtual const char *getTargetNodeName(unsigned Opcode) const; 79 80 /// LowerOperation - Provide custom lowering hooks for some operations. 81 /// 82 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 83 84 /// LowerArguments - This hook must be implemented to indicate how we should 85 /// lower the arguments for the specified function, into the specified DAG. 86 virtual std::vector<SDOperand> 87 LowerArguments(Function &F, SelectionDAG &DAG); 88 89 /// LowerCallTo - This hook lowers an abstract call to a function into an 90 /// actual call. 91 virtual std::pair<SDOperand, SDOperand> 92 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, 93 unsigned CC, 94 bool isTailCall, SDOperand Callee, ArgListTy &Args, 95 SelectionDAG &DAG); 96 97 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 98 MachineBasicBlock *MBB); 99 100 ConstraintType getConstraintType(char ConstraintLetter) const; 101 std::vector<unsigned> 102 getRegClassForInlineAsmConstraint(const std::string &Constraint, 103 MVT::ValueType VT) const; 104 bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter); 105 }; 106} 107 108#endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H 109