PPCJITInfo.cpp revision 32d7e6ebde29faeea75ecb718b4281414b0eea0b
1//===-- PPCJITInfo.cpp - Implement the JIT interfaces for the PowerPC -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the JIT interfaces for the 32-bit PowerPC target. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "jit" 15#include "PPCJITInfo.h" 16#include "PPCRelocations.h" 17#include "PPCTargetMachine.h" 18#include "llvm/Function.h" 19#include "llvm/System/Memory.h" 20#include "llvm/Support/Debug.h" 21#include "llvm/Support/ErrorHandling.h" 22#include "llvm/Support/raw_ostream.h" 23using namespace llvm; 24 25static TargetJITInfo::JITCompilerFn JITCompilerFunction; 26 27#define BUILD_ADDIS(RD,RS,IMM16) \ 28 ((15 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 65535)) 29#define BUILD_ORI(RD,RS,UIMM16) \ 30 ((24 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535)) 31#define BUILD_ORIS(RD,RS,UIMM16) \ 32 ((25 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535)) 33#define BUILD_RLDICR(RD,RS,SH,ME) \ 34 ((30 << 26) | ((RS) << 21) | ((RD) << 16) | (((SH) & 31) << 11) | \ 35 (((ME) & 63) << 6) | (1 << 2) | ((((SH) >> 5) & 1) << 1)) 36#define BUILD_MTSPR(RS,SPR) \ 37 ((31 << 26) | ((RS) << 21) | ((SPR) << 16) | (467 << 1)) 38#define BUILD_BCCTRx(BO,BI,LINK) \ 39 ((19 << 26) | ((BO) << 21) | ((BI) << 16) | (528 << 1) | ((LINK) & 1)) 40#define BUILD_B(TARGET, LINK) \ 41 ((18 << 26) | (((TARGET) & 0x00FFFFFF) << 2) | ((LINK) & 1)) 42 43// Pseudo-ops 44#define BUILD_LIS(RD,IMM16) BUILD_ADDIS(RD,0,IMM16) 45#define BUILD_SLDI(RD,RS,IMM6) BUILD_RLDICR(RD,RS,IMM6,63-IMM6) 46#define BUILD_MTCTR(RS) BUILD_MTSPR(RS,9) 47#define BUILD_BCTR(LINK) BUILD_BCCTRx(20,0,LINK) 48 49static void EmitBranchToAt(uint64_t At, uint64_t To, bool isCall, bool is64Bit){ 50 intptr_t Offset = ((intptr_t)To - (intptr_t)At) >> 2; 51 unsigned *AtI = (unsigned*)(intptr_t)At; 52 53 if (Offset >= -(1 << 23) && Offset < (1 << 23)) { // In range? 54 AtI[0] = BUILD_B(Offset, isCall); // b/bl target 55 } else if (!is64Bit) { 56 AtI[0] = BUILD_LIS(12, To >> 16); // lis r12, hi16(address) 57 AtI[1] = BUILD_ORI(12, 12, To); // ori r12, r12, lo16(address) 58 AtI[2] = BUILD_MTCTR(12); // mtctr r12 59 AtI[3] = BUILD_BCTR(isCall); // bctr/bctrl 60 } else { 61 AtI[0] = BUILD_LIS(12, To >> 48); // lis r12, hi16(address) 62 AtI[1] = BUILD_ORI(12, 12, To >> 32); // ori r12, r12, lo16(address) 63 AtI[2] = BUILD_SLDI(12, 12, 32); // sldi r12, r12, 32 64 AtI[3] = BUILD_ORIS(12, 12, To >> 16); // oris r12, r12, hi16(address) 65 AtI[4] = BUILD_ORI(12, 12, To); // ori r12, r12, lo16(address) 66 AtI[5] = BUILD_MTCTR(12); // mtctr r12 67 AtI[6] = BUILD_BCTR(isCall); // bctr/bctrl 68 } 69} 70 71extern "C" void PPC32CompilationCallback(); 72extern "C" void PPC64CompilationCallback(); 73 74#if (defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)) && \ 75 !(defined(__ppc64__) || defined(__FreeBSD__)) 76// CompilationCallback stub - We can't use a C function with inline assembly in 77// it, because we the prolog/epilog inserted by GCC won't work for us. Instead, 78// write our own wrapper, which does things our way, so we have complete control 79// over register saving and restoring. 80asm( 81 ".text\n" 82 ".align 2\n" 83 ".globl _PPC32CompilationCallback\n" 84"_PPC32CompilationCallback:\n" 85 // Make space for 8 ints r[3-10] and 13 doubles f[1-13] and the 86 // FIXME: need to save v[0-19] for altivec? 87 // FIXME: could shrink frame 88 // Set up a proper stack frame 89 // FIXME Layout 90 // PowerPC64 ABI linkage - 24 bytes 91 // parameters - 32 bytes 92 // 13 double registers - 104 bytes 93 // 8 int registers - 32 bytes 94 "mflr r0\n" 95 "stw r0, 8(r1)\n" 96 "stwu r1, -208(r1)\n" 97 // Save all int arg registers 98 "stw r10, 204(r1)\n" "stw r9, 200(r1)\n" 99 "stw r8, 196(r1)\n" "stw r7, 192(r1)\n" 100 "stw r6, 188(r1)\n" "stw r5, 184(r1)\n" 101 "stw r4, 180(r1)\n" "stw r3, 176(r1)\n" 102 // Save all call-clobbered FP regs. 103 "stfd f13, 168(r1)\n" "stfd f12, 160(r1)\n" 104 "stfd f11, 152(r1)\n" "stfd f10, 144(r1)\n" 105 "stfd f9, 136(r1)\n" "stfd f8, 128(r1)\n" 106 "stfd f7, 120(r1)\n" "stfd f6, 112(r1)\n" 107 "stfd f5, 104(r1)\n" "stfd f4, 96(r1)\n" 108 "stfd f3, 88(r1)\n" "stfd f2, 80(r1)\n" 109 "stfd f1, 72(r1)\n" 110 // Arguments to Compilation Callback: 111 // r3 - our lr (address of the call instruction in stub plus 4) 112 // r4 - stub's lr (address of instruction that called the stub plus 4) 113 // r5 - is64Bit - always 0. 114 "mr r3, r0\n" 115 "lwz r2, 208(r1)\n" // stub's frame 116 "lwz r4, 8(r2)\n" // stub's lr 117 "li r5, 0\n" // 0 == 32 bit 118 "bl _PPCCompilationCallbackC\n" 119 "mtctr r3\n" 120 // Restore all int arg registers 121 "lwz r10, 204(r1)\n" "lwz r9, 200(r1)\n" 122 "lwz r8, 196(r1)\n" "lwz r7, 192(r1)\n" 123 "lwz r6, 188(r1)\n" "lwz r5, 184(r1)\n" 124 "lwz r4, 180(r1)\n" "lwz r3, 176(r1)\n" 125 // Restore all FP arg registers 126 "lfd f13, 168(r1)\n" "lfd f12, 160(r1)\n" 127 "lfd f11, 152(r1)\n" "lfd f10, 144(r1)\n" 128 "lfd f9, 136(r1)\n" "lfd f8, 128(r1)\n" 129 "lfd f7, 120(r1)\n" "lfd f6, 112(r1)\n" 130 "lfd f5, 104(r1)\n" "lfd f4, 96(r1)\n" 131 "lfd f3, 88(r1)\n" "lfd f2, 80(r1)\n" 132 "lfd f1, 72(r1)\n" 133 // Pop 3 frames off the stack and branch to target 134 "lwz r1, 208(r1)\n" 135 "lwz r2, 8(r1)\n" 136 "mtlr r2\n" 137 "bctr\n" 138 ); 139 140#elif defined(__PPC__) && !defined(__ppc64__) 141// Linux & FreeBSD / PPC 32 support 142 143// CompilationCallback stub - We can't use a C function with inline assembly in 144// it, because we the prolog/epilog inserted by GCC won't work for us. Instead, 145// write our own wrapper, which does things our way, so we have complete control 146// over register saving and restoring. 147asm( 148 ".text\n" 149 ".align 2\n" 150 ".globl PPC32CompilationCallback\n" 151"PPC32CompilationCallback:\n" 152 // Make space for 8 ints r[3-10] and 8 doubles f[1-8] and the 153 // FIXME: need to save v[0-19] for altivec? 154 // FIXME: could shrink frame 155 // Set up a proper stack frame 156 // FIXME Layout 157 // 8 double registers - 64 bytes 158 // 8 int registers - 32 bytes 159 "mflr 0\n" 160 "stw 0, 4(1)\n" 161 "stwu 1, -104(1)\n" 162 // Save all int arg registers 163 "stw 10, 100(1)\n" "stw 9, 96(1)\n" 164 "stw 8, 92(1)\n" "stw 7, 88(1)\n" 165 "stw 6, 84(1)\n" "stw 5, 80(1)\n" 166 "stw 4, 76(1)\n" "stw 3, 72(1)\n" 167 // Save all call-clobbered FP regs. 168 "stfd 8, 64(1)\n" 169 "stfd 7, 56(1)\n" "stfd 6, 48(1)\n" 170 "stfd 5, 40(1)\n" "stfd 4, 32(1)\n" 171 "stfd 3, 24(1)\n" "stfd 2, 16(1)\n" 172 "stfd 1, 8(1)\n" 173 // Arguments to Compilation Callback: 174 // r3 - our lr (address of the call instruction in stub plus 4) 175 // r4 - stub's lr (address of instruction that called the stub plus 4) 176 // r5 - is64Bit - always 0. 177 "mr 3, 0\n" 178 "lwz 5, 104(1)\n" // stub's frame 179 "lwz 4, 4(5)\n" // stub's lr 180 "li 5, 0\n" // 0 == 32 bit 181 "bl PPCCompilationCallbackC\n" 182 "mtctr 3\n" 183 // Restore all int arg registers 184 "lwz 10, 100(1)\n" "lwz 9, 96(1)\n" 185 "lwz 8, 92(1)\n" "lwz 7, 88(1)\n" 186 "lwz 6, 84(1)\n" "lwz 5, 80(1)\n" 187 "lwz 4, 76(1)\n" "lwz 3, 72(1)\n" 188 // Restore all FP arg registers 189 "lfd 8, 64(1)\n" 190 "lfd 7, 56(1)\n" "lfd 6, 48(1)\n" 191 "lfd 5, 40(1)\n" "lfd 4, 32(1)\n" 192 "lfd 3, 24(1)\n" "lfd 2, 16(1)\n" 193 "lfd 1, 8(1)\n" 194 // Pop 3 frames off the stack and branch to target 195 "lwz 1, 104(1)\n" 196 "lwz 0, 4(1)\n" 197 "mtlr 0\n" 198 "bctr\n" 199 ); 200#else 201void PPC32CompilationCallback() { 202 llvm_unreachable("This is not a power pc, you can't execute this!"); 203} 204#endif 205 206#if (defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)) && \ 207 defined(__ppc64__) 208asm( 209 ".text\n" 210 ".align 2\n" 211 ".globl _PPC64CompilationCallback\n" 212"_PPC64CompilationCallback:\n" 213 // Make space for 8 ints r[3-10] and 13 doubles f[1-13] and the 214 // FIXME: need to save v[0-19] for altivec? 215 // Set up a proper stack frame 216 // Layout 217 // PowerPC64 ABI linkage - 48 bytes 218 // parameters - 64 bytes 219 // 13 double registers - 104 bytes 220 // 8 int registers - 64 bytes 221 "mflr r0\n" 222 "std r0, 16(r1)\n" 223 "stdu r1, -280(r1)\n" 224 // Save all int arg registers 225 "std r10, 272(r1)\n" "std r9, 264(r1)\n" 226 "std r8, 256(r1)\n" "std r7, 248(r1)\n" 227 "std r6, 240(r1)\n" "std r5, 232(r1)\n" 228 "std r4, 224(r1)\n" "std r3, 216(r1)\n" 229 // Save all call-clobbered FP regs. 230 "stfd f13, 208(r1)\n" "stfd f12, 200(r1)\n" 231 "stfd f11, 192(r1)\n" "stfd f10, 184(r1)\n" 232 "stfd f9, 176(r1)\n" "stfd f8, 168(r1)\n" 233 "stfd f7, 160(r1)\n" "stfd f6, 152(r1)\n" 234 "stfd f5, 144(r1)\n" "stfd f4, 136(r1)\n" 235 "stfd f3, 128(r1)\n" "stfd f2, 120(r1)\n" 236 "stfd f1, 112(r1)\n" 237 // Arguments to Compilation Callback: 238 // r3 - our lr (address of the call instruction in stub plus 4) 239 // r4 - stub's lr (address of instruction that called the stub plus 4) 240 // r5 - is64Bit - always 1. 241 "mr r3, r0\n" 242 "ld r2, 280(r1)\n" // stub's frame 243 "ld r4, 16(r2)\n" // stub's lr 244 "li r5, 1\n" // 1 == 64 bit 245 "bl _PPCCompilationCallbackC\n" 246 "mtctr r3\n" 247 // Restore all int arg registers 248 "ld r10, 272(r1)\n" "ld r9, 264(r1)\n" 249 "ld r8, 256(r1)\n" "ld r7, 248(r1)\n" 250 "ld r6, 240(r1)\n" "ld r5, 232(r1)\n" 251 "ld r4, 224(r1)\n" "ld r3, 216(r1)\n" 252 // Restore all FP arg registers 253 "lfd f13, 208(r1)\n" "lfd f12, 200(r1)\n" 254 "lfd f11, 192(r1)\n" "lfd f10, 184(r1)\n" 255 "lfd f9, 176(r1)\n" "lfd f8, 168(r1)\n" 256 "lfd f7, 160(r1)\n" "lfd f6, 152(r1)\n" 257 "lfd f5, 144(r1)\n" "lfd f4, 136(r1)\n" 258 "lfd f3, 128(r1)\n" "lfd f2, 120(r1)\n" 259 "lfd f1, 112(r1)\n" 260 // Pop 3 frames off the stack and branch to target 261 "ld r1, 280(r1)\n" 262 "ld r2, 16(r1)\n" 263 "mtlr r2\n" 264 "bctr\n" 265 ); 266#else 267void PPC64CompilationCallback() { 268 llvm_unreachable("This is not a power pc, you can't execute this!"); 269} 270#endif 271 272extern "C" void *PPCCompilationCallbackC(unsigned *StubCallAddrPlus4, 273 unsigned *OrigCallAddrPlus4, 274 bool is64Bit) { 275 // Adjust the pointer to the address of the call instruction in the stub 276 // emitted by emitFunctionStub, rather than the instruction after it. 277 unsigned *StubCallAddr = StubCallAddrPlus4 - 1; 278 unsigned *OrigCallAddr = OrigCallAddrPlus4 - 1; 279 280 void *Target = JITCompilerFunction(StubCallAddr); 281 282 // Check to see if *OrigCallAddr is a 'bl' instruction, and if we can rewrite 283 // it to branch directly to the destination. If so, rewrite it so it does not 284 // need to go through the stub anymore. 285 unsigned OrigCallInst = *OrigCallAddr; 286 if ((OrigCallInst >> 26) == 18) { // Direct call. 287 intptr_t Offset = ((intptr_t)Target - (intptr_t)OrigCallAddr) >> 2; 288 289 if (Offset >= -(1 << 23) && Offset < (1 << 23)) { // In range? 290 // Clear the original target out. 291 OrigCallInst &= (63 << 26) | 3; 292 // Fill in the new target. 293 OrigCallInst |= (Offset & ((1 << 24)-1)) << 2; 294 // Replace the call. 295 *OrigCallAddr = OrigCallInst; 296 } 297 } 298 299 // Assert that we are coming from a stub that was created with our 300 // emitFunctionStub. 301 if ((*StubCallAddr >> 26) == 18) 302 StubCallAddr -= 3; 303 else { 304 assert((*StubCallAddr >> 26) == 19 && "Call in stub is not indirect!"); 305 StubCallAddr -= is64Bit ? 9 : 6; 306 } 307 308 // Rewrite the stub with an unconditional branch to the target, for any users 309 // who took the address of the stub. 310 EmitBranchToAt((intptr_t)StubCallAddr, (intptr_t)Target, false, is64Bit); 311 312 // Put the address of the target function to call and the address to return to 313 // after calling the target function in a place that is easy to get on the 314 // stack after we restore all regs. 315 return Target; 316} 317 318 319 320TargetJITInfo::LazyResolverFn 321PPCJITInfo::getLazyResolverFunction(JITCompilerFn Fn) { 322 JITCompilerFunction = Fn; 323 return is64Bit ? PPC64CompilationCallback : PPC32CompilationCallback; 324} 325 326TargetJITInfo::StubLayout PPCJITInfo::getStubLayout() { 327 // The stub contains up to 10 4-byte instructions, aligned at 4 bytes: 3 328 // instructions to save the caller's address if this is a lazy-compilation 329 // stub, plus a 1-, 4-, or 7-instruction sequence to load an arbitrary address 330 // into a register and jump through it. 331 StubLayout Result = {10*4, 4}; 332 return Result; 333} 334 335#if (defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)) && \ 336defined(__APPLE__) 337extern "C" void sys_icache_invalidate(const void *Addr, size_t len); 338#endif 339 340void *PPCJITInfo::emitFunctionStub(const Function* F, void *Fn, 341 JITCodeEmitter &JCE) { 342 // If this is just a call to an external function, emit a branch instead of a 343 // call. The code is the same except for one bit of the last instruction. 344 if (Fn != (void*)(intptr_t)PPC32CompilationCallback && 345 Fn != (void*)(intptr_t)PPC64CompilationCallback) { 346 void *Addr = (void*)JCE.getCurrentPCValue(); 347 JCE.emitWordBE(0); 348 JCE.emitWordBE(0); 349 JCE.emitWordBE(0); 350 JCE.emitWordBE(0); 351 JCE.emitWordBE(0); 352 JCE.emitWordBE(0); 353 JCE.emitWordBE(0); 354 EmitBranchToAt((intptr_t)Addr, (intptr_t)Fn, false, is64Bit); 355 sys::Memory::InvalidateInstructionCache(Addr, 7*4); 356 return Addr; 357 } 358 359 void *Addr = (void*)JCE.getCurrentPCValue(); 360 if (is64Bit) { 361 JCE.emitWordBE(0xf821ffb1); // stdu r1,-80(r1) 362 JCE.emitWordBE(0x7d6802a6); // mflr r11 363 JCE.emitWordBE(0xf9610060); // std r11, 96(r1) 364 } else if (TM.getSubtargetImpl()->isDarwinABI()){ 365 JCE.emitWordBE(0x9421ffe0); // stwu r1,-32(r1) 366 JCE.emitWordBE(0x7d6802a6); // mflr r11 367 JCE.emitWordBE(0x91610028); // stw r11, 40(r1) 368 } else { 369 JCE.emitWordBE(0x9421ffe0); // stwu r1,-32(r1) 370 JCE.emitWordBE(0x7d6802a6); // mflr r11 371 JCE.emitWordBE(0x91610024); // stw r11, 36(r1) 372 } 373 intptr_t BranchAddr = (intptr_t)JCE.getCurrentPCValue(); 374 JCE.emitWordBE(0); 375 JCE.emitWordBE(0); 376 JCE.emitWordBE(0); 377 JCE.emitWordBE(0); 378 JCE.emitWordBE(0); 379 JCE.emitWordBE(0); 380 JCE.emitWordBE(0); 381 EmitBranchToAt(BranchAddr, (intptr_t)Fn, true, is64Bit); 382 sys::Memory::InvalidateInstructionCache(Addr, 10*4); 383 return Addr; 384} 385 386 387void PPCJITInfo::relocate(void *Function, MachineRelocation *MR, 388 unsigned NumRelocs, unsigned char* GOTBase) { 389 for (unsigned i = 0; i != NumRelocs; ++i, ++MR) { 390 unsigned *RelocPos = (unsigned*)Function + MR->getMachineCodeOffset()/4; 391 intptr_t ResultPtr = (intptr_t)MR->getResultPointer(); 392 switch ((PPC::RelocationType)MR->getRelocationType()) { 393 default: llvm_unreachable("Unknown relocation type!"); 394 case PPC::reloc_pcrel_bx: 395 // PC-relative relocation for b and bl instructions. 396 ResultPtr = (ResultPtr-(intptr_t)RelocPos) >> 2; 397 assert(ResultPtr >= -(1 << 23) && ResultPtr < (1 << 23) && 398 "Relocation out of range!"); 399 *RelocPos |= (ResultPtr & ((1 << 24)-1)) << 2; 400 break; 401 case PPC::reloc_pcrel_bcx: 402 // PC-relative relocation for BLT,BLE,BEQ,BGE,BGT,BNE, or other 403 // bcx instructions. 404 ResultPtr = (ResultPtr-(intptr_t)RelocPos) >> 2; 405 assert(ResultPtr >= -(1 << 13) && ResultPtr < (1 << 13) && 406 "Relocation out of range!"); 407 *RelocPos |= (ResultPtr & ((1 << 14)-1)) << 2; 408 break; 409 case PPC::reloc_absolute_high: // high bits of ref -> low 16 of instr 410 case PPC::reloc_absolute_low: { // low bits of ref -> low 16 of instr 411 ResultPtr += MR->getConstantVal(); 412 413 // If this is a high-part access, get the high-part. 414 if (MR->getRelocationType() == PPC::reloc_absolute_high) { 415 // If the low part will have a carry (really a borrow) from the low 416 // 16-bits into the high 16, add a bit to borrow from. 417 if (((int)ResultPtr << 16) < 0) 418 ResultPtr += 1 << 16; 419 ResultPtr >>= 16; 420 } 421 422 // Do the addition then mask, so the addition does not overflow the 16-bit 423 // immediate section of the instruction. 424 unsigned LowBits = (*RelocPos + ResultPtr) & 65535; 425 unsigned HighBits = *RelocPos & ~65535; 426 *RelocPos = LowBits | HighBits; // Slam into low 16-bits 427 break; 428 } 429 case PPC::reloc_absolute_low_ix: { // low bits of ref -> low 14 of instr 430 ResultPtr += MR->getConstantVal(); 431 // Do the addition then mask, so the addition does not overflow the 16-bit 432 // immediate section of the instruction. 433 unsigned LowBits = (*RelocPos + ResultPtr) & 0xFFFC; 434 unsigned HighBits = *RelocPos & 0xFFFF0003; 435 *RelocPos = LowBits | HighBits; // Slam into low 14-bits. 436 break; 437 } 438 } 439 } 440} 441 442void PPCJITInfo::replaceMachineCodeForFunction(void *Old, void *New) { 443 EmitBranchToAt((intptr_t)Old, (intptr_t)New, false, is64Bit); 444} 445