PPCJITInfo.cpp revision f522068412218cd14b2c2df74a3437717d255381
1//===-- PPCJITInfo.cpp - Implement the JIT interfaces for the PowerPC -----===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the JIT interfaces for the 32-bit PowerPC target. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "jit" 15#include "PPCJITInfo.h" 16#include "PPCRelocations.h" 17#include "PPCTargetMachine.h" 18#include "llvm/Function.h" 19#include "llvm/CodeGen/MachineCodeEmitter.h" 20#include "llvm/System/Memory.h" 21#include "llvm/Support/Debug.h" 22using namespace llvm; 23 24static TargetJITInfo::JITCompilerFn JITCompilerFunction; 25 26#define BUILD_ADDIS(RD,RS,IMM16) \ 27 ((15 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 65535)) 28#define BUILD_ORI(RD,RS,UIMM16) \ 29 ((24 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535)) 30#define BUILD_ORIS(RD,RS,UIMM16) \ 31 ((25 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535)) 32#define BUILD_RLDICR(RD,RS,SH,ME) \ 33 ((30 << 26) | ((RS) << 21) | ((RD) << 16) | (((SH) & 31) << 11) | \ 34 (((ME) & 63) << 6) | (1 << 2) | ((((SH) >> 5) & 1) << 1)) 35#define BUILD_MTSPR(RS,SPR) \ 36 ((31 << 26) | ((RS) << 21) | ((SPR) << 16) | (467 << 1)) 37#define BUILD_BCCTRx(BO,BI,LINK) \ 38 ((19 << 26) | ((BO) << 21) | ((BI) << 16) | (528 << 1) | ((LINK) & 1)) 39#define BUILD_B(TARGET, LINK) \ 40 ((18 << 26) | (((TARGET) & 0x00FFFFFF) << 2) | ((LINK) & 1)) 41 42// Pseudo-ops 43#define BUILD_LIS(RD,IMM16) BUILD_ADDIS(RD,0,IMM16) 44#define BUILD_SLDI(RD,RS,IMM6) BUILD_RLDICR(RD,RS,IMM6,63-IMM6) 45#define BUILD_MTCTR(RS) BUILD_MTSPR(RS,9) 46#define BUILD_BCTR(LINK) BUILD_BCCTRx(20,0,LINK) 47 48static void EmitBranchToAt(uint64_t At, uint64_t To, bool isCall, bool is64Bit){ 49 intptr_t Offset = ((intptr_t)To - (intptr_t)At) >> 2; 50 unsigned *AtI = (unsigned*)(intptr_t)At; 51 52 if (Offset >= -(1 << 23) && Offset < (1 << 23)) { // In range? 53 AtI[0] = BUILD_B(Offset, isCall); // b/bl target 54 } else if (!is64Bit) { 55 AtI[0] = BUILD_LIS(12, To >> 16); // lis r12, hi16(address) 56 AtI[1] = BUILD_ORI(12, 12, To); // ori r12, r12, lo16(address) 57 AtI[2] = BUILD_MTCTR(12); // mtctr r12 58 AtI[3] = BUILD_BCTR(isCall); // bctr/bctrl 59 } else { 60 AtI[0] = BUILD_LIS(12, To >> 48); // lis r12, hi16(address) 61 AtI[1] = BUILD_ORI(12, 12, To >> 32); // ori r12, r12, lo16(address) 62 AtI[2] = BUILD_SLDI(12, 12, 32); // sldi r12, r12, 32 63 AtI[3] = BUILD_ORIS(12, 12, To >> 16); // oris r12, r12, hi16(address) 64 AtI[4] = BUILD_ORI(12, 12, To); // ori r12, r12, lo16(address) 65 AtI[5] = BUILD_MTCTR(12); // mtctr r12 66 AtI[6] = BUILD_BCTR(isCall); // bctr/bctrl 67 } 68} 69 70extern "C" void PPC32CompilationCallback(); 71extern "C" void PPC64CompilationCallback(); 72 73#if (defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)) && \ 74 !(defined(__ppc64__) || defined(__FreeBSD__)) 75// CompilationCallback stub - We can't use a C function with inline assembly in 76// it, because we the prolog/epilog inserted by GCC won't work for us. Instead, 77// write our own wrapper, which does things our way, so we have complete control 78// over register saving and restoring. 79asm( 80 ".text\n" 81 ".align 2\n" 82 ".globl _PPC32CompilationCallback\n" 83"_PPC32CompilationCallback:\n" 84 // Make space for 8 ints r[3-10] and 13 doubles f[1-13] and the 85 // FIXME: need to save v[0-19] for altivec? 86 // FIXME: could shrink frame 87 // Set up a proper stack frame 88 // FIXME Layout 89 // PowerPC64 ABI linkage - 24 bytes 90 // parameters - 32 bytes 91 // 13 double registers - 104 bytes 92 // 8 int registers - 32 bytes 93 "mflr r0\n" 94 "stw r0, 8(r1)\n" 95 "stwu r1, -208(r1)\n" 96 // Save all int arg registers 97 "stw r10, 204(r1)\n" "stw r9, 200(r1)\n" 98 "stw r8, 196(r1)\n" "stw r7, 192(r1)\n" 99 "stw r6, 188(r1)\n" "stw r5, 184(r1)\n" 100 "stw r4, 180(r1)\n" "stw r3, 176(r1)\n" 101 // Save all call-clobbered FP regs. 102 "stfd f13, 168(r1)\n" "stfd f12, 160(r1)\n" 103 "stfd f11, 152(r1)\n" "stfd f10, 144(r1)\n" 104 "stfd f9, 136(r1)\n" "stfd f8, 128(r1)\n" 105 "stfd f7, 120(r1)\n" "stfd f6, 112(r1)\n" 106 "stfd f5, 104(r1)\n" "stfd f4, 96(r1)\n" 107 "stfd f3, 88(r1)\n" "stfd f2, 80(r1)\n" 108 "stfd f1, 72(r1)\n" 109 // Arguments to Compilation Callback: 110 // r3 - our lr (address of the call instruction in stub plus 4) 111 // r4 - stub's lr (address of instruction that called the stub plus 4) 112 // r5 - is64Bit - always 0. 113 "mr r3, r0\n" 114 "lwz r2, 208(r1)\n" // stub's frame 115 "lwz r4, 8(r2)\n" // stub's lr 116 "li r5, 0\n" // 0 == 32 bit 117 "bl _PPCCompilationCallbackC\n" 118 "mtctr r3\n" 119 // Restore all int arg registers 120 "lwz r10, 204(r1)\n" "lwz r9, 200(r1)\n" 121 "lwz r8, 196(r1)\n" "lwz r7, 192(r1)\n" 122 "lwz r6, 188(r1)\n" "lwz r5, 184(r1)\n" 123 "lwz r4, 180(r1)\n" "lwz r3, 176(r1)\n" 124 // Restore all FP arg registers 125 "lfd f13, 168(r1)\n" "lfd f12, 160(r1)\n" 126 "lfd f11, 152(r1)\n" "lfd f10, 144(r1)\n" 127 "lfd f9, 136(r1)\n" "lfd f8, 128(r1)\n" 128 "lfd f7, 120(r1)\n" "lfd f6, 112(r1)\n" 129 "lfd f5, 104(r1)\n" "lfd f4, 96(r1)\n" 130 "lfd f3, 88(r1)\n" "lfd f2, 80(r1)\n" 131 "lfd f1, 72(r1)\n" 132 // Pop 3 frames off the stack and branch to target 133 "lwz r1, 208(r1)\n" 134 "lwz r2, 8(r1)\n" 135 "mtlr r2\n" 136 "bctr\n" 137 ); 138 139#elif defined(__PPC__) && !defined(__ppc64__) 140// Linux & FreeBSD / PPC 32 support 141 142// CompilationCallback stub - We can't use a C function with inline assembly in 143// it, because we the prolog/epilog inserted by GCC won't work for us. Instead, 144// write our own wrapper, which does things our way, so we have complete control 145// over register saving and restoring. 146asm( 147 ".text\n" 148 ".align 2\n" 149 ".globl PPC32CompilationCallback\n" 150"PPC32CompilationCallback:\n" 151 // Make space for 8 ints r[3-10] and 8 doubles f[1-8] and the 152 // FIXME: need to save v[0-19] for altivec? 153 // FIXME: could shrink frame 154 // Set up a proper stack frame 155 // FIXME Layout 156 // 8 double registers - 64 bytes 157 // 8 int registers - 32 bytes 158 "mflr 0\n" 159 "stw 0, 4(1)\n" 160 "stwu 1, -104(1)\n" 161 // Save all int arg registers 162 "stw 10, 100(1)\n" "stw 9, 96(1)\n" 163 "stw 8, 92(1)\n" "stw 7, 88(1)\n" 164 "stw 6, 84(1)\n" "stw 5, 80(1)\n" 165 "stw 4, 76(1)\n" "stw 3, 72(1)\n" 166 // Save all call-clobbered FP regs. 167 "stfd 8, 64(1)\n" 168 "stfd 7, 56(1)\n" "stfd 6, 48(1)\n" 169 "stfd 5, 40(1)\n" "stfd 4, 32(1)\n" 170 "stfd 3, 24(1)\n" "stfd 2, 16(1)\n" 171 "stfd 1, 8(1)\n" 172 // Arguments to Compilation Callback: 173 // r3 - our lr (address of the call instruction in stub plus 4) 174 // r4 - stub's lr (address of instruction that called the stub plus 4) 175 // r5 - is64Bit - always 0. 176 "mr 3, 0\n" 177 "lwz 5, 104(1)\n" // stub's frame 178 "lwz 4, 4(5)\n" // stub's lr 179 "li 5, 0\n" // 0 == 32 bit 180 "bl PPCCompilationCallbackC\n" 181 "mtctr 3\n" 182 // Restore all int arg registers 183 "lwz 10, 100(1)\n" "lwz 9, 96(1)\n" 184 "lwz 8, 92(1)\n" "lwz 7, 88(1)\n" 185 "lwz 6, 84(1)\n" "lwz 5, 80(1)\n" 186 "lwz 4, 76(1)\n" "lwz 3, 72(1)\n" 187 // Restore all FP arg registers 188 "lfd 8, 64(1)\n" 189 "lfd 7, 56(1)\n" "lfd 6, 48(1)\n" 190 "lfd 5, 40(1)\n" "lfd 4, 32(1)\n" 191 "lfd 3, 24(1)\n" "lfd 2, 16(1)\n" 192 "lfd 1, 8(1)\n" 193 // Pop 3 frames off the stack and branch to target 194 "lwz 1, 104(1)\n" 195 "lwz 0, 4(1)\n" 196 "mtlr 0\n" 197 "bctr\n" 198 ); 199#else 200void PPC32CompilationCallback() { 201 assert(0 && "This is not a power pc, you can't execute this!"); 202 abort(); 203} 204#endif 205 206#if (defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)) && \ 207 defined(__ppc64__) 208asm( 209 ".text\n" 210 ".align 2\n" 211 ".globl _PPC64CompilationCallback\n" 212"_PPC64CompilationCallback:\n" 213 // Make space for 8 ints r[3-10] and 13 doubles f[1-13] and the 214 // FIXME: need to save v[0-19] for altivec? 215 // Set up a proper stack frame 216 // Layout 217 // PowerPC64 ABI linkage - 48 bytes 218 // parameters - 64 bytes 219 // 13 double registers - 104 bytes 220 // 8 int registers - 64 bytes 221 "mflr r0\n" 222 "std r0, 16(r1)\n" 223 "stdu r1, -280(r1)\n" 224 // Save all int arg registers 225 "std r10, 272(r1)\n" "std r9, 264(r1)\n" 226 "std r8, 256(r1)\n" "std r7, 248(r1)\n" 227 "std r6, 240(r1)\n" "std r5, 232(r1)\n" 228 "std r4, 224(r1)\n" "std r3, 216(r1)\n" 229 // Save all call-clobbered FP regs. 230 "stfd f13, 208(r1)\n" "stfd f12, 200(r1)\n" 231 "stfd f11, 192(r1)\n" "stfd f10, 184(r1)\n" 232 "stfd f9, 176(r1)\n" "stfd f8, 168(r1)\n" 233 "stfd f7, 160(r1)\n" "stfd f6, 152(r1)\n" 234 "stfd f5, 144(r1)\n" "stfd f4, 136(r1)\n" 235 "stfd f3, 128(r1)\n" "stfd f2, 120(r1)\n" 236 "stfd f1, 112(r1)\n" 237 // Arguments to Compilation Callback: 238 // r3 - our lr (address of the call instruction in stub plus 4) 239 // r4 - stub's lr (address of instruction that called the stub plus 4) 240 // r5 - is64Bit - always 1. 241 "mr r3, r0\n" 242 "ld r2, 280(r1)\n" // stub's frame 243 "ld r4, 16(r2)\n" // stub's lr 244 "li r5, 1\n" // 1 == 64 bit 245 "bl _PPCCompilationCallbackC\n" 246 "mtctr r3\n" 247 // Restore all int arg registers 248 "ld r10, 272(r1)\n" "ld r9, 264(r1)\n" 249 "ld r8, 256(r1)\n" "ld r7, 248(r1)\n" 250 "ld r6, 240(r1)\n" "ld r5, 232(r1)\n" 251 "ld r4, 224(r1)\n" "ld r3, 216(r1)\n" 252 // Restore all FP arg registers 253 "lfd f13, 208(r1)\n" "lfd f12, 200(r1)\n" 254 "lfd f11, 192(r1)\n" "lfd f10, 184(r1)\n" 255 "lfd f9, 176(r1)\n" "lfd f8, 168(r1)\n" 256 "lfd f7, 160(r1)\n" "lfd f6, 152(r1)\n" 257 "lfd f5, 144(r1)\n" "lfd f4, 136(r1)\n" 258 "lfd f3, 128(r1)\n" "lfd f2, 120(r1)\n" 259 "lfd f1, 112(r1)\n" 260 // Pop 3 frames off the stack and branch to target 261 "ld r1, 280(r1)\n" 262 "ld r2, 16(r1)\n" 263 "mtlr r2\n" 264 "bctr\n" 265 ); 266#else 267void PPC64CompilationCallback() { 268 assert(0 && "This is not a power pc, you can't execute this!"); 269 abort(); 270} 271#endif 272 273extern "C" void *PPCCompilationCallbackC(unsigned *StubCallAddrPlus4, 274 unsigned *OrigCallAddrPlus4, 275 bool is64Bit) { 276 // Adjust the pointer to the address of the call instruction in the stub 277 // emitted by emitFunctionStub, rather than the instruction after it. 278 unsigned *StubCallAddr = StubCallAddrPlus4 - 1; 279 unsigned *OrigCallAddr = OrigCallAddrPlus4 - 1; 280 281 void *Target = JITCompilerFunction(StubCallAddr); 282 283 // Check to see if *OrigCallAddr is a 'bl' instruction, and if we can rewrite 284 // it to branch directly to the destination. If so, rewrite it so it does not 285 // need to go through the stub anymore. 286 unsigned OrigCallInst = *OrigCallAddr; 287 if ((OrigCallInst >> 26) == 18) { // Direct call. 288 intptr_t Offset = ((intptr_t)Target - (intptr_t)OrigCallAddr) >> 2; 289 290 if (Offset >= -(1 << 23) && Offset < (1 << 23)) { // In range? 291 // Clear the original target out. 292 OrigCallInst &= (63 << 26) | 3; 293 // Fill in the new target. 294 OrigCallInst |= (Offset & ((1 << 24)-1)) << 2; 295 // Replace the call. 296 *OrigCallAddr = OrigCallInst; 297 } 298 } 299 300 // Assert that we are coming from a stub that was created with our 301 // emitFunctionStub. 302 if ((*StubCallAddr >> 26) == 18) 303 StubCallAddr -= 3; 304 else { 305 assert((*StubCallAddr >> 26) == 19 && "Call in stub is not indirect!"); 306 StubCallAddr -= is64Bit ? 9 : 6; 307 } 308 309 // Rewrite the stub with an unconditional branch to the target, for any users 310 // who took the address of the stub. 311 EmitBranchToAt((intptr_t)StubCallAddr, (intptr_t)Target, false, is64Bit); 312 313 // Put the address of the target function to call and the address to return to 314 // after calling the target function in a place that is easy to get on the 315 // stack after we restore all regs. 316 return Target; 317} 318 319 320 321TargetJITInfo::LazyResolverFn 322PPCJITInfo::getLazyResolverFunction(JITCompilerFn Fn) { 323 JITCompilerFunction = Fn; 324 return is64Bit ? PPC64CompilationCallback : PPC32CompilationCallback; 325} 326 327#if (defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)) && \ 328defined(__APPLE__) 329extern "C" void sys_icache_invalidate(const void *Addr, size_t len); 330#endif 331 332void *PPCJITInfo::emitFunctionStub(const Function* F, void *Fn, 333 MachineCodeEmitter &MCE) { 334 // If this is just a call to an external function, emit a branch instead of a 335 // call. The code is the same except for one bit of the last instruction. 336 if (Fn != (void*)(intptr_t)PPC32CompilationCallback && 337 Fn != (void*)(intptr_t)PPC64CompilationCallback) { 338 MCE.startFunctionStub(F, 7*4); 339 intptr_t Addr = (intptr_t)MCE.getCurrentPCValue(); 340 MCE.emitWordBE(0); 341 MCE.emitWordBE(0); 342 MCE.emitWordBE(0); 343 MCE.emitWordBE(0); 344 MCE.emitWordBE(0); 345 MCE.emitWordBE(0); 346 MCE.emitWordBE(0); 347 EmitBranchToAt(Addr, (intptr_t)Fn, false, is64Bit); 348 sys::Memory::InvalidateInstructionCache((void*)Addr, 7*4); 349 return MCE.finishFunctionStub(F); 350 } 351 352 MCE.startFunctionStub(F, 10*4); 353 intptr_t Addr = (intptr_t)MCE.getCurrentPCValue(); 354 if (is64Bit) { 355 MCE.emitWordBE(0xf821ffb1); // stdu r1,-80(r1) 356 MCE.emitWordBE(0x7d6802a6); // mflr r11 357 MCE.emitWordBE(0xf9610060); // std r11, 96(r1) 358 } else if (TM.getSubtargetImpl()->isMachoABI()){ 359 MCE.emitWordBE(0x9421ffe0); // stwu r1,-32(r1) 360 MCE.emitWordBE(0x7d6802a6); // mflr r11 361 MCE.emitWordBE(0x91610028); // stw r11, 40(r1) 362 } else { 363 MCE.emitWordBE(0x9421ffe0); // stwu r1,-32(r1) 364 MCE.emitWordBE(0x7d6802a6); // mflr r11 365 MCE.emitWordBE(0x91610024); // stw r11, 36(r1) 366 } 367 intptr_t BranchAddr = (intptr_t)MCE.getCurrentPCValue(); 368 MCE.emitWordBE(0); 369 MCE.emitWordBE(0); 370 MCE.emitWordBE(0); 371 MCE.emitWordBE(0); 372 MCE.emitWordBE(0); 373 MCE.emitWordBE(0); 374 MCE.emitWordBE(0); 375 EmitBranchToAt(BranchAddr, (intptr_t)Fn, true, is64Bit); 376 sys::Memory::InvalidateInstructionCache((void*)Addr, 10*4); 377 return MCE.finishFunctionStub(F); 378} 379 380 381void PPCJITInfo::relocate(void *Function, MachineRelocation *MR, 382 unsigned NumRelocs, unsigned char* GOTBase) { 383 for (unsigned i = 0; i != NumRelocs; ++i, ++MR) { 384 unsigned *RelocPos = (unsigned*)Function + MR->getMachineCodeOffset()/4; 385 intptr_t ResultPtr = (intptr_t)MR->getResultPointer(); 386 switch ((PPC::RelocationType)MR->getRelocationType()) { 387 default: assert(0 && "Unknown relocation type!"); 388 case PPC::reloc_pcrel_bx: 389 // PC-relative relocation for b and bl instructions. 390 ResultPtr = (ResultPtr-(intptr_t)RelocPos) >> 2; 391 assert(ResultPtr >= -(1 << 23) && ResultPtr < (1 << 23) && 392 "Relocation out of range!"); 393 *RelocPos |= (ResultPtr & ((1 << 24)-1)) << 2; 394 break; 395 case PPC::reloc_pcrel_bcx: 396 // PC-relative relocation for BLT,BLE,BEQ,BGE,BGT,BNE, or other 397 // bcx instructions. 398 ResultPtr = (ResultPtr-(intptr_t)RelocPos) >> 2; 399 assert(ResultPtr >= -(1 << 13) && ResultPtr < (1 << 13) && 400 "Relocation out of range!"); 401 *RelocPos |= (ResultPtr & ((1 << 14)-1)) << 2; 402 break; 403 case PPC::reloc_absolute_high: // high bits of ref -> low 16 of instr 404 case PPC::reloc_absolute_low: { // low bits of ref -> low 16 of instr 405 ResultPtr += MR->getConstantVal(); 406 407 // If this is a high-part access, get the high-part. 408 if (MR->getRelocationType() == PPC::reloc_absolute_high) { 409 // If the low part will have a carry (really a borrow) from the low 410 // 16-bits into the high 16, add a bit to borrow from. 411 if (((int)ResultPtr << 16) < 0) 412 ResultPtr += 1 << 16; 413 ResultPtr >>= 16; 414 } 415 416 // Do the addition then mask, so the addition does not overflow the 16-bit 417 // immediate section of the instruction. 418 unsigned LowBits = (*RelocPos + ResultPtr) & 65535; 419 unsigned HighBits = *RelocPos & ~65535; 420 *RelocPos = LowBits | HighBits; // Slam into low 16-bits 421 break; 422 } 423 case PPC::reloc_absolute_low_ix: { // low bits of ref -> low 14 of instr 424 ResultPtr += MR->getConstantVal(); 425 // Do the addition then mask, so the addition does not overflow the 16-bit 426 // immediate section of the instruction. 427 unsigned LowBits = (*RelocPos + ResultPtr) & 0xFFFC; 428 unsigned HighBits = *RelocPos & 0xFFFF0003; 429 *RelocPos = LowBits | HighBits; // Slam into low 14-bits. 430 break; 431 } 432 } 433 } 434} 435 436void PPCJITInfo::replaceMachineCodeForFunction(void *Old, void *New) { 437 EmitBranchToAt((intptr_t)Old, (intptr_t)New, false, is64Bit); 438} 439