SparcInstrInfo.cpp revision 746ad69e088176819981b4b2c5ac8dcd49f5e60e
17c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner//===- SparcInstrInfo.cpp - Sparc Instruction Information -------*- C++ -*-===// 2b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman// 3e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke// The LLVM Compiler Infrastructure 4e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 7b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman// 8e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke//===----------------------------------------------------------------------===// 9e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke// 107c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner// This file contains the Sparc implementation of the TargetInstrInfo class. 11e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke// 12e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke//===----------------------------------------------------------------------===// 13e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke 147c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner#include "SparcInstrInfo.h" 15d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson#include "SparcSubtarget.h" 167c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner#include "Sparc.h" 17718cb665ca6ce2bc4d8e8479f46a45db91b49f86Owen Anderson#include "llvm/ADT/STLExtras.h" 18d68a07650cdb2e18f18f362ba533459aa10e01b6Dan Gohman#include "llvm/ADT/SmallVector.h" 19e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke#include "llvm/CodeGen/MachineInstrBuilder.h" 20db486a6d5311944f61b92db9f6074944dbbdb242Chris Lattner#include "llvm/CodeGen/MachineRegisterInfo.h" 21c25e7581b9b8088910da31702d4ca21c4734c6d7Torok Edwin#include "llvm/Support/ErrorHandling.h" 227c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner#include "SparcGenInstrInfo.inc" 23db486a6d5311944f61b92db9f6074944dbbdb242Chris Lattner#include "SparcMachineFunctionInfo.h" 241ddf475b6a3d748427546ab8f65a712c8eea3a0fChris Lattnerusing namespace llvm; 25e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke 267c90f73a1b06040d971a3dd95a491031ae6238d5Chris LattnerSparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST) 27641055225092833197efe8e5bce01d50bcf1daaeChris Lattner : TargetInstrInfoImpl(SparcInsts, array_lengthof(SparcInsts)), 28d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson RI(ST, *this), Subtarget(ST) { 29e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke} 30e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke 3169d39091fe2af94d1ceebca526eabede98831a65Chris Lattnerstatic bool isZeroImm(const MachineOperand &op) { 32d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman return op.isImm() && op.getImm() == 0; 334658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke} 344658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke 351d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner/// Return true if the instruction is a register to register move and 361d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner/// leave the source and dest operands in the passed parameters. 371d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner/// 387c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattnerbool SparcInstrInfo::isMoveInstr(const MachineInstr &MI, 3904ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng unsigned &SrcReg, unsigned &DstReg, 4004ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng unsigned &SrcSR, unsigned &DstSR) const { 4104ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng SrcSR = DstSR = 0; // No sub-registers. 4204ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng 434658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke // We look for 3 kinds of patterns here: 444658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke // or with G0 or 0 454658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke // add with G0 or 0 464658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke // fmovs or FpMOVD (pseudo double move). 477c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner if (MI.getOpcode() == SP::ORrr || MI.getOpcode() == SP::ADDrr) { 487c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner if (MI.getOperand(1).getReg() == SP::G0) { 494658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke DstReg = MI.getOperand(0).getReg(); 504658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke SrcReg = MI.getOperand(2).getReg(); 514658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke return true; 527c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner } else if (MI.getOperand(2).getReg() == SP::G0) { 534658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke DstReg = MI.getOperand(0).getReg(); 544658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke SrcReg = MI.getOperand(1).getReg(); 554658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke return true; 564658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke } 577c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner } else if ((MI.getOpcode() == SP::ORri || MI.getOpcode() == SP::ADDri) && 58d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isReg()) { 5969d39091fe2af94d1ceebca526eabede98831a65Chris Lattner DstReg = MI.getOperand(0).getReg(); 6069d39091fe2af94d1ceebca526eabede98831a65Chris Lattner SrcReg = MI.getOperand(1).getReg(); 6169d39091fe2af94d1ceebca526eabede98831a65Chris Lattner return true; 627c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner } else if (MI.getOpcode() == SP::FMOVS || MI.getOpcode() == SP::FpMOVD || 637c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner MI.getOpcode() == SP::FMOVD) { 641d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner SrcReg = MI.getOperand(1).getReg(); 651d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner DstReg = MI.getOperand(0).getReg(); 661d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner return true; 671d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner } 681d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner return false; 691d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner} 705ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner 715ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// isLoadFromStackSlot - If the specified machine instruction is a direct 725ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// load from a stack slot, return the virtual or physical register number of 735ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// the destination along with the FrameIndex of the loaded stack slot. If 745ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// not, return 0. This predicate must return 0 if the instruction has 755ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// any side effects other than loading from the stack slot. 76cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohmanunsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 777c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner int &FrameIndex) const { 787c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner if (MI->getOpcode() == SP::LDri || 797c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner MI->getOpcode() == SP::LDFri || 807c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner MI->getOpcode() == SP::LDDFri) { 81d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() && 829a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner MI->getOperand(2).getImm() == 0) { 838aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner FrameIndex = MI->getOperand(1).getIndex(); 845ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner return MI->getOperand(0).getReg(); 855ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner } 865ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner } 875ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner return 0; 885ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner} 895ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner 905ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// isStoreToStackSlot - If the specified machine instruction is a direct 915ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// store to a stack slot, return the virtual or physical register number of 925ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// the source reg along with the FrameIndex of the loaded stack slot. If 935ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// not, return 0. This predicate must return 0 if the instruction has 945ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// any side effects other than storing to the stack slot. 95cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohmanunsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 967c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner int &FrameIndex) const { 977c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner if (MI->getOpcode() == SP::STri || 987c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner MI->getOpcode() == SP::STFri || 997c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner MI->getOpcode() == SP::STDFri) { 100d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() && 1019a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner MI->getOperand(1).getImm() == 0) { 1028aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner FrameIndex = MI->getOperand(0).getIndex(); 1035ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner return MI->getOperand(2).getReg(); 1045ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner } 1055ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner } 1065ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner return 0; 1075ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner} 108e87146ace88464be4ea4f8869830642c40178f1fChris Lattner 1096ae3626a4fda14e6250ac8d8ff487efb8952cdf7Evan Chengunsigned 1106ae3626a4fda14e6250ac8d8ff487efb8952cdf7Evan ChengSparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, 1116ae3626a4fda14e6250ac8d8ff487efb8952cdf7Evan Cheng MachineBasicBlock *FBB, 11244eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson const SmallVectorImpl<MachineOperand> &Cond)const{ 113d552eee4a05789e80ef3298df473edb888471302Dale Johannesen // FIXME this should probably take a DebugLoc argument 114c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc dl; 115e87146ace88464be4ea4f8869830642c40178f1fChris Lattner // Can only insert uncond branches so far. 116e87146ace88464be4ea4f8869830642c40178f1fChris Lattner assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!"); 117d552eee4a05789e80ef3298df473edb888471302Dale Johannesen BuildMI(&MBB, dl, get(SP::BA)).addMBB(TBB); 1186ae3626a4fda14e6250ac8d8ff487efb8952cdf7Evan Cheng return 1; 1193d7d39ab1549f5ab7a929ec18a3e6481862cf247Rafael Espindola} 120d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson 121940f83e772ca2007d62faffc83094bd7e8da6401Owen Andersonbool SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB, 122d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling MachineBasicBlock::iterator I, 123d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling unsigned DestReg, unsigned SrcReg, 124d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling const TargetRegisterClass *DestRC, 125d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling const TargetRegisterClass *SrcRC) const { 126d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson if (DestRC != SrcRC) { 127940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson // Not yet supported! 128940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson return false; 129d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } 130d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson 131c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 132d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling if (I != MBB.end()) DL = I->getDebugLoc(); 133d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling 134d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson if (DestRC == SP::IntRegsRegisterClass) 135d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg); 136d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson else if (DestRC == SP::FPRegsRegisterClass) 137d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg).addReg(SrcReg); 138d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson else if (DestRC == SP::DFPRegsRegisterClass) 139d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg) 140d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson .addReg(SrcReg); 141d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson else 142940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson // Can't copy this register 143940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson return false; 144940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson 145940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson return true; 146d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson} 147f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 148f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersonvoid SparcInstrInfo:: 149f6372aa1cc568df19da7c5023e83c75aa9404a07Owen AndersonstoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 150f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned SrcReg, bool isKill, int FI, 151746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 152746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 153c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 154d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling if (I != MBB.end()) DL = I->getDebugLoc(); 155d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling 156f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // On the order of operands here: think "[FrameIdx + 0] = SrcReg". 157f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (RC == SP::IntRegsRegisterClass) 158d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0) 159587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(SrcReg, getKillRegState(isKill)); 160f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else if (RC == SP::FPRegsRegisterClass) 161d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0) 162587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(SrcReg, getKillRegState(isKill)); 163f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else if (RC == SP::DFPRegsRegisterClass) 164d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0) 165587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4Bill Wendling .addReg(SrcReg, getKillRegState(isKill)); 166f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else 167c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Can't store this register to stack slot"); 168f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 169f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 170f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersonvoid SparcInstrInfo:: 171f6372aa1cc568df19da7c5023e83c75aa9404a07Owen AndersonloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 172f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned DestReg, int FI, 173746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterClass *RC, 174746ad69e088176819981b4b2c5ac8dcd49f5e60eEvan Cheng const TargetRegisterInfo *TRI) const { 175c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc DL; 176d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling if (I != MBB.end()) DL = I->getDebugLoc(); 177d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling 178f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (RC == SP::IntRegsRegisterClass) 179d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0); 180f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else if (RC == SP::FPRegsRegisterClass) 181d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0); 182f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else if (RC == SP::DFPRegsRegisterClass) 183d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0); 184f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else 185c23197a26f34f559ea9797de51e187087c039c42Torok Edwin llvm_unreachable("Can't load this register from stack slot"); 186f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 187f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 188c54baa2d43730f1804acfb4f4e738fba72f966bdDan GohmanMachineInstr *SparcInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 189c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* MI, 1908e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman const SmallVectorImpl<unsigned> &Ops, 191c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman int FI) const { 19243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if (Ops.size() != 1) return NULL; 19343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 19443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned OpNum = Ops[0]; 19543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson bool isFloat = false; 19643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson MachineInstr *NewMI = NULL; 19743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson switch (MI->getOpcode()) { 19843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson case SP::ORrr: 199d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman if (MI->getOperand(1).isReg() && MI->getOperand(1).getReg() == SP::G0&& 200d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI->getOperand(0).isReg() && MI->getOperand(2).isReg()) { 20143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if (OpNum == 0) // COPY -> STORE 202d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMI = BuildMI(MF, MI->getDebugLoc(), get(SP::STri)) 203d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling .addFrameIndex(FI) 204d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling .addImm(0) 205d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling .addReg(MI->getOperand(2).getReg()); 20643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson else // COPY -> LOAD 207d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMI = BuildMI(MF, MI->getDebugLoc(), get(SP::LDri), 208d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling MI->getOperand(0).getReg()) 209d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling .addFrameIndex(FI) 210d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling .addImm(0); 21143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 21243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson break; 21343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson case SP::FMOVS: 21443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson isFloat = true; 21543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson // FALLTHROUGH 21643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson case SP::FMOVD: 2179f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng if (OpNum == 0) { // COPY -> STORE 2189f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 2199f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng bool isKill = MI->getOperand(1).isKill(); 2202578ba26e72e36dde64be0f52a2788480aad3378Evan Cheng bool isUndef = MI->getOperand(1).isUndef(); 221d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMI = BuildMI(MF, MI->getDebugLoc(), 222d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling get(isFloat ? SP::STFri : SP::STDFri)) 223d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling .addFrameIndex(FI) 224d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling .addImm(0) 2252578ba26e72e36dde64be0f52a2788480aad3378Evan Cheng .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef)); 2269f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng } else { // COPY -> LOAD 2279f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 2289f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng bool isDead = MI->getOperand(0).isDead(); 2292578ba26e72e36dde64be0f52a2788480aad3378Evan Cheng bool isUndef = MI->getOperand(0).isUndef(); 230d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMI = BuildMI(MF, MI->getDebugLoc(), 231d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling get(isFloat ? SP::LDFri : SP::LDDFri)) 2322578ba26e72e36dde64be0f52a2788480aad3378Evan Cheng .addReg(DstReg, RegState::Define | 2332578ba26e72e36dde64be0f52a2788480aad3378Evan Cheng getDeadRegState(isDead) | getUndefRegState(isUndef)) 234d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling .addFrameIndex(FI) 235d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling .addImm(0); 2369f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng } 23743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson break; 23843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 23943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 24043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return NewMI; 2419c5525f4fa177e20077710c980f08e2f8de06e39Duncan Sands} 242db486a6d5311944f61b92db9f6074944dbbdb242Chris Lattner 243db486a6d5311944f61b92db9f6074944dbbdb242Chris Lattnerunsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const 244db486a6d5311944f61b92db9f6074944dbbdb242Chris Lattner{ 245db486a6d5311944f61b92db9f6074944dbbdb242Chris Lattner SparcMachineFunctionInfo *SparcFI = MF->getInfo<SparcMachineFunctionInfo>(); 246db486a6d5311944f61b92db9f6074944dbbdb242Chris Lattner unsigned GlobalBaseReg = SparcFI->getGlobalBaseReg(); 247db486a6d5311944f61b92db9f6074944dbbdb242Chris Lattner if (GlobalBaseReg != 0) 248db486a6d5311944f61b92db9f6074944dbbdb242Chris Lattner return GlobalBaseReg; 249db486a6d5311944f61b92db9f6074944dbbdb242Chris Lattner 250db486a6d5311944f61b92db9f6074944dbbdb242Chris Lattner // Insert the set of GlobalBaseReg into the first MBB of the function 251db486a6d5311944f61b92db9f6074944dbbdb242Chris Lattner MachineBasicBlock &FirstMBB = MF->front(); 252db486a6d5311944f61b92db9f6074944dbbdb242Chris Lattner MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 253db486a6d5311944f61b92db9f6074944dbbdb242Chris Lattner MachineRegisterInfo &RegInfo = MF->getRegInfo(); 254db486a6d5311944f61b92db9f6074944dbbdb242Chris Lattner 255db486a6d5311944f61b92db9f6074944dbbdb242Chris Lattner GlobalBaseReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 256db486a6d5311944f61b92db9f6074944dbbdb242Chris Lattner 257db486a6d5311944f61b92db9f6074944dbbdb242Chris Lattner 258c7f3ace20c325521c68335a1689645b43b06ddf0Chris Lattner DebugLoc dl; 259db486a6d5311944f61b92db9f6074944dbbdb242Chris Lattner 260db486a6d5311944f61b92db9f6074944dbbdb242Chris Lattner BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg); 261db486a6d5311944f61b92db9f6074944dbbdb242Chris Lattner SparcFI->setGlobalBaseReg(GlobalBaseReg); 262db486a6d5311944f61b92db9f6074944dbbdb242Chris Lattner return GlobalBaseReg; 263db486a6d5311944f61b92db9f6074944dbbdb242Chris Lattner} 264