SparcInstrInfo.cpp revision cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2
17c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner//===- SparcInstrInfo.cpp - Sparc Instruction Information -------*- C++ -*-===// 2b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman// 3e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke// The LLVM Compiler Infrastructure 4e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 7b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman// 8e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke//===----------------------------------------------------------------------===// 9e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke// 107c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner// This file contains the Sparc implementation of the TargetInstrInfo class. 11e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke// 12e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke//===----------------------------------------------------------------------===// 13e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke 147c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner#include "SparcInstrInfo.h" 15d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson#include "SparcSubtarget.h" 167c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner#include "Sparc.h" 17718cb665ca6ce2bc4d8e8479f46a45db91b49f86Owen Anderson#include "llvm/ADT/STLExtras.h" 18e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke#include "llvm/CodeGen/MachineInstrBuilder.h" 197c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner#include "SparcGenInstrInfo.inc" 201ddf475b6a3d748427546ab8f65a712c8eea3a0fChris Lattnerusing namespace llvm; 21e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke 227c90f73a1b06040d971a3dd95a491031ae6238d5Chris LattnerSparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST) 23641055225092833197efe8e5bce01d50bcf1daaeChris Lattner : TargetInstrInfoImpl(SparcInsts, array_lengthof(SparcInsts)), 24d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson RI(ST, *this), Subtarget(ST) { 25e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke} 26e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke 2769d39091fe2af94d1ceebca526eabede98831a65Chris Lattnerstatic bool isZeroImm(const MachineOperand &op) { 28d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman return op.isImm() && op.getImm() == 0; 294658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke} 304658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke 311d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner/// Return true if the instruction is a register to register move and 321d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner/// leave the source and dest operands in the passed parameters. 331d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner/// 347c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattnerbool SparcInstrInfo::isMoveInstr(const MachineInstr &MI, 357c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner unsigned &SrcReg, unsigned &DstReg) const { 364658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke // We look for 3 kinds of patterns here: 374658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke // or with G0 or 0 384658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke // add with G0 or 0 394658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke // fmovs or FpMOVD (pseudo double move). 407c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner if (MI.getOpcode() == SP::ORrr || MI.getOpcode() == SP::ADDrr) { 417c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner if (MI.getOperand(1).getReg() == SP::G0) { 424658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke DstReg = MI.getOperand(0).getReg(); 434658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke SrcReg = MI.getOperand(2).getReg(); 444658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke return true; 457c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner } else if (MI.getOperand(2).getReg() == SP::G0) { 464658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke DstReg = MI.getOperand(0).getReg(); 474658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke SrcReg = MI.getOperand(1).getReg(); 484658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke return true; 494658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke } 507c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner } else if ((MI.getOpcode() == SP::ORri || MI.getOpcode() == SP::ADDri) && 51d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isReg()) { 5269d39091fe2af94d1ceebca526eabede98831a65Chris Lattner DstReg = MI.getOperand(0).getReg(); 5369d39091fe2af94d1ceebca526eabede98831a65Chris Lattner SrcReg = MI.getOperand(1).getReg(); 5469d39091fe2af94d1ceebca526eabede98831a65Chris Lattner return true; 557c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner } else if (MI.getOpcode() == SP::FMOVS || MI.getOpcode() == SP::FpMOVD || 567c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner MI.getOpcode() == SP::FMOVD) { 571d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner SrcReg = MI.getOperand(1).getReg(); 581d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner DstReg = MI.getOperand(0).getReg(); 591d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner return true; 601d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner } 611d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner return false; 621d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner} 635ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner 645ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// isLoadFromStackSlot - If the specified machine instruction is a direct 655ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// load from a stack slot, return the virtual or physical register number of 665ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// the destination along with the FrameIndex of the loaded stack slot. If 675ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// not, return 0. This predicate must return 0 if the instruction has 685ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// any side effects other than loading from the stack slot. 69cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohmanunsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 707c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner int &FrameIndex) const { 717c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner if (MI->getOpcode() == SP::LDri || 727c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner MI->getOpcode() == SP::LDFri || 737c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner MI->getOpcode() == SP::LDDFri) { 74d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() && 759a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner MI->getOperand(2).getImm() == 0) { 768aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner FrameIndex = MI->getOperand(1).getIndex(); 775ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner return MI->getOperand(0).getReg(); 785ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner } 795ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner } 805ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner return 0; 815ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner} 825ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner 835ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// isStoreToStackSlot - If the specified machine instruction is a direct 845ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// store to a stack slot, return the virtual or physical register number of 855ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// the source reg along with the FrameIndex of the loaded stack slot. If 865ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// not, return 0. This predicate must return 0 if the instruction has 875ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// any side effects other than storing to the stack slot. 88cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohmanunsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 897c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner int &FrameIndex) const { 907c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner if (MI->getOpcode() == SP::STri || 917c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner MI->getOpcode() == SP::STFri || 927c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner MI->getOpcode() == SP::STDFri) { 93d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() && 949a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner MI->getOperand(1).getImm() == 0) { 958aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner FrameIndex = MI->getOperand(0).getIndex(); 965ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner return MI->getOperand(2).getReg(); 975ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner } 985ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner } 995ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner return 0; 1005ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner} 101e87146ace88464be4ea4f8869830642c40178f1fChris Lattner 1026ae3626a4fda14e6250ac8d8ff487efb8952cdf7Evan Chengunsigned 1036ae3626a4fda14e6250ac8d8ff487efb8952cdf7Evan ChengSparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, 1046ae3626a4fda14e6250ac8d8ff487efb8952cdf7Evan Cheng MachineBasicBlock *FBB, 10544eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson const SmallVectorImpl<MachineOperand> &Cond)const{ 106e87146ace88464be4ea4f8869830642c40178f1fChris Lattner // Can only insert uncond branches so far. 107e87146ace88464be4ea4f8869830642c40178f1fChris Lattner assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!"); 108c0f64ffab93d11fb27a3b8a0707b77400918a20eEvan Cheng BuildMI(&MBB, get(SP::BA)).addMBB(TBB); 1096ae3626a4fda14e6250ac8d8ff487efb8952cdf7Evan Cheng return 1; 1103d7d39ab1549f5ab7a929ec18a3e6481862cf247Rafael Espindola} 111d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson 112940f83e772ca2007d62faffc83094bd7e8da6401Owen Andersonbool SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB, 113d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson MachineBasicBlock::iterator I, 114d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson unsigned DestReg, unsigned SrcReg, 115d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson const TargetRegisterClass *DestRC, 116d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson const TargetRegisterClass *SrcRC) const { 117d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson if (DestRC != SrcRC) { 118940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson // Not yet supported! 119940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson return false; 120d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } 121d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson 122d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson if (DestRC == SP::IntRegsRegisterClass) 123d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson BuildMI(MBB, I, get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg); 124d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson else if (DestRC == SP::FPRegsRegisterClass) 125d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson BuildMI(MBB, I, get(SP::FMOVS), DestReg).addReg(SrcReg); 126d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson else if (DestRC == SP::DFPRegsRegisterClass) 127d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson BuildMI(MBB, I, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg) 128d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson .addReg(SrcReg); 129d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson else 130940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson // Can't copy this register 131940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson return false; 132940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson 133940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson return true; 134d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson} 135f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 136f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersonvoid SparcInstrInfo:: 137f6372aa1cc568df19da7c5023e83c75aa9404a07Owen AndersonstoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 138f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned SrcReg, bool isKill, int FI, 139f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC) const { 140f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // On the order of operands here: think "[FrameIdx + 0] = SrcReg". 141f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (RC == SP::IntRegsRegisterClass) 142f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson BuildMI(MBB, I, get(SP::STri)).addFrameIndex(FI).addImm(0) 143f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(SrcReg, false, false, isKill); 144f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else if (RC == SP::FPRegsRegisterClass) 145f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson BuildMI(MBB, I, get(SP::STFri)).addFrameIndex(FI).addImm(0) 146f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(SrcReg, false, false, isKill); 147f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else if (RC == SP::DFPRegsRegisterClass) 148f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson BuildMI(MBB, I, get(SP::STDFri)).addFrameIndex(FI).addImm(0) 149f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(SrcReg, false, false, isKill); 150f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else 151f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(0 && "Can't store this register to stack slot"); 152f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 153f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 154f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersonvoid SparcInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, 155f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson bool isKill, 156f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineOperand> &Addr, 157f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC, 158f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineInstr*> &NewMIs) const { 159f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned Opc = 0; 160f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (RC == SP::IntRegsRegisterClass) 161f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = SP::STri; 162f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else if (RC == SP::FPRegsRegisterClass) 163f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = SP::STFri; 164f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else if (RC == SP::DFPRegsRegisterClass) 165f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = SP::STDFri; 166f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else 167f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(0 && "Can't load this register"); 1688e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman MachineInstrBuilder MIB = BuildMI(MF, get(Opc)); 169f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson for (unsigned i = 0, e = Addr.size(); i != e; ++i) { 170f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineOperand &MO = Addr[i]; 171d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman if (MO.isReg()) 172f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MIB.addReg(MO.getReg()); 173d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman else if (MO.isImm()) 174f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MIB.addImm(MO.getImm()); 175f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else { 176d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman assert(MO.isFI()); 177f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MIB.addFrameIndex(MO.getIndex()); 178f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 179f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 180f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MIB.addReg(SrcReg, false, false, isKill); 181f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(MIB); 182f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson return; 183f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 184f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 185f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersonvoid SparcInstrInfo:: 186f6372aa1cc568df19da7c5023e83c75aa9404a07Owen AndersonloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 187f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned DestReg, int FI, 188f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC) const { 189f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (RC == SP::IntRegsRegisterClass) 190f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson BuildMI(MBB, I, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0); 191f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else if (RC == SP::FPRegsRegisterClass) 192f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson BuildMI(MBB, I, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0); 193f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else if (RC == SP::DFPRegsRegisterClass) 194f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson BuildMI(MBB, I, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0); 195f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else 196f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(0 && "Can't load this register from stack slot"); 197f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 198f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 199f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersonvoid SparcInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 200f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineOperand> &Addr, 201f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC, 202f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineInstr*> &NewMIs) const { 203f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned Opc = 0; 204f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (RC == SP::IntRegsRegisterClass) 205f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = SP::LDri; 206f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else if (RC == SP::FPRegsRegisterClass) 207f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = SP::LDFri; 208f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else if (RC == SP::DFPRegsRegisterClass) 209f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = SP::LDDFri; 210f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else 211f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(0 && "Can't load this register"); 2128e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); 213f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson for (unsigned i = 0, e = Addr.size(); i != e; ++i) { 214f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineOperand &MO = Addr[i]; 215d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman if (MO.isReg()) 216f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MIB.addReg(MO.getReg()); 217d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman else if (MO.isImm()) 218f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MIB.addImm(MO.getImm()); 219f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else { 220d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman assert(MO.isFI()); 221f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MIB.addFrameIndex(MO.getIndex()); 222f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 223f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 224f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(MIB); 225f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson return; 226f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 22743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 2285fd79d0560570fed977788a86fa038b898564dfaEvan ChengMachineInstr *SparcInstrInfo::foldMemoryOperand(MachineFunction &MF, 2295fd79d0560570fed977788a86fa038b898564dfaEvan Cheng MachineInstr* MI, 2308e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman const SmallVectorImpl<unsigned> &Ops, 2315fd79d0560570fed977788a86fa038b898564dfaEvan Cheng int FI) const { 23243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if (Ops.size() != 1) return NULL; 23343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 23443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned OpNum = Ops[0]; 23543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson bool isFloat = false; 23643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson MachineInstr *NewMI = NULL; 23743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson switch (MI->getOpcode()) { 23843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson case SP::ORrr: 239d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman if (MI->getOperand(1).isReg() && MI->getOperand(1).getReg() == SP::G0&& 240d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI->getOperand(0).isReg() && MI->getOperand(2).isReg()) { 24143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if (OpNum == 0) // COPY -> STORE 2428e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman NewMI = BuildMI(MF, get(SP::STri)).addFrameIndex(FI).addImm(0) 24343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson .addReg(MI->getOperand(2).getReg()); 24443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson else // COPY -> LOAD 2458e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman NewMI = BuildMI(MF, get(SP::LDri), MI->getOperand(0).getReg()) 24643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson .addFrameIndex(FI).addImm(0); 24743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 24843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson break; 24943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson case SP::FMOVS: 25043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson isFloat = true; 25143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson // FALLTHROUGH 25243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson case SP::FMOVD: 2539f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng if (OpNum == 0) { // COPY -> STORE 2549f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 2559f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng bool isKill = MI->getOperand(1).isKill(); 2568e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman NewMI = BuildMI(MF, get(isFloat ? SP::STFri : SP::STDFri)) 2579f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng .addFrameIndex(FI).addImm(0).addReg(SrcReg, false, false, isKill); 2589f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng } else { // COPY -> LOAD 2599f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 2609f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng bool isDead = MI->getOperand(0).isDead(); 2618e5f2c6f65841542e2a7092553fe42a00048e4c7Dan Gohman NewMI = BuildMI(MF, get(isFloat ? SP::LDFri : SP::LDDFri)) 2629f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng .addReg(DstReg, true, false, false, isDead).addFrameIndex(FI).addImm(0); 2639f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng } 26443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson break; 26543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 26643dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 26743dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return NewMI; 2689c5525f4fa177e20077710c980f08e2f8de06e39Duncan Sands} 269