SparcInstrInfo.cpp revision d552eee4a05789e80ef3298df473edb888471302
17c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner//===- SparcInstrInfo.cpp - Sparc Instruction Information -------*- C++ -*-===// 2b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman// 3e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke// The LLVM Compiler Infrastructure 4e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 7b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0Misha Brukman// 8e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke//===----------------------------------------------------------------------===// 9e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke// 107c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner// This file contains the Sparc implementation of the TargetInstrInfo class. 11e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke// 12e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke//===----------------------------------------------------------------------===// 13e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke 147c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner#include "SparcInstrInfo.h" 15d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson#include "SparcSubtarget.h" 167c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner#include "Sparc.h" 17718cb665ca6ce2bc4d8e8479f46a45db91b49f86Owen Anderson#include "llvm/ADT/STLExtras.h" 18d68a07650cdb2e18f18f362ba533459aa10e01b6Dan Gohman#include "llvm/ADT/SmallVector.h" 19e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke#include "llvm/CodeGen/MachineInstrBuilder.h" 207c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner#include "SparcGenInstrInfo.inc" 211ddf475b6a3d748427546ab8f65a712c8eea3a0fChris Lattnerusing namespace llvm; 22e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke 237c90f73a1b06040d971a3dd95a491031ae6238d5Chris LattnerSparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST) 24641055225092833197efe8e5bce01d50bcf1daaeChris Lattner : TargetInstrInfoImpl(SparcInsts, array_lengthof(SparcInsts)), 25d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson RI(ST, *this), Subtarget(ST) { 26e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke} 27e785e531f4495068ee46cabd926939eec15a565aBrian Gaeke 2869d39091fe2af94d1ceebca526eabede98831a65Chris Lattnerstatic bool isZeroImm(const MachineOperand &op) { 29d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman return op.isImm() && op.getImm() == 0; 304658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke} 314658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke 321d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner/// Return true if the instruction is a register to register move and 331d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner/// leave the source and dest operands in the passed parameters. 341d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner/// 357c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattnerbool SparcInstrInfo::isMoveInstr(const MachineInstr &MI, 3604ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng unsigned &SrcReg, unsigned &DstReg, 3704ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng unsigned &SrcSR, unsigned &DstSR) const { 3804ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng SrcSR = DstSR = 0; // No sub-registers. 3904ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1Evan Cheng 404658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke // We look for 3 kinds of patterns here: 414658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke // or with G0 or 0 424658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke // add with G0 or 0 434658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke // fmovs or FpMOVD (pseudo double move). 447c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner if (MI.getOpcode() == SP::ORrr || MI.getOpcode() == SP::ADDrr) { 457c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner if (MI.getOperand(1).getReg() == SP::G0) { 464658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke DstReg = MI.getOperand(0).getReg(); 474658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke SrcReg = MI.getOperand(2).getReg(); 484658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke return true; 497c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner } else if (MI.getOperand(2).getReg() == SP::G0) { 504658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke DstReg = MI.getOperand(0).getReg(); 514658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke SrcReg = MI.getOperand(1).getReg(); 524658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke return true; 534658ba13a816f54f9a5e36fc6ae6456ed1b8e62dBrian Gaeke } 547c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner } else if ((MI.getOpcode() == SP::ORri || MI.getOpcode() == SP::ADDri) && 55d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isReg()) { 5669d39091fe2af94d1ceebca526eabede98831a65Chris Lattner DstReg = MI.getOperand(0).getReg(); 5769d39091fe2af94d1ceebca526eabede98831a65Chris Lattner SrcReg = MI.getOperand(1).getReg(); 5869d39091fe2af94d1ceebca526eabede98831a65Chris Lattner return true; 597c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner } else if (MI.getOpcode() == SP::FMOVS || MI.getOpcode() == SP::FpMOVD || 607c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner MI.getOpcode() == SP::FMOVD) { 611d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner SrcReg = MI.getOperand(1).getReg(); 621d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner DstReg = MI.getOperand(0).getReg(); 631d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner return true; 641d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner } 651d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner return false; 661d6dc974631a8920a4e5a801a6c7cd4753ae8a8eChris Lattner} 675ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner 685ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// isLoadFromStackSlot - If the specified machine instruction is a direct 695ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// load from a stack slot, return the virtual or physical register number of 705ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// the destination along with the FrameIndex of the loaded stack slot. If 715ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// not, return 0. This predicate must return 0 if the instruction has 725ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// any side effects other than loading from the stack slot. 73cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohmanunsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 747c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner int &FrameIndex) const { 757c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner if (MI->getOpcode() == SP::LDri || 767c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner MI->getOpcode() == SP::LDFri || 777c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner MI->getOpcode() == SP::LDDFri) { 78d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() && 799a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner MI->getOperand(2).getImm() == 0) { 808aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner FrameIndex = MI->getOperand(1).getIndex(); 815ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner return MI->getOperand(0).getReg(); 825ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner } 835ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner } 845ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner return 0; 855ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner} 865ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner 875ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// isStoreToStackSlot - If the specified machine instruction is a direct 885ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// store to a stack slot, return the virtual or physical register number of 895ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// the source reg along with the FrameIndex of the loaded stack slot. If 905ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// not, return 0. This predicate must return 0 if the instruction has 915ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner/// any side effects other than storing to the stack slot. 92cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2Dan Gohmanunsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 937c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner int &FrameIndex) const { 947c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner if (MI->getOpcode() == SP::STri || 957c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner MI->getOpcode() == SP::STFri || 967c90f73a1b06040d971a3dd95a491031ae6238d5Chris Lattner MI->getOpcode() == SP::STDFri) { 97d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() && 989a1ceaedc282f0cae31f2723f4d6c00c7b88fe90Chris Lattner MI->getOperand(1).getImm() == 0) { 998aa797aa51cd4ea1ec6f46f4891a6897944b75b2Chris Lattner FrameIndex = MI->getOperand(0).getIndex(); 1005ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner return MI->getOperand(2).getReg(); 1015ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner } 1025ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner } 1035ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner return 0; 1045ccc7225db0cb4d738045ade8e8c38d5345ac08aChris Lattner} 105e87146ace88464be4ea4f8869830642c40178f1fChris Lattner 1066ae3626a4fda14e6250ac8d8ff487efb8952cdf7Evan Chengunsigned 1076ae3626a4fda14e6250ac8d8ff487efb8952cdf7Evan ChengSparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, 1086ae3626a4fda14e6250ac8d8ff487efb8952cdf7Evan Cheng MachineBasicBlock *FBB, 10944eb65cf58e3ab9b5621ce72256d1621a18aeed7Owen Anderson const SmallVectorImpl<MachineOperand> &Cond)const{ 110d552eee4a05789e80ef3298df473edb888471302Dale Johannesen // FIXME this should probably take a DebugLoc argument 111d552eee4a05789e80ef3298df473edb888471302Dale Johannesen DebugLoc dl = DebugLoc::getUnknownLoc(); 112e87146ace88464be4ea4f8869830642c40178f1fChris Lattner // Can only insert uncond branches so far. 113e87146ace88464be4ea4f8869830642c40178f1fChris Lattner assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!"); 114d552eee4a05789e80ef3298df473edb888471302Dale Johannesen BuildMI(&MBB, dl, get(SP::BA)).addMBB(TBB); 1156ae3626a4fda14e6250ac8d8ff487efb8952cdf7Evan Cheng return 1; 1163d7d39ab1549f5ab7a929ec18a3e6481862cf247Rafael Espindola} 117d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson 118940f83e772ca2007d62faffc83094bd7e8da6401Owen Andersonbool SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB, 119d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling MachineBasicBlock::iterator I, 120d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling unsigned DestReg, unsigned SrcReg, 121d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling const TargetRegisterClass *DestRC, 122d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling const TargetRegisterClass *SrcRC) const { 123d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson if (DestRC != SrcRC) { 124940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson // Not yet supported! 125940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson return false; 126d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson } 127d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson 128d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling DebugLoc DL = DebugLoc::getUnknownLoc(); 129d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling if (I != MBB.end()) DL = I->getDebugLoc(); 130d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling 131d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson if (DestRC == SP::IntRegsRegisterClass) 132d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg); 133d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson else if (DestRC == SP::FPRegsRegisterClass) 134d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg).addReg(SrcReg); 135d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson else if (DestRC == SP::DFPRegsRegisterClass) 136d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg) 137d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson .addReg(SrcReg); 138d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson else 139940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson // Can't copy this register 140940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson return false; 141940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson 142940f83e772ca2007d62faffc83094bd7e8da6401Owen Anderson return true; 143d10fd9791c20fd8368fa0ce94b626b769c6c8ba0Owen Anderson} 144f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 145f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersonvoid SparcInstrInfo:: 146f6372aa1cc568df19da7c5023e83c75aa9404a07Owen AndersonstoreRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 147f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned SrcReg, bool isKill, int FI, 148f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC) const { 149d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling DebugLoc DL = DebugLoc::getUnknownLoc(); 150d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling if (I != MBB.end()) DL = I->getDebugLoc(); 151d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling 152f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson // On the order of operands here: think "[FrameIdx + 0] = SrcReg". 153f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (RC == SP::IntRegsRegisterClass) 154d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0) 155f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(SrcReg, false, false, isKill); 156f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else if (RC == SP::FPRegsRegisterClass) 157d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0) 158f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(SrcReg, false, false, isKill); 159f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else if (RC == SP::DFPRegsRegisterClass) 160d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0) 161f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson .addReg(SrcReg, false, false, isKill); 162f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else 163f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(0 && "Can't store this register to stack slot"); 164f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 165f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 166f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersonvoid SparcInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, 167d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling bool isKill, 168d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling SmallVectorImpl<MachineOperand> &Addr, 169d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling const TargetRegisterClass *RC, 170f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineInstr*> &NewMIs) const { 171f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned Opc = 0; 17221b5541814d57d0a31f353948e4e933dbb1af6a4Dale Johannesen DebugLoc DL = DebugLoc::getUnknownLoc(); 173f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (RC == SP::IntRegsRegisterClass) 174f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = SP::STri; 175f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else if (RC == SP::FPRegsRegisterClass) 176f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = SP::STFri; 177f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else if (RC == SP::DFPRegsRegisterClass) 178f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = SP::STDFri; 179f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else 180f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(0 && "Can't load this register"); 18121b5541814d57d0a31f353948e4e933dbb1af6a4Dale Johannesen MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); 182f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson for (unsigned i = 0, e = Addr.size(); i != e; ++i) { 183f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineOperand &MO = Addr[i]; 184d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman if (MO.isReg()) 185f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MIB.addReg(MO.getReg()); 186d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman else if (MO.isImm()) 187f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MIB.addImm(MO.getImm()); 188f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else { 189d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman assert(MO.isFI()); 190f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MIB.addFrameIndex(MO.getIndex()); 191f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 192f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 193f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MIB.addReg(SrcReg, false, false, isKill); 194f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(MIB); 195f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson return; 196f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 197f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 198f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersonvoid SparcInstrInfo:: 199f6372aa1cc568df19da7c5023e83c75aa9404a07Owen AndersonloadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 200f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned DestReg, int FI, 201f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson const TargetRegisterClass *RC) const { 202d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling DebugLoc DL = DebugLoc::getUnknownLoc(); 203d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling if (I != MBB.end()) DL = I->getDebugLoc(); 204d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling 205f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (RC == SP::IntRegsRegisterClass) 206d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0); 207f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else if (RC == SP::FPRegsRegisterClass) 208d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0); 209f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else if (RC == SP::DFPRegsRegisterClass) 210d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0); 211f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else 212f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(0 && "Can't load this register from stack slot"); 213f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 214f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson 215f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Andersonvoid SparcInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 216d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling SmallVectorImpl<MachineOperand> &Addr, 217d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling const TargetRegisterClass *RC, 218f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson SmallVectorImpl<MachineInstr*> &NewMIs) const { 219f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson unsigned Opc = 0; 220f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson if (RC == SP::IntRegsRegisterClass) 221f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = SP::LDri; 222f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else if (RC == SP::FPRegsRegisterClass) 223f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = SP::LDFri; 224f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else if (RC == SP::DFPRegsRegisterClass) 225f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson Opc = SP::LDDFri; 226f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else 227f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson assert(0 && "Can't load this register"); 22821b5541814d57d0a31f353948e4e933dbb1af6a4Dale Johannesen DebugLoc DL = DebugLoc::getUnknownLoc(); 22921b5541814d57d0a31f353948e4e933dbb1af6a4Dale Johannesen MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); 230f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson for (unsigned i = 0, e = Addr.size(); i != e; ++i) { 231f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MachineOperand &MO = Addr[i]; 232d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman if (MO.isReg()) 233f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MIB.addReg(MO.getReg()); 234d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman else if (MO.isImm()) 235f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MIB.addImm(MO.getImm()); 236f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson else { 237d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman assert(MO.isFI()); 238f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson MIB.addFrameIndex(MO.getIndex()); 239f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 240f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson } 241f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson NewMIs.push_back(MIB); 242f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson return; 243f6372aa1cc568df19da7c5023e83c75aa9404a07Owen Anderson} 24443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 245c54baa2d43730f1804acfb4f4e738fba72f966bdDan GohmanMachineInstr *SparcInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 246c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman MachineInstr* MI, 2478e8b8a223c2b0e69f44c0639f846260c8011668fDan Gohman const SmallVectorImpl<unsigned> &Ops, 248c54baa2d43730f1804acfb4f4e738fba72f966bdDan Gohman int FI) const { 24943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if (Ops.size() != 1) return NULL; 25043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 25143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson unsigned OpNum = Ops[0]; 25243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson bool isFloat = false; 25343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson MachineInstr *NewMI = NULL; 25443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson switch (MI->getOpcode()) { 25543dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson case SP::ORrr: 256d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman if (MI->getOperand(1).isReg() && MI->getOperand(1).getReg() == SP::G0&& 257d735b8019b0f297d7c14b55adcd887af24d8e602Dan Gohman MI->getOperand(0).isReg() && MI->getOperand(2).isReg()) { 25843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson if (OpNum == 0) // COPY -> STORE 259d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMI = BuildMI(MF, MI->getDebugLoc(), get(SP::STri)) 260d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling .addFrameIndex(FI) 261d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling .addImm(0) 262d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling .addReg(MI->getOperand(2).getReg()); 26343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson else // COPY -> LOAD 264d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMI = BuildMI(MF, MI->getDebugLoc(), get(SP::LDri), 265d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling MI->getOperand(0).getReg()) 266d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling .addFrameIndex(FI) 267d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling .addImm(0); 26843dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 26943dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson break; 27043dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson case SP::FMOVS: 27143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson isFloat = true; 27243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson // FALLTHROUGH 27343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson case SP::FMOVD: 2749f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng if (OpNum == 0) { // COPY -> STORE 2759f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng unsigned SrcReg = MI->getOperand(1).getReg(); 2769f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng bool isKill = MI->getOperand(1).isKill(); 277d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMI = BuildMI(MF, MI->getDebugLoc(), 278d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling get(isFloat ? SP::STFri : SP::STDFri)) 279d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling .addFrameIndex(FI) 280d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling .addImm(0) 281d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling .addReg(SrcReg, false, false, isKill); 2829f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng } else { // COPY -> LOAD 2839f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng unsigned DstReg = MI->getOperand(0).getReg(); 2849f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng bool isDead = MI->getOperand(0).isDead(); 285d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling NewMI = BuildMI(MF, MI->getDebugLoc(), 286d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling get(isFloat ? SP::LDFri : SP::LDDFri)) 287d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling .addReg(DstReg, true, false, false, isDead) 288d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling .addFrameIndex(FI) 289d1c321a89ab999b9bb602b0f398ecd4c2022262cBill Wendling .addImm(0); 2909f1c8317a4676945b4961ddb9827ef2412551620Evan Cheng } 29143dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson break; 29243dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson } 29343dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson 29443dbe05279b753aabda571d9c83eaeb36987001aOwen Anderson return NewMI; 2959c5525f4fa177e20077710c980f08e2f8de06e39Duncan Sands} 296