X86AsmBackend.cpp revision 78c10eeaa57d1c6c4b7781d3c0bcb0cfbbc43b5c 
1//===-- X86AsmBackend.cpp - X86 Assembler Backend -------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#include "llvm/MC/MCAsmBackend.h"
11#include "MCTargetDesc/X86BaseInfo.h"
12#include "MCTargetDesc/X86FixupKinds.h"
13#include "llvm/ADT/Twine.h"
14#include "llvm/MC/MCAssembler.h"
15#include "llvm/MC/MCELFObjectWriter.h"
16#include "llvm/MC/MCExpr.h"
17#include "llvm/MC/MCFixupKindInfo.h"
18#include "llvm/MC/MCMachObjectWriter.h"
19#include "llvm/MC/MCObjectWriter.h"
20#include "llvm/MC/MCSectionCOFF.h"
21#include "llvm/MC/MCSectionELF.h"
22#include "llvm/MC/MCSectionMachO.h"
23#include "llvm/Object/MachOFormat.h"
24#include "llvm/Support/CommandLine.h"
25#include "llvm/Support/ELF.h"
26#include "llvm/Support/ErrorHandling.h"
27#include "llvm/Support/raw_ostream.h"
28#include "llvm/Target/TargetRegistry.h"
29using namespace llvm;
30
31// Option to allow disabling arithmetic relaxation to workaround PR9807, which
32// is useful when running bitwise comparison experiments on Darwin. We should be
33// able to remove this once PR9807 is resolved.
34static cl::opt<bool>
35MCDisableArithRelaxation("mc-x86-disable-arith-relaxation",
36         cl::desc("Disable relaxation of arithmetic instruction for X86"));
37
38static unsigned getFixupKindLog2Size(unsigned Kind) {
39  switch (Kind) {
40  default: assert(0 && "invalid fixup kind!");
41  case FK_PCRel_1:
42  case FK_Data_1: return 0;
43  case FK_PCRel_2:
44  case FK_Data_2: return 1;
45  case FK_PCRel_4:
46  case X86::reloc_riprel_4byte:
47  case X86::reloc_riprel_4byte_movq_load:
48  case X86::reloc_signed_4byte:
49  case X86::reloc_global_offset_table:
50  case FK_Data_4: return 2;
51  case FK_PCRel_8:
52  case FK_Data_8: return 3;
53  }
54}
55
56namespace {
57
58class X86ELFObjectWriter : public MCELFObjectTargetWriter {
59public:
60  X86ELFObjectWriter(bool is64Bit, Triple::OSType OSType, uint16_t EMachine,
61                     bool HasRelocationAddend)
62    : MCELFObjectTargetWriter(is64Bit, OSType, EMachine, HasRelocationAddend) {}
63};
64
65class X86AsmBackend : public MCAsmBackend {
66public:
67  X86AsmBackend(const Target &T)
68    : MCAsmBackend() {}
69
70  unsigned getNumFixupKinds() const {
71    return X86::NumTargetFixupKinds;
72  }
73
74  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
75    const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = {
76      { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
77      { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel},
78      { "reloc_signed_4byte", 0, 4 * 8, 0},
79      { "reloc_global_offset_table", 0, 4 * 8, 0}
80    };
81
82    if (Kind < FirstTargetFixupKind)
83      return MCAsmBackend::getFixupKindInfo(Kind);
84
85    assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
86           "Invalid kind!");
87    return Infos[Kind - FirstTargetFixupKind];
88  }
89
90  void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
91                  uint64_t Value) const {
92    unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
93
94    assert(Fixup.getOffset() + Size <= DataSize &&
95           "Invalid fixup offset!");
96    for (unsigned i = 0; i != Size; ++i)
97      Data[Fixup.getOffset() + i] = uint8_t(Value >> (i * 8));
98  }
99
100  bool MayNeedRelaxation(const MCInst &Inst) const;
101
102  void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
103
104  bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
105};
106} // end anonymous namespace
107
108static unsigned getRelaxedOpcodeBranch(unsigned Op) {
109  switch (Op) {
110  default:
111    return Op;
112
113  case X86::JAE_1: return X86::JAE_4;
114  case X86::JA_1:  return X86::JA_4;
115  case X86::JBE_1: return X86::JBE_4;
116  case X86::JB_1:  return X86::JB_4;
117  case X86::JE_1:  return X86::JE_4;
118  case X86::JGE_1: return X86::JGE_4;
119  case X86::JG_1:  return X86::JG_4;
120  case X86::JLE_1: return X86::JLE_4;
121  case X86::JL_1:  return X86::JL_4;
122  case X86::JMP_1: return X86::JMP_4;
123  case X86::JNE_1: return X86::JNE_4;
124  case X86::JNO_1: return X86::JNO_4;
125  case X86::JNP_1: return X86::JNP_4;
126  case X86::JNS_1: return X86::JNS_4;
127  case X86::JO_1:  return X86::JO_4;
128  case X86::JP_1:  return X86::JP_4;
129  case X86::JS_1:  return X86::JS_4;
130  }
131}
132
133static unsigned getRelaxedOpcodeArith(unsigned Op) {
134  switch (Op) {
135  default:
136    return Op;
137
138    // IMUL
139  case X86::IMUL16rri8: return X86::IMUL16rri;
140  case X86::IMUL16rmi8: return X86::IMUL16rmi;
141  case X86::IMUL32rri8: return X86::IMUL32rri;
142  case X86::IMUL32rmi8: return X86::IMUL32rmi;
143  case X86::IMUL64rri8: return X86::IMUL64rri32;
144  case X86::IMUL64rmi8: return X86::IMUL64rmi32;
145
146    // AND
147  case X86::AND16ri8: return X86::AND16ri;
148  case X86::AND16mi8: return X86::AND16mi;
149  case X86::AND32ri8: return X86::AND32ri;
150  case X86::AND32mi8: return X86::AND32mi;
151  case X86::AND64ri8: return X86::AND64ri32;
152  case X86::AND64mi8: return X86::AND64mi32;
153
154    // OR
155  case X86::OR16ri8: return X86::OR16ri;
156  case X86::OR16mi8: return X86::OR16mi;
157  case X86::OR32ri8: return X86::OR32ri;
158  case X86::OR32mi8: return X86::OR32mi;
159  case X86::OR64ri8: return X86::OR64ri32;
160  case X86::OR64mi8: return X86::OR64mi32;
161
162    // XOR
163  case X86::XOR16ri8: return X86::XOR16ri;
164  case X86::XOR16mi8: return X86::XOR16mi;
165  case X86::XOR32ri8: return X86::XOR32ri;
166  case X86::XOR32mi8: return X86::XOR32mi;
167  case X86::XOR64ri8: return X86::XOR64ri32;
168  case X86::XOR64mi8: return X86::XOR64mi32;
169
170    // ADD
171  case X86::ADD16ri8: return X86::ADD16ri;
172  case X86::ADD16mi8: return X86::ADD16mi;
173  case X86::ADD32ri8: return X86::ADD32ri;
174  case X86::ADD32mi8: return X86::ADD32mi;
175  case X86::ADD64ri8: return X86::ADD64ri32;
176  case X86::ADD64mi8: return X86::ADD64mi32;
177
178    // SUB
179  case X86::SUB16ri8: return X86::SUB16ri;
180  case X86::SUB16mi8: return X86::SUB16mi;
181  case X86::SUB32ri8: return X86::SUB32ri;
182  case X86::SUB32mi8: return X86::SUB32mi;
183  case X86::SUB64ri8: return X86::SUB64ri32;
184  case X86::SUB64mi8: return X86::SUB64mi32;
185
186    // CMP
187  case X86::CMP16ri8: return X86::CMP16ri;
188  case X86::CMP16mi8: return X86::CMP16mi;
189  case X86::CMP32ri8: return X86::CMP32ri;
190  case X86::CMP32mi8: return X86::CMP32mi;
191  case X86::CMP64ri8: return X86::CMP64ri32;
192  case X86::CMP64mi8: return X86::CMP64mi32;
193
194    // PUSH
195  case X86::PUSHi8: return X86::PUSHi32;
196  case X86::PUSHi16: return X86::PUSHi32;
197  case X86::PUSH64i8: return X86::PUSH64i32;
198  case X86::PUSH64i16: return X86::PUSH64i32;
199  }
200}
201
202static unsigned getRelaxedOpcode(unsigned Op) {
203  unsigned R = getRelaxedOpcodeArith(Op);
204  if (R != Op)
205    return R;
206  return getRelaxedOpcodeBranch(Op);
207}
208
209bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
210  // Branches can always be relaxed.
211  if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
212    return true;
213
214  if (MCDisableArithRelaxation)
215    return false;
216
217  // Check if this instruction is ever relaxable.
218  if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
219    return false;
220
221
222  // Check if it has an expression and is not RIP relative.
223  bool hasExp = false;
224  bool hasRIP = false;
225  for (unsigned i = 0; i < Inst.getNumOperands(); ++i) {
226    const MCOperand &Op = Inst.getOperand(i);
227    if (Op.isExpr())
228      hasExp = true;
229
230    if (Op.isReg() && Op.getReg() == X86::RIP)
231      hasRIP = true;
232  }
233
234  // FIXME: Why exactly do we need the !hasRIP? Is it just a limitation on
235  // how we do relaxations?
236  return hasExp && !hasRIP;
237}
238
239// FIXME: Can tblgen help at all here to verify there aren't other instructions
240// we can relax?
241void X86AsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
242  // The only relaxations X86 does is from a 1byte pcrel to a 4byte pcrel.
243  unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
244
245  if (RelaxedOp == Inst.getOpcode()) {
246    SmallString<256> Tmp;
247    raw_svector_ostream OS(Tmp);
248    Inst.dump_pretty(OS);
249    OS << "\n";
250    report_fatal_error("unexpected instruction to relax: " + OS.str());
251  }
252
253  Res = Inst;
254  Res.setOpcode(RelaxedOp);
255}
256
257/// WriteNopData - Write optimal nops to the output file for the \arg Count
258/// bytes.  This returns the number of bytes written.  It may return 0 if
259/// the \arg Count is more than the maximum optimal nops.
260bool X86AsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
261  static const uint8_t Nops[10][10] = {
262    // nop
263    {0x90},
264    // xchg %ax,%ax
265    {0x66, 0x90},
266    // nopl (%[re]ax)
267    {0x0f, 0x1f, 0x00},
268    // nopl 0(%[re]ax)
269    {0x0f, 0x1f, 0x40, 0x00},
270    // nopl 0(%[re]ax,%[re]ax,1)
271    {0x0f, 0x1f, 0x44, 0x00, 0x00},
272    // nopw 0(%[re]ax,%[re]ax,1)
273    {0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00},
274    // nopl 0L(%[re]ax)
275    {0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00},
276    // nopl 0L(%[re]ax,%[re]ax,1)
277    {0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
278    // nopw 0L(%[re]ax,%[re]ax,1)
279    {0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
280    // nopw %cs:0L(%[re]ax,%[re]ax,1)
281    {0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00},
282  };
283
284  // Write an optimal sequence for the first 15 bytes.
285  const uint64_t OptimalCount = (Count < 16) ? Count : 15;
286  const uint64_t Prefixes = OptimalCount <= 10 ? 0 : OptimalCount - 10;
287  for (uint64_t i = 0, e = Prefixes; i != e; i++)
288    OW->Write8(0x66);
289  const uint64_t Rest = OptimalCount - Prefixes;
290  for (uint64_t i = 0, e = Rest; i != e; i++)
291    OW->Write8(Nops[Rest - 1][i]);
292
293  // Finish with single byte nops.
294  for (uint64_t i = OptimalCount, e = Count; i != e; ++i)
295   OW->Write8(0x90);
296
297  return true;
298}
299
300/* *** */
301
302namespace {
303class ELFX86AsmBackend : public X86AsmBackend {
304public:
305  Triple::OSType OSType;
306  ELFX86AsmBackend(const Target &T, Triple::OSType _OSType)
307    : X86AsmBackend(T), OSType(_OSType) {
308    HasReliableSymbolDifference = true;
309  }
310
311  virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
312    const MCSectionELF &ES = static_cast<const MCSectionELF&>(Section);
313    return ES.getFlags() & ELF::SHF_MERGE;
314  }
315};
316
317class ELFX86_32AsmBackend : public ELFX86AsmBackend {
318public:
319  ELFX86_32AsmBackend(const Target &T, Triple::OSType OSType)
320    : ELFX86AsmBackend(T, OSType) {}
321
322  MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
323    return createELFObjectWriter(createELFObjectTargetWriter(),
324                                 OS, /*IsLittleEndian*/ true);
325  }
326
327  MCELFObjectTargetWriter *createELFObjectTargetWriter() const {
328    return new X86ELFObjectWriter(false, OSType, ELF::EM_386, false);
329  }
330};
331
332class ELFX86_64AsmBackend : public ELFX86AsmBackend {
333public:
334  ELFX86_64AsmBackend(const Target &T, Triple::OSType OSType)
335    : ELFX86AsmBackend(T, OSType) {}
336
337  MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
338    return createELFObjectWriter(createELFObjectTargetWriter(),
339                                 OS, /*IsLittleEndian*/ true);
340  }
341
342  MCELFObjectTargetWriter *createELFObjectTargetWriter() const {
343    return new X86ELFObjectWriter(true, OSType, ELF::EM_X86_64, true);
344  }
345};
346
347class WindowsX86AsmBackend : public X86AsmBackend {
348  bool Is64Bit;
349
350public:
351  WindowsX86AsmBackend(const Target &T, bool is64Bit)
352    : X86AsmBackend(T)
353    , Is64Bit(is64Bit) {
354  }
355
356  MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
357    return createWinCOFFObjectWriter(OS, Is64Bit);
358  }
359};
360
361class DarwinX86AsmBackend : public X86AsmBackend {
362public:
363  DarwinX86AsmBackend(const Target &T)
364    : X86AsmBackend(T) { }
365};
366
367class DarwinX86_32AsmBackend : public DarwinX86AsmBackend {
368public:
369  DarwinX86_32AsmBackend(const Target &T)
370    : DarwinX86AsmBackend(T) {}
371
372  MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
373    return createX86MachObjectWriter(OS, /*Is64Bit=*/false,
374                                     object::mach::CTM_i386,
375                                     object::mach::CSX86_ALL);
376  }
377};
378
379class DarwinX86_64AsmBackend : public DarwinX86AsmBackend {
380public:
381  DarwinX86_64AsmBackend(const Target &T)
382    : DarwinX86AsmBackend(T) {
383    HasReliableSymbolDifference = true;
384  }
385
386  MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
387    return createX86MachObjectWriter(OS, /*Is64Bit=*/true,
388                                     object::mach::CTM_x86_64,
389                                     object::mach::CSX86_ALL);
390  }
391
392  virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
393    // Temporary labels in the string literals sections require symbols. The
394    // issue is that the x86_64 relocation format does not allow symbol +
395    // offset, and so the linker does not have enough information to resolve the
396    // access to the appropriate atom unless an external relocation is used. For
397    // non-cstring sections, we expect the compiler to use a non-temporary label
398    // for anything that could have an addend pointing outside the symbol.
399    //
400    // See <rdar://problem/4765733>.
401    const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
402    return SMO.getType() == MCSectionMachO::S_CSTRING_LITERALS;
403  }
404
405  virtual bool isSectionAtomizable(const MCSection &Section) const {
406    const MCSectionMachO &SMO = static_cast<const MCSectionMachO&>(Section);
407    // Fixed sized data sections are uniqued, they cannot be diced into atoms.
408    switch (SMO.getType()) {
409    default:
410      return true;
411
412    case MCSectionMachO::S_4BYTE_LITERALS:
413    case MCSectionMachO::S_8BYTE_LITERALS:
414    case MCSectionMachO::S_16BYTE_LITERALS:
415    case MCSectionMachO::S_LITERAL_POINTERS:
416    case MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS:
417    case MCSectionMachO::S_LAZY_SYMBOL_POINTERS:
418    case MCSectionMachO::S_MOD_INIT_FUNC_POINTERS:
419    case MCSectionMachO::S_MOD_TERM_FUNC_POINTERS:
420    case MCSectionMachO::S_INTERPOSING:
421      return false;
422    }
423  }
424};
425
426} // end anonymous namespace
427
428MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T, StringRef TT) {
429  Triple TheTriple(TT);
430
431  if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
432    return new DarwinX86_32AsmBackend(T);
433
434  if (TheTriple.isOSWindows())
435    return new WindowsX86AsmBackend(T, false);
436
437  return new ELFX86_32AsmBackend(T, TheTriple.getOS());
438}
439
440MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T, StringRef TT) {
441  Triple TheTriple(TT);
442
443  if (TheTriple.isOSDarwin() || TheTriple.getEnvironment() == Triple::MachO)
444    return new DarwinX86_64AsmBackend(T);
445
446  if (TheTriple.isOSWindows())
447    return new WindowsX86AsmBackend(T, true);
448
449  return new ELFX86_64AsmBackend(T, TheTriple.getOS());
450}
451