Searched defs:imm (Results 1 - 22 of 22) sorted by relevance

/external/webkit/JavaScriptCore/assembler/
H A DARMAssembler.cpp54 ARMWord ARMAssembler::getOp2(ARMWord imm) argument
58 if (imm <= 0xff)
59 return OP2_IMM | imm;
61 if ((imm & 0xff000000) == 0) {
62 imm <<= 8;
66 imm = (imm << 24) | (imm >> 8);
70 if ((imm & 0xff000000) == 0) {
71 imm <<
91 genInt(int reg, ARMWord imm, bool positive) argument
200 getImm(ARMWord imm, int tmpReg, bool invert) argument
220 moveImm(ARMWord imm, int dest) argument
240 encodeComplexImm(ARMWord imm, int dest) argument
[all...]
H A DMacroAssembler.h91 void poke(ImmPtr imm, int index = 0) argument
93 storePtr(imm, Address(stackPointerRegister, (index * sizeof(void*))));
98 void branchPtr(Condition cond, RegisterID op1, ImmPtr imm, Label target) argument
100 branchPtr(cond, op1, imm).linkTo(target, this);
108 void branch32(Condition cond, RegisterID op1, Imm32 imm, Label target) argument
110 branch32(cond, op1, imm).linkTo(target, this);
143 void addPtr(Imm32 imm, RegisterID srcDest) argument
145 add32(imm, srcDest);
148 void addPtr(ImmPtr imm, RegisterID dest) argument
150 add32(Imm32(imm), des
153 addPtr(Imm32 imm, RegisterID src, RegisterID dest) argument
163 andPtr(Imm32 imm, RegisterID srcDest) argument
173 orPtr(ImmPtr imm, RegisterID dest) argument
178 orPtr(Imm32 imm, RegisterID dest) argument
188 subPtr(Imm32 imm, RegisterID dest) argument
193 subPtr(ImmPtr imm, RegisterID dest) argument
203 xorPtr(Imm32 imm, RegisterID srcDest) argument
249 storePtr(ImmPtr imm, ImplicitAddress address) argument
254 storePtr(ImmPtr imm, void* address) argument
326 branchSubPtr(Condition cond, Imm32 imm, RegisterID dest) argument
[all...]
H A DMacroAssemblerX86.h57 void add32(Imm32 imm, RegisterID src, RegisterID dest) argument
59 m_assembler.leal_mr(imm.m_value, src, dest);
62 void add32(Imm32 imm, AbsoluteAddress address) argument
64 m_assembler.addl_im(imm.m_value, address.m_ptr);
67 void addWithCarry32(Imm32 imm, AbsoluteAddress address) argument
69 m_assembler.adcl_im(imm.m_value, address.m_ptr);
72 void and32(Imm32 imm, AbsoluteAddress address) argument
74 m_assembler.andl_im(imm.m_value, address.m_ptr);
77 void or32(Imm32 imm, AbsoluteAddress address) argument
79 m_assembler.orl_im(imm
82 sub32(Imm32 imm, AbsoluteAddress address) argument
103 store32(Imm32 imm, void* address) argument
[all...]
H A DMacroAssemblerX86_64.h56 void add32(Imm32 imm, AbsoluteAddress address) argument
59 add32(imm, Address(scratchRegister));
62 void and32(Imm32 imm, AbsoluteAddress address) argument
65 and32(imm, Address(scratchRegister));
68 void or32(Imm32 imm, AbsoluteAddress address) argument
71 or32(imm, Address(scratchRegister));
74 void sub32(Imm32 imm, AbsoluteAddress address) argument
77 sub32(imm, Address(scratchRegister));
103 void store32(Imm32 imm, void* address) argument
106 move(imm, X86Register
142 addPtr(Imm32 imm, RegisterID srcDest) argument
147 addPtr(ImmPtr imm, RegisterID dest) argument
153 addPtr(Imm32 imm, RegisterID src, RegisterID dest) argument
158 addPtr(Imm32 imm, Address address) argument
163 addPtr(Imm32 imm, AbsoluteAddress address) argument
174 andPtr(Imm32 imm, RegisterID srcDest) argument
184 orPtr(ImmPtr imm, RegisterID dest) argument
190 orPtr(Imm32 imm, RegisterID dest) argument
200 subPtr(Imm32 imm, RegisterID dest) argument
205 subPtr(ImmPtr imm, RegisterID dest) argument
216 xorPtr(Imm32 imm, RegisterID srcDest) argument
270 storePtr(ImmPtr imm, ImplicitAddress address) argument
382 branchSubPtr(Condition cond, Imm32 imm, RegisterID dest) argument
[all...]
H A DMacroAssemblerARM.h89 void add32(Imm32 imm, Address address) argument
92 add32(imm, ARMRegisters::S1);
96 void add32(Imm32 imm, RegisterID dest) argument
98 m_assembler.adds_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
112 void and32(Imm32 imm, RegisterID dest) argument
114 ARMWord w = m_assembler.getImm(imm.m_value, ARMRegisters::S0, true);
130 void lshift32(Imm32 imm, RegisterID dest) argument
132 m_assembler.movs_r(dest, m_assembler.lsl(dest, imm.m_value & 0x1f));
144 void mul32(Imm32 imm, RegisterID src, RegisterID dest) argument
146 move(imm, ARMRegister
165 or32(Imm32 imm, RegisterID dest) argument
179 rshift32(Imm32 imm, RegisterID dest) argument
189 sub32(Imm32 imm, RegisterID dest) argument
194 sub32(Imm32 imm, Address address) argument
212 xor32(Imm32 imm, RegisterID dest) argument
278 store32(Imm32 imm, ImplicitAddress address) argument
293 store32(Imm32 imm, void* address) argument
319 push(Imm32 imm) argument
325 move(Imm32 imm, RegisterID dest) argument
338 move(ImmPtr imm, RegisterID dest) argument
477 branchAdd32(Condition cond, Imm32 imm, RegisterID dest) argument
506 branchMul32(Condition cond, Imm32 imm, RegisterID src, RegisterID dest) argument
526 branchSub32(Condition cond, Imm32 imm, RegisterID dest) argument
619 add32(Imm32 imm, RegisterID src, RegisterID dest) argument
624 add32(Imm32 imm, AbsoluteAddress address) argument
633 sub32(Imm32 imm, AbsoluteAddress address) argument
[all...]
H A DMacroAssemblerARMv7.h128 void add32(Imm32 imm, RegisterID dest) argument
130 add32(imm, dest, dest);
133 void add32(Imm32 imm, RegisterID src, RegisterID dest) argument
135 ARMThumbImmediate armImm = ARMThumbImmediate::makeUInt12OrEncodedImm(imm.m_value);
139 move(imm, dataTempRegister);
144 void add32(Imm32 imm, Address address) argument
148 ARMThumbImmediate armImm = ARMThumbImmediate::makeUInt12OrEncodedImm(imm.m_value);
154 move(imm, addressTempRegister);
167 void add32(Imm32 imm, AbsoluteAddress address) argument
171 ARMThumbImmediate armImm = ARMThumbImmediate::makeUInt12OrEncodedImm(imm
189 and32(Imm32 imm, RegisterID dest) argument
210 lshift32(Imm32 imm, RegisterID dest) argument
220 mul32(Imm32 imm, RegisterID src, RegisterID dest) argument
236 or32(Imm32 imm, RegisterID dest) argument
257 rshift32(Imm32 imm, RegisterID dest) argument
267 sub32(Imm32 imm, RegisterID dest) argument
278 sub32(Imm32 imm, Address address) argument
301 sub32(Imm32 imm, AbsoluteAddress address) argument
323 xor32(Imm32 imm, RegisterID dest) argument
444 store32(Imm32 imm, ImplicitAddress address) argument
456 store32(Imm32 imm, void* address) argument
605 push(Imm32 imm) argument
615 move(Imm32 imm, RegisterID dest) argument
641 move(ImmPtr imm, RegisterID dest) argument
688 int32_t imm = right.m_value; local
706 int32_t imm = mask.m_value; local
861 branchAdd32(Condition cond, Imm32 imm, RegisterID dest) argument
882 branchMul32(Condition cond, Imm32 imm, RegisterID src, RegisterID dest) argument
898 branchSub32(Condition cond, Imm32 imm, RegisterID dest) argument
977 moveWithPatch(Imm32 imm, RegisterID dst) argument
983 moveWithPatch(ImmPtr imm, RegisterID dst) argument
1044 ARMThumbImmediate imm = ARMThumbImmediate::makeUInt12OrEncodedImm(address.offset); local
1091 moveFixedWidthEncoding(Imm32 imm, RegisterID dst) argument
[all...]
H A DMacroAssemblerX86Common.h96 void add32(Imm32 imm, Address address) argument
98 m_assembler.addl_im(imm.m_value, address.offset, address.base);
101 void add32(Imm32 imm, RegisterID dest) argument
103 m_assembler.addl_ir(imm.m_value, dest);
121 void and32(Imm32 imm, RegisterID dest) argument
123 m_assembler.andl_ir(imm.m_value, dest);
136 void and32(Imm32 imm, Address address) argument
138 m_assembler.andl_im(imm.m_value, address.offset, address.base);
141 void lshift32(Imm32 imm, RegisterID dest) argument
143 m_assembler.shll_i8r(imm
178 mul32(Imm32 imm, RegisterID src, RegisterID dest) argument
208 or32(Imm32 imm, RegisterID dest) argument
223 or32(Imm32 imm, Address address) argument
250 rshift32(Imm32 imm, RegisterID dest) argument
260 sub32(Imm32 imm, RegisterID dest) argument
265 sub32(Imm32 imm, Address address) argument
286 xor32(Imm32 imm, Address dest) argument
291 xor32(Imm32 imm, RegisterID dest) argument
356 store32(Imm32 imm, ImplicitAddress address) argument
525 push(Imm32 imm) argument
535 move(Imm32 imm, RegisterID dest) argument
554 move(ImmPtr imm, RegisterID dest) argument
581 move(ImmPtr imm, RegisterID dest) argument
755 branchAdd32(Condition cond, Imm32 imm, RegisterID dest) argument
797 branchMul32(Condition cond, Imm32 imm, RegisterID src, RegisterID dest) argument
811 branchSub32(Condition cond, Imm32 imm, RegisterID dest) argument
818 branchSub32(Condition cond, Imm32 imm, Address dest) argument
[all...]
H A DARMAssembler.h425 void ldr_imm(int rd, ARMWord imm, Condition cc = AL) argument
427 m_buffer.putIntWithConstantInt(static_cast<ARMWord>(cc) | DTR | DT_LOAD | DT_UP | RN(ARMRegisters::pc) | RD(rd), imm, true); local
430 void ldr_un_imm(int rd, ARMWord imm, Condition cc = AL) argument
432 m_buffer.putIntWithConstantInt(static_cast<ARMWord>(cc) | DTR | DT_LOAD | DT_UP | RN(ARMRegisters::pc) | RD(rd), imm); local
638 // Must be an ldr ..., [pc +/- imm]
649 // Must be an ldr ..., [pc +/- imm]
761 static ARMWord getOp2Byte(ARMWord imm) argument
763 ASSERT(imm <= 0xff);
764 return OP2_IMMh | (imm & 0x0f) | ((imm
770 getImm16Op2(ARMWord imm) argument
[all...]
H A DX86Assembler.h281 void push_i32(int imm) argument
284 m_formatter.immediate32(imm);
300 void adcl_im(int imm, void* addr) argument
302 if (CAN_SIGN_EXTEND_8_32(imm)) {
304 m_formatter.immediate8(imm);
307 m_formatter.immediate32(imm);
327 void addl_ir(int imm, RegisterID dst) argument
329 if (CAN_SIGN_EXTEND_8_32(imm)) {
331 m_formatter.immediate8(imm);
334 m_formatter.immediate32(imm);
338 addl_im(int imm, int offset, RegisterID base) argument
355 addq_ir(int imm, RegisterID dst) argument
366 addq_im(int imm, int offset, RegisterID base) argument
377 addl_im(int imm, void* addr) argument
404 andl_ir(int imm, RegisterID dst) argument
415 andl_im(int imm, int offset, RegisterID base) argument
432 andq_ir(int imm, RegisterID dst) argument
443 andl_im(int imm, void* addr) argument
490 orl_ir(int imm, RegisterID dst) argument
501 orl_im(int imm, int offset, RegisterID base) argument
518 orq_ir(int imm, RegisterID dst) argument
529 orl_im(int imm, void* addr) argument
556 subl_ir(int imm, RegisterID dst) argument
567 subl_im(int imm, int offset, RegisterID base) argument
584 subq_ir(int imm, RegisterID dst) argument
595 subl_im(int imm, void* addr) argument
622 xorl_im(int imm, int offset, RegisterID base) argument
633 xorl_ir(int imm, RegisterID dst) argument
650 xorq_ir(int imm, RegisterID dst) argument
662 sarl_i8r(int imm, RegisterID dst) argument
677 shll_i8r(int imm, RegisterID dst) argument
698 sarq_i8r(int imm, RegisterID dst) argument
747 cmpl_ir(int imm, RegisterID dst) argument
758 cmpl_ir_force32(int imm, RegisterID dst) argument
764 cmpl_im(int imm, int offset, RegisterID base) argument
775 cmpl_im(int imm, int offset, RegisterID base, RegisterID index, int scale) argument
786 cmpl_im_force32(int imm, int offset, RegisterID base) argument
808 cmpq_ir(int imm, RegisterID dst) argument
819 cmpq_im(int imm, int offset, RegisterID base) argument
830 cmpq_im(int imm, int offset, RegisterID base, RegisterID index, int scale) argument
846 cmpl_im(int imm, void* addr) argument
864 cmpw_im(int imm, int offset, RegisterID base, RegisterID index, int scale) argument
882 testl_i32r(int imm, RegisterID dst) argument
888 testl_i32m(int imm, int offset, RegisterID base) argument
894 testl_i32m(int imm, int offset, RegisterID base, RegisterID index, int scale) argument
906 testq_i32r(int imm, RegisterID dst) argument
912 testq_i32m(int imm, int offset, RegisterID base) argument
918 testq_i32m(int imm, int offset, RegisterID base, RegisterID index, int scale) argument
931 testb_i8r(int imm, RegisterID dst) argument
1026 movl_i32r(int imm, RegisterID dst) argument
1032 movl_i32m(int imm, int offset, RegisterID base) argument
1096 movq_i32m(int imm, int offset, RegisterID base) argument
1102 movq_i64r(int64_t imm, RegisterID dst) argument
1131 movl_i32m(int imm, void* addr) argument
1854 immediate8(int imm) argument
1859 immediate16(int imm) argument
1864 immediate32(int imm) argument
1869 immediate64(int64_t imm) argument
[all...]
H A DARMv7Assembler.h716 void add(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
722 ASSERT(imm.isValid());
725 if (!(rd & 8) && imm.isUInt10()) {
726 m_formatter.oneWordOp5Reg3Imm8(OP_ADD_SP_imm_T1, rd, imm.getUInt10() >> 2);
728 } else if ((rd == ARMRegisters::sp) && imm.isUInt9()) {
729 m_formatter.oneWordOp9Imm7(OP_ADD_SP_imm_T2, imm.getUInt9() >> 2);
733 if (imm.isUInt3()) {
734 m_formatter.oneWordOp7Reg3Reg3Reg3(OP_ADD_imm_T1, (RegisterID)imm.getUInt3(), rn, rd);
736 } else if ((rd == rn) && imm.isUInt8()) {
737 m_formatter.oneWordOp5Reg3Imm8(OP_ADD_imm_T2, rd, imm
773 add_S(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
813 ARM_and(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
877 bkpt(uint8_t imm=0) argument
882 cmn(RegisterID rn, ARMThumbImmediate imm) argument
890 cmp(RegisterID rn, ARMThumbImmediate imm) argument
917 eor(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
966 ldr(RegisterID rt, RegisterID rn, ARMThumbImmediate imm) argument
1026 ldrh(RegisterID rt, RegisterID rn, ARMThumbImmediate imm) argument
1115 movT3(RegisterID rd, ARMThumbImmediate imm) argument
1124 mov(RegisterID rd, ARMThumbImmediate imm) argument
1142 movt(RegisterID rd, ARMThumbImmediate imm) argument
1149 mvn(RegisterID rd, ARMThumbImmediate imm) argument
1172 orr(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
1225 str(RegisterID rt, RegisterID rn, ARMThumbImmediate imm) argument
1285 sub(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
1333 sub_S(RegisterID rd, RegisterID rn, ARMThumbImmediate imm) argument
1376 tst(RegisterID rn, ARMThumbImmediate imm) argument
1419 vldr(FPRegisterID rd, RegisterID rn, int32_t imm) argument
1445 vstr(FPRegisterID rd, RegisterID rn, int32_t imm) argument
1619 vmem(FPRegisterID rd, RegisterID rn, int32_t imm, bool isLoad) argument
1735 twoWordOp5i6Imm4Reg4EncodedImmFirst(uint16_t op, ARMThumbImmediate imm) argument
1739 twoWordOp5i6Imm4Reg4EncodedImmSecond(uint16_t rd, ARMThumbImmediate imm) argument
1746 oneWordOp5Reg3Imm8(OpcodeID op, RegisterID rd, uint8_t imm) argument
1751 oneWordOp5Imm5Reg3Reg3(OpcodeID op, uint8_t imm, RegisterID reg1, RegisterID reg2) argument
1761 oneWordOp8Imm8(OpcodeID op, uint8_t imm) argument
1770 oneWordOp9Imm7(OpcodeID op, uint8_t imm) argument
1798 twoWordOp5i6Imm4Reg4EncodedImm(OpcodeID1 op, int imm4, RegisterID rd, ARMThumbImmediate imm) argument
1807 twoWordOp12Reg4Reg4Imm12(OpcodeID1 op, RegisterID reg1, RegisterID reg2, uint16_t imm) argument
[all...]
/external/v8/src/mips/
H A Ddisasm-mips.cc218 int32_t imm = instr->Imm16Field(); local
220 "%u", imm);
226 int32_t imm = ((instr->Imm16Field())<<16)>>16; local
228 "%d", imm);
234 int32_t imm = instr->Imm16Field(); local
236 "0x%x", imm);
242 int32_t imm = instr->Imm26Field(); local
244 "%d", imm);
/external/v8/src/arm/
H A Ddisasm-arm.cc239 int imm = (immed8 >> rotate) | (immed8 << (32 - rotate)); local
241 "#%d", imm);
H A Dsimulator-arm.cc1082 int imm = (immed8 >> rotate) | (immed8 << (32 - rotate)); local
1083 *carry_out = (rotate == 0) ? c_flag_ : (imm < 0);
1084 return imm;
1455 // Format(instr, "and'cond's 'rd, 'rn, 'imm");
1467 // Format(instr, "eor'cond's 'rd, 'rn, 'imm");
1479 // Format(instr, "sub'cond's 'rd, 'rn, 'imm");
1492 // Format(instr, "rsb'cond's 'rd, 'rn, 'imm");
1505 // Format(instr, "add'cond's 'rd, 'rn, 'imm");
1518 Format(instr, "adc'cond's 'rd, 'rn, 'imm");
1524 Format(instr, "sbc'cond's 'rd, 'rn, 'imm");
[all...]
/external/v8/src/ia32/
H A Ddisasm-ia32.cc529 int32_t imm = *reinterpret_cast<int32_t*>(data+2); local
530 AppendToBuffer("test %s,0x%x", NameOfCPURegister(rm), imm);
535 int32_t imm = *reinterpret_cast<int32_t*>(data+1+count); local
536 AppendToBuffer(",0x%x", imm);
910 int32_t imm = local
915 imm);
1008 int32_t imm = is_byte ? *data : *reinterpret_cast<int32_t*>(data); local
1009 AppendToBuffer(",0x%x", imm);
1026 int32_t imm = *data; local
1027 AppendToBuffer(",0x%x", imm);
[all...]
H A Dassembler-ia32.cc502 PrintF("%d push/pop (imm->reg) eliminated\n", pc_offset());
525 PrintF("%d push/pop (imm->reg) eliminated\n", pc_offset());
537 PrintF("%d push/pop (imm->reg) eliminated\n", pc_offset());
913 void Assembler::cmp(const Operand& op, const Immediate& imm) { argument
916 emit_arith(7, op, imm);
1246 void Assembler::test(Register reg, const Immediate& imm) { argument
1251 if (imm.rmode_ == RelocInfo::NONE && is_uint8(imm.x_) && reg.code() < 4) {
1252 uint8_t imm8 = imm.x_;
1268 emit(imm);
1289 test(const Operand& op, const Immediate& imm) argument
[all...]
/external/webkit/JavaScriptCore/yarr/
H A DRegexJIT.cpp258 void storeToFrame(Imm32 imm, unsigned frameLocation) argument
260 poke(imm, frameLocation);
/external/qemu/
H A Darm-dis.c1781 int imm; local
1783 imm = (given & 0xf) | ((given & 0xe0) >> 1);
1785 /* Is ``imm'' a negative number? */
1786 if (imm & 0x40)
1787 imm |= (-1 << 7);
1789 func (stream, "%d", imm);
2993 int imm; local
2995 imm = (given & 0xf) | ((given & 0xfff00) >> 4);
2996 func (stream, "%d", imm);
3187 long imm local
3377 unsigned int bits = 0, imm, imm8, mod; local
3400 unsigned int imm = 0; local
3411 unsigned int imm = 0; local
3423 unsigned int imm = 0; local
[all...]
/external/qemu/tcg/ppc/
H A Dtcg-target.c944 int imm; local
953 imm = 1;
958 imm = 1;
963 imm = 0;
973 imm = 1;
978 imm = 0;
988 imm = 1;
993 imm = 0;
1001 if (imm)
/external/qemu/tcg/ppc64/
H A Dtcg-target.c918 int imm; local
927 imm = 1;
932 imm = 1;
937 imm = 0;
947 imm = 1;
952 imm = 0;
962 imm = 1;
967 imm = 0;
975 if (imm)
/external/v8/src/x64/
H A Dassembler-x64.cc1007 void Assembler::imul(Register dst, Register src, Immediate imm) { argument
1011 if (is_int8(imm.value_)) {
1014 emit(imm.value_);
1018 emitl(imm.value_);
1222 void Assembler::movb(Register dst, Immediate imm) { argument
1228 emit(imm.value_);
H A Ddisasm-x64.cc1274 int32_t imm = *data == 0x6B ? *(data + 2) local
1277 NameOfCPURegister(rm), imm);
1341 int32_t imm = is_byte ? *data : *reinterpret_cast<int32_t*>(data); local
1342 AppendToBuffer(",0x%x", imm);
1351 int32_t imm = *data; local
1352 AppendToBuffer(",0x%x", imm);
/external/qemu/target-arm/
H A Dtranslate.c4120 uint32_t imm; local
4531 imm = (uint8_t) shift;
4532 imm |= imm << 8;
4533 imm |= imm << 16;
4536 imm = (uint16_t) shift;
4537 imm |= imm << 16;
4541 imm
7147 uint32_t insn, imm, shift, offset; local
[all...]

Completed in 348 milliseconds