1/* $NetBSD: disassem.c,v 1.14 2003/03/27 16:58:36 mycroft Exp $ */ 2 3/*- 4 * Copyright (c) 1996 Mark Brinicombe. 5 * Copyright (c) 1996 Brini. 6 * 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Brini. 20 * 4. The name of the company nor the name of the author may be used to 21 * endorse or promote products derived from this software without specific 22 * prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * RiscBSD kernel project 37 * 38 * db_disasm.c 39 * 40 * Kernel disassembler 41 * 42 * Created : 10/02/96 43 * 44 * Structured after the sparc/sparc/db_disasm.c by David S. Miller & 45 * Paul Kranenburg 46 * 47 * This code is not complete. Not all instructions are disassembled. 48 */ 49 50#include <sys/cdefs.h> 51//__FBSDID("$FreeBSD: /repoman/r/ncvs/src/sys/arm/arm/disassem.c,v 1.2 2005/01/05 21:58:47 imp Exp $"); 52#include <sys/param.h> 53#include <stdio.h> 54#include <stdarg.h> 55 56#include "disassem.h" 57#include "armreg.h" 58//#include <ddb/ddb.h> 59 60/* 61 * General instruction format 62 * 63 * insn[cc][mod] [operands] 64 * 65 * Those fields with an uppercase format code indicate that the field 66 * follows directly after the instruction before the separator i.e. 67 * they modify the instruction rather than just being an operand to 68 * the instruction. The only exception is the writeback flag which 69 * follows a operand. 70 * 71 * 72 * 2 - print Operand 2 of a data processing instruction 73 * d - destination register (bits 12-15) 74 * n - n register (bits 16-19) 75 * s - s register (bits 8-11) 76 * o - indirect register rn (bits 16-19) (used by swap) 77 * m - m register (bits 0-3) 78 * a - address operand of ldr/str instruction 79 * e - address operand of ldrh/strh instruction 80 * l - register list for ldm/stm instruction 81 * f - 1st fp operand (register) (bits 12-14) 82 * g - 2nd fp operand (register) (bits 16-18) 83 * h - 3rd fp operand (register/immediate) (bits 0-4) 84 * b - branch address 85 * t - thumb branch address (bits 24, 0-23) 86 * k - breakpoint comment (bits 0-3, 8-19) 87 * X - block transfer type 88 * Y - block transfer type (r13 base) 89 * c - comment field bits(0-23) 90 * p - saved or current status register 91 * F - PSR transfer fields 92 * D - destination-is-r15 (P) flag on TST, TEQ, CMP, CMN 93 * L - co-processor transfer size 94 * S - set status flag 95 * P - fp precision 96 * Q - fp precision (for ldf/stf) 97 * R - fp rounding 98 * v - co-processor data transfer registers + addressing mode 99 * W - writeback flag 100 * x - instruction in hex 101 * # - co-processor number 102 * y - co-processor data processing registers 103 * z - co-processor register transfer registers 104 */ 105 106struct arm32_insn { 107 u_int mask; 108 u_int pattern; 109 const char* name; 110 const char* format; 111}; 112 113static const struct arm32_insn arm32_i[] = { 114 { 0x0fffffff, 0x0ff00000, "imb", "c" }, /* Before swi */ 115 { 0x0fffffff, 0x0ff00001, "imbrange", "c" }, /* Before swi */ 116 { 0x0f000000, 0x0f000000, "swi", "c" }, 117 { 0xfe000000, 0xfa000000, "blx", "t" }, /* Before b and bl */ 118 { 0x0f000000, 0x0a000000, "b", "b" }, 119 { 0x0f000000, 0x0b000000, "bl", "b" }, 120 { 0x0fe000f0, 0x00000090, "mul", "Snms" }, 121 { 0x0fe000f0, 0x00200090, "mla", "Snmsd" }, 122 { 0x0fe000f0, 0x00800090, "umull", "Sdnms" }, 123 { 0x0fe000f0, 0x00c00090, "smull", "Sdnms" }, 124 { 0x0fe000f0, 0x00a00090, "umlal", "Sdnms" }, 125 { 0x0fe000f0, 0x00e00090, "smlal", "Sdnms" }, 126 { 0x0d700000, 0x04200000, "strt", "daW" }, 127 { 0x0d700000, 0x04300000, "ldrt", "daW" }, 128 { 0x0d700000, 0x04600000, "strbt", "daW" }, 129 { 0x0d700000, 0x04700000, "ldrbt", "daW" }, 130 { 0x0c500000, 0x04000000, "str", "daW" }, 131 { 0x0c500000, 0x04100000, "ldr", "daW" }, 132 { 0x0c500000, 0x04400000, "strb", "daW" }, 133 { 0x0c500000, 0x04500000, "ldrb", "daW" }, 134 { 0x0e1f0000, 0x080d0000, "stm", "YnWl" },/* separate out r13 base */ 135 { 0x0e1f0000, 0x081d0000, "ldm", "YnWl" },/* separate out r13 base */ 136 { 0x0e100000, 0x08000000, "stm", "XnWl" }, 137 { 0x0e100000, 0x08100000, "ldm", "XnWl" }, 138 { 0x0e1000f0, 0x00100090, "ldrb", "deW" }, 139 { 0x0e1000f0, 0x00000090, "strb", "deW" }, 140 { 0x0e1000f0, 0x001000d0, "ldrsb", "deW" }, 141 { 0x0e1000f0, 0x001000b0, "ldrh", "deW" }, 142 { 0x0e1000f0, 0x000000b0, "strh", "deW" }, 143 { 0x0e1000f0, 0x001000f0, "ldrsh", "deW" }, 144 { 0x0f200090, 0x00200090, "und", "x" }, /* Before data processing */ 145 { 0x0e1000d0, 0x000000d0, "und", "x" }, /* Before data processing */ 146 { 0x0ff00ff0, 0x01000090, "swp", "dmo" }, 147 { 0x0ff00ff0, 0x01400090, "swpb", "dmo" }, 148 { 0x0fbf0fff, 0x010f0000, "mrs", "dp" }, /* Before data processing */ 149 { 0x0fb0fff0, 0x0120f000, "msr", "pFm" },/* Before data processing */ 150 { 0x0fb0f000, 0x0320f000, "msr", "pF2" },/* Before data processing */ 151 { 0x0ffffff0, 0x012fff10, "bx", "m" }, 152 { 0x0fff0ff0, 0x016f0f10, "clz", "dm" }, 153 { 0x0ffffff0, 0x012fff30, "blx", "m" }, 154 { 0xfff000f0, 0xe1200070, "bkpt", "k" }, 155 { 0x0de00000, 0x00000000, "and", "Sdn2" }, 156 { 0x0de00000, 0x00200000, "eor", "Sdn2" }, 157 { 0x0de00000, 0x00400000, "sub", "Sdn2" }, 158 { 0x0de00000, 0x00600000, "rsb", "Sdn2" }, 159 { 0x0de00000, 0x00800000, "add", "Sdn2" }, 160 { 0x0de00000, 0x00a00000, "adc", "Sdn2" }, 161 { 0x0de00000, 0x00c00000, "sbc", "Sdn2" }, 162 { 0x0de00000, 0x00e00000, "rsc", "Sdn2" }, 163 { 0x0df00000, 0x01100000, "tst", "Dn2" }, 164 { 0x0df00000, 0x01300000, "teq", "Dn2" }, 165 { 0x0df00000, 0x01500000, "cmp", "Dn2" }, 166 { 0x0df00000, 0x01700000, "cmn", "Dn2" }, 167 { 0x0de00000, 0x01800000, "orr", "Sdn2" }, 168 { 0x0de00000, 0x01a00000, "mov", "Sd2" }, 169 { 0x0de00000, 0x01c00000, "bic", "Sdn2" }, 170 { 0x0de00000, 0x01e00000, "mvn", "Sd2" }, 171 { 0x0ff08f10, 0x0e000100, "adf", "PRfgh" }, 172 { 0x0ff08f10, 0x0e100100, "muf", "PRfgh" }, 173 { 0x0ff08f10, 0x0e200100, "suf", "PRfgh" }, 174 { 0x0ff08f10, 0x0e300100, "rsf", "PRfgh" }, 175 { 0x0ff08f10, 0x0e400100, "dvf", "PRfgh" }, 176 { 0x0ff08f10, 0x0e500100, "rdf", "PRfgh" }, 177 { 0x0ff08f10, 0x0e600100, "pow", "PRfgh" }, 178 { 0x0ff08f10, 0x0e700100, "rpw", "PRfgh" }, 179 { 0x0ff08f10, 0x0e800100, "rmf", "PRfgh" }, 180 { 0x0ff08f10, 0x0e900100, "fml", "PRfgh" }, 181 { 0x0ff08f10, 0x0ea00100, "fdv", "PRfgh" }, 182 { 0x0ff08f10, 0x0eb00100, "frd", "PRfgh" }, 183 { 0x0ff08f10, 0x0ec00100, "pol", "PRfgh" }, 184 { 0x0f008f10, 0x0e000100, "fpbop", "PRfgh" }, 185 { 0x0ff08f10, 0x0e008100, "mvf", "PRfh" }, 186 { 0x0ff08f10, 0x0e108100, "mnf", "PRfh" }, 187 { 0x0ff08f10, 0x0e208100, "abs", "PRfh" }, 188 { 0x0ff08f10, 0x0e308100, "rnd", "PRfh" }, 189 { 0x0ff08f10, 0x0e408100, "sqt", "PRfh" }, 190 { 0x0ff08f10, 0x0e508100, "log", "PRfh" }, 191 { 0x0ff08f10, 0x0e608100, "lgn", "PRfh" }, 192 { 0x0ff08f10, 0x0e708100, "exp", "PRfh" }, 193 { 0x0ff08f10, 0x0e808100, "sin", "PRfh" }, 194 { 0x0ff08f10, 0x0e908100, "cos", "PRfh" }, 195 { 0x0ff08f10, 0x0ea08100, "tan", "PRfh" }, 196 { 0x0ff08f10, 0x0eb08100, "asn", "PRfh" }, 197 { 0x0ff08f10, 0x0ec08100, "acs", "PRfh" }, 198 { 0x0ff08f10, 0x0ed08100, "atn", "PRfh" }, 199 { 0x0f008f10, 0x0e008100, "fpuop", "PRfh" }, 200 { 0x0e100f00, 0x0c000100, "stf", "QLv" }, 201 { 0x0e100f00, 0x0c100100, "ldf", "QLv" }, 202 { 0x0ff00f10, 0x0e000110, "flt", "PRgd" }, 203 { 0x0ff00f10, 0x0e100110, "fix", "PRdh" }, 204 { 0x0ff00f10, 0x0e200110, "wfs", "d" }, 205 { 0x0ff00f10, 0x0e300110, "rfs", "d" }, 206 { 0x0ff00f10, 0x0e400110, "wfc", "d" }, 207 { 0x0ff00f10, 0x0e500110, "rfc", "d" }, 208 { 0x0ff0ff10, 0x0e90f110, "cmf", "PRgh" }, 209 { 0x0ff0ff10, 0x0eb0f110, "cnf", "PRgh" }, 210 { 0x0ff0ff10, 0x0ed0f110, "cmfe", "PRgh" }, 211 { 0x0ff0ff10, 0x0ef0f110, "cnfe", "PRgh" }, 212 { 0xff100010, 0xfe000010, "mcr2", "#z" }, 213 { 0x0f100010, 0x0e000010, "mcr", "#z" }, 214 { 0xff100010, 0xfe100010, "mrc2", "#z" }, 215 { 0x0f100010, 0x0e100010, "mrc", "#z" }, 216 { 0xff000010, 0xfe000000, "cdp2", "#y" }, 217 { 0x0f000010, 0x0e000000, "cdp", "#y" }, 218 { 0xfe100090, 0xfc100000, "ldc2", "L#v" }, 219 { 0x0e100090, 0x0c100000, "ldc", "L#v" }, 220 { 0xfe100090, 0xfc000000, "stc2", "L#v" }, 221 { 0x0e100090, 0x0c000000, "stc", "L#v" }, 222 { 0xf550f000, 0xf550f000, "pld", "ne" }, 223 { 0x0ff00ff0, 0x01000050, "qaad", "dmn" }, 224 { 0x0ff00ff0, 0x01400050, "qdaad", "dmn" }, 225 { 0x0ff00ff0, 0x01600050, "qdsub", "dmn" }, 226 { 0x0ff00ff0, 0x01200050, "dsub", "dmn" }, 227 { 0x0ff000f0, 0x01000080, "smlabb", "nmsd" }, // d & n inverted!! 228 { 0x0ff000f0, 0x010000a0, "smlatb", "nmsd" }, // d & n inverted!! 229 { 0x0ff000f0, 0x010000c0, "smlabt", "nmsd" }, // d & n inverted!! 230 { 0x0ff000f0, 0x010000e0, "smlatt", "nmsd" }, // d & n inverted!! 231 { 0x0ff000f0, 0x01400080, "smlalbb","ndms" }, // d & n inverted!! 232 { 0x0ff000f0, 0x014000a0, "smlaltb","ndms" }, // d & n inverted!! 233 { 0x0ff000f0, 0x014000c0, "smlalbt","ndms" }, // d & n inverted!! 234 { 0x0ff000f0, 0x014000e0, "smlaltt","ndms" }, // d & n inverted!! 235 { 0x0ff000f0, 0x01200080, "smlawb", "nmsd" }, // d & n inverted!! 236 { 0x0ff0f0f0, 0x012000a0, "smulwb","nms" }, // d & n inverted!! 237 { 0x0ff000f0, 0x012000c0, "smlawt", "nmsd" }, // d & n inverted!! 238 { 0x0ff0f0f0, 0x012000e0, "smulwt","nms" }, // d & n inverted!! 239 { 0x0ff0f0f0, 0x01600080, "smulbb","nms" }, // d & n inverted!! 240 { 0x0ff0f0f0, 0x016000a0, "smultb","nms" }, // d & n inverted!! 241 { 0x0ff0f0f0, 0x016000c0, "smulbt","nms" }, // d & n inverted!! 242 { 0x0ff0f0f0, 0x016000e0, "smultt","nms" }, // d & n inverted!! 243 { 0x00000000, 0x00000000, NULL, NULL } 244}; 245 246static char const arm32_insn_conditions[][4] = { 247 "eq", "ne", "cs", "cc", 248 "mi", "pl", "vs", "vc", 249 "hi", "ls", "ge", "lt", 250 "gt", "le", "", "nv" 251}; 252 253static char const insn_block_transfers[][4] = { 254 "da", "ia", "db", "ib" 255}; 256 257static char const insn_stack_block_transfers[][4] = { 258 "ed", "ea", "fd", "fa" 259}; 260 261static char const op_shifts[][4] = { 262 "lsl", "lsr", "asr", "ror" 263}; 264 265static char const insn_fpa_rounding[][2] = { 266 "", "p", "m", "z" 267}; 268 269static char const insn_fpa_precision[][2] = { 270 "s", "d", "e", "p" 271}; 272 273static char const insn_fpaconstants[][8] = { 274 "0.0", "1.0", "2.0", "3.0", 275 "4.0", "5.0", "0.5", "10.0" 276}; 277 278#define insn_condition(x) arm32_insn_conditions[(x >> 28) & 0x0f] 279#define insn_blktrans(x) insn_block_transfers[(x >> 23) & 3] 280#define insn_stkblktrans(x) insn_stack_block_transfers[(x >> 23) & 3] 281#define op2_shift(x) op_shifts[(x >> 5) & 3] 282#define insn_fparnd(x) insn_fpa_rounding[(x >> 5) & 0x03] 283#define insn_fpaprec(x) insn_fpa_precision[(((x >> 18) & 2)|(x >> 7)) & 1] 284#define insn_fpaprect(x) insn_fpa_precision[(((x >> 21) & 2)|(x >> 15)) & 1] 285#define insn_fpaimm(x) insn_fpaconstants[x & 0x07] 286 287/* Local prototypes */ 288static void disasm_register_shift(const disasm_interface_t *di, u_int insn); 289static void disasm_print_reglist(const disasm_interface_t *di, u_int insn); 290static void disasm_insn_ldrstr(const disasm_interface_t *di, u_int insn, 291 u_int loc); 292static void disasm_insn_ldrhstrh(const disasm_interface_t *di, u_int insn, 293 u_int loc); 294static void disasm_insn_ldcstc(const disasm_interface_t *di, u_int insn, 295 u_int loc); 296static u_int disassemble_readword(u_int address); 297static void disassemble_printaddr(u_int address); 298 299u_int 300disasm(const disasm_interface_t *di, u_int loc, int altfmt) 301{ 302 const struct arm32_insn *i_ptr = &arm32_i[0]; 303 304 u_int insn; 305 int matchp; 306 int branch; 307 const char* f_ptr; 308 int fmt; 309 310 fmt = 0; 311 matchp = 0; 312 insn = di->di_readword(loc); 313 314/* di->di_printf("loc=%08x insn=%08x : ", loc, insn);*/ 315 316 while (i_ptr->name) { 317 if ((insn & i_ptr->mask) == i_ptr->pattern) { 318 matchp = 1; 319 break; 320 } 321 i_ptr++; 322 } 323 324 if (!matchp) { 325 di->di_printf("und%s\t%08x\n", insn_condition(insn), insn); 326 return(loc + INSN_SIZE); 327 } 328 329 /* If instruction forces condition code, don't print it. */ 330 if ((i_ptr->mask & 0xf0000000) == 0xf0000000) 331 di->di_printf("%s", i_ptr->name); 332 else 333 di->di_printf("%s%s", i_ptr->name, insn_condition(insn)); 334 335 f_ptr = i_ptr->format; 336 337 /* Insert tab if there are no instruction modifiers */ 338 339 if (*(f_ptr) < 'A' || *(f_ptr) > 'Z') { 340 ++fmt; 341 di->di_printf("\t"); 342 } 343 344 while (*f_ptr) { 345 switch (*f_ptr) { 346 /* 2 - print Operand 2 of a data processing instruction */ 347 case '2': 348 if (insn & 0x02000000) { 349 int rotate= ((insn >> 7) & 0x1e); 350 351 di->di_printf("#0x%08x", 352 (insn & 0xff) << (32 - rotate) | 353 (insn & 0xff) >> rotate); 354 } else { 355 disasm_register_shift(di, insn); 356 } 357 break; 358 /* d - destination register (bits 12-15) */ 359 case 'd': 360 di->di_printf("r%d", ((insn >> 12) & 0x0f)); 361 break; 362 /* D - insert 'p' if Rd is R15 */ 363 case 'D': 364 if (((insn >> 12) & 0x0f) == 15) 365 di->di_printf("p"); 366 break; 367 /* n - n register (bits 16-19) */ 368 case 'n': 369 di->di_printf("r%d", ((insn >> 16) & 0x0f)); 370 break; 371 /* s - s register (bits 8-11) */ 372 case 's': 373 di->di_printf("r%d", ((insn >> 8) & 0x0f)); 374 break; 375 /* o - indirect register rn (bits 16-19) (used by swap) */ 376 case 'o': 377 di->di_printf("[r%d]", ((insn >> 16) & 0x0f)); 378 break; 379 /* m - m register (bits 0-4) */ 380 case 'm': 381 di->di_printf("r%d", ((insn >> 0) & 0x0f)); 382 break; 383 /* a - address operand of ldr/str instruction */ 384 case 'a': 385 disasm_insn_ldrstr(di, insn, loc); 386 break; 387 /* e - address operand of ldrh/strh instruction */ 388 case 'e': 389 disasm_insn_ldrhstrh(di, insn, loc); 390 break; 391 /* l - register list for ldm/stm instruction */ 392 case 'l': 393 disasm_print_reglist(di, insn); 394 break; 395 /* f - 1st fp operand (register) (bits 12-14) */ 396 case 'f': 397 di->di_printf("f%d", (insn >> 12) & 7); 398 break; 399 /* g - 2nd fp operand (register) (bits 16-18) */ 400 case 'g': 401 di->di_printf("f%d", (insn >> 16) & 7); 402 break; 403 /* h - 3rd fp operand (register/immediate) (bits 0-4) */ 404 case 'h': 405 if (insn & (1 << 3)) 406 di->di_printf("#%s", insn_fpaimm(insn)); 407 else 408 di->di_printf("f%d", insn & 7); 409 break; 410 /* b - branch address */ 411 case 'b': 412 branch = ((insn << 2) & 0x03ffffff); 413 if (branch & 0x02000000) 414 branch |= 0xfc000000; 415 di->di_printaddr(loc + 8 + branch); 416 break; 417 /* t - blx address */ 418 case 't': 419 branch = ((insn << 2) & 0x03ffffff) | 420 (insn >> 23 & 0x00000002); 421 if (branch & 0x02000000) 422 branch |= 0xfc000000; 423 di->di_printaddr(loc + 8 + branch); 424 break; 425 /* X - block transfer type */ 426 case 'X': 427 di->di_printf("%s", insn_blktrans(insn)); 428 break; 429 /* Y - block transfer type (r13 base) */ 430 case 'Y': 431 di->di_printf("%s", insn_stkblktrans(insn)); 432 break; 433 /* c - comment field bits(0-23) */ 434 case 'c': 435 di->di_printf("0x%08x", (insn & 0x00ffffff)); 436 break; 437 /* k - breakpoint comment (bits 0-3, 8-19) */ 438 case 'k': 439 di->di_printf("0x%04x", 440 (insn & 0x000fff00) >> 4 | (insn & 0x0000000f)); 441 break; 442 /* p - saved or current status register */ 443 case 'p': 444 if (insn & 0x00400000) 445 di->di_printf("spsr"); 446 else 447 di->di_printf("cpsr"); 448 break; 449 /* F - PSR transfer fields */ 450 case 'F': 451 di->di_printf("_"); 452 if (insn & (1 << 16)) 453 di->di_printf("c"); 454 if (insn & (1 << 17)) 455 di->di_printf("x"); 456 if (insn & (1 << 18)) 457 di->di_printf("s"); 458 if (insn & (1 << 19)) 459 di->di_printf("f"); 460 break; 461 /* B - byte transfer flag */ 462 case 'B': 463 if (insn & 0x00400000) 464 di->di_printf("b"); 465 break; 466 /* L - co-processor transfer size */ 467 case 'L': 468 if (insn & (1 << 22)) 469 di->di_printf("l"); 470 break; 471 /* S - set status flag */ 472 case 'S': 473 if (insn & 0x00100000) 474 di->di_printf("s"); 475 break; 476 /* P - fp precision */ 477 case 'P': 478 di->di_printf("%s", insn_fpaprec(insn)); 479 break; 480 /* Q - fp precision (for ldf/stf) */ 481 case 'Q': 482 break; 483 /* R - fp rounding */ 484 case 'R': 485 di->di_printf("%s", insn_fparnd(insn)); 486 break; 487 /* W - writeback flag */ 488 case 'W': 489 if (insn & (1 << 21)) 490 di->di_printf("!"); 491 break; 492 /* # - co-processor number */ 493 case '#': 494 di->di_printf("p%d", (insn >> 8) & 0x0f); 495 break; 496 /* v - co-processor data transfer registers+addressing mode */ 497 case 'v': 498 disasm_insn_ldcstc(di, insn, loc); 499 break; 500 /* x - instruction in hex */ 501 case 'x': 502 di->di_printf("0x%08x", insn); 503 break; 504 /* y - co-processor data processing registers */ 505 case 'y': 506 di->di_printf("%d, ", (insn >> 20) & 0x0f); 507 508 di->di_printf("c%d, c%d, c%d", (insn >> 12) & 0x0f, 509 (insn >> 16) & 0x0f, insn & 0x0f); 510 511 di->di_printf(", %d", (insn >> 5) & 0x07); 512 break; 513 /* z - co-processor register transfer registers */ 514 case 'z': 515 di->di_printf("%d, ", (insn >> 21) & 0x07); 516 di->di_printf("r%d, c%d, c%d, %d", 517 (insn >> 12) & 0x0f, (insn >> 16) & 0x0f, 518 insn & 0x0f, (insn >> 5) & 0x07); 519 520/* if (((insn >> 5) & 0x07) != 0) 521 di->di_printf(", %d", (insn >> 5) & 0x07);*/ 522 break; 523 default: 524 di->di_printf("[%c - unknown]", *f_ptr); 525 break; 526 } 527 if (*(f_ptr+1) >= 'A' && *(f_ptr+1) <= 'Z') 528 ++f_ptr; 529 else if (*(++f_ptr)) { 530 ++fmt; 531 if (fmt == 1) 532 di->di_printf("\t"); 533 else 534 di->di_printf(", "); 535 } 536 }; 537 538 di->di_printf("\n"); 539 540 return(loc + INSN_SIZE); 541} 542 543 544static void 545disasm_register_shift(const disasm_interface_t *di, u_int insn) 546{ 547 di->di_printf("r%d", (insn & 0x0f)); 548 if ((insn & 0x00000ff0) == 0) 549 ; 550 else if ((insn & 0x00000ff0) == 0x00000060) 551 di->di_printf(", rrx"); 552 else { 553 if (insn & 0x10) 554 di->di_printf(", %s r%d", op2_shift(insn), 555 (insn >> 8) & 0x0f); 556 else 557 di->di_printf(", %s #%d", op2_shift(insn), 558 (insn >> 7) & 0x1f); 559 } 560} 561 562 563static void 564disasm_print_reglist(const disasm_interface_t *di, u_int insn) 565{ 566 int loop; 567 int start; 568 int comma; 569 570 di->di_printf("{"); 571 start = -1; 572 comma = 0; 573 574 for (loop = 0; loop < 17; ++loop) { 575 if (start != -1) { 576 if (loop == 16 || !(insn & (1 << loop))) { 577 if (comma) 578 di->di_printf(", "); 579 else 580 comma = 1; 581 if (start == loop - 1) 582 di->di_printf("r%d", start); 583 else 584 di->di_printf("r%d-r%d", start, loop - 1); 585 start = -1; 586 } 587 } else { 588 if (insn & (1 << loop)) 589 start = loop; 590 } 591 } 592 di->di_printf("}"); 593 594 if (insn & (1 << 22)) 595 di->di_printf("^"); 596} 597 598static void 599disasm_insn_ldrstr(const disasm_interface_t *di, u_int insn, u_int loc) 600{ 601 int offset; 602 603 offset = insn & 0xfff; 604 if ((insn & 0x032f0000) == 0x010f0000) { 605 /* rA = pc, immediate index */ 606 if (insn & 0x00800000) 607 loc += offset; 608 else 609 loc -= offset; 610 di->di_printaddr(loc + 8); 611 } else { 612 di->di_printf("[r%d", (insn >> 16) & 0x0f); 613 if ((insn & 0x03000fff) != 0x01000000) { 614 di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]"); 615 if (!(insn & 0x00800000)) 616 di->di_printf("-"); 617 if (insn & (1 << 25)) 618 disasm_register_shift(di, insn); 619 else 620 di->di_printf("#0x%03x", offset); 621 } 622 if (insn & (1 << 24)) 623 di->di_printf("]"); 624 } 625} 626 627static void 628disasm_insn_ldrhstrh(const disasm_interface_t *di, u_int insn, u_int loc) 629{ 630 int offset; 631 632 offset = ((insn & 0xf00) >> 4) | (insn & 0xf); 633 if ((insn & 0x004f0000) == 0x004f0000) { 634 /* rA = pc, immediate index */ 635 if (insn & 0x00800000) 636 loc += offset; 637 else 638 loc -= offset; 639 di->di_printaddr(loc + 8); 640 } else { 641 di->di_printf("[r%d", (insn >> 16) & 0x0f); 642 if ((insn & 0x01400f0f) != 0x01400000) { 643 di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]"); 644 if (!(insn & 0x00800000)) 645 di->di_printf("-"); 646 if (insn & (1 << 22)) 647 di->di_printf("#0x%02x", offset); 648 else 649 di->di_printf("r%d", (insn & 0x0f)); 650 } 651 if (insn & (1 << 24)) 652 di->di_printf("]"); 653 } 654} 655 656static void 657disasm_insn_ldcstc(const disasm_interface_t *di, u_int insn, u_int loc) 658{ 659 if (((insn >> 8) & 0xf) == 1) 660 di->di_printf("f%d, ", (insn >> 12) & 0x07); 661 else 662 di->di_printf("c%d, ", (insn >> 12) & 0x0f); 663 664 di->di_printf("[r%d", (insn >> 16) & 0x0f); 665 666 di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]"); 667 668 if (!(insn & (1 << 23))) 669 di->di_printf("-"); 670 671 di->di_printf("#0x%03x", (insn & 0xff) << 2); 672 673 if (insn & (1 << 24)) 674 di->di_printf("]"); 675 676 if (insn & (1 << 21)) 677 di->di_printf("!"); 678} 679 680static u_int 681disassemble_readword(u_int address) 682{ 683 return(*((u_int *)address)); 684} 685 686static void 687disassemble_printaddr(u_int address) 688{ 689 printf("0x%08x", address); 690} 691 692static void 693disassemble_printf(const char *fmt, ...) { 694 va_list ap; 695 va_start(ap, fmt); 696 vprintf(fmt, ap); 697 va_end(ap); 698} 699 700static const disasm_interface_t disassemble_di = { 701 disassemble_readword, disassemble_printaddr, disassemble_printf 702}; 703 704void 705disassemble(u_int address) 706{ 707 708 (void)disasm(&disassemble_di, address, 0); 709} 710 711/* End of disassem.c */ 712