| c35a2ef53d0cccd6f924eeba36633220ec67c32e |
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17-Jun-2010 |
Andy McFadden <fadden@android.com> |
Add opcodes for volatile field accesses
This adds instructions for {i,s}{get,put}{,-object}-volatile, for a
total of eight new instructions.
On SMP systems, these instructions will be substituted in for existing
field access instructions, either by dexopt or during just-in-time
verification. Unlike the wide-volatile instructions, these will not be
used at all when the VM is not built for SMP.
(Ideally we'd omit the volatile instruction implementations entirely on
non-SMP builds, but that requires a little work in gen-mterp.py.)
The change defines and implements the opcodes and support methods, but
does not cause them to be used.
Also, changed dvmQuasiAtomicRead64's argument to be const.
Change-Id: I9e44fe881e87f27aa41f6c6e898ec4402cb5493e
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| 7365493ad8d360c1dcf9cd8b6eee62747af01cae |
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09-Jun-2010 |
Carl Shapiro <cshapiro@google.com> |
Remove repeated newlines at the end of files.
Change-Id: I1e3d103a7b932ef21acedb6438c0f26b315df28f
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| de75089fb7216d19e9c22cce4dc62a49513477d3 |
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09-Jun-2010 |
Carl Shapiro <cshapiro@google.com> |
Remove trailing whitespace.
Change-Id: I95534bb2b88eaf48f2329282041118cd034c812b
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| fbdcfb9ea9e2a78f295834424c3f24986ea45dac |
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29-May-2010 |
Brian Carlstrom <bdc@google.com> |
Merge remote branch 'goog/dalvik-dev' into dalvik-dev-to-master
Change-Id: I0c0edb3ebf0d5e040d6bbbf60269fab0deb70ef9
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| 861b33855aff080278ea5125e4372a2d4bf8aef5 |
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06-Mar-2010 |
Andy McFadden <fadden@android.com> |
Make wide-volatile loads and stores atomic.
This implements the four wide-volatile instructions added in a previous
change, and modifies the verifier to substitute the opcodes into the
instruction stream when appropriate.
For mterp, the ARM wide get/put instructions now have conditional code
that replaces ldrd/strd with a call to the quasiatomic functions. The
C version does essentially the same thing. ARMv4T lacks ldrd/stdrd, and
uses separate implementations for the wide field accesses, so those were
updated as well. x86 will just use stubs.
The JIT should punt these to the interpreter.
Change-Id: Ife88559ed1a698c3267d43c454896f6b12081c0f
Also:
- We don't seem to be using the negative widths in the instruction
table. Not sure they're useful anymore.
- Tabs -> spaces in x86-atom throw-verification-error impl.
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| 5387824f19033ed51a945fbc8c2b574998404b3d |
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05-Mar-2010 |
Andy McFadden <fadden@android.com> |
Add instructions for volatile wide fields.
This adds four new instructions for accessing volatile wide fields (long
and double). The JLS requires that such accesses are atomic, but the
VM doesn't otherwise make guarantees about the atomicity of reads and
writes on 64-bit fields.
There are no behavioral changes. This just adds definitions for the new
instructions and a couple of tests. The current implementation is just
the non-volatile form of the instructions or a C stub, but since we're
not generating them it doesn't really matter yet.
Also:
- bumped Dalvik version to 1.3.0
- added a note to the x86-atom TODO list
For bug 1633591.
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| 4abe4014d3fa6fcdaff6869ca1d60de15a72d124 |
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26-Feb-2010 |
Andy McFadden <fadden@android.com> |
Update a few things in x86-atom.
This replaced unuses opcodes EC and EF with C stubs for the breakpoint
and execute-inline/range instructions, which were added after the last
bunch of stuff we rolled out to eclair open-source. I also rebuilt the
"out" dir to pick up the various other changes.
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| 22d404a75a00cda0b0ebed1034c2808ba060b05f |
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07-Apr-2009 |
Johnnie Birch <johnnie.l.birch.jr@intel.com> |
This is a contribution of x86-atom targeted assembly for the fast byte-code interpreter engine. This is an initial contribution with minimal optimizations that target the Intel ATOM processor. We expect to continuously improve this code. It is expected that there will be a discussion on the potential merge of this code and similar efforts (i.e. the mterp/x86 directory first included with cupcake). While this code is intended to target ATOM and not a generic X-86 processor, we were able to show the following improvements over the c-portable interpreter using the simulator build:
Build: TARGET_SIMULATOR: true
TARGET_BUILD_TYPE: release
TARGET_PRODUCT: sim
Environment: Intel(R) Core(TM)2 Quad CPU Q9550 @ 2.83GHz
PI = Portable Interpreter
IA = Fast IA Interpreter
Embedded CaffeineMark: (IA-PI)/PI: Average of 70% improvement on overall score
SPECjbb2000*: (IA-PI)/PI: Average of 37% improvement on raw score
SPECjvm98*: (PI/IA) Speedup: Mtrt: 1.2; Jess: 1.34; Compress: 1.57; Db: 1.46; Jack: 1.28
* SPECjbb2000 - 1 warehouse. Noncompliant - modified to run on Dalvik
* SPECjvm98 - Noncompliant - modified to run on Dalivk
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