1// Copyright 2006-2009 the V8 project authors. All rights reserved.
2// Redistribution and use in source and binary forms, with or without
3// modification, are permitted provided that the following conditions are
4// met:
5//
6//     * Redistributions of source code must retain the above copyright
7//       notice, this list of conditions and the following disclaimer.
8//     * Redistributions in binary form must reproduce the above
9//       copyright notice, this list of conditions and the following
10//       disclaimer in the documentation and/or other materials provided
11//       with the distribution.
12//     * Neither the name of Google Inc. nor the names of its
13//       contributors may be used to endorse or promote products derived
14//       from this software without specific prior written permission.
15//
16// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
28// CPU specific code for arm independent of OS goes here.
29#if defined(__arm__)
30#include <sys/syscall.h>  // for cache flushing.
31#endif
32
33#include "v8.h"
34
35#include "cpu.h"
36#include "macro-assembler.h"
37
38namespace v8 {
39namespace internal {
40
41void CPU::Setup() {
42  CpuFeatures::Probe();
43}
44
45
46void CPU::FlushICache(void* start, size_t size) {
47#if !defined (__arm__)
48  // Not generating ARM instructions for C-code. This means that we are
49  // building an ARM emulator based target. No I$ flushes are necessary.
50  // None of this code ends up in the snapshot so there are no issues
51  // around whether or not to generate the code when building snapshots.
52#else
53  // Ideally, we would call
54  //   syscall(__ARM_NR_cacheflush, start,
55  //           reinterpret_cast<intptr_t>(start) + size, 0);
56  // however, syscall(int, ...) is not supported on all platforms, especially
57  // not when using EABI, so we call the __ARM_NR_cacheflush syscall directly.
58
59  register uint32_t beg asm("a1") = reinterpret_cast<uint32_t>(start);
60  register uint32_t end asm("a2") =
61      reinterpret_cast<uint32_t>(start) + size;
62  register uint32_t flg asm("a3") = 0;
63  #ifdef __ARM_EABI__
64    #if defined (__arm__) && !defined(__thumb__)
65      // __arm__ may be defined in thumb mode.
66      register uint32_t scno asm("r7") = __ARM_NR_cacheflush;
67      asm volatile(
68          "swi 0x0"
69          : "=r" (beg)
70          : "0" (beg), "r" (end), "r" (flg), "r" (scno));
71    #else
72      // r7 is reserved by the EABI in thumb mode.
73      asm volatile(
74      "@   Enter ARM Mode  \n\t"
75          "adr r3, 1f      \n\t"
76          "bx  r3          \n\t"
77          ".ALIGN 4        \n\t"
78          ".ARM            \n"
79      "1:  push {r7}       \n\t"
80          "mov r7, %4      \n\t"
81          "swi 0x0         \n\t"
82          "pop {r7}        \n\t"
83      "@   Enter THUMB Mode\n\t"
84          "adr r3, 2f+1    \n\t"
85          "bx  r3          \n\t"
86          ".THUMB          \n"
87      "2:                  \n\t"
88          : "=r" (beg)
89          : "0" (beg), "r" (end), "r" (flg), "r" (__ARM_NR_cacheflush)
90          : "r3");
91    #endif
92  #else
93    #if defined (__arm__) && !defined(__thumb__)
94      // __arm__ may be defined in thumb mode.
95      asm volatile(
96          "swi %1"
97          : "=r" (beg)
98          : "i" (__ARM_NR_cacheflush), "0" (beg), "r" (end), "r" (flg));
99    #else
100      // Do not use the value of __ARM_NR_cacheflush in the inline assembly
101      // below, because the thumb mode value would be used, which would be
102      // wrong, since we switch to ARM mode before executing the swi instruction
103      asm volatile(
104      "@   Enter ARM Mode  \n\t"
105          "adr r3, 1f      \n\t"
106          "bx  r3          \n\t"
107          ".ALIGN 4        \n\t"
108          ".ARM            \n"
109      "1:  swi 0x9f0002    \n"
110      "@   Enter THUMB Mode\n\t"
111          "adr r3, 2f+1    \n\t"
112          "bx  r3          \n\t"
113          ".THUMB          \n"
114      "2:                  \n\t"
115          : "=r" (beg)
116          : "0" (beg), "r" (end), "r" (flg)
117          : "r3");
118    #endif
119  #endif
120#endif
121}
122
123
124void CPU::DebugBreak() {
125#if !defined (__arm__) || !defined(CAN_USE_ARMV5_INSTRUCTIONS)
126  UNIMPLEMENTED();  // when building ARM emulator target
127#else
128  asm volatile("bkpt 0");
129#endif
130}
131
132} }  // namespace v8::internal
133