| dee83c90bb7bda57f6d0db2d8f9138f411ecdbbc |
|
13-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Also inflate register classes around inline asm.
Now that MI->getRegClassConstraint() can also handle inline assembly,
don't bail when recomputing the register class of a virtual register
used by inline asm.
This fixes PR11078.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141836 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| e27e1ca3c90b69e78242c98a669337f84ccded7f |
|
01-Oct-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move getCommonSubClass() into TRI.
It will soon need the context.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140896 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| 91fb536a345dc268e5b73dbddb9bee4cba87b28f |
|
22-Sep-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a MinNumRegs argument to MRI::constrainRegClass().
The function will refuse to use a register class with fewer registers
than MinNumRegs. This can be used by clients to avoid accidentally
increase register pressure too much.
The default value of MinNumRegs=0 doesn't affect how constrainRegClass()
works.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140339 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| 6d1fd0b979cb88809ebb77a24f4da69e1d67606b |
|
09-Aug-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Move CalculateRegClass to MRI::recomputeRegClass.
This function doesn't have anything to do with spill weights, and MRI
already has functions for manipulating the register class of a virtual
register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137123 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| 73e7dced3892f2abb4344526147d4df0f62aee61 |
|
30-Jul-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add an isSSA() flag to MachineRegisterInfo.
This flag is true from isel to register allocation when the machine
function is required to be in SSA form. The TwoAddressInstructionPass
and PHIElimination passes clear the flag.
The SSA flag wil be used by the machine code verifier to check for SSA
form, and eventually an assertion can enforce it in +Asserts builds.
This will catch the common target error of creating machine code with
multiple defs of a virtual register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136532 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| f46e7e3d7ff56d91572350c45ade83f4deea0139 |
|
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Remove RegClass2VRegMap from MachineRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133967 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| f462e3fac7ac67503657d63dc35330d0b19359b3 |
|
03-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Make it possible to have unallocatable register classes.
Some register classes are only used for instruction operand constraints.
They should never be used for virtual registers. Previously, those
register classes were given an empty allocation order, but now you can
say 'let isAllocatable=0' in the register class definition.
TableGen calculates if a register is part of any allocatable register
class, and makes that information available in TargetRegisterDesc::inAllocatableClass.
The goal here is to eliminate use cases for overriding allocation_order_*
methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132508 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| 68e6beeccc0b9ac2e8d3687a8a5b7d4b172edca1 |
|
22-Feb-2011 |
Devang Patel <dpatel@apple.com> |
Revert r124611 - "Keep track of incoming argument's location while emitting LiveIns."
In other words, do not keep track of argument's location. The debugger (gdb) is not prepared to see line table entries for arguments. For the debugger, "second" line table entry marks beginning of function body.
This requires some coordination with debugger to get this working.
- The debugger needs to be aware of prolog_end attribute attached with line table entries.
- The compiler needs to accurately mark prolog_end in line table entries (at -O0 and at -O1+)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126155 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| e9a7ea68653689966417443b8ac2528c1d9d3ccf |
|
31-Jan-2011 |
Devang Patel <dpatel@apple.com> |
Keep track of incoming argument's location while emitting LiveIns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124611 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| 994c727b5790e5c976e32c75364d78eb9b22a568 |
|
09-Jan-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use IndexedMap for MachineRegisterInfo as well. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123106 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| bf4699c56100a0184bbe4fb53937c7204ca1ceb0 |
|
07-Oct-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add MachineRegisterInfo::constrainRegClass and use it in MachineCSE.
This function is intended to be used when inserting a machine instruction that
trivially restricts the legal registers, like LEA requiring a GR32_NOSP
argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115875 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| 1e1098c6f39590e1e74e5cb3c2a1652d8f3cb16a |
|
11-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace copyRegToReg with COPY everywhere in lib/CodeGen except for FastISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108062 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| fe5e4dabbf05f3b7b8c6d652adb6b500e5dec8cd |
|
25-Jun-2010 |
Dan Gohman <gohman@apple.com> |
Teach EmitLiveInCopies to omit copies for unused virtual registers,
and to clean up unused incoming physregs from the live-in list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106805 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| 71f095b20a2b1710d35b81fced4ae8b2ca1a6f61 |
|
18-Jun-2010 |
Dan Gohman <gohman@apple.com> |
Don't leak RegClass2VRegMap, which is now a new[] array instead of a
std::vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106298 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| a606d955de3b0f777131d74162eb6f11b5f95d75 |
|
18-Jun-2010 |
Dan Gohman <gohman@apple.com> |
Start TargetRegisterClass indices at 0 instead of 1, so that
MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106296 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| 0f9c658558f70ba0017575019adbbd0b0b6b13e5 |
|
29-May-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Remove unused function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105100 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| 701d4d309f892d34428e3078f350d3d28d7d2a94 |
|
29-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Remove schedule-livein-copies. It's not being used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105095 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| 3946043a80a043b3cf43b34bf068feaadc46485b |
|
24-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Avoid adding duplicate function live-in's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104560 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| 49b4589978ca181537c8ae694ac4c8d58d27a09a |
|
13-May-2010 |
Dan Gohman <gohman@apple.com> |
Add a utility function for conservatively clearing kill flags, and make
use of it in MachineCSE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103726 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| 8e8b3cb9371e60b22d1f401ec63a774c6115e98d |
|
11-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Silence warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103508 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| 82b07dc4995d48065bd95affff4d8513a5cad4f2 |
|
11-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Simplify the tracking of used physregs to a bulk bitor followed by a transitive
closure after allocating all blocks.
Add a few more test cases for -regalloc=fast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103500 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| 34dcc6fadca0a1117cdbd0e9b35c991a55b6e556 |
|
06-May-2010 |
Dan Gohman <gohman@apple.com> |
Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
doesn't have to guess.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| 2ad0fcf794924f618a7240741cc14a39be99d0f2 |
|
29-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Replace r102368 with code that's less fragile. This creates DBG_VALUE instructions for function arguments early and insert them after instruction selection is done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102554 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| f48023b3cf80f3a360cfef94b1e0d0084fd5d760 |
|
26-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Insert dbg_value instructions for function entry block liveins (i.e. function arguments).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102368 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| b13033f61c897224a0be2784faa721ff294c5254 |
|
14-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Move the code for initialing the entry block livein set out of
SelectionDAGISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101258 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| 98708260f55cab997a5db77e930a2bd35f4172aa |
|
14-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Move the code for emitting livein copies out of SelectionDAGISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101254 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| 13e73f483ef2ba630962dad3125393292533b756 |
|
13-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Move MachineRegisterInfo's isLiveIn and isLiveOut out of line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101145 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| 1423c70b8f1b1a757c640fac9a17cb015012e8e9 |
|
03-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add MachineRegisterInfo::hasOneUse and hasOneNonDBGUse.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97663 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| 2bf0649e053d1589689d2e4cf32c7bf1e5e6ae12 |
|
26-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Simplify a few more uses of reg_iterator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82812 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| 358dec51804ee52e47ea3a47c9248086e458ad7c |
|
15-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Part 1.
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.
Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0
If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.
- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.
This is work in progress, not yet enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| 90f95f88c6ce09c6744777dc9d140c3c77203b92 |
|
14-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Move register allocation preference (or hint) from LiveInterval to MachineRegisterInfo. This allows more passes to set them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73346 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| 33f1c68cba4e905fdd2bf7d2848c52052d46fbff |
|
15-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Move MachineRegisterInfo::setRegClass out of line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69126 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| 2e3e5bf42742a7421b513829101501f2de6d2b02 |
|
08-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Move createVirtualRegister out-of-line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60684 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| 11a26f3697ea6520022ea6d3fa6a07b3c1b988cd |
|
20-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add a register class -> virtual registers map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57844 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| 03bafaf802579d0c659af6f2bc1ca539ac0704ca |
|
07-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Assert that all MachineInstrs update PhysRegUseDefLists in
their cleanup code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53194 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| 1eb5cf9c7d0b0b04402eddc007b0de414488baf4 |
|
13-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Added debugging routine dumpUses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47042 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| 6f0d024a534af18d9e60b3ea757376cd8a3a980e |
|
10-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Rename MRegisterInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| e138b3dd1ff02d826233482831318708a166ed93 |
|
01-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
switch the register iterator to act more like hte LLVM value iterator: dereferencing
it now returns the machineinstr of the use. To get the operand, use I.getOperand().
Add a new MachineRegisterInfo::replaceRegWith, which is basically like
Value::replaceAllUsesWith.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45482 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| a91a7d594ff1e1503731ca92f72e627bdfd18f3f |
|
01-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Add a trivial but handy function to efficiently return the machine
instruction that defines the specified vreg. Crazy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45480 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| 62ed6b9ade63bf01717ce5274fa11e93e873d245 |
|
01-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Implement automatically updated def/use lists for all MachineInstr register
operands. The lists are currently kept in MachineRegisterInfo, but it does
not yet provide an iterator interface to them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45477 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|
| 84bc5427d6883f73cfeae3da640acd011d35c006 |
|
31-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled. Given this expanded name, we can start
moving other stuff into it. For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.
Update all the clients to match.
This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/MachineRegisterInfo.cpp
|