f39031b360f135ece3bdc86151804dd1f3f51733 |
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05-Aug-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Detect proper register sub-classes. Some instructions require restricted register classes, but most of the time that doesn't affect register allocation. For example, some instructions don't work with the stack pointer, but that is a reserved register anyway. Sometimes it matters, GR32_ABCD only has 4 allocatable registers. For such a proper sub-class, the register allocator should try to enable register class inflation since that makes more registers available for allocation. Make sure only legal super-classes are considered. For example, tGPR is not a proper sub-class in Thumb mode, but in ARM mode it is. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136981 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/RegisterClassInfo.h
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39b5abf507b43da6b92f68b86406e0015ead18e9 |
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18-Jul-2011 |
Frits van Bommel <fvbommel@gmail.com> |
Migrate LLVM and Clang to use the new makeArrayRef(...) functions where previously explicit non-default constructors were used. Mostly mechanical with some manual reformatting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135390 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/RegisterClassInfo.h
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a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576d |
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24-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Starting to refactor Target to separate out code that's needed to fully describe target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/RegisterClassInfo.h
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448ab3ab395ffc9e7fc04d2d6afb41fcac74070d |
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03-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Avoid calling TRI->getAllocatableSet in RAFast. When compiling a program with lots of small functions like 483.xalancbmk, this makes RAFast 11% faster. Add some comments to clarify the difference between unallocatable and reserved registers. It's quite subtle. The fast register allocator depends on EFLAGS' not being allocatable on x86. That way it can completely avoid tracking liveness, and it won't mind when there are multiple uses of a single def. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132514 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/RegisterClassInfo.h
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6edf90b8a7168e53409d161fb8b285094c4c9182 |
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03-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Just use a SmallVector. I was confused whether new uint8_t[] would zero-initialize the returned array, and it seems that so is gcc-4.0. This should fix the test failures on darwin 9. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132500 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/RegisterClassInfo.h
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491a13691d3b30b8288dfc6e01ad6a58f69a4ce6 |
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02-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a RegisterClassInfo class that lazily caches information about register classes. It provides information for each register class that cannot be determined statically, like: - The number of allocatable registers in a class after filtering out the reserved and invalid registers. - The preferred allocation order with registers that overlap callee-saved registers last. - The last callee-saved register that overlaps a given physical register. This information usually doesn't change between functions, so it is reused for compiling multiple functions when possible. The many possible combinations of reserved and callee saves registers makes it unfeasible to compute this information statically in TableGen. Use RegisterClassInfo to count available registers in various heuristics in SimpleRegisterCoalescing, making the pass run 4% faster. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132450 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/RegisterClassInfo.h
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