| 12c7e90d369b4605aac0ddbd252231beacb2aabb |
|
13-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding of Thumb2 shifted register operands with RRX shifts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139606 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 885f1a0c048e07fca56bc256702c58eae50ae71f |
|
13-Sep-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Zap some junk from the ARM instruction descriptions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139575 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| fd92d2e106acfbf13ed29b5d15f3a690cd8699b2 |
|
12-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding of PC-relative LDRSHW with an immediate offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139537 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 08fef885eb39339a47e3be7f0842b1db33683003 |
|
10-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139422 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| b6aed508e310e31dcb080e761ca856127cec0773 |
|
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| a77295db19527503d6b290e4f34f273d0a789365 |
|
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRD(immediate).
Refactor operand handling for STRD as well. Tests for that forthcoming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 721cb1fde07423fd1905338d443172a8028ad634 |
|
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding for tBcc with immediate offset operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138889 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 559c277aa9242dd5b32d2f2ccc353d938f886ee9 |
|
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix roundtripping of Thumb BL/BLX instructions with immediate offsets instead of labels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138874 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 21df36c57afc588c8073a070a47e3ba45fa87270 |
|
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding of CBZ/CBNZ Thumb2 instructions with immediate offsets rather than labels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138837 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| a7710edd98d71a81c43f8e3889cf0c790885d1b8 |
|
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding of PC-relative Thumb1 LDR's when using immediate offsets instead of labels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138835 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 391ac65377f2ad5e48a796e75120959e22430605 |
|
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding of Thumb1 B instructions with immediate offsets, which is necessary for round-tripping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138834 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 10096dbdef22a10a6a4444437c935ab428545525 |
|
30-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Clean up whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138833 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 0da10cf44d0f22111dae728bb535ade2283d976b |
|
29-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Improve handling of #-0 offsets for many more pre-indexed addressing modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138754 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| f1eab597b2316c6cfcabfcee98895fedb2071722 |
|
27-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138675 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| d7568e1c355f5e364eddafc15c6d5553559f32a5 |
|
27-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Correct encoding of BL with immediate offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138673 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 96425c846494c1c20a4c931f4783571295ab170c |
|
26-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 70939ee1415722d7f39f13faf9b3644b96007996 |
|
17-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM clean up the imm_sr operand class representation.
Represent the operand value as it will be encoded in the instruction. This
allows removing the specialized encoder and decoder methods entirely. Add
an assembler match class while we're at it to lay groundwork for parsing the
thumb shift instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137879 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 3dac0bec7e7874ffb378385b6160bd2117184ca9 |
|
11-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 6d74631062e4464326eb5c680a4d62d340fa42eb |
|
08-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix encodings for Thumb ASR and LSR immediate operands. They encode the range 1-32, with 32 encoded as 0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137062 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 16578b50889329eb62774148091ba0f38b681a09 |
|
05-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM simplify the postidx_reg operand encoding.
The immediate portion of the operand is just a boolean (the 'U' bit indicating
add vs. subtract). Treat it as such.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136969 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 7ce057983ea7b8ad42d5cca1bb5d3f6941662269 |
|
04-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM refactoring assembly parsing of memory address operands.
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.
The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.
This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.
Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 354712c5a506449676e6fcac6b623af4092e7100 |
|
28-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Update comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136367 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 5de728cfe1a922ac9b13546dca94526b2fa693b6 |
|
28-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.
This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.
rdar://8204588
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136292 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| fb8989e64024547e4ad5ab6fe4d94fe146a7899f |
|
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding of SBFX and UBFX.
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136264 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| 85bfd3b023d4d70936006eadd86588b03e5f40c0 |
|
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM cleanup of rot_imm encoding.
Start of cleaning this up a bit. First step is to remove the encoder hook by
storing the operand as the bits it'll actually encode to so it can just be
directly used. Map it to the assembly source values 8/16/24 when we print it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136152 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|
| be74029f44c32efc09274a16cbff588ad10dc5ea |
|
23-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink ARM mc routines into MCTargetDesc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135825 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
|