Searched defs:RC (Results 1 - 25 of 102) sorted by relevance

12345

/external/llvm/lib/Target/CellSPU/
H A DSPURegisterInfo.h54 virtual unsigned getRegPressureLimit( const TargetRegisterClass *RC, argument
95 const TargetRegisterClass *RC,
H A DSPUFrameLowering.cpp251 const TargetRegisterClass *RC = &SPU::R32CRegClass; local
252 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
253 RC->getAlignment(),
H A DSPURegisterInfo.cpp347 const TargetRegisterClass *RC,
351 unsigned Reg = RS->FindUnusedReg(RC);
353 Reg = RS->scavengeRegister(RC, II, SPAdj);
345 findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, const TargetRegisterClass *RC, int SPAdj) const argument
/external/llvm/lib/CodeGen/
H A DAllocationOrder.cpp29 const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg); local
45 TRI.getRawAllocationOrder(RC, HintPair.first, Hint,
65 ArrayRef<unsigned> O = RCI.getOrder(RC);
72 !RC->contains(Hint) || RCI.isReserved(Hint)))
H A DLiveStackAnalysis.cpp55 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { argument
61 S2RCMap.insert(std::make_pair(Slot, RC));
65 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC);
77 const TargetRegisterClass *RC = getIntervalRegClass(Slot); local
78 if (RC)
79 OS << " [" << RC->getName() << "]\n";
H A DAggressiveAntiDepBreaker.h44 /// RC - The register class
45 const TargetRegisterClass *RC; member in struct:llvm::AggressiveAntiDepState::__anon6601
H A DExecutionDepsFix.cpp110 const TargetRegisterClass *const RC; member in class:__anon6615::ExeDepsFix
124 : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {}
457 assert(NumRegs == RC->getNumRegs() && "Bad regclass");
462 for (TargetRegisterClass::const_iterator I = RC->begin(), E = RC->end();
472 // Given a PhysReg, AliasMap[PhysReg] is either the relevant index into RC,
475 for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i)
476 for (const unsigned *AI = TRI->getOverlaps(RC->getRegister(i)); *AI; ++AI)
521 llvm::createExecutionDependencyFixPass(const TargetRegisterClass *RC) {
[all...]
H A DMachineRegisterInfo.cpp46 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { argument
47 VRegInfo[Reg].first = RC;
52 const TargetRegisterClass *RC,
55 if (OldRC == RC)
56 return RC;
57 const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC);
51 constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs) argument
H A DProcessImplicitDefs.cpp276 const TargetRegisterClass* RC = MRI->getRegClass(Reg); local
277 unsigned NewVReg = MRI->createVirtualRegister(RC);
H A DCriticalAntiDepBreaker.cpp386 const TargetRegisterClass *RC)
388 ArrayRef<unsigned> Order = RegClassInfo.getOrder(RC);
597 const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg] : 0; local
598 assert((AntiDepReg == 0 || RC != NULL) &&
600 if (RC == reinterpret_cast<TargetRegisterClass *>(-1))
614 RC)) {
382 findSuitableFreeRegister(RegRefIter RegRefBegin, RegRefIter RegRefEnd, unsigned AntiDepReg, unsigned LastNewReg, const TargetRegisterClass *RC) argument
H A DLocalStackSlotAllocation.cpp321 const TargetRegisterClass *RC = TRI->getPointerRegClass(); local
322 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
/external/llvm/lib/Target/Blackfin/
H A DBlackfinFrameLowering.cpp122 const TargetRegisterClass *RC = BF::DPRegisterClass; local
126 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
127 RC->getAlignment(),
H A DBlackfinISelDAGToDAG.cpp119 static inline bool isCC(const TargetRegisterClass *RC) { argument
120 return BF::AnyCCRegClass.hasSubClassEq(RC);
123 static inline bool isDCC(const TargetRegisterClass *RC) { argument
124 return BF::DRegClass.hasSubClassEq(RC) || isCC(RC);
H A DBlackfinInstrInfo.cpp162 const TargetRegisterClass *RC) {
166 return Test.hasSubClassEq(RC);
175 const TargetRegisterClass *RC,
179 if (inClass(BF::DPRegClass, SrcReg, RC)) {
187 if (inClass(BF::D16RegClass, SrcReg, RC)) {
195 if (inClass(BF::AnyCCRegClass, SrcReg, RC)) {
204 RC->getName()).c_str());
212 const TargetRegisterClass *RC,
222 const TargetRegisterClass *RC,
225 if (inClass(BF::DPRegClass, DestReg, RC)) {
160 inClass(const TargetRegisterClass &Test, unsigned Reg, const TargetRegisterClass *RC) argument
170 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
208 storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const argument
218 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
250 loadRegFromAddr(MachineFunction &MF, unsigned DestReg, SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const argument
[all...]
H A DBlackfinRegisterInfo.cpp180 const TargetRegisterClass *RC,
183 unsigned Reg = RS->FindUnusedReg(RC);
185 Reg = RS->scavengeRegister(RC, II, SPAdj);
178 findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, const TargetRegisterClass *RC, int SPAdj) argument
/external/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp48 const TargetRegisterClass *RC,
50 assert((RC == ARM::tGPRRegisterClass ||
54 if (RC == ARM::tGPRRegisterClass ||
77 const TargetRegisterClass *RC,
79 assert((RC == ARM::tGPRRegisterClass ||
83 if (RC == ARM::tGPRRegisterClass ||
46 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
75 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
H A DThumb2InstrInfo.cpp122 const TargetRegisterClass *RC,
124 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
125 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass ||
126 RC == ARM::GPRnopcRegisterClass) {
144 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
150 const TargetRegisterClass *RC,
152 if (RC == ARM::GPRRegisterClass || RC
120 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
148 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
[all...]
/external/llvm/lib/Target/
H A DTargetRegisterInfo.cpp62 const TargetRegisterClass* RC = *I; local
63 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
64 (!BestRC || BestRC->hasSubClass(RC)))
65 BestRC = RC;
75 const TargetRegisterClass *RC, BitVector &R){
76 ArrayRef<unsigned> Order = RC->getRawAllocationOrder(MF);
82 const TargetRegisterClass *RC) const {
84 if (RC) {
85 getAllocatableSetForRC(MF, RC, Allocatabl
74 getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R) argument
[all...]
/external/dropbear/libtomcrypt/src/ciphers/
H A Dnoekeon.c33 static const ulong32 RC[] = { variable
129 a ^= RC[i]; \
141 a ^= RC[16];
185 a ^= RC[i]; \
197 a ^= RC[0];
/external/llvm/lib/Target/Alpha/
H A DAlphaInstrInfo.cpp146 const TargetRegisterClass *RC,
155 if (RC == Alpha::F4RCRegisterClass)
159 else if (RC == Alpha::F8RCRegisterClass)
163 else if (RC == Alpha::GPRCRegisterClass)
175 const TargetRegisterClass *RC,
182 if (RC == Alpha::F4RCRegisterClass)
185 else if (RC == Alpha::F8RCRegisterClass)
188 else if (RC == Alpha::GPRCRegisterClass)
143 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
172 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
/external/llvm/lib/Target/MBlaze/
H A DMBlazeInstrInfo.cpp95 const TargetRegisterClass *RC,
105 const TargetRegisterClass *RC,
93 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
103 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
/external/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp38 const TargetRegisterClass *RC,
52 if (RC == &MSP430::GR16RegClass)
56 else if (RC == &MSP430::GR8RegClass)
67 const TargetRegisterClass *RC,
81 if (RC == &MSP430::GR16RegClass)
84 else if (RC == &MSP430::GR8RegClass)
35 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
64 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
/external/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp289 const TargetRegisterClass *RC,
295 if (RC == SP::IntRegsRegisterClass)
298 else if (RC == SP::FPRegsRegisterClass)
301 else if (RC == SP::DFPRegsRegisterClass)
311 const TargetRegisterClass *RC,
316 if (RC == SP::IntRegsRegisterClass)
318 else if (RC == SP::FPRegsRegisterClass)
320 else if (RC == SP::DFPRegsRegisterClass)
287 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
309 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
/external/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp46 const TargetRegisterClass *RC,
52 if (RC == &SystemZ::GR32RegClass ||
53 RC == &SystemZ::ADDR32RegClass)
55 else if (RC == &SystemZ::GR64RegClass ||
56 RC == &SystemZ::ADDR64RegClass) {
58 } else if (RC == &SystemZ::FP32RegClass) {
60 } else if (RC == &SystemZ::FP64RegClass) {
62 } else if (RC == &SystemZ::GR64PRegClass) {
64 } else if (RC == &SystemZ::GR128RegClass) {
76 const TargetRegisterClass *RC,
43 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
73 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
[all...]
/external/llvm/utils/TableGen/
H A DFastISelEmitter.cpp36 const CodeGenRegisterClass *RC; member in struct:__anon7231::InstructionMemo
250 const CodeGenRegisterClass *RC = 0;
254 RC = &Target.getRegisterClass(OpLeafRec);
256 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec);
261 if (!RC)
267 if (DstRC != RC && !DstRC->hasSubClass(RC))
270 DstRC = RC;
643 OS << InstNS << Memo.RC->getName() << "RegisterClass";
735 OS << InstNS << Memo.RC
[all...]

Completed in 1629 milliseconds

12345