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Searched defs:Insn (Results 1 - 5 of 5) sorted by relevance

/external/llvm/utils/TableGen/
H A D	PseudoLoweringEmitter.cpp	`27 addDagOperandMapping(Record Rec, DagInit Dag, CodeGenInstruction &Insn, argument 46 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) 50 Insn.Operands[BaseIdx + i].Rec->getName() + "'"); 54 for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I) 56 OpsAdded += Insn.Operands[i].MINumOperands; 65 addDagOperandMapping(Rec, SubDag, Insn, OperandMap, BaseIdx + i); 93 CodeGenInstruction Insn(Operator); 95 if (Insn.isCodeGenOnly \|\| Insn.isPseudo) 99 if (Insn [all...]`
H A D	ARMDecoderEmitter.cpp	424 void insnWithID(insn_t &Insn, unsigned Opcode) const { argument 431 Insn[i] = bitFromBits(Bits, i); 437 Insn[21] = BIT_TRUE; 450 bool fieldFromInsn(uint64_t &Field, insn_t &Insn, unsigned StartBit, 479 insn_t &Insn); 558 insn_t Insn; local 561 Owner->insnWithID(Insn, Owner->Opcodes[i]); 565 bool ok = Owner->fieldFromInsn(Field, Insn, StartBit, NumBits); 853 bool ARMFilterChooser::fieldFromInsn(uint64_t &Field, insn_t &Insn, argument 858 if (Insn[StartBi 933 getIslands(std::vector<unsigned> &StartBits, std::vector<unsigned> &EndBits, std::vector<uint64_t> &FieldVals, insn_t &Insn) argument 998 insn_t Insn; local 1117 insn_t Insn; local [all...]
H A D	FixedLenDecoderEmitter.cpp	285 void insnWithID(insn_t &Insn, unsigned Opcode) const { argument 289 Insn.push_back(bitFromBits(Bits, i)); 302 bool fieldFromInsn(uint64_t &Field, insn_t &Insn, unsigned StartBit, 331 insn_t &Insn); 396 insn_t Insn; local 399 Owner->insnWithID(Insn, Owner->Opcodes[i]); 403 bool ok = Owner->fieldFromInsn(Field, Insn, StartBit, NumBits); 603 bool FilterChooser::fieldFromInsn(uint64_t &Field, insn_t &Insn, argument 608 if (Insn[StartBit + i] == BIT_UNSET) 611 if (Insn[StartBi 683 getIslands(std::vector<unsigned> &StartBits, std::vector<unsigned> &EndBits, std::vector<uint64_t> &FieldVals, insn_t &Insn) argument 812 insn_t Insn; local 956 insn_t Insn; local [all...]
/external/llvm/lib/Transforms/Scalar/
H A D	CodeGenPrepare.cpp	`235 Instruction Insn = dyn_cast<Instruction>(UPN->getIncomingValue(I)); local 236 if (Insn && Insn->getParent() == BB && 237 Insn->getParent() != UPN->getIncomingBlock(I)) 1154 Instruction Insn = BI; ++BI; local 1155 DbgValueInst *DVI = dyn_cast<DbgValueInst>(Insn); 1157 PrevNonDbgInst = Insn;`
/external/llvm/lib/Target/ARM/Disassembler/
H A D	ARMDisassembler.cpp	143 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn, 145 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, 148 unsigned Insn, 151 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn, 153 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn, 155 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn, 157 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn, 161 unsigned Insn, 164 static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 166 static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, 1181 DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 1326 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 1470 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 1581 DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 1610 DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 1695 DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 1735 DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 1775 DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 1799 DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 1825 DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 1898 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 1945 DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 2194 DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 2444 DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 2483 DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 2519 DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 2554 DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 2607 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 2652 DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 2695 DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 2726 DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn, uint64_t Address, const void Decoder) argument 2832 DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 2970 DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3015 DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn, uint64_t Address, const void Decoder) argument 3026 DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn, uint64_t Address, const void Decoder) argument 3051 DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn, uint64_t Address, const void Decoder) argument 3062 DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3094 DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3110 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3223 DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3246 DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3273 DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3298 DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3326 DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3351 DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3376 DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3435 DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3493 DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3560 DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3624 DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3694 DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3758 DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3832 DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3897 DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3923 DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3949 DecodeIT(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 3976 DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 4013 DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn, uint64_t Address, const void Decoder) argument 4047 DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn, uint64_t Address, const void *Decoder) argument [all...]

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