Searched defs:OpNum (Results 1 - 18 of 18) sorted by relevance

/external/llvm/lib/Target/MSP430/
H A DMSP430AsmPrinter.cpp49 void printOperand(const MachineInstr *MI, int OpNum,
51 void printSrcMemOperand(const MachineInstr *MI, int OpNum,
64 void MSP430AsmPrinter::printOperand(const MachineInstr *MI, int OpNum, argument
66 const MachineOperand &MO = MI->getOperand(OpNum);
111 void MSP430AsmPrinter::printSrcMemOperand(const MachineInstr *MI, int OpNum, argument
113 const MachineOperand &Base = MI->getOperand(OpNum);
114 const MachineOperand &Disp = MI->getOperand(OpNum+1);
121 printOperand(MI, OpNum+1, O, "nohash");
126 printOperand(MI, OpNum, O);
/external/llvm/lib/Target/SystemZ/
H A DSystemZAsmPrinter.cpp46 void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
48 void printPCRelImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
49 void printRIAddrOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
51 void printRRIAddrOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
53 void printS16ImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O) { argument
54 O << (int16_t)MI->getOperand(OpNum).getImm();
56 void printU16ImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O) { argument
57 O << (uint16_t)MI->getOperand(OpNum).getImm();
59 void printS32ImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O) { argument
60 O << (int32_t)MI->getOperand(OpNum)
62 printU32ImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O) argument
82 printPCRelImmOperand(const MachineInstr *MI, int OpNum, raw_ostream &O) argument
121 printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O, const char *Modifier) argument
180 printRIAddrOperand(const MachineInstr *MI, int OpNum, raw_ostream &O, const char *Modifier) argument
196 printRRIAddrOperand(const MachineInstr *MI, int OpNum, raw_ostream &O, const char *Modifier) argument
[all...]
/external/llvm/lib/Target/
H A DTargetInstrInfo.cpp31 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, argument
33 if (OpNum >= MCID.getNumOperands())
36 short RegClass = MCID.OpInfo[OpNum].RegClass;
37 if (MCID.OpInfo[OpNum].isLookupPtrRegClass())
/external/llvm/lib/Target/Mips/
H A DMipsAsmPrinter.cpp298 unsigned OpNum, unsigned AsmVariant,
304 const MachineOperand &MO = MI->getOperand(OpNum);
297 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument
/external/llvm/utils/PerfectShuffle/
H A DPerfectShuffle.cpp106 unsigned short OpNum; member in struct:Operator
112 : ShuffleMask(shufflemask), OpNum(opnum), Name(name), Cost(cost) {
394 unsigned OpNum = ShufTab[i].Op ? ShufTab[i].Op->OpNum : 0;
395 assert(OpNum < 16 && "Too few bits to encode operation!");
402 unsigned Val = (CostSat << 30) | (OpNum << 26) | (LHS << 13) | RHS;
/external/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp63 unsigned OpNum) {
64 unsigned SrcReg = MI.getOperand(OpNum).getReg();
65 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
62 getVEXRegisterEncoding(const MCInst &MI, unsigned OpNum) argument
/external/llvm/include/llvm/MC/
H A DMCInstrDesc.h149 int getOperandConstraint(unsigned OpNum, argument
151 if (OpNum < NumOperands &&
152 (OpInfo[OpNum].Constraints & (1 << Constraint))) {
154 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
/external/llvm/lib/CodeGen/
H A DRegAllocFast.cpp75 unsigned short LastOpNum; // OpNum on LastUse.
164 LiveRegMap::iterator defineVirtReg(MachineInstr *MI, unsigned OpNum,
166 LiveRegMap::iterator reloadVirtReg(MachineInstr *MI, unsigned OpNum,
169 bool setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg);
541 RAFast::defineVirtReg(MachineInstr *MI, unsigned OpNum, argument
567 LR.LastOpNum = OpNum;
575 RAFast::reloadVirtReg(MachineInstr *MI, unsigned OpNum, argument
583 MachineOperand &MO = MI->getOperand(OpNum);
619 LR.LastOpNum = OpNum;
624 // setPhysReg - Change operand OpNum i
627 setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg) argument
[all...]
/external/llvm/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp224 void ARMInstPrinter::printT2LdrLabelOperand(const MCInst *MI, unsigned OpNum, argument
226 const MCOperand &MO1 = MI->getOperand(OpNum);
240 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum, argument
242 const MCOperand &MO1 = MI->getOperand(OpNum);
243 const MCOperand &MO2 = MI->getOperand(OpNum+1);
244 const MCOperand &MO3 = MI->getOperand(OpNum+2);
258 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum, argument
260 const MCOperand &MO1 = MI->getOperand(OpNum);
261 const MCOperand &MO2 = MI->getOperand(OpNum+1);
367 unsigned OpNum,
366 printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
446 printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
464 printPostIdxImm8Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
472 printPostIdxRegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
480 printPostIdxImm8s4Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
489 printLdStmModeOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
496 printAddrMode5Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
518 printAddrMode6Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
531 printAddrMode7Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
537 printAddrMode6OffsetOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
547 printBitfieldInvMaskImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
558 printMemBOption(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
564 printShiftImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
575 printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
584 printPKHASRShiftImm(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
594 printRegisterList(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
604 printSetendOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
613 printCPSIMod(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
619 printCPSIFlag(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
631 printMSRMaskOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
684 printPredicateOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
691 printMandatoryPredicateOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
698 printSBitModifierOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
707 printNoHashImmediate(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
712 printPImmediate(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
717 printCImmediate(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
722 printCoprocOptionImm(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
727 printPCLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
732 printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
737 printThumbSRImm(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
743 printThumbITMask(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
820 printT2SOOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
836 printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O) argument
[all...]
/external/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp327 unsigned OpNum = 3; // First 'rest' of operands. local
365 OpNum = 4;
386 OpNum = 0;
395 OpNum = 2;
403 OpNum = 0;
410 OpNum = 2;
460 for (unsigned e = MI->getNumOperands(); OpNum != e; ++OpNum)
461 MIB.addOperand(MI->getOperand(OpNum));
H A DARMAsmPrinter.cpp313 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, argument
315 const MachineOperand &MO = MI->getOperand(OpNum);
401 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, argument
411 if (MI->getOperand(OpNum).isReg()) {
413 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
419 if (!MI->getOperand(OpNum).isImm())
421 O << MI->getOperand(OpNum).getImm();
425 printOperand(MI, OpNum, O);
431 if (MI->getOperand(OpNum).isReg()) {
432 unsigned Reg = MI->getOperand(OpNum)
512 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument
900 int OpNum = 1; local
949 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1; local
[all...]
H A DARMISelLowering.cpp4234 unsigned OpNum = (PFEntry >> 26) & 0x0F; local
4256 if (OpNum == OP_COPY) {
4267 switch (OpNum) {
4285 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
4291 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
4295 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
4299 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
4303 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp261 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
263 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
265 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
267 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1180 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, argument
1182 const MCOperand &MO1 = MI.getOperand(OpNum);
1183 const MCOperand &MO2 = MI.getOperand(OpNum+1);
1184 const MCOperand &MO3 = MI.getOperand(OpNum+2);
1198 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, argument
1200 const MCOperand &MO1 = MI.getOperand(OpNum);
1219 getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups) const argument
1235 getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups) const argument
[all...]
/external/llvm/lib/Bitcode/Reader/
H A DBitcodeReader.cpp2162 unsigned OpNum = 0; local
2164 if (getValueTypePair(Record, OpNum, NextValueNo, LHS) ||
2165 getValue(Record, OpNum, LHS->getType(), RHS) ||
2166 OpNum+1 > Record.size())
2169 int Opc = GetDecodedBinaryOpcode(Record[OpNum++], LHS->getType());
2173 if (OpNum < Record.size()) {
2178 if (Record[OpNum] & (1 << bitc::OBO_NO_SIGNED_WRAP))
2180 if (Record[OpNum] & (1 << bitc::OBO_NO_UNSIGNED_WRAP))
2186 if (Record[OpNum] & (1 << bitc::PEO_EXACT))
2193 unsigned OpNum local
2209 unsigned OpNum = 0; local
2231 unsigned OpNum = 0; local
2252 unsigned OpNum = 0; local
2277 unsigned OpNum = 0; local
2292 unsigned OpNum = 0; local
2317 unsigned OpNum = 0; local
2328 unsigned OpNum = 0; local
2341 unsigned OpNum = 0; local
2361 unsigned OpNum = 0; local
2385 unsigned OpNum = 0; local
2471 unsigned OpNum = 4; local
2600 unsigned OpNum = 0; local
2612 unsigned OpNum = 0; local
2633 unsigned OpNum = 0; local
2647 unsigned OpNum = 0; local
2670 unsigned OpNum = 0; local
2690 unsigned OpNum = 0; local
2730 unsigned OpNum = 2; local
[all...]
/external/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp2850 unsigned OpNum = Ops[0]; local
2860 if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2862 } else if (OpNum == 0) { // If operand 0
2871 } else if (OpNum == 1) {
2873 } else if (OpNum == 2) {
H A DX86ISelLowering.cpp4600 unsigned OpNum = (Index == 0) ? 1 : 0; local
4601 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG,
4693 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4696 int OpIdx, int NumElems, unsigned &OpNum) {
4716 OpNum = SeenV1 ? 0 : 1;
4695 isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE, int OpIdx, int NumElems, unsigned &OpNum) argument
/external/llvm/lib/Transforms/Scalar/
H A DGVN.cpp1900 unsigned OpNum = UI.getOperandNo(); local
1904 User->setOperand(OpNum, To);
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp4119 unsigned OpNum = (PFEntry >> 26) & 0x0F; local
4136 if (OpNum == OP_COPY) {
4147 switch (OpNum) {

Completed in 567 milliseconds