Searched refs:OpIdx (Results 1 - 21 of 21) sorted by relevance

/external/llvm/include/llvm/Analysis/
H A DConstantsScanner.h28 unsigned OpIdx; // Operand index member in class:llvm::constant_iterator
33 assert(!InstI.atEnd() && OpIdx < InstI->getNumOperands() &&
35 return isa<Constant>(InstI->getOperand(OpIdx));
39 inline constant_iterator(const Function *F) : InstI(inst_begin(F)), OpIdx(0) {
47 : InstI(inst_end(F)), OpIdx(0) {
50 inline bool operator==(const _Self& x) const { return OpIdx == x.OpIdx &&
56 return cast<Constant>(InstI->getOperand(OpIdx));
61 ++OpIdx;
64 while (OpIdx < NumOperand
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/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp78 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
81 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
87 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
92 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
96 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
100 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
104 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
109 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
114 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
119 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
165 getLdStmModeOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
431 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const argument
459 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, unsigned FixupKind, SmallVectorImpl<MCFixup> &Fixups) argument
496 getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
508 getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
519 getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
530 getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
541 getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
569 getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
582 getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
597 getARMBLXTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
614 getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
637 getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
656 getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
673 getThumbAdrLabelOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
685 getThumbAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &) const argument
699 getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
747 getT2Imm8s4OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
778 getT2AddrModeImm8s4OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
818 getT2AddrModeImm0_1020s4OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
843 getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
891 getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
920 getAddrMode2OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
934 getAddrMode2OffsetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
956 getPostIdxRegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
967 getAddrMode3OffsetOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
986 getAddrMode3OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
1009 getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
1024 getAddrModeISOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
1038 getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
1048 getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
1086 getSORegRegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
1133 getSORegImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
1251 getT2SORegOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups) const argument
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/external/llvm/lib/Target/ARM/
H A DARMCodeEmitter.cpp103 unsigned OpIdx);
156 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
157 return getMachineOpValue(MI, MI.getOperand(OpIdx));
249 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
251 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
291 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
293 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
295 uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx)
297 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
1009 unsigned OpIdx) {
1006 getMachineSoRegOpValue(const MachineInstr &MI, const MCInstrDesc &MCID, const MachineOperand &MO, unsigned OpIdx) argument
1107 unsigned OpIdx = 0; local
1215 unsigned OpIdx = 0; local
1286 unsigned OpIdx = 0; local
1376 unsigned OpIdx = 0; local
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H A DARMExpandPseudoInsts.cpp419 unsigned OpIdx = 0; local
421 bool DstIsDead = MI.getOperand(OpIdx).isDead();
422 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
433 MIB.addOperand(MI.getOperand(OpIdx++));
436 MIB.addOperand(MI.getOperand(OpIdx++));
437 MIB.addOperand(MI.getOperand(OpIdx++));
440 MIB.addOperand(MI.getOperand(OpIdx++));
447 SrcOpIdx = OpIdx++;
450 MIB.addOperand(MI.getOperand(OpIdx++));
451 MIB.addOperand(MI.getOperand(OpIdx
483 unsigned OpIdx = 0; local
532 unsigned OpIdx = 0; local
613 unsigned OpIdx = 0; local
977 unsigned OpIdx = 0; local
1007 unsigned OpIdx = 0; local
1038 unsigned OpIdx = 0; local
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H A DARMBaseInstrInfo.cpp1957 unsigned OpIdx = Commute ? 2 : 1;
1958 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
1959 bool isKill = UseMI->getOperand(OpIdx).isKill();
/external/llvm/include/llvm/CodeGen/
H A DProcessImplicitDefs.h34 unsigned OpIdx,
H A DMachineInstr.h393 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
394 /// getOperand(OpIdx) does not belong to an inline asm operand group.
397 /// containing OpIdx.
402 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = 0) const;
405 /// operand OpIdx. For normal instructions, this is derived from the
412 getRegClassConstraint(unsigned OpIdx,
/external/llvm/utils/TableGen/
H A DCodeEmitterGen.cpp107 unsigned OpIdx; local
108 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) {
110 OpIdx = CGI.Operands[OpIdx].MIOperandNo;
111 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) &&
118 OpIdx = NumberedOp++;
121 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx);
132 " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx);
139 " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")";
H A DCodeGenInstruction.cpp135 unsigned OpIdx; local
136 if (hasOperandNamed(Name, OpIdx)) return OpIdx;
142 /// given name. If so, return true and set OpIdx to the index of the
144 bool CGIOperandList::hasOperandNamed(StringRef Name, unsigned &OpIdx) const {
148 OpIdx = i;
171 unsigned OpIdx = getOperandNamed(OpName); local
175 if (OperandList[OpIdx].MINumOperands > 1 && !AllowWholeOp &&
181 return std::make_pair(OpIdx, 0U);
185 DagInit *MIOpInfo = OperandList[OpIdx]
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H A DCodeGenInstruction.h159 /// given name. If so, return true and set OpIdx to the index of the
161 bool hasOperandNamed(StringRef Name, unsigned &OpIdx) const;
/external/llvm/lib/CodeGen/
H A DProcessImplicitDefs.cpp49 unsigned Reg, unsigned OpIdx,
51 switch(OpIdx) {
263 unsigned OpIdx = Ops[j]; local
264 RMI->RemoveOperand(OpIdx-j);
48 CanTurnIntoImplicitDef(MachineInstr *MI, unsigned Reg, unsigned OpIdx, SmallSet<unsigned, 8> &ImpDefRegs) argument
H A DMachineInstr.cpp829 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx, argument
832 assert(OpIdx < getNumOperands() && "OpIdx out of range");
835 if (OpIdx < InlineAsm::MIOp_FirstOperand)
847 if (i + NumOps > OpIdx) {
858 MachineInstr::getRegClassConstraint(unsigned OpIdx,
863 return TII->getRegClass(getDesc(), OpIdx, TRI);
865 if (!getOperand(OpIdx).isReg())
870 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx,
1600 unsigned OpIdx = DeadOps.back(); local
1652 unsigned OpIdx = DeadOps.back(); local
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H A DDwarfEHPrepare.cpp190 unsigned OpIdx = Sel->getNumArgOperands() - 1; local
191 GlobalVariable *GV = dyn_cast<GlobalVariable>(Sel->getArgOperand(OpIdx));
193 Sel->setArgOperand(OpIdx, EHCatchAllValue->getInitializer());
H A DLiveIntervalAnalysis.cpp1056 unsigned OpIdx = Ops[i]; local
1057 MachineOperand &MO = MI->getOperand(OpIdx);
1065 if (MI->isRegTiedToDefOperand(OpIdx)) {
1071 FoldOps.push_back(OpIdx);
H A DMachineLICM.cpp230 unsigned Reg, unsigned OpIdx,
669 unsigned Reg, unsigned OpIdx,
668 getRegisterClassIDAndCost(const MachineInstr *MI, unsigned Reg, unsigned OpIdx, unsigned &RCId, unsigned &RCCost) const argument
H A DRegisterCoalescer.cpp724 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false); local
725 NewMI->getOperand(OpIdx).setIsKill();
/external/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.h104 unsigned OpIdx, SDep& dep) const;
H A DScheduleDAGSDNodes.cpp579 unsigned OpIdx, SDep& dep) const{
587 unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
590 OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs();
591 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
578 ComputeOperandLatency(SDNode *Def, SDNode *Use, unsigned OpIdx, SDep& dep) const argument
H A DLegalizeVectorTypes.cpp1418 for (unsigned i = 0, OpIdx = Idx+1; i < NumToInsert; i++, OpIdx++) {
1420 ConcatOps[OpIdx], DAG.getIntPtrConstant(i));
/external/llvm/lib/Target/MBlaze/MCTargetDesc/
H A DMBlazeMCCodeEmitter.cpp51 unsigned getMachineOpValue(const MCInst &MI, unsigned OpIdx) const {
52 return getMachineOpValue(MI, MI.getOperand(OpIdx));
/external/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp4693 /// starting from its index OpIdx. Also tell OpNum which source vector operand.
4696 int OpIdx, int NumElems, unsigned &OpNum) {
4700 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) {
4712 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2))
4695 isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE, int OpIdx, int NumElems, unsigned &OpNum) argument

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