Searched refs:Reg2 (Results 1 - 13 of 13) sorted by relevance

/external/llvm/lib/Target/SystemZ/
H A DSystemZInstrBuilder.h84 unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2) {
86 .addReg(Reg2, getKillRegState(isKill2));
83 addRegReg(const MachineInstrBuilder &MIB, unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2) argument
/external/llvm/lib/CodeGen/
H A DTargetInstrInfoImpl.cpp79 unsigned Reg2 = MI->getOperand(Idx2).getReg(); local
87 Reg0 = Reg2;
88 } else if (HasDef && Reg0 == Reg2 &&
101 .addReg(Reg2, getKillRegState(Reg2IsKill))
105 .addReg(Reg2, getKillRegState(Reg2IsKill))
112 MI->getOperand(Idx1).setReg(Reg2);
H A DAggressiveAntiDepBreaker.h101 // UnionGroups - Union Reg1's and Reg2's groups to form a new
104 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
H A DAggressiveAntiDepBreaker.cpp80 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) argument
87 unsigned Group2 = GetGroup(Reg2);
H A DStrongPHIElimination.cpp441 void StrongPHIElimination::unionRegs(unsigned Reg1, unsigned Reg2) { argument
443 Node *Node2 = RegNodeMap[Reg2]->getLeader();
/external/llvm/include/llvm/MC/
H A DMCRegisterInfo.h85 bool contains(unsigned Reg1, unsigned Reg2) const {
86 return contains(Reg1) && contains(Reg2);
/external/llvm/lib/Target/X86/
H A DX86InstrBuilder.h117 unsigned Reg2, bool isKill2) {
119 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
115 addRegReg(const MachineInstrBuilder &MIB, unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2) argument
H A DX86FastISel.cpp1472 unsigned Reg2 = getRegForValue(Op2); local
1474 if (Reg1 == 0 || Reg2 == 0)
1490 .addReg(Reg1).addReg(Reg2);
/external/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp620 CodeGenRegister *Reg2 = i1->second; local
622 if (Reg1 == Reg2)
624 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs();
631 if (Reg2 == Reg3)
714 CodeGenRegister *Reg2 = getReg(RegList[i2]); local
715 CodeGenRegister::Set &Overlaps2 = Map[Reg2];
716 const CodeGenRegister::SuperRegList &Supers2 = Reg2->getSuperRegs();
717 // Reg overlaps Reg2 which implies it overlaps supers(Reg2).
718 Overlaps.insert(Reg2);
[all...]
/external/llvm/include/llvm/Target/
H A DTargetRegisterInfo.h86 bool contains(unsigned Reg1, unsigned Reg2) const {
87 return MC->contains(Reg1, Reg2);
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp127 unsigned Reg2 = MI->getOperand(2).getReg(); local
147 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
151 .addReg(Reg2, getKillRegState(Reg2IsKill))
158 MI->getOperand(0).setReg(Reg2);
160 MI->getOperand(1).setReg(Reg2);
/external/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp607 unsigned Reg2 = MI->getOperand(2).getReg(); local
608 if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
/external/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp1776 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); local
1777 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2298 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(), local
2300 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);

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