4a0a18af4a9a47466a6077a158387ba4f57bf636 |
|
01-Sep-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Permit remat of partial register defs when it is safe. An instruction may define part of a register where the other bits are undefined. In that case, it is safe to rematerialize the instruction. For example: %vreg2:ssub_0<def> = VLDRS <cp#0>, 0, pred:14, pred:%noreg, %vreg2<imp-def> The extra <imp-def> operand indicates that the instruction does not read the other parts of the virtual register, so a remat is safe. This patch simply allows multiple def operands for the virtual register. It is MI->readsVirtualRegister() that determines if we depend on a previous value so remat is impossible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138953 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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9d548d0343774636e72713d678a078c8e808ed29 |
|
01-Sep-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Prevent remat of partial register redefinitions. An instruction that redefines only part of a larger register can never be rematerialized since the virtual register value depends on the old value in other parts of the register. This was fixed for the inline spiller in r138794. This patch fixes the problem for all register allocators, and includes a small test case. <rdar://problem/10032939> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138944 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
|
cb08f18d5b88ffa4ba8efd7cac0b8820d6f0ec71 |
|
23-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Follow up to Jim's r138278. This fixes commuteInstruction so it handles two-address instructions correctly. I'll let Jim add a test case. :-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138289 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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2df3f58a0b3937f2cbd76d3417d2905ca86cf8fa |
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08-Aug-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Hoist hasLoadFromStackSlot and hasStoreToStackSlot. These the methods are target-independent since they simply scan the memory operands. They can live in TargetInstrInfoImpl. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137063 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
|
e837dead3c8dc3445ef6a0e2322179c57e264a13 |
|
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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fa226bccaa90c520cac154df74069bbabb976eab |
|
02-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use TRI::has{Sub,Super}ClassEq() where possible. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132455 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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08c5a347a05e73a34c70ec8b694b1e89b96a6bf5 |
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21-Apr-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Permit remat when a virtual register has multiple defs. TII::isTriviallyReMaterializable() shouldn't depend on any properties of the register being defined by the instruction. Rematerialization is going to create a new virtual register anyway. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129882 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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c8bfd1d78ff9a307d1d4cb57cce4549b538e60f4 |
|
21-Jan-2011 |
Andrew Trick <atrick@apple.com> |
Convert -enable-sched-cycles and -enable-sched-hazard to -disable flags. They are still not enable in this revision. Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with the scheduler's model of operand latency in the selection DAG. Generalized unit tests to work with sched-cycles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123969 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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9fe2009956fc40f3aea46fb3c38dcfb61c4aca46 |
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20-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sorry, several patches in one. TargetInstrInfo: Change produceSameValue() to take MachineRegisterInfo as an optional argument. When in SSA form, targets can use it to make more aggressive equality analysis. Machine LICM: 1. Eliminate isLoadFromConstantMemory, use MI.isInvariantLoad instead. 2. Fix a bug which prevent CSE of instructions which are not re-materializable. 3. Use improved form of produceSameValue. ARM: 1. Teach ARM produceSameValue to look pass some PIC labels. 2. Look for operands from different loads of different constant pool entries which have same values. 3. Re-implement PIC GA materialization using movw + movt. Combine the pair with a "add pc" or "ldr [pc]" to form pseudo instructions. This makes it possible to re-materialize the instruction, allow machine LICM to hoist the set of instructions out of the loop and make it possible to CSE them. It's a bit hacky, but it significantly improve code quality. 4. Some minor bug fixes as well. With the fixes, using movw + movt to materialize GAs significantly outperform the load from constantpool method. 186.crafty and 255.vortex improved > 20%, 254.gap and 176.gcc ~10%. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123905 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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c36b7069b42bece963b7e6adf020353ce990ef76 |
|
08-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Do not model all INLINEASM instructions as having unmodelled side effects. Instead encode llvm IR level property "HasSideEffects" in an operand (shared with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check the operand when the instruction is an INLINEASM. This allows memory instructions to be moved around INLINEASM instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123044 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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2da8bc8a5f7705ac131184cd247f48500da0d74e |
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24-Dec-2010 |
Andrew Trick <atrick@apple.com> |
Various bits of framework needed for precise machine-level selection DAG scheduling during isel. Most new functionality is currently guarded by -enable-sched-cycles and -enable-sched-hazard. Added InstrItineraryData::IssueWidth field, currently derived from ARM itineraries, but could be initialized differently on other targets. Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is active, and if so how many cycles of state it holds. Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry into the scheduler's available queue. ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to get information about it's SUnits, provides RecedeCycle for bottom-up scheduling, correctly computes scoreboard depth, tracks IssueCount, and considers potential stall cycles when checking for hazards. ScheduleDAGRRList now models machine cycles and hazards (under flags). It tracks MinAvailableCycle, drives the hazard recognizer and priority queue's ready filter, manages a new PendingQueue, properly accounts for stall cycles, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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6b1207267f01877ff9b351786c902cb2ecd354c0 |
|
08-Dec-2010 |
Andrew Trick <atrick@apple.com> |
Generalize PostRAHazardRecognizer so it can be used in any pass for both forward and backward scheduling. Rename it to ScoreboardHazardRecognizer (Scoreboard is one word). Remove integer division from the scoreboard's critical path. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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93a95ae8a9d8eb19dc0d90281473be2fb1c05a17 |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
force clients of MachineFunction::getMachineMemOperand to provide a MachinePointerInfo, propagating the type out a level of API. Remove the old MachineFunction::getMachineMemOperand impl. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114393 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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3ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1 |
|
10-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Teach if-converter to be more careful with predicating instructions that would take multiple cycles to decode. For the current if-converter clients (actually only ARM), the instructions that are predicated on false are not nops. They would still take machine cycles to decode. Micro-coded instructions such as LDM / STM can potentially take multiple cycles to decode. If-converter should take treat them as non-micro-coded simple instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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134d8eec8789184c7a7290ee101ca3d6f62f384a |
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22-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
remove the JIT "NeedsExactSize" feature and supporting logic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109167 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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9fac4159ddf65d90ebcccd80a0ba513cd8e95be1 |
|
13-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Don't add memory operands to storeRegToStackSlot / loadRegFromStackSlot results, they already have one. This fixes the himenobmtxpa miscompilation on ARM. The PostRA scheduler got confused by the double memoperand and hoisted a stack slot load above a store to the same slot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108219 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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744b3a5acdbd4d0fac9c6a7c9ad702502cc3cc37 |
|
11-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove TargetInstrInfo::copyRegToReg entirely. Targets must now implement TargetInstrInfo::copyPhysReg instead. There is no longer a default implementation forwarding to copyRegToReg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108095 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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1f32340d95ac480bfc74bcfd00fd5cffbe078652 |
|
09-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Automatically fold COPY instructions into stack load/store. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108012 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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e05442d50806e2850eae1571958816028093df85 |
|
09-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Change TII::foldMemoryOperand API to require the machine instruction to be inserted in a MBB, and return an already inserted MI. This target API change is necessary to allow foldMemoryOperand to call storeToStackSlot and loadFromStackSlot when folding a COPY to a stack slot reference in a target independent way. The foldMemoryOperandImpl hook is going to change in the same way, but I'll wait until COPY folding is actually implemented. Most targets only fold copies and won't need to specialize this hook at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107991 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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3651d92d91062ea4b1ee8b2a88eca03bd39e1968 |
|
08-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add TargetInstrInfo::copyPhysReg hook and use it from LowerSubregs. This target hook is intended to replace copyRegToReg entirely, but for now it calls copyRegToReg. Any remaining calls to copyRegToReg wil be replaced by COPY instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107854 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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4d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855 |
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22-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Tail merging pass shall not break up IT blocks. rdar://8115404 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106517 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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86050dc8cc0aaea8c9dfeb89de02cafbd7f48d92 |
|
19-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Allow ARM if-converter to be run after post allocation scheduling. - This fixed a number of bugs in if-converter, tail merging, and post-allocation scheduler. If-converter now runs branch folding / tail merging first to maximize if-conversion opportunities. - Also changed the t2IT instruction slightly. It now defines the ITSTATE register which is read by instructions in the IT block. - Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't change the instruction ordering in the IT block (since IT mask has been finalized). It also ensures no other instructions can be scheduled between instructions in the IT block. This is not yet enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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774bc882fdb3bbb0558075360c6e5bc510a0bdad |
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14-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Do away with SimpleHazardRecognizer.h. It's not used and offers little value. - Rename ExactHazardRecognizer to PostRAHazardRecognizer and move its header to include to allow targets to extend it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105959 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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44acc24117b1a9eafb7b9b993731ca0115569ea2 |
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12-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Code formatting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105861 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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9edf7deb37f0f97664f279040fa15d89f32e23d9 |
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03-Jun-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Slightly change the meaning of the reMaterialize target hook when the original instruction defines subregisters. Any existing subreg indices on the original instruction are preserved or composed with the new subreg index. Also substitute multiple operands mentioning the original register by using the new MachineInstr::substituteRegister() function. This is necessary because there will soon be <imp-def> operands added to non read-modify-write partial definitions. This instruction: %reg1234:foo = FLAP %reg1234<imp-def> will reMaterialize(%reg3333, bar) like this: %reg3333:bar-foo = FLAP %reg333:bar<imp-def> Finally, replace the TargetRegisterInfo pointer argument with a reference to indicate that it cannot be NULL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105358 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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75361b69f3f327842b9dad69fa7f28ae3b688412 |
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08-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
rename llvm::llvm_report_error -> llvm::report_fatal_error git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100709 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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506049f29f4f202a8e45feb916cc0264440a7f6d |
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03-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Change MachineInstr::isIdenticalTo to take a new option that determines whether it should skip checking defs or at least virtual register defs. This subsumes part of the TargetInstrInfo::isIdentical functionality. - Eliminate TargetInstrInfo::isIdentical and replace it with produceSameValue. In the default case, produceSameValue just checks whether two machine instructions are identical (except for virtual register defs). But targets may override it to check for unusual cases (e.g. ARM pic loads from constant pools). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97628 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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30ac0467ced4627a9b84d8a1d3ca5e8706ddad63 |
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07-Jan-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add Target hook to duplicate machine instructions. Some instructions refer to unique labels, and so cannot be trivially cloned with CloneMachineInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92873 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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7896c9f436a4eda5ec15e882a7505ba482a2fcd0 |
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03-Dec-2009 |
Chris Lattner <sabre@nondot.org> |
improve portability to avoid conflicting with std::next in c++'0x. Patch by Howard Hinnant! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90365 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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39aa7251a27735479305b3e7a9629b9c2a6abcc3 |
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16-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Check if subreg index is zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88899 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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d57cdd5683ea926e489067364fb7ffe5fd5d35ee |
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14-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo. - If destination is a physical register and it has a subreg index, use the sub-register instead. This fixes PR5423. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88745 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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78e5c1140adc926e7c004748c1c912bfddd875b4 |
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07-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical except it doesn't care if the definitions' virtual registers differ. This is used by machine LICM and other MI passes to perform CSE. - Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical. Since pc relative constantpool entries are always different, this requires it it check if the values can actually the same. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86328 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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ff89dcb06fbd103373436e2d0ae85f252fae2254 |
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18-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
-Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed stack slots and giving them different PseudoSourceValue's did not fix the problem of post-alloc scheduling miscompiling llvm itself. - Apply Dan's conservative workaround by assuming any non fixed stack slots can alias other memory locations. This means a load from spill slot #1 cannot move above a store of spill slot #2. - Enable post-alloc scheduling for x86 at optimization leverl Default and above. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84424 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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20270c909357e5e501cac1f5393430dfacfc57d8 |
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18-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Only fixed stack objects and spill slots should be get FixedStack PseudoSourceValue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84411 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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6553155172a2e74feff1253837daa608123de54a |
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17-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Revert 84315 for now. Re-thinking the patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84321 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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bf125583f8bd8196a34921276add7f304b7c1433 |
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17-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Rename getFixedStack to getStackObject. The stack objects represented are not necessarily fixed. Only those will negative frame indices are "fixed." git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84315 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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3a6b9eb868f579b945aa8ec8fadf65e4dd913555 |
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12-Oct-2009 |
Dale Johannesen <dalej@apple.com> |
Revert the kludge in 76703. I got a clean bootstrap of FSF-style PPC, so there is some reason to believe the original bug (which was never analyzed) has been fixed, probably by 82266. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83871 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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a70dca156fa76d452f54829b5c5f962ddfd94ef2 |
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10-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Factor out LiveIntervalAnalysis' code to determine whether an instruction is trivially rematerializable and integrate it into TargetInstrInfo::isTriviallyReMaterializable. This way, all places that need to know whether an instruction is rematerializable will get the same answer. This enables the useful parts of the aggressive-remat option by default -- using AliasAnalysis to determine whether a memory location is invariant, and removes the questionable parts -- rematting operations with virtual register inputs that may not be live everywhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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c76909abfec876c6b751d693ebd3df07df686aa0 |
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25-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Improve MachineMemOperand handling. - Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions. This eliminates MachineInstr's std::list member and allows the data to be created by isel and live for the remainder of codegen, avoiding a lot of copying and unnecessary translation. This also shrinks MemSDNode. - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated fields for MachineMemOperands. - Change MemSDNode to have a MachineMemOperand member instead of its own fields with the same information. This introduces some redundancy, but it's more consistent with what MachineInstr will eventually want. - Ignore alignment when searching for redundant loads for CSE, but remember the greatest alignment. Target-specific code which previously used MemOperandSDNodes with generic SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range so that the SelectionDAG framework knows that MachineMemOperand information is available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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28f02fdd76f4efc05d14649e0eec90ce8e71e17e |
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21-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Change MachineMemOperand's alignment value to be the alignment of the base pointer, without the offset. This matches MemSDNode's new alignment behavior, and holds more interesting information. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82473 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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fc6ad402fb267cba1625801444aad30da43d383a |
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22-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Let each target determines whether a machine instruction is dead. If true, that allows late codeine passes to delete it. This is considered a workaround. The problem is some targets are not modeling side effects correctly. PPC is apparently one of those. This patch allows ppc llvm-gcc to bootstrap on Darwin. Once we find out which instruction definitions are wrong, we can remove the PPCInstrInfo workaround. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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378445303b10b092a898a75131141a8259cff50b |
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16-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Let callers decide the sub-register index on the def operand of rematerialized instructions. Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75900 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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34c75093f085c7958fa3bd31f3c4a50942d83505 |
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11-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use findCommutedOpIndices to find the operands to commute. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75312 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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261ce1d5f89155d2e6f914f281db2004c89ee839 |
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10-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove TargetInstrInfo::CommuteChangesDestination and added findCommutedOpIndices which returns the operand indices which are swapped (when applicable). This allows for some code clean up and future enhancements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75264 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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498c2903e28b56b73b8056335ad7f1eb6347b8ed |
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01-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
CommuteChangesDestination() should check if to-be-commuted instruction defines any register. Also teaches the default commuteInstruction() to commute instruction without definitions (e.g. X86::test / ARM::tsp). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74602 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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587daedce2d6c2b2d380b6a5843a6f8b6cfc79e4 |
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13-May-2009 |
Bill Wendling <isanbard@gmail.com> |
Change MachineInstrBuilder::addReg() to take a flag instead of a list of booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71722 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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d62e06c53b8b7e555617dc9b24b98c007d63de5d |
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03-Feb-2009 |
Bill Wendling <isanbard@gmail.com> |
Explicitly pass in debug location information to BuildMI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63599 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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c54baa2d43730f1804acfb4f4e738fba72f966bd |
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03-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Split foldMemoryOperand into public non-virtual and protected virtual parts, and add target-independent code to add/preserve MachineMemOperands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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d735b8019b0f297d7c14b55adcd887af24d8e602 |
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03-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Switch the MachineOperand accessors back to the short names like isReg, etc., from isRegister, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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014278e6a11fa0767853b831e5bf51b95bf541c5 |
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13-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Remove isImm(), isReg(), and friends, in favor of isImmediate(), isRegister(), and friends, to avoid confusion about having two different names with the same meaning. I'm not attached to the longer names, and would be ok with changing to the shorter names if others prefer it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56189 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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3885578a36072dd55c3381b99d4a88299dddbfa3 |
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11-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix a 80 column violation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56097 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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44eb65cf58e3ab9b5621ce72256d1621a18aeed7 |
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15-Aug-2008 |
Owen Anderson <resistor@mac.com> |
Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54802 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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8e5f2c6f65841542e2a7092553fe42a00048e4c7 |
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08-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Pool-allocation for MachineInstrs, MachineBasicBlocks, and MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53212 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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58dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6 |
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16-Jun-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add option to commuteInstruction() which forces it to create a new (commuted) instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52308 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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52e724ad7e679ee590f4bd763d55280586a8f1bc |
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16-Apr-2008 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49809 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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ca1267c02b025cc719190b05f9e1a5d174a9caf7 |
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31-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48995 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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f20db159541bf27f5d2fdf8d4ba1c8b270b936df |
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15-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Added CommuteChangesDestination(). This returns true if commuting the specified machine instr will change its definition register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47166 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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9cec00e7f1dec7c3142d81c1256d198afa3718d3 |
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13-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Simplify. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47058 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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a4d16a1f0dcdd1ab2862737105f900e2c577532d |
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13-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
commuteInstr() can now commute non-ssa machine instrs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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749c6f6b5ed301c84aac562e414486549d7b98eb |
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07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename TargetInstrDescriptor -> TargetInstrDesc. Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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8ca5c67c6e95fdcf5ddb2f06586873c843dd0cde |
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07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Add predicates methods to TargetOperandInfo, and switch all clients over to using them, instead of diddling Flags directly. Change the various flags from const variables to enums. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45677 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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69244300b8a0112efb44b6273ecea4ca6264b8cf |
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07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects that it is cheap and efficient to get. Move a variety of predicates from TargetInstrInfo into TargetInstrDescriptor, which makes it much easier to query a predicate when you don't have TII around. Now you can use MI->getDesc()->isBranch() instead of going through TII, and this is much more efficient anyway. Not all of the predicates have been moved over yet. Update old code that used MI->getInstrDescriptor()->Flags to use the new predicates in many places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45674 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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641055225092833197efe8e5bce01d50bcf1daae |
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01-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Fix a problem where lib/Target/TargetInstrInfo.h would include and use a header file from libcodegen. This violates a layering order: codegen depends on target, not the other way around. The fix to this is to split TII into two classes, TII and TargetInstrInfoImpl, which defines stuff that depends on libcodegen. It is defined in libcodegen, where the base is not. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45475 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
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