TargetInstrInfoImpl.cpp revision 8e5f2c6f65841542e2a7092553fe42a00048e4c7 
1//===-- TargetInstrInfoImpl.cpp - Target Instruction Information ----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the TargetInstrInfoImpl class, it just provides default
11// implementations of various methods.
12//
13//===----------------------------------------------------------------------===//
14
15#include "llvm/Target/TargetInstrInfo.h"
16#include "llvm/CodeGen/MachineInstr.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18using namespace llvm;
19
20// commuteInstruction - The default implementation of this method just exchanges
21// operand 1 and 2.
22MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI,
23                                                      bool NewMI) const {
24  assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
25         "This only knows how to commute register operands so far");
26  unsigned Reg1 = MI->getOperand(1).getReg();
27  unsigned Reg2 = MI->getOperand(2).getReg();
28  bool Reg1IsKill = MI->getOperand(1).isKill();
29  bool Reg2IsKill = MI->getOperand(2).isKill();
30  bool ChangeReg0 = false;
31  if (MI->getOperand(0).getReg() == Reg1) {
32    // Must be two address instruction!
33    assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
34           "Expecting a two-address instruction!");
35    Reg2IsKill = false;
36    ChangeReg0 = true;
37  }
38
39  if (NewMI) {
40    // Create a new instruction.
41    unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
42    bool Reg0IsDead = MI->getOperand(0).isDead();
43    MachineFunction &MF = *MI->getParent()->getParent();
44    return BuildMI(MF, MI->getDesc())
45      .addReg(Reg0, true, false, false, Reg0IsDead)
46      .addReg(Reg2, false, false, Reg2IsKill)
47      .addReg(Reg1, false, false, Reg1IsKill);
48  }
49
50  if (ChangeReg0)
51    MI->getOperand(0).setReg(Reg2);
52  MI->getOperand(2).setReg(Reg1);
53  MI->getOperand(1).setReg(Reg2);
54  MI->getOperand(2).setIsKill(Reg1IsKill);
55  MI->getOperand(1).setIsKill(Reg2IsKill);
56  return MI;
57}
58
59/// CommuteChangesDestination - Return true if commuting the specified
60/// instruction will also changes the destination operand. Also return the
61/// current operand index of the would be new destination register by
62/// reference. This can happen when the commutable instruction is also a
63/// two-address instruction.
64bool TargetInstrInfoImpl::CommuteChangesDestination(MachineInstr *MI,
65                                                    unsigned &OpIdx) const{
66  assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
67         "This only knows how to commute register operands so far");
68  if (MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
69    // Must be two address instruction!
70    assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
71           "Expecting a two-address instruction!");
72    OpIdx = 2;
73    return true;
74  }
75  return false;
76}
77
78
79bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
80                                const std::vector<MachineOperand> &Pred) const {
81  bool MadeChange = false;
82  const TargetInstrDesc &TID = MI->getDesc();
83  if (!TID.isPredicable())
84    return false;
85
86  for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
87    if (TID.OpInfo[i].isPredicate()) {
88      MachineOperand &MO = MI->getOperand(i);
89      if (MO.isReg()) {
90        MO.setReg(Pred[j].getReg());
91        MadeChange = true;
92      } else if (MO.isImm()) {
93        MO.setImm(Pred[j].getImm());
94        MadeChange = true;
95      } else if (MO.isMBB()) {
96        MO.setMBB(Pred[j].getMBB());
97        MadeChange = true;
98      }
99      ++j;
100    }
101  }
102  return MadeChange;
103}
104
105void TargetInstrInfoImpl::reMaterialize(MachineBasicBlock &MBB,
106                                        MachineBasicBlock::iterator I,
107                                        unsigned DestReg,
108                                        const MachineInstr *Orig) const {
109  MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
110  MI->getOperand(0).setReg(DestReg);
111  MBB.insert(I, MI);
112}
113
114unsigned
115TargetInstrInfoImpl::GetFunctionSizeInBytes(const MachineFunction &MF) const {
116  unsigned FnSize = 0;
117  for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
118       MBBI != E; ++MBBI) {
119    const MachineBasicBlock &MBB = *MBBI;
120    for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end(); I != E; ++I)
121      FnSize += GetInstSizeInBytes(I);
122  }
123  return FnSize;
124}
125