TargetInstrInfoImpl.cpp revision 774bc882fdb3bbb0558075360c6e5bc510a0bdad 
1//===-- TargetInstrInfoImpl.cpp - Target Instruction Information ----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the TargetInstrInfoImpl class, it just provides default
11// implementations of various methods.
12//
13//===----------------------------------------------------------------------===//
14
15#include "llvm/Target/TargetInstrInfo.h"
16#include "llvm/Target/TargetMachine.h"
17#include "llvm/Target/TargetRegisterInfo.h"
18#include "llvm/ADT/SmallVector.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineInstr.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineMemOperand.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
24#include "llvm/CodeGen/PostRAHazardRecognizer.h"
25#include "llvm/CodeGen/PseudoSourceValue.h"
26#include "llvm/Support/ErrorHandling.h"
27#include "llvm/Support/raw_ostream.h"
28using namespace llvm;
29
30// commuteInstruction - The default implementation of this method just exchanges
31// the two operands returned by findCommutedOpIndices.
32MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI,
33                                                      bool NewMI) const {
34  const TargetInstrDesc &TID = MI->getDesc();
35  bool HasDef = TID.getNumDefs();
36  if (HasDef && !MI->getOperand(0).isReg())
37    // No idea how to commute this instruction. Target should implement its own.
38    return 0;
39  unsigned Idx1, Idx2;
40  if (!findCommutedOpIndices(MI, Idx1, Idx2)) {
41    std::string msg;
42    raw_string_ostream Msg(msg);
43    Msg << "Don't know how to commute: " << *MI;
44    report_fatal_error(Msg.str());
45  }
46
47  assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
48         "This only knows how to commute register operands so far");
49  unsigned Reg1 = MI->getOperand(Idx1).getReg();
50  unsigned Reg2 = MI->getOperand(Idx2).getReg();
51  bool Reg1IsKill = MI->getOperand(Idx1).isKill();
52  bool Reg2IsKill = MI->getOperand(Idx2).isKill();
53  bool ChangeReg0 = false;
54  if (HasDef && MI->getOperand(0).getReg() == Reg1) {
55    // Must be two address instruction!
56    assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
57           "Expecting a two-address instruction!");
58    Reg2IsKill = false;
59    ChangeReg0 = true;
60  }
61
62  if (NewMI) {
63    // Create a new instruction.
64    unsigned Reg0 = HasDef
65      ? (ChangeReg0 ? Reg2 : MI->getOperand(0).getReg()) : 0;
66    bool Reg0IsDead = HasDef ? MI->getOperand(0).isDead() : false;
67    MachineFunction &MF = *MI->getParent()->getParent();
68    if (HasDef)
69      return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
70        .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
71        .addReg(Reg2, getKillRegState(Reg2IsKill))
72        .addReg(Reg1, getKillRegState(Reg2IsKill));
73    else
74      return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
75        .addReg(Reg2, getKillRegState(Reg2IsKill))
76        .addReg(Reg1, getKillRegState(Reg2IsKill));
77  }
78
79  if (ChangeReg0)
80    MI->getOperand(0).setReg(Reg2);
81  MI->getOperand(Idx2).setReg(Reg1);
82  MI->getOperand(Idx1).setReg(Reg2);
83  MI->getOperand(Idx2).setIsKill(Reg1IsKill);
84  MI->getOperand(Idx1).setIsKill(Reg2IsKill);
85  return MI;
86}
87
88/// findCommutedOpIndices - If specified MI is commutable, return the two
89/// operand indices that would swap value. Return true if the instruction
90/// is not in a form which this routine understands.
91bool TargetInstrInfoImpl::findCommutedOpIndices(MachineInstr *MI,
92                                                unsigned &SrcOpIdx1,
93                                                unsigned &SrcOpIdx2) const {
94  const TargetInstrDesc &TID = MI->getDesc();
95  if (!TID.isCommutable())
96    return false;
97  // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this
98  // is not true, then the target must implement this.
99  SrcOpIdx1 = TID.getNumDefs();
100  SrcOpIdx2 = SrcOpIdx1 + 1;
101  if (!MI->getOperand(SrcOpIdx1).isReg() ||
102      !MI->getOperand(SrcOpIdx2).isReg())
103    // No idea.
104    return false;
105  return true;
106}
107
108
109bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
110                            const SmallVectorImpl<MachineOperand> &Pred) const {
111  bool MadeChange = false;
112  const TargetInstrDesc &TID = MI->getDesc();
113  if (!TID.isPredicable())
114    return false;
115
116  for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
117    if (TID.OpInfo[i].isPredicate()) {
118      MachineOperand &MO = MI->getOperand(i);
119      if (MO.isReg()) {
120        MO.setReg(Pred[j].getReg());
121        MadeChange = true;
122      } else if (MO.isImm()) {
123        MO.setImm(Pred[j].getImm());
124        MadeChange = true;
125      } else if (MO.isMBB()) {
126        MO.setMBB(Pred[j].getMBB());
127        MadeChange = true;
128      }
129      ++j;
130    }
131  }
132  return MadeChange;
133}
134
135void TargetInstrInfoImpl::reMaterialize(MachineBasicBlock &MBB,
136                                        MachineBasicBlock::iterator I,
137                                        unsigned DestReg,
138                                        unsigned SubIdx,
139                                        const MachineInstr *Orig,
140                                        const TargetRegisterInfo &TRI) const {
141  MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
142  MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
143  MBB.insert(I, MI);
144}
145
146bool TargetInstrInfoImpl::produceSameValue(const MachineInstr *MI0,
147                                           const MachineInstr *MI1) const {
148  return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
149}
150
151MachineInstr *TargetInstrInfoImpl::duplicate(MachineInstr *Orig,
152                                             MachineFunction &MF) const {
153  assert(!Orig->getDesc().isNotDuplicable() &&
154         "Instruction cannot be duplicated");
155  return MF.CloneMachineInstr(Orig);
156}
157
158unsigned
159TargetInstrInfoImpl::GetFunctionSizeInBytes(const MachineFunction &MF) const {
160  unsigned FnSize = 0;
161  for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
162       MBBI != E; ++MBBI) {
163    const MachineBasicBlock &MBB = *MBBI;
164    for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
165         I != E; ++I)
166      FnSize += GetInstSizeInBytes(I);
167  }
168  return FnSize;
169}
170
171/// foldMemoryOperand - Attempt to fold a load or store of the specified stack
172/// slot into the specified machine instruction for the specified operand(s).
173/// If this is possible, a new instruction is returned with the specified
174/// operand folded, otherwise NULL is returned. The client is responsible for
175/// removing the old instruction and adding the new one in the instruction
176/// stream.
177MachineInstr*
178TargetInstrInfo::foldMemoryOperand(MachineFunction &MF,
179                                   MachineInstr* MI,
180                                   const SmallVectorImpl<unsigned> &Ops,
181                                   int FrameIndex) const {
182  unsigned Flags = 0;
183  for (unsigned i = 0, e = Ops.size(); i != e; ++i)
184    if (MI->getOperand(Ops[i]).isDef())
185      Flags |= MachineMemOperand::MOStore;
186    else
187      Flags |= MachineMemOperand::MOLoad;
188
189  // Ask the target to do the actual folding.
190  MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, FrameIndex);
191  if (!NewMI) return 0;
192
193  assert((!(Flags & MachineMemOperand::MOStore) ||
194          NewMI->getDesc().mayStore()) &&
195         "Folded a def to a non-store!");
196  assert((!(Flags & MachineMemOperand::MOLoad) ||
197          NewMI->getDesc().mayLoad()) &&
198         "Folded a use to a non-load!");
199  const MachineFrameInfo &MFI = *MF.getFrameInfo();
200  assert(MFI.getObjectOffset(FrameIndex) != -1);
201  MachineMemOperand *MMO =
202    MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIndex),
203                            Flags, /*Offset=*/0,
204                            MFI.getObjectSize(FrameIndex),
205                            MFI.getObjectAlignment(FrameIndex));
206  NewMI->addMemOperand(MF, MMO);
207
208  return NewMI;
209}
210
211/// foldMemoryOperand - Same as the previous version except it allows folding
212/// of any load and store from / to any address, not just from a specific
213/// stack slot.
214MachineInstr*
215TargetInstrInfo::foldMemoryOperand(MachineFunction &MF,
216                                   MachineInstr* MI,
217                                   const SmallVectorImpl<unsigned> &Ops,
218                                   MachineInstr* LoadMI) const {
219  assert(LoadMI->getDesc().canFoldAsLoad() && "LoadMI isn't foldable!");
220#ifndef NDEBUG
221  for (unsigned i = 0, e = Ops.size(); i != e; ++i)
222    assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!");
223#endif
224
225  // Ask the target to do the actual folding.
226  MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, LoadMI);
227  if (!NewMI) return 0;
228
229  // Copy the memoperands from the load to the folded instruction.
230  NewMI->setMemRefs(LoadMI->memoperands_begin(),
231                    LoadMI->memoperands_end());
232
233  return NewMI;
234}
235
236bool TargetInstrInfo::
237isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
238                                         AliasAnalysis *AA) const {
239  const MachineFunction &MF = *MI->getParent()->getParent();
240  const MachineRegisterInfo &MRI = MF.getRegInfo();
241  const TargetMachine &TM = MF.getTarget();
242  const TargetInstrInfo &TII = *TM.getInstrInfo();
243  const TargetRegisterInfo &TRI = *TM.getRegisterInfo();
244
245  // A load from a fixed stack slot can be rematerialized. This may be
246  // redundant with subsequent checks, but it's target-independent,
247  // simple, and a common case.
248  int FrameIdx = 0;
249  if (TII.isLoadFromStackSlot(MI, FrameIdx) &&
250      MF.getFrameInfo()->isImmutableObjectIndex(FrameIdx))
251    return true;
252
253  const TargetInstrDesc &TID = MI->getDesc();
254
255  // Avoid instructions obviously unsafe for remat.
256  if (TID.hasUnmodeledSideEffects() || TID.isNotDuplicable() ||
257      TID.mayStore())
258    return false;
259
260  // Avoid instructions which load from potentially varying memory.
261  if (TID.mayLoad() && !MI->isInvariantLoad(AA))
262    return false;
263
264  // If any of the registers accessed are non-constant, conservatively assume
265  // the instruction is not rematerializable.
266  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
267    const MachineOperand &MO = MI->getOperand(i);
268    if (!MO.isReg()) continue;
269    unsigned Reg = MO.getReg();
270    if (Reg == 0)
271      continue;
272
273    // Check for a well-behaved physical register.
274    if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
275      if (MO.isUse()) {
276        // If the physreg has no defs anywhere, it's just an ambient register
277        // and we can freely move its uses. Alternatively, if it's allocatable,
278        // it could get allocated to something with a def during allocation.
279        if (!MRI.def_empty(Reg))
280          return false;
281        BitVector AllocatableRegs = TRI.getAllocatableSet(MF, 0);
282        if (AllocatableRegs.test(Reg))
283          return false;
284        // Check for a def among the register's aliases too.
285        for (const unsigned *Alias = TRI.getAliasSet(Reg); *Alias; ++Alias) {
286          unsigned AliasReg = *Alias;
287          if (!MRI.def_empty(AliasReg))
288            return false;
289          if (AllocatableRegs.test(AliasReg))
290            return false;
291        }
292      } else {
293        // A physreg def. We can't remat it.
294        return false;
295      }
296      continue;
297    }
298
299    // Only allow one virtual-register def, and that in the first operand.
300    if (MO.isDef() != (i == 0))
301      return false;
302
303    // For the def, it should be the only def of that register.
304    if (MO.isDef() && (llvm::next(MRI.def_begin(Reg)) != MRI.def_end() ||
305                       MRI.isLiveIn(Reg)))
306      return false;
307
308    // Don't allow any virtual-register uses. Rematting an instruction with
309    // virtual register uses would length the live ranges of the uses, which
310    // is not necessarily a good idea, certainly not "trivial".
311    if (MO.isUse())
312      return false;
313  }
314
315  // Everything checked out.
316  return true;
317}
318
319// Default implementation of CreateTargetPostRAHazardRecognizer.
320ScheduleHazardRecognizer *TargetInstrInfoImpl::
321CreateTargetPostRAHazardRecognizer(const InstrItineraryData &II) const {
322  return (ScheduleHazardRecognizer *)new PostRAHazardRecognizer(II);
323}
324