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Searched refs:Rm (Results 1 - 9 of 9) sorted by relevance

/external/llvm/lib/Target/ARM/Disassembler/
H A D	ARMDisassembler.cpp	1023 unsigned Rm = fieldFromInstruction32(Val, 0, 4); local 1028 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1060 unsigned Rm = fieldFromInstruction32(Val, 0, 4); local 1065 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1332 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local 1394 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1434 unsigned Rm = fieldFromInstruction32(Val, 0, 4); local 1457 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1476 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local 1568 Inst.addOperand(MCOperand::CreateImm(U \| (imm << 4) \| Rm)); 1831 unsigned Rm = fieldFromInstruction32(Insn, 8, 4); local 1932 unsigned Rm = fieldFromInstruction32(Val, 0, 4); local 1954 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local 2203 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local 2451 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local 2490 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local 2526 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local 2561 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local 2658 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local 2703 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local 2773 unsigned Rm = fieldFromInstruction32(Val, 3, 3); local 2820 unsigned Rm = fieldFromInstruction32(Val, 2, 4); local 3040 unsigned Rm = fieldFromInstruction16(Insn, 3, 4); local 3065 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local 3099 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local 3308 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local 3381 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local 3440 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local 3498 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local 3565 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local 3629 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local 3699 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local 3763 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local 3837 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local 3902 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local 3928 unsigned Rm = fieldFromInstruction32(Insn, 0, 4); local [all...]
/external/qemu/
H A D	trace.c	894 int Rm = (insn & 15); local 905 result += 2 + _interlock_use(Rm) + _interlock_use(Rs); 909 int Rm = (insn & 15); local 920 result += 3 + _interlock_use(Rm) + _interlock_use(Rs); 924 int Rm = (insn & 15); local 927 result = 2 + _interlock_use(Rm); 932 int Rm = (insn & 15); local 936 result += _interlock_use(Rn) + _interlock_use(Rm); 955 int Rm = (insn & 15); local 959 result += _interlock_use(Rn) + _interlock_use(Rm); 988 int Rm = (insn & 15); local 997 int Rm = (insn & 15); local 1005 int Rm = (insn & 15); local 1017 int Rm = (insn & 15); local 1059 int Rm = (insn & 15); local 1192 int Rm = (insn >> 3) & 7; local 1203 int Rm = (insn >> 6) & 7; local 1228 int Rm = (insn >> 3) & 7; local 1240 int Rm = ((insn >> 3) & 15); local 1249 int Rm = (insn >> 3) & 15; local 1271 int Rm = (insn >> 6) & 7; local [all...]
H A D	i386-dis.c	`349 #define Rm { OP_R, m_mode } macro 1058 { "movZ", { Rm, Cm } }, 1059 { "movZ", { Rm, Dm } }, 1060 { "movZ", { Cm, Rm } }, 1061 { "movZ", { Dm, Rm } },`
H A D	arm-dis.c	`1228 %S print a possibly-shifted Rm 3465 unsigned int Rm = (i8 & 0x0f); local 3467 func (stream, ", %s", arm_regnames[Rm]);`
/external/qemu/distrib/sdl-1.2.12/src/video/
H A D	SDL_pixels.c	`143 int Rm=0,Gm=0,Bm=0; local 152 Rm\|=1<<i; 155 fprintf(stderr,"Rw=%d Rm=0x%02X\n",Rw,Rm); 189 r=(r<<format->Rloss)\|((r*Rm)>>Rw);`
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A D	ARMMCCodeEmitter.cpp	`687 // [Rn, Rm] 688 // {5-3} = Rm 693 unsigned Rm = getARMRegisterNumbering(MO2.getReg()); local 694 return (Rm << 3) \| Rn; 897 unsigned Rm = getARMRegisterNumbering(MO1.getReg()); local 906 // {3-0} = Rm 910 uint32_t Binary = Rm; 923 // {13} 1 == imm12, 0 == Rm 925 // {11-0} imm12/Rm 936 // {13} 1 == imm12, 0 == Rm [all...]`
/external/v8/src/arm/
H A D	disasm-arm.cc	`336 } else if (format[1] == 'm') { // 'rm: Rm register 684 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the 695 // The order of registers is: <RdLo>, <RdHi>, <Rm>, <Rs>`
/external/valgrind/main/none/tests/arm/
H A D	vfp.stdout.exp	922 vstr d9, [r6, #+4] :: Dd 0xa0a0a0a0 0xa0a0a0a0 (int) (Rm + shift) 0xa0a0a0a0 923 vstr d16, [r9, #-4] :: Dd 0xb1b1b1b1 0xb1b1b1b1 (int) (Rm + shift) 0xb1b1b1b1 924 vstr d30, [r12] :: Dd 0xc2c2c2c2 0xc2c2c2c2 (int) (Rm + shift) 0xc2c2c2c2 925 vstr d22, [r9, #+8] :: Dd 0xd4d4d4d4 0xd4d4d4d4 (int) (Rm + shift) 0xd4d4d4d4 926 vstr d29, [r2, #-8] :: Dd 0x00000000 0x00000000 (int) (Rm + shift) 0x0000 927 vstr d8, [r8, #+8] :: Dd 0x11111111 0x11111111 (int) (Rm + shift) 0x11111111 928 vstr d11, [r12, #-4] :: Dd 0x22222222 0x22222222 (int) (Rm + shift) 0x22222222 929 vstr d18, [r3] :: Dd 0x33333333 0x33333333 (int) (Rm + shift) 0x33333333 930 vstr d5, [r10, #+8] :: Dd 0x99999999 0x99999999 (int) (Rm + shift) 0x99999999 931 vstr d17, [r10] :: Dd 0x77777777 0x77777777 (int) (Rm [all...]
H A D	v6intThumb.stdout.exp	`567 ADDS-16 Rd, Rn, Rm 620 SUBS-16 Rd, Rn, Rm 757 LSLS-16 Rd, Rm, imm5 782 LSRS-16 Rd, Rm, imm5 807 ASRS-16 Rd, Rm, imm5 2094 ADD{S}.W Rd, Rn, Rm, {shift} 3343 SUBB{S}.W Rd, Rn, Rm, {shift} 4592 RSB{S}.W Rd, Rn, Rm, {shift} 5841 ADC{S}.W Rd, Rn, Rm, {shift} 7090 SBC{S}.W Rd, Rn, Rm, {shif [all...]`

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