ARMMCCodeEmitter.cpp revision 54fea632b161f98e96ec7275922e35102bcecc5d 
1//===-- ARM/ARMMCCodeEmitter.cpp - Convert ARM code to machine code -------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the ARMMCCodeEmitter class.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "arm-emitter"
15#include "ARM.h"
16#include "ARMAddressingModes.h"
17#include "ARMFixupKinds.h"
18#include "ARMInstrInfo.h"
19#include "llvm/MC/MCCodeEmitter.h"
20#include "llvm/MC/MCExpr.h"
21#include "llvm/MC/MCInst.h"
22#include "llvm/ADT/Statistic.h"
23#include "llvm/Support/raw_ostream.h"
24using namespace llvm;
25
26STATISTIC(MCNumEmitted, "Number of MC instructions emitted.");
27STATISTIC(MCNumCPRelocations, "Number of constant pool relocations created.");
28
29namespace {
30class ARMMCCodeEmitter : public MCCodeEmitter {
31  ARMMCCodeEmitter(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
32  void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
33  const TargetMachine &TM;
34  const TargetInstrInfo &TII;
35  MCContext &Ctx;
36
37public:
38  ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx)
39    : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
40  }
41
42  ~ARMMCCodeEmitter() {}
43
44  unsigned getNumFixupKinds() const { return 2; }
45
46  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
47    const static MCFixupKindInfo Infos[] = {
48      { "fixup_arm_pcrel_12", 2, 12, MCFixupKindInfo::FKF_IsPCRel },
49      { "fixup_arm_vfp_pcrel_12", 3, 8, MCFixupKindInfo::FKF_IsPCRel },
50    };
51
52    if (Kind < FirstTargetFixupKind)
53      return MCCodeEmitter::getFixupKindInfo(Kind);
54
55    assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
56           "Invalid kind!");
57    return Infos[Kind - FirstTargetFixupKind];
58  }
59  unsigned getMachineSoImmOpValue(unsigned SoImm) const;
60
61  // getBinaryCodeForInstr - TableGen'erated function for getting the
62  // binary encoding for an instruction.
63  unsigned getBinaryCodeForInstr(const MCInst &MI,
64                                 SmallVectorImpl<MCFixup> &Fixups) const;
65
66  /// getMachineOpValue - Return binary encoding of operand. If the machine
67  /// operand requires relocation, record the relocation and return zero.
68  unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
69                             SmallVectorImpl<MCFixup> &Fixups) const;
70
71  bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
72                              unsigned &Reg, unsigned &Imm,
73                              SmallVectorImpl<MCFixup> &Fixups) const;
74
75  /// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
76  /// operand.
77  uint32_t getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
78                                   SmallVectorImpl<MCFixup> &Fixups) const;
79
80  /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
81  /// operand as needed by load/store instructions.
82  uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
83                               SmallVectorImpl<MCFixup> &Fixups) const;
84
85  /// getAddrMode5OpValue - Return encoding info for 'reg +/- imm8' operand.
86  uint32_t getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
87                               SmallVectorImpl<MCFixup> &Fixups) const;
88
89  /// getCCOutOpValue - Return encoding of the 's' bit.
90  unsigned getCCOutOpValue(const MCInst &MI, unsigned Op,
91                           SmallVectorImpl<MCFixup> &Fixups) const {
92    // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
93    // '1' respectively.
94    return MI.getOperand(Op).getReg() == ARM::CPSR;
95  }
96
97  /// getSOImmOpValue - Return an encoded 12-bit shifted-immediate value.
98  unsigned getSOImmOpValue(const MCInst &MI, unsigned Op,
99                           SmallVectorImpl<MCFixup> &Fixups) const {
100    unsigned SoImm = MI.getOperand(Op).getImm();
101    int SoImmVal = ARM_AM::getSOImmVal(SoImm);
102    assert(SoImmVal != -1 && "Not a valid so_imm value!");
103
104    // Encode rotate_imm.
105    unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
106      << ARMII::SoRotImmShift;
107
108    // Encode immed_8.
109    Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
110    return Binary;
111  }
112
113  /// getSORegOpValue - Return an encoded so_reg shifted register value.
114  unsigned getSORegOpValue(const MCInst &MI, unsigned Op,
115                           SmallVectorImpl<MCFixup> &Fixups) const;
116
117  unsigned getRotImmOpValue(const MCInst &MI, unsigned Op,
118                            SmallVectorImpl<MCFixup> &Fixups) const {
119    switch (MI.getOperand(Op).getImm()) {
120    default: assert (0 && "Not a valid rot_imm value!");
121    case 0:  return 0;
122    case 8:  return 1;
123    case 16: return 2;
124    case 24: return 3;
125    }
126  }
127
128  unsigned getImmMinusOneOpValue(const MCInst &MI, unsigned Op,
129                                 SmallVectorImpl<MCFixup> &Fixups) const {
130    return MI.getOperand(Op).getImm() - 1;
131  }
132
133  unsigned getNEONVcvtImm32OpValue(const MCInst &MI, unsigned Op,
134                                   SmallVectorImpl<MCFixup> &Fixups) const {
135    return 64 - MI.getOperand(Op).getImm();
136  }
137
138  unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
139                                      SmallVectorImpl<MCFixup> &Fixups) const;
140
141  unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op,
142                                  SmallVectorImpl<MCFixup> &Fixups) const;
143  unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
144                                      SmallVectorImpl<MCFixup> &Fixups) const;
145  unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
146                                     SmallVectorImpl<MCFixup> &Fixups) const;
147
148  void EmitByte(unsigned char C, raw_ostream &OS) const {
149    OS << (char)C;
150  }
151
152  void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
153    // Output the constant in little endian byte order.
154    for (unsigned i = 0; i != Size; ++i) {
155      EmitByte(Val & 255, OS);
156      Val >>= 8;
157    }
158  }
159
160  void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
161                         SmallVectorImpl<MCFixup> &Fixups) const;
162};
163
164} // end anonymous namespace
165
166MCCodeEmitter *llvm::createARMMCCodeEmitter(const Target &, TargetMachine &TM,
167                                            MCContext &Ctx) {
168  return new ARMMCCodeEmitter(TM, Ctx);
169}
170
171/// getMachineOpValue - Return binary encoding of operand. If the machine
172/// operand requires relocation, record the relocation and return zero.
173unsigned ARMMCCodeEmitter::
174getMachineOpValue(const MCInst &MI, const MCOperand &MO,
175                  SmallVectorImpl<MCFixup> &Fixups) const {
176  if (MO.isReg()) {
177    unsigned Reg = MO.getReg();
178    unsigned RegNo = getARMRegisterNumbering(Reg);
179
180    // Q registers are encodes as 2x their register number.
181    switch (Reg) {
182    default:
183      return RegNo;
184    case ARM::Q0:  case ARM::Q1:  case ARM::Q2:  case ARM::Q3:
185    case ARM::Q4:  case ARM::Q5:  case ARM::Q6:  case ARM::Q7:
186    case ARM::Q8:  case ARM::Q9:  case ARM::Q10: case ARM::Q11:
187    case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
188      return 2 * RegNo;
189    }
190  } else if (MO.isImm()) {
191    return static_cast<unsigned>(MO.getImm());
192  } else if (MO.isFPImm()) {
193    return static_cast<unsigned>(APFloat(MO.getFPImm())
194                     .bitcastToAPInt().getHiBits(32).getLimitedValue());
195  }
196
197#ifndef NDEBUG
198  errs() << MO;
199#endif
200  llvm_unreachable(0);
201  return 0;
202}
203
204/// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
205bool ARMMCCodeEmitter::
206EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,
207                       unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
208  const MCOperand &MO  = MI.getOperand(OpIdx);
209  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
210
211  Reg = getARMRegisterNumbering(MO.getReg());
212
213  int32_t SImm = MO1.getImm();
214  bool isAdd = true;
215
216  // Special value for #-0
217  if (SImm == INT32_MIN)
218    SImm = 0;
219
220  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
221  if (SImm < 0) {
222    SImm = -SImm;
223    isAdd = false;
224  }
225
226  Imm = SImm;
227  return isAdd;
228}
229
230/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12' operand.
231uint32_t ARMMCCodeEmitter::
232getAddrModeImm12OpValue(const MCInst &MI, unsigned OpIdx,
233                        SmallVectorImpl<MCFixup> &Fixups) const {
234  // {17-13} = reg
235  // {12}    = (U)nsigned (add == '1', sub == '0')
236  // {11-0}  = imm12
237  unsigned Reg, Imm12;
238  bool isAdd = true;
239  // If The first operand isn't a register, we have a label reference.
240  const MCOperand &MO = MI.getOperand(OpIdx);
241  if (!MO.isReg()) {
242    Reg = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
243    Imm12 = 0;
244
245    assert(MO.isExpr() && "Unexpected machine operand type!");
246    const MCExpr *Expr = MO.getExpr();
247    MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_pcrel_12);
248    Fixups.push_back(MCFixup::Create(0, Expr, Kind));
249
250    ++MCNumCPRelocations;
251  } else
252    isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm12, Fixups);
253
254  uint32_t Binary = Imm12 & 0xfff;
255  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
256  if (isAdd)
257    Binary |= (1 << 12);
258  Binary |= (Reg << 13);
259  return Binary;
260}
261
262uint32_t ARMMCCodeEmitter::
263getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
264                    SmallVectorImpl<MCFixup> &Fixups) const {
265  const MCOperand &MO = MI.getOperand(OpIdx);
266  const MCOperand &MO1 = MI.getOperand(OpIdx+1);
267  const MCOperand &MO2 = MI.getOperand(OpIdx+2);
268  unsigned Rn = getARMRegisterNumbering(MO.getReg());
269  unsigned Rm = getARMRegisterNumbering(MO1.getReg());
270  ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
271  unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
272  bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
273  unsigned SBits;
274  // LSL - 00
275  // LSR - 01
276  // ASR - 10
277  // ROR - 11
278  switch (ShOp) {
279  default: llvm_unreachable("Unknown shift opc!");
280  case ARM_AM::lsl: SBits = 0x0; break;
281  case ARM_AM::lsr: SBits = 0x1; break;
282  case ARM_AM::asr: SBits = 0x2; break;
283  case ARM_AM::ror: SBits = 0x3; break;
284  }
285
286  // {16-13} = Rn
287  // {12}    = isAdd
288  // {11-0}  = shifter
289  //  {3-0}  = Rm
290  //  {4}    = 0
291  //  {6-5}  = type
292  //  {11-7} = imm
293  int64_t Binary = Rm;
294  Binary |= Rn << 13;
295  Binary |= SBits << 5;
296  Binary |= ShImm << 7;
297  if (isAdd)
298    Binary |= 1 << 12;
299  return Binary;
300}
301
302/// getAddrMode5OpValue - Return encoding info for 'reg +/- imm12' operand.
303uint32_t ARMMCCodeEmitter::
304getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
305                    SmallVectorImpl<MCFixup> &Fixups) const {
306  // {12-9} = reg
307  // {8}    = (U)nsigned (add == '1', sub == '0')
308  // {7-0}  = imm8
309  unsigned Reg, Imm8;
310  // If The first operand isn't a register, we have a label reference.
311  const MCOperand &MO = MI.getOperand(OpIdx);
312  if (!MO.isReg()) {
313    Reg = getARMRegisterNumbering(ARM::PC);   // Rn is PC.
314    Imm8 = 0;
315
316    assert(MO.isExpr() && "Unexpected machine operand type!");
317    const MCExpr *Expr = MO.getExpr();
318    MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_vfp_pcrel_12);
319    Fixups.push_back(MCFixup::Create(0, Expr, Kind));
320
321    ++MCNumCPRelocations;
322  } else
323    EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm8, Fixups);
324
325  uint32_t Binary = ARM_AM::getAM5Offset(Imm8);
326  // Immediate is always encoded as positive. The 'U' bit controls add vs sub.
327  if (ARM_AM::getAM5Op(Imm8) == ARM_AM::add)
328    Binary |= (1 << 8);
329  Binary |= (Reg << 9);
330  return Binary;
331}
332
333unsigned ARMMCCodeEmitter::
334getSORegOpValue(const MCInst &MI, unsigned OpIdx,
335                SmallVectorImpl<MCFixup> &Fixups) const {
336  // Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
337  // shifted. The second is either Rs, the amount to shift by, or reg0 in which
338  // case the imm contains the amount to shift by.
339  //
340  // {3-0} = Rm.
341  // {4}   = 1 if reg shift, 0 if imm shift
342  // {6-5} = type
343  //    If reg shift:
344  //      {11-8} = Rs
345  //      {7}    = 0
346  //    else (imm shift)
347  //      {11-7} = imm
348
349  const MCOperand &MO  = MI.getOperand(OpIdx);
350  const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
351  const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
352  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
353
354  // Encode Rm.
355  unsigned Binary = getARMRegisterNumbering(MO.getReg());
356
357  // Encode the shift opcode.
358  unsigned SBits = 0;
359  unsigned Rs = MO1.getReg();
360  if (Rs) {
361    // Set shift operand (bit[7:4]).
362    // LSL - 0001
363    // LSR - 0011
364    // ASR - 0101
365    // ROR - 0111
366    // RRX - 0110 and bit[11:8] clear.
367    switch (SOpc) {
368    default: llvm_unreachable("Unknown shift opc!");
369    case ARM_AM::lsl: SBits = 0x1; break;
370    case ARM_AM::lsr: SBits = 0x3; break;
371    case ARM_AM::asr: SBits = 0x5; break;
372    case ARM_AM::ror: SBits = 0x7; break;
373    case ARM_AM::rrx: SBits = 0x6; break;
374    }
375  } else {
376    // Set shift operand (bit[6:4]).
377    // LSL - 000
378    // LSR - 010
379    // ASR - 100
380    // ROR - 110
381    switch (SOpc) {
382    default: llvm_unreachable("Unknown shift opc!");
383    case ARM_AM::lsl: SBits = 0x0; break;
384    case ARM_AM::lsr: SBits = 0x2; break;
385    case ARM_AM::asr: SBits = 0x4; break;
386    case ARM_AM::ror: SBits = 0x6; break;
387    }
388  }
389
390  Binary |= SBits << 4;
391  if (SOpc == ARM_AM::rrx)
392    return Binary;
393
394  // Encode the shift operation Rs or shift_imm (except rrx).
395  if (Rs) {
396    // Encode Rs bit[11:8].
397    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
398    return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
399  }
400
401  // Encode shift_imm bit[11:7].
402  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
403}
404
405unsigned ARMMCCodeEmitter::
406getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
407                               SmallVectorImpl<MCFixup> &Fixups) const {
408  // 10 bits. lower 5 bits are are the lsb of the mask, high five bits are the
409  // msb of the mask.
410  const MCOperand &MO = MI.getOperand(Op);
411  uint32_t v = ~MO.getImm();
412  uint32_t lsb = CountTrailingZeros_32(v);
413  uint32_t msb = (32 - CountLeadingZeros_32 (v)) - 1;
414  assert (v != 0 && lsb < 32 && msb < 32 && "Illegal bitfield mask!");
415  return lsb | (msb << 5);
416}
417
418unsigned ARMMCCodeEmitter::
419getRegisterListOpValue(const MCInst &MI, unsigned Op,
420                       SmallVectorImpl<MCFixup> &Fixups) const {
421  // Convert a list of GPRs into a bitfield (R0 -> bit 0). For each
422  // register in the list, set the corresponding bit.
423  unsigned Binary = 0;
424  for (unsigned i = Op, e = MI.getNumOperands(); i < e; ++i) {
425    unsigned regno = getARMRegisterNumbering(MI.getOperand(i).getReg());
426    Binary |= 1 << regno;
427  }
428  return Binary;
429}
430
431unsigned ARMMCCodeEmitter::
432getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op,
433                           SmallVectorImpl<MCFixup> &Fixups) const {
434  const MCOperand &Reg = MI.getOperand(Op);
435  const MCOperand &Imm = MI.getOperand(Op + 1);
436
437  unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
438  unsigned Align = 0;
439
440  switch (Imm.getImm()) {
441  default: break;
442  case 2:
443  case 4:
444  case 8:  Align = 0x01; break;
445  case 16: Align = 0x02; break;
446  case 32: Align = 0x03; break;
447  }
448
449  return RegNo | (Align << 4);
450}
451
452unsigned ARMMCCodeEmitter::
453getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
454                          SmallVectorImpl<MCFixup> &Fixups) const {
455  const MCOperand &MO = MI.getOperand(Op);
456  if (MO.getReg() == 0) return 0x0D;
457  return MO.getReg();
458}
459
460void ARMMCCodeEmitter::
461EncodeInstruction(const MCInst &MI, raw_ostream &OS,
462                  SmallVectorImpl<MCFixup> &Fixups) const {
463  // Pseudo instructions don't get encoded.
464  const TargetInstrDesc &Desc = TII.get(MI.getOpcode());
465  if ((Desc.TSFlags & ARMII::FormMask) == ARMII::Pseudo)
466    return;
467
468  EmitConstant(getBinaryCodeForInstr(MI, Fixups), 4, OS);
469  ++MCNumEmitted;  // Keep track of the # of mi's emitted.
470}
471
472#include "ARMGenMCCodeEmitter.inc"
473