1//===-- MipsISelLowering.h - Mips DAG Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Mips uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef MipsISELLOWERING_H
16#define MipsISELLOWERING_H
17
18#include "llvm/CodeGen/SelectionDAG.h"
19#include "llvm/Target/TargetLowering.h"
20#include "Mips.h"
21#include "MipsSubtarget.h"
22
23namespace llvm {
24  namespace MipsISD {
25    enum NodeType {
26      // Start the numbering from where ISD NodeType finishes.
27      FIRST_NUMBER = ISD::BUILTIN_OP_END,
28
29      // Jump and link (call)
30      JmpLink,
31
32      // Get the Higher 16 bits from a 32-bit immediate
33      // No relation with Mips Hi register
34      Hi,
35
36      // Get the Lower 16 bits from a 32-bit immediate
37      // No relation with Mips Lo register
38      Lo,
39
40      // Handle gp_rel (small data/bss sections) relocation.
41      GPRel,
42
43      // General Dynamic TLS
44      TlsGd,
45
46      // Local Exec TLS
47      TprelHi,
48      TprelLo,
49
50      // Thread Pointer
51      ThreadPointer,
52
53      // Floating Point Branch Conditional
54      FPBrcond,
55
56      // Floating Point Compare
57      FPCmp,
58
59      // Floating Point Conditional Moves
60      CMovFP_T,
61      CMovFP_F,
62
63      // Floating Point Rounding
64      FPRound,
65
66      // Return
67      Ret,
68
69      // MAdd/Sub nodes
70      MAdd,
71      MAddu,
72      MSub,
73      MSubu,
74
75      // DivRem(u)
76      DivRem,
77      DivRemU,
78
79      BuildPairF64,
80      ExtractElementF64,
81
82      WrapperPIC,
83
84      DynAlloc,
85
86      Sync,
87
88      Ext,
89      Ins
90    };
91  }
92
93  //===--------------------------------------------------------------------===//
94  // TargetLowering Implementation
95  //===--------------------------------------------------------------------===//
96
97  class MipsTargetLowering : public TargetLowering  {
98  public:
99    explicit MipsTargetLowering(MipsTargetMachine &TM);
100
101    virtual bool allowsUnalignedMemoryAccesses (EVT VT) const;
102
103    /// LowerOperation - Provide custom lowering hooks for some operations.
104    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
105
106    /// getTargetNodeName - This method returns the name of a target specific
107    //  DAG node.
108    virtual const char *getTargetNodeName(unsigned Opcode) const;
109
110    /// getSetCCResultType - get the ISD::SETCC result ValueType
111    EVT getSetCCResultType(EVT VT) const;
112
113    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
114  private:
115    // Subtarget Info
116    const MipsSubtarget *Subtarget;
117
118    bool HasMips64, IsN64;
119
120    // Lower Operand helpers
121    SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
122                            CallingConv::ID CallConv, bool isVarArg,
123                            const SmallVectorImpl<ISD::InputArg> &Ins,
124                            DebugLoc dl, SelectionDAG &DAG,
125                            SmallVectorImpl<SDValue> &InVals) const;
126
127    // Lower Operand specifics
128    SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
129    SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
130    SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
131    SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
132    SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
133    SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
134    SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
135    SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
136    SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
137    SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
138    SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
139    SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG& DAG) const;
140    SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
141
142    virtual SDValue
143      LowerFormalArguments(SDValue Chain,
144                           CallingConv::ID CallConv, bool isVarArg,
145                           const SmallVectorImpl<ISD::InputArg> &Ins,
146                           DebugLoc dl, SelectionDAG &DAG,
147                           SmallVectorImpl<SDValue> &InVals) const;
148
149    virtual SDValue
150      LowerCall(SDValue Chain, SDValue Callee,
151                CallingConv::ID CallConv, bool isVarArg,
152                bool &isTailCall,
153                const SmallVectorImpl<ISD::OutputArg> &Outs,
154                const SmallVectorImpl<SDValue> &OutVals,
155                const SmallVectorImpl<ISD::InputArg> &Ins,
156                DebugLoc dl, SelectionDAG &DAG,
157                SmallVectorImpl<SDValue> &InVals) const;
158
159    virtual SDValue
160      LowerReturn(SDValue Chain,
161                  CallingConv::ID CallConv, bool isVarArg,
162                  const SmallVectorImpl<ISD::OutputArg> &Outs,
163                  const SmallVectorImpl<SDValue> &OutVals,
164                  DebugLoc dl, SelectionDAG &DAG) const;
165
166    virtual MachineBasicBlock *
167      EmitInstrWithCustomInserter(MachineInstr *MI,
168                                  MachineBasicBlock *MBB) const;
169
170    // Inline asm support
171    ConstraintType getConstraintType(const std::string &Constraint) const;
172
173    /// Examine constraint string and operand type and determine a weight value.
174    /// The operand object must already have been set up with the operand type.
175    ConstraintWeight getSingleConstraintMatchWeight(
176      AsmOperandInfo &info, const char *constraint) const;
177
178    std::pair<unsigned, const TargetRegisterClass*>
179              getRegForInlineAsmConstraint(const std::string &Constraint,
180              EVT VT) const;
181
182    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
183
184    /// isFPImmLegal - Returns true if the target can instruction select the
185    /// specified FP immediate natively. If false, the legalizer will
186    /// materialize the FP immediate as a load from a constant pool.
187    virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
188
189    MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
190                    unsigned Size, unsigned BinOpcode, bool Nand = false) const;
191    MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
192                    MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode,
193                    bool Nand = false) const;
194    MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
195                                  MachineBasicBlock *BB, unsigned Size) const;
196    MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI,
197                                  MachineBasicBlock *BB, unsigned Size) const;
198  };
199}
200
201#endif // MipsISELLOWERING_H
202