/external/llvm/lib/Target/Mips/ |
H A D | MipsMachineFunction.cpp | 43 const TargetRegisterClass *RC; local 44 RC = ST.isABI_N64() ? 47 return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC);
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/external/llvm/lib/Target/CellSPU/ |
H A D | SPURegisterInfo.h | 54 virtual unsigned getRegPressureLimit( const TargetRegisterClass *RC, argument 95 const TargetRegisterClass *RC,
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H A D | SPUFrameLowering.cpp | 252 const TargetRegisterClass *RC = &SPU::R32CRegClass; local 253 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 254 RC->getAlignment(),
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H A D | SPURegisterInfo.cpp | 347 const TargetRegisterClass *RC, 351 unsigned Reg = RS->FindUnusedReg(RC); 353 Reg = RS->scavengeRegister(RC, II, SPAdj); 345 findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, const TargetRegisterClass *RC, int SPAdj) const argument
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H A D | SPUInstrInfo.cpp | 142 const TargetRegisterClass *RC, 147 if (RC == SPU::GPRCRegisterClass) { 149 } else if (RC == SPU::R64CRegisterClass) { 151 } else if (RC == SPU::R64FPRegisterClass) { 153 } else if (RC == SPU::R32CRegisterClass) { 155 } else if (RC == SPU::R32FPRegisterClass) { 157 } else if (RC == SPU::R16CRegisterClass) { 159 } else if (RC == SPU::R8CRegisterClass) { 161 } else if (RC == SPU::VECREGRegisterClass) { 177 const TargetRegisterClass *RC, 139 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 174 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument [all...] |
/external/llvm/lib/CodeGen/ |
H A D | AllocationOrder.cpp | 29 const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg); local 45 TRI.getRawAllocationOrder(RC, HintPair.first, Hint, 65 ArrayRef<unsigned> O = RCI.getOrder(RC); 72 !RC->contains(Hint) || RCI.isReserved(Hint)))
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H A D | LiveStackAnalysis.cpp | 55 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { argument 61 S2RCMap.insert(std::make_pair(Slot, RC)); 65 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC); 77 const TargetRegisterClass *RC = getIntervalRegClass(Slot); local 78 if (RC) 79 OS << " [" << RC->getName() << "]\n";
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H A D | AggressiveAntiDepBreaker.h | 44 /// RC - The register class 45 const TargetRegisterClass *RC; member in struct:llvm::AggressiveAntiDepState::__anon7330
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H A D | ProcessImplicitDefs.cpp | 280 const TargetRegisterClass* RC = MRI->getRegClass(Reg); local 281 unsigned NewVReg = MRI->createVirtualRegister(RC);
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H A D | VirtRegMap.cpp | 71 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) { argument 72 int SS = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(), 73 RC->getAlignment()); 93 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg); local 94 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
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H A D | CriticalAntiDepBreaker.cpp | 402 const TargetRegisterClass *RC) 404 ArrayRef<unsigned> Order = RegClassInfo.getOrder(RC); 615 const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg] : 0; local 616 assert((AntiDepReg == 0 || RC != NULL) && 618 if (RC == reinterpret_cast<TargetRegisterClass *>(-1)) 632 RC)) { 398 findSuitableFreeRegister(RegRefIter RegRefBegin, RegRefIter RegRefEnd, unsigned AntiDepReg, unsigned LastNewReg, const TargetRegisterClass *RC) argument
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H A D | LocalStackSlotAllocation.cpp | 317 const TargetRegisterClass *RC = TRI->getPointerRegClass(); local 318 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
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H A D | MachineRegisterInfo.cpp | 45 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { argument 46 VRegInfo[Reg].first = RC; 51 const TargetRegisterClass *RC, 54 if (OldRC == RC) 55 return RC; 56 const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC); 50 constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs) argument
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H A D | PHIElimination.cpp | 231 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg); local 232 entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
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H A D | PeepholeOptimizer.cpp | 232 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg); local 244 unsigned NewVR = MRI->createVirtualRegister(RC);
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H A D | RegisterScavenging.cpp | 237 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const { 238 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 250 BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) { argument 252 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 331 unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC, argument 336 TRI->getAllocatableSet(*I->getParent()->getParent(), RC); 350 BitVector Available = getRegsAvailable(RC); 373 if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SRe [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | Thumb1InstrInfo.cpp | 54 const TargetRegisterClass *RC, 56 assert((RC == ARM::tGPRRegisterClass || 60 if (RC == ARM::tGPRRegisterClass || 82 const TargetRegisterClass *RC, 84 assert((RC == ARM::tGPRRegisterClass || 88 if (RC == ARM::tGPRRegisterClass || 52 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 80 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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H A D | Thumb2InstrInfo.cpp | 127 const TargetRegisterClass *RC, 129 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass || 130 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass || 131 RC == ARM::GPRnopcRegisterClass) { 148 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI); 154 const TargetRegisterClass *RC, 156 if (RC == ARM::GPRRegisterClass || RC 125 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 152 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument [all...] |
/external/llvm/lib/Target/ |
H A D | TargetRegisterInfo.cpp | 60 const TargetRegisterClass* RC = *I; local 61 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) && 62 (!BestRC || BestRC->hasSubClass(RC))) 63 BestRC = RC; 73 const TargetRegisterClass *RC, BitVector &R){ 74 ArrayRef<uint16_t> Order = RC->getRawAllocationOrder(MF); 80 const TargetRegisterClass *RC) const { 82 if (RC) { 83 getAllocatableSetForRC(MF, RC, Allocatabl 72 getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R) argument [all...] |
/external/dropbear/libtomcrypt/src/ciphers/ |
H A D | noekeon.c | 33 static const ulong32 RC[] = { variable 129 a ^= RC[i]; \ 141 a ^= RC[16]; 185 a ^= RC[i]; \ 197 a ^= RC[0];
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/external/llvm/lib/Target/MBlaze/ |
H A D | MBlazeInstrInfo.cpp | 95 const TargetRegisterClass *RC, 105 const TargetRegisterClass *RC, 93 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 103 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430InstrInfo.cpp | 37 const TargetRegisterClass *RC, 50 if (RC == &MSP430::GR16RegClass) 54 else if (RC == &MSP430::GR8RegClass) 65 const TargetRegisterClass *RC, 78 if (RC == &MSP430::GR16RegClass) 81 else if (RC == &MSP430::GR8RegClass) 34 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 62 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/llvm/lib/Target/X86/ |
H A D | X86VZeroUpper.cpp | 148 const TargetRegisterClass *RC = X86::VR256RegisterClass; local 149 for (TargetRegisterClass::iterator i = RC->begin(), e = RC->end();
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/external/llvm/utils/TableGen/ |
H A D | FastISelEmitter.cpp | 35 const CodeGenRegisterClass *RC; member in struct:__anon7992::InstructionMemo 249 const CodeGenRegisterClass *RC = 0; 253 RC = &Target.getRegisterClass(OpLeafRec); 255 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec); 260 if (!RC) 266 if (DstRC != RC && !DstRC->hasSubClass(RC)) 269 DstRC = RC; 642 OS << InstNS << Memo.RC->getName() << "RegisterClass"; 734 OS << InstNS << Memo.RC [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 116 const TargetRegisterClass *RC = 0; local 118 RC = TII->getRegClass(II, i+II.getNumDefs(), TRI); 120 UseRC = RC; 121 else if (RC) { 123 TRI->getCommonSubClass(UseRC, RC); 199 const TargetRegisterClass *RC = TII->getRegClass(II, i, TRI); local 218 if (RegRC == RC) { 230 assert(RC && "Isn't a register operand!"); 231 VRBase = MRI->createVirtualRegister(RC); 255 const TargetRegisterClass *RC local [all...] |