Searched refs:v16i8 (Results 1 - 12 of 12) sorted by relevance
| /external/llvm/test/CodeGen/CellSPU/useful-harnesses/ |
| H A D | vecoperations.c | 3 typedef unsigned char v16i8 __attribute__((ext_vector_type(16))); typedef
10 void print_v16i8(const char *str, const v16i8 v) {
13 v16i8 vec;
24 void print_v16i8_hex(const char *str, const v16i8 v) {
27 v16i8 vec;
68 v16i8 v16i8_mpy(v16i8 v1, v16i8 v2) {
72 v16i8 v16i8_add(v16i8 v
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | ValueTypes.h | 62 v16i8 = 16, // 16 x i8 enumerator in enum:llvm::MVT::SimpleValueType
203 case v16i8:
230 case v16i8:
286 case v16i8:
358 if (NumElements == 16) return MVT::v16i8;
501 return (V==MVT::v16i8 || V==MVT::v8i16 || V==MVT::v4i32 ||
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| /external/llvm/lib/VMCore/ |
| H A D | ValueTypes.cpp | 122 case MVT::v16i8: return "v16i8";
171 case MVT::v16i8: return VectorType::get(Type::getInt8Ty(Context), 16);
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 320 // We promote all shuffles to v16i8.
322 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
364 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
376 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
381 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
386 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
577 assert(N->getValueType(0) == MVT::v16i8 &&
615 assert(N->getValueType(0) == MVT::v16i8 &&
651 assert(N->getValueType(0) == MVT::v16i8 &&
663 // splatted with a v16i8 mas
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| /external/llvm/lib/Target/X86/InstPrinter/ |
| H A D | X86InstComments.cpp | 118 DecodeUNPCKHMask(MVT::v16i8, ShuffleMask);
126 DecodeUNPCKHMask(MVT::v16i8, ShuffleMask);
211 DecodeUNPCKLMask(MVT::v16i8, ShuffleMask);
219 DecodeUNPCKLMask(MVT::v16i8, ShuffleMask);
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| /external/llvm/lib/Target/CellSPU/ |
| H A D | SPUISelLowering.cpp | 400 addRegisterClass(MVT::v16i8, SPU::VECREGRegisterClass);
452 setOperationAction(ISD::AND, MVT::v16i8, Custom);
453 setOperationAction(ISD::OR, MVT::v16i8, Custom);
454 setOperationAction(ISD::XOR, MVT::v16i8, Custom);
550 %1 v16i8,ch = load
551 %2 v16i8,ch = rotate %1
682 // Convert the loaded v16i8 vector to the appropriate vector type
1180 case MVT::v16i8:
1234 SDValue ArgVal = DAG.getRegister(VReg, MVT::v16i8);
1331 case MVT::v16i8
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| H A D | SPUISelDAGToDAG.cpp | 589 case MVT::v16i8:
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| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 838 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass);
843 setOperationAction(ISD::ADD, MVT::v16i8, Legal);
848 setOperationAction(ISD::SUB, MVT::v16i8, Legal);
861 setOperationAction(ISD::SETCC, MVT::v16i8, Custom);
865 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
873 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom);
878 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) {
906 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
907 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) {
956 setOperationAction(ISD::VSELECT, MVT::v16i8, Lega
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| H A D | X86FastISel.cpp | 270 case MVT::v16i8:
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| /external/llvm/utils/TableGen/ |
| H A D | CodeGenTarget.cpp | 73 case MVT::v16i8: return "MVT::v16i8";
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1625 case MVT::v16i8: OpcodeIndex = 0; break;
1761 case MVT::v16i8: OpcodeIndex = 0; break;
2091 RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
2830 case MVT::v16i8: Opc = ARM::VZIPq8; break;
2850 case MVT::v16i8: Opc = ARM::VUZPq8; break;
2869 case MVT::v16i8: Opc = ARM::VTRNq8; break;
3347 SDValue RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
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| H A D | ARMISelLowering.cpp | 468 addQRTypeForNEON(MVT::v16i8);
860 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
3710 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
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