| /external/llvm/test/CodeGen/CellSPU/useful-harnesses/ |
| H A D | vecoperations.c | 4 typedef short v8i16 __attribute__((ext_vector_type(16))); typedef
38 void print_v8i16_hex(const char *str, v8i16 v) {
41 v8i16 vec;
143 v8i16 v01 = { 0x1a87, 0x0a14, 0x5014, 0xfff0,
|
| /external/llvm/include/llvm/CodeGen/ |
| H A D | ValueTypes.h | 66 v8i16 = 20, // 8 x i16 enumerator in enum:llvm::MVT::SimpleValueType
207 case v8i16:
233 case v8i16:
287 case v8i16:
364 if (NumElements == 8) return MVT::v8i16;
501 return (V==MVT::v16i8 || V==MVT::v8i16 || V==MVT::v4i32 ||
|
| /external/llvm/lib/VMCore/ |
| H A D | ValueTypes.cpp | 126 case MVT::v8i16: return "v8i16";
175 case MVT::v8i16: return VectorType::get(Type::getInt16Ty(Context), 8);
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| H A D | X86InstComments.cpp | 141 DecodeUNPCKHMask(MVT::v8i16, ShuffleMask);
149 DecodeUNPCKHMask(MVT::v8i16, ShuffleMask);
234 DecodeUNPCKLMask(MVT::v8i16, ShuffleMask);
242 DecodeUNPCKLMask(MVT::v8i16, ShuffleMask);
|
| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 839 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass);
844 setOperationAction(ISD::ADD, MVT::v8i16, Legal);
849 setOperationAction(ISD::SUB, MVT::v8i16, Legal);
852 setOperationAction(ISD::MUL, MVT::v8i16, Legal);
862 setOperationAction(ISD::SETCC, MVT::v8i16, Custom);
866 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
867 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
874 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom);
906 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64.
965 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custo
[all...] |
| H A D | X86FastISel.cpp | 269 case MVT::v8i16:
|
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 375 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
380 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
387 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
1733 case MVT::v8i16:
1956 case MVT::v8i16:
1986 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2133 case MVT::v8i16:
2267 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
3337 case MVT::v8i16:
3407 ArgType==MVT::v8i16 || ArgTyp
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| H A D | SPUISelLowering.cpp | 401 addRegisterClass(MVT::v8i16, SPU::VECREGRegisterClass);
1179 case MVT::v8i16:
1330 case MVT::v8i16:
1703 DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i16, &Ops[0], Ops.size()));
1705 case MVT::v8i16: {
1860 maskVT = MVT::v8i16;
1968 case MVT::v8i16: n_copies = 8; VT = MVT::i16; break;
|
| H A D | SPUISelDAGToDAG.cpp | 182 if (((vecVT == MVT::v8i16) &&
590 case MVT::v8i16:
|
| /external/llvm/utils/TableGen/ |
| H A D | CodeGenTarget.cpp | 77 case MVT::v8i16: return "MVT::v8i16";
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1626 case MVT::v8i16: OpcodeIndex = 1; break;
1762 case MVT::v8i16: OpcodeIndex = 1; break;
1922 case MVT::v8i16: OpcodeIndex = 0; break;
2831 case MVT::v8i16: Opc = ARM::VZIPq16; break;
2851 case MVT::v8i16: Opc = ARM::VUZPq16; break;
2870 case MVT::v8i16: Opc = ARM::VTRNq16; break;
|
| H A D | ARMISelLowering.cpp | 469 addQRTypeForNEON(MVT::v8i16);
525 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
860 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
3715 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
4973 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
4974 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
4988 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
5008 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
5009 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
5023 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N
[all...] |