1/*------------------------------------------------------------------------ 2 * smc9000.h 3 * 4 * Copyright (C) 1998 by Daniel Engström 5 * Copyright (C) 1996 by Erik Stahlman 6 * 7 * This software may be used and distributed according to the terms 8 * of the GNU Public License, incorporated herein by reference. 9 * 10 * This file contains register information and access macros for 11 * the SMC91xxx chipset. 12 * 13 * Information contained in this file was obtained from the SMC91C94 14 * manual from SMC. To get a copy, if you really want one, you can find 15 * information under www.smsc.com in the components division. 16 * ( this thanks to advice from Donald Becker ). 17 * 18 * Authors 19 * Daniel Engström <daniel.engstrom@riksnett.no> 20 * Erik Stahlman <erik@vt.edu> 21 * 22 * History 23 * 96-01-06 Erik Stahlman moved definitions here from main .c 24 * file 25 * 96-01-19 Erik Stahlman polished this up some, and added 26 * better error handling 27 * 98-09-25 Daniel Engström adjusted for Etherboot 28 * 98-09-27 Daniel Engström moved some static strings back to the 29 * main .c file 30 * --------------------------------------------------------------------------*/ 31#ifndef _SMC9000_H_ 32# define _SMC9000_H_ 33 34/* I want some simple types */ 35typedef unsigned char byte; 36typedef unsigned short word; 37typedef unsigned long int dword; 38 39/*--------------------------------------------------------------- 40 * 41 * A description of the SMC registers is probably in order here, 42 * although for details, the SMC datasheet is invaluable. 43 * 44 * Basically, the chip has 4 banks of registers ( 0 to 3 ), which 45 * are accessed by writing a number into the BANK_SELECT register 46 * ( I also use a SMC_SELECT_BANK macro for this ). 47 * 48 * The banks are configured so that for most purposes, bank 2 is all 49 * that is needed for simple run time tasks. 50 * ----------------------------------------------------------------------*/ 51 52/* 53 * Bank Select Register: 54 * 55 * yyyy yyyy 0000 00xx 56 * xx = bank number 57 * yyyy yyyy = 0x33, for identification purposes. 58 */ 59#define BANK_SELECT 14 60 61/* BANK 0 */ 62 63#define TCR 0 /* transmit control register */ 64#define TCR_ENABLE 0x0001 /* if this is 1, we can transmit */ 65#define TCR_FDUPLX 0x0800 /* receive packets sent out */ 66#define TCR_STP_SQET 0x1000 /* stop transmitting if Signal quality error */ 67#define TCR_MON_CNS 0x0400 /* monitors the carrier status */ 68#define TCR_PAD_ENABLE 0x0080 /* pads short packets to 64 bytes */ 69 70#define TCR_CLEAR 0 /* do NOTHING */ 71/* the normal settings for the TCR register : */ 72#define TCR_NORMAL (TCR_ENABLE | TCR_PAD_ENABLE) 73 74 75#define EPH_STATUS 2 76#define ES_LINK_OK 0x4000 /* is the link integrity ok ? */ 77 78#define RCR 4 79#define RCR_SOFTRESET 0x8000 /* resets the chip */ 80#define RCR_STRIP_CRC 0x200 /* strips CRC */ 81#define RCR_ENABLE 0x100 /* IFF this is set, we can receive packets */ 82#define RCR_ALMUL 0x4 /* receive all multicast packets */ 83#define RCR_PROMISC 0x2 /* enable promiscuous mode */ 84 85/* the normal settings for the RCR register : */ 86#define RCR_NORMAL (RCR_STRIP_CRC | RCR_ENABLE) 87#define RCR_CLEAR 0x0 /* set it to a base state */ 88 89#define COUNTER 6 90#define MIR 8 91#define MCR 10 92/* 12 is reserved */ 93 94/* BANK 1 */ 95#define CONFIG 0 96#define CFG_AUI_SELECT 0x100 97#define BASE 2 98#define ADDR0 4 99#define ADDR1 6 100#define ADDR2 8 101#define GENERAL 10 102#define CONTROL 12 103#define CTL_POWERDOWN 0x2000 104#define CTL_LE_ENABLE 0x80 105#define CTL_CR_ENABLE 0x40 106#define CTL_TE_ENABLE 0x0020 107#define CTL_AUTO_RELEASE 0x0800 108#define CTL_EPROM_ACCESS 0x0003 /* high if Eprom is being read */ 109 110/* BANK 2 */ 111#define MMU_CMD 0 112#define MC_BUSY 1 /* only readable bit in the register */ 113#define MC_NOP 0 114#define MC_ALLOC 0x20 /* or with number of 256 byte packets */ 115#define MC_RESET 0x40 116#define MC_REMOVE 0x60 /* remove the current rx packet */ 117#define MC_RELEASE 0x80 /* remove and release the current rx packet */ 118#define MC_FREEPKT 0xA0 /* Release packet in PNR register */ 119#define MC_ENQUEUE 0xC0 /* Enqueue the packet for transmit */ 120 121#define PNR_ARR 2 122#define FIFO_PORTS 4 123 124#define FP_RXEMPTY 0x8000 125#define FP_TXEMPTY 0x80 126 127#define POINTER 6 128#define PTR_READ 0x2000 129#define PTR_RCV 0x8000 130#define PTR_AUTOINC 0x4000 131#define PTR_AUTO_INC 0x0040 132 133#define DATA_1 8 134#define DATA_2 10 135#define INTERRUPT 12 136 137#define INT_MASK 13 138#define IM_RCV_INT 0x1 139#define IM_TX_INT 0x2 140#define IM_TX_EMPTY_INT 0x4 141#define IM_ALLOC_INT 0x8 142#define IM_RX_OVRN_INT 0x10 143#define IM_EPH_INT 0x20 144#define IM_ERCV_INT 0x40 /* not on SMC9192 */ 145 146/* BANK 3 */ 147#define MULTICAST1 0 148#define MULTICAST2 2 149#define MULTICAST3 4 150#define MULTICAST4 6 151#define MGMT 8 152#define REVISION 10 /* ( hi: chip id low: rev # ) */ 153 154 155/* this is NOT on SMC9192 */ 156#define ERCV 12 157 158/* Note that 9194 and 9196 have the smame chip id, 159 * the 9196 will have revisions starting at 6 */ 160#define CHIP_9190 3 161#define CHIP_9194 4 162#define CHIP_9195 5 163#define CHIP_9196 4 164#define CHIP_91100 7 165#define CHIP_91100FD 8 166 167#define REV_9196 6 168 169/* 170 * Transmit status bits 171 */ 172#define TS_SUCCESS 0x0001 173#define TS_LOSTCAR 0x0400 174#define TS_LATCOL 0x0200 175#define TS_16COL 0x0010 176 177/* 178 * Receive status bits 179 */ 180#define RS_ALGNERR 0x8000 181#define RS_BADCRC 0x2000 182#define RS_ODDFRAME 0x1000 183#define RS_TOOLONG 0x0800 184#define RS_TOOSHORT 0x0400 185#define RS_MULTICAST 0x0001 186#define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) 187 188 189/*------------------------------------------------------------------------- 190 * I define some macros to make it easier to do somewhat common 191 * or slightly complicated, repeated tasks. 192 --------------------------------------------------------------------------*/ 193 194/* select a register bank, 0 to 3 */ 195 196#define SMC_SELECT_BANK(x, y) { _outw( y, x + BANK_SELECT ); } 197 198/* define a small delay for the reset */ 199#define SMC_DELAY(x) { inw( x + RCR );\ 200 inw( x + RCR );\ 201 inw( x + RCR ); } 202 203 204#endif /* _SMC_9000_H_ */ 205 206