ARMAsmBackend.cpp revision 256ba4f42a16da2b3ffc757aa7bf191890765580
1//===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#include "MCTargetDesc/ARMMCTargetDesc.h" 11#include "MCTargetDesc/ARMBaseInfo.h" 12#include "MCTargetDesc/ARMFixupKinds.h" 13#include "MCTargetDesc/ARMAddressingModes.h" 14#include "llvm/ADT/Twine.h" 15#include "llvm/MC/MCAssembler.h" 16#include "llvm/MC/MCDirectives.h" 17#include "llvm/MC/MCELFObjectWriter.h" 18#include "llvm/MC/MCExpr.h" 19#include "llvm/MC/MCMachObjectWriter.h" 20#include "llvm/MC/MCObjectWriter.h" 21#include "llvm/MC/MCSectionELF.h" 22#include "llvm/MC/MCSectionMachO.h" 23#include "llvm/MC/MCAsmBackend.h" 24#include "llvm/MC/MCSubtargetInfo.h" 25#include "llvm/MC/MCValue.h" 26#include "llvm/Object/MachOFormat.h" 27#include "llvm/Support/ELF.h" 28#include "llvm/Support/ErrorHandling.h" 29#include "llvm/Support/raw_ostream.h" 30using namespace llvm; 31 32namespace { 33class ARMELFObjectWriter : public MCELFObjectTargetWriter { 34public: 35 ARMELFObjectWriter(uint8_t OSABI) 36 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM, 37 /*HasRelocationAddend*/ false) {} 38}; 39 40class ARMAsmBackend : public MCAsmBackend { 41 const MCSubtargetInfo* STI; 42 bool isThumbMode; // Currently emitting Thumb code. 43public: 44 ARMAsmBackend(const Target &T, const StringRef TT) 45 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")), 46 isThumbMode(TT.startswith("thumb")) {} 47 48 ~ARMAsmBackend() { 49 delete STI; 50 } 51 52 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; } 53 54 bool hasNOP() const { 55 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0; 56 } 57 58 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { 59 const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = { 60// This table *must* be in the order that the fixup_* kinds are defined in 61// ARMFixupKinds.h. 62// 63// Name Offset (bits) Size (bits) Flags 64{ "fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 65{ "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 66 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 67{ "fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 68{ "fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 69{ "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 70 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 71{ "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel | 72 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 73{ "fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 74{ "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 75 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 76{ "fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 77{ "fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 78{ "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 79{ "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 80{ "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 81{ "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 82{ "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 83{ "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 84{ "fixup_arm_thumb_cp", 0, 8, MCFixupKindInfo::FKF_IsPCRel }, 85{ "fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel }, 86// movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19. 87{ "fixup_arm_movt_hi16", 0, 20, 0 }, 88{ "fixup_arm_movw_lo16", 0, 20, 0 }, 89{ "fixup_t2_movt_hi16", 0, 20, 0 }, 90{ "fixup_t2_movw_lo16", 0, 20, 0 }, 91{ "fixup_arm_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 92{ "fixup_arm_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 93{ "fixup_t2_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 94{ "fixup_t2_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 95 }; 96 97 if (Kind < FirstTargetFixupKind) 98 return MCAsmBackend::getFixupKindInfo(Kind); 99 100 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 101 "Invalid kind!"); 102 return Infos[Kind - FirstTargetFixupKind]; 103 } 104 105 /// processFixupValue - Target hook to process the literal value of a fixup 106 /// if necessary. 107 void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout, 108 const MCFixup &Fixup, const MCFragment *DF, 109 MCValue &Target, uint64_t &Value) { 110 // Some fixups to thumb function symbols need the low bit (thumb bit) 111 // twiddled. 112 if ((unsigned)Fixup.getKind() != ARM::fixup_arm_ldst_pcrel_12 && 113 (unsigned)Fixup.getKind() != ARM::fixup_t2_ldst_pcrel_12 && 114 (unsigned)Fixup.getKind() != ARM::fixup_arm_thumb_cp) { 115 if (const MCSymbolRefExpr *A = Target.getSymA()) { 116 const MCSymbol &Sym = A->getSymbol().AliasedSymbol(); 117 if (Asm.isThumbFunc(&Sym)) 118 Value |= 1; 119 } 120 } 121 } 122 123 bool mayNeedRelaxation(const MCInst &Inst) const; 124 125 bool fixupNeedsRelaxation(const MCFixup &Fixup, 126 uint64_t Value, 127 const MCInstFragment *DF, 128 const MCAsmLayout &Layout) const; 129 130 void relaxInstruction(const MCInst &Inst, MCInst &Res) const; 131 132 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const; 133 134 void handleAssemblerFlag(MCAssemblerFlag Flag) { 135 switch (Flag) { 136 default: break; 137 case MCAF_Code16: 138 setIsThumb(true); 139 break; 140 case MCAF_Code32: 141 setIsThumb(false); 142 break; 143 } 144 } 145 146 unsigned getPointerSize() const { return 4; } 147 bool isThumb() const { return isThumbMode; } 148 void setIsThumb(bool it) { isThumbMode = it; } 149}; 150} // end anonymous namespace 151 152static unsigned getRelaxedOpcode(unsigned Op) { 153 switch (Op) { 154 default: return Op; 155 case ARM::tBcc: return ARM::t2Bcc; 156 case ARM::tLDRpciASM: return ARM::t2LDRpci; 157 } 158} 159 160bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const { 161 if (getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode()) 162 return true; 163 return false; 164} 165 166bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, 167 uint64_t Value, 168 const MCInstFragment *DF, 169 const MCAsmLayout &Layout) const { 170 switch (Fixup.getKind()) { 171 default: assert(0 && "Unexpected fixup kind in fixupNeedsRelaxation()!"); 172 case ARM::fixup_arm_thumb_bcc: { 173 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the 174 // low bit being an implied zero. There's an implied +4 offset for the 175 // branch, so we adjust the other way here to determine what's 176 // encodable. 177 // 178 // Relax if the value is too big for a (signed) i8. 179 int64_t Offset = int64_t(Value) - 4; 180 return Offset > 254 || Offset < -256; 181 } 182 case ARM::fixup_arm_thumb_cp: { 183 int64_t Offset = int64_t(Value) - 4; 184 return Offset > 4095 || Offset < 0; 185 } 186 } 187 llvm_unreachable("Invalid switch/cash!?"); 188} 189 190void ARMAsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const { 191 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode()); 192 193 // Sanity check w/ diagnostic if we get here w/ a bogus instruction. 194 if (RelaxedOp == Inst.getOpcode()) { 195 SmallString<256> Tmp; 196 raw_svector_ostream OS(Tmp); 197 Inst.dump_pretty(OS); 198 OS << "\n"; 199 report_fatal_error("unexpected instruction to relax: " + OS.str()); 200 } 201 202 // The instructions we're relaxing have (so far) the same operands. 203 // We just need to update to the proper opcode. 204 Res = Inst; 205 Res.setOpcode(RelaxedOp); 206} 207 208bool ARMAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { 209 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8 210 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP 211 const uint32_t ARMv4_NopEncoding = 0xe1a0000; // using MOV r0,r0 212 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP 213 if (isThumb()) { 214 const uint16_t nopEncoding = hasNOP() ? Thumb2_16bitNopEncoding 215 : Thumb1_16bitNopEncoding; 216 uint64_t NumNops = Count / 2; 217 for (uint64_t i = 0; i != NumNops; ++i) 218 OW->Write16(nopEncoding); 219 if (Count & 1) 220 OW->Write8(0); 221 return true; 222 } 223 // ARM mode 224 const uint32_t nopEncoding = hasNOP() ? ARMv6T2_NopEncoding 225 : ARMv4_NopEncoding; 226 uint64_t NumNops = Count / 4; 227 for (uint64_t i = 0; i != NumNops; ++i) 228 OW->Write32(nopEncoding); 229 // FIXME: should this function return false when unable to write exactly 230 // 'Count' bytes with NOP encodings? 231 switch (Count % 4) { 232 default: break; // No leftover bytes to write 233 case 1: OW->Write8(0); break; 234 case 2: OW->Write16(0); break; 235 case 3: OW->Write16(0); OW->Write8(0xa0); break; 236 } 237 238 return true; 239} 240 241static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { 242 switch (Kind) { 243 default: 244 llvm_unreachable("Unknown fixup kind!"); 245 case FK_Data_1: 246 case FK_Data_2: 247 case FK_Data_4: 248 return Value; 249 case ARM::fixup_arm_movt_hi16: 250 Value >>= 16; 251 // Fallthrough 252 case ARM::fixup_arm_movw_lo16: 253 case ARM::fixup_arm_movt_hi16_pcrel: 254 case ARM::fixup_arm_movw_lo16_pcrel: { 255 unsigned Hi4 = (Value & 0xF000) >> 12; 256 unsigned Lo12 = Value & 0x0FFF; 257 // inst{19-16} = Hi4; 258 // inst{11-0} = Lo12; 259 Value = (Hi4 << 16) | (Lo12); 260 return Value; 261 } 262 case ARM::fixup_t2_movt_hi16: 263 Value >>= 16; 264 // Fallthrough 265 case ARM::fixup_t2_movw_lo16: 266 case ARM::fixup_t2_movt_hi16_pcrel: //FIXME: Shouldn't this be shifted like 267 // the other hi16 fixup? 268 case ARM::fixup_t2_movw_lo16_pcrel: { 269 unsigned Hi4 = (Value & 0xF000) >> 12; 270 unsigned i = (Value & 0x800) >> 11; 271 unsigned Mid3 = (Value & 0x700) >> 8; 272 unsigned Lo8 = Value & 0x0FF; 273 // inst{19-16} = Hi4; 274 // inst{26} = i; 275 // inst{14-12} = Mid3; 276 // inst{7-0} = Lo8; 277 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8); 278 uint64_t swapped = (Value & 0xFFFF0000) >> 16; 279 swapped |= (Value & 0x0000FFFF) << 16; 280 return swapped; 281 } 282 case ARM::fixup_arm_ldst_pcrel_12: 283 // ARM PC-relative values are offset by 8. 284 Value -= 4; 285 // FALLTHROUGH 286 case ARM::fixup_t2_ldst_pcrel_12: { 287 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 288 Value -= 4; 289 bool isAdd = true; 290 if ((int64_t)Value < 0) { 291 Value = -Value; 292 isAdd = false; 293 } 294 assert ((Value < 4096) && "Out of range pc-relative fixup value!"); 295 Value |= isAdd << 23; 296 297 // Same addressing mode as fixup_arm_pcrel_10, 298 // but with 16-bit halfwords swapped. 299 if (Kind == ARM::fixup_t2_ldst_pcrel_12) { 300 uint64_t swapped = (Value & 0xFFFF0000) >> 16; 301 swapped |= (Value & 0x0000FFFF) << 16; 302 return swapped; 303 } 304 305 return Value; 306 } 307 case ARM::fixup_thumb_adr_pcrel_10: 308 return ((Value - 4) >> 2) & 0xff; 309 case ARM::fixup_arm_adr_pcrel_12: { 310 // ARM PC-relative values are offset by 8. 311 Value -= 8; 312 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100 313 if ((int64_t)Value < 0) { 314 Value = -Value; 315 opc = 2; // 0b0010 316 } 317 assert(ARM_AM::getSOImmVal(Value) != -1 && 318 "Out of range pc-relative fixup value!"); 319 // Encode the immediate and shift the opcode into place. 320 return ARM_AM::getSOImmVal(Value) | (opc << 21); 321 } 322 323 case ARM::fixup_t2_adr_pcrel_12: { 324 Value -= 4; 325 unsigned opc = 0; 326 if ((int64_t)Value < 0) { 327 Value = -Value; 328 opc = 5; 329 } 330 331 uint32_t out = (opc << 21); 332 out |= (Value & 0x800) << 15; 333 out |= (Value & 0x700) << 4; 334 out |= (Value & 0x0FF); 335 336 uint64_t swapped = (out & 0xFFFF0000) >> 16; 337 swapped |= (out & 0x0000FFFF) << 16; 338 return swapped; 339 } 340 341 case ARM::fixup_arm_condbranch: 342 case ARM::fixup_arm_uncondbranch: 343 // These values don't encode the low two bits since they're always zero. 344 // Offset by 8 just as above. 345 return 0xffffff & ((Value - 8) >> 2); 346 case ARM::fixup_t2_uncondbranch: { 347 Value = Value - 4; 348 Value >>= 1; // Low bit is not encoded. 349 350 uint32_t out = 0; 351 bool I = Value & 0x800000; 352 bool J1 = Value & 0x400000; 353 bool J2 = Value & 0x200000; 354 J1 ^= I; 355 J2 ^= I; 356 357 out |= I << 26; // S bit 358 out |= !J1 << 13; // J1 bit 359 out |= !J2 << 11; // J2 bit 360 out |= (Value & 0x1FF800) << 5; // imm6 field 361 out |= (Value & 0x0007FF); // imm11 field 362 363 uint64_t swapped = (out & 0xFFFF0000) >> 16; 364 swapped |= (out & 0x0000FFFF) << 16; 365 return swapped; 366 } 367 case ARM::fixup_t2_condbranch: { 368 Value = Value - 4; 369 Value >>= 1; // Low bit is not encoded. 370 371 uint64_t out = 0; 372 out |= (Value & 0x80000) << 7; // S bit 373 out |= (Value & 0x40000) >> 7; // J2 bit 374 out |= (Value & 0x20000) >> 4; // J1 bit 375 out |= (Value & 0x1F800) << 5; // imm6 field 376 out |= (Value & 0x007FF); // imm11 field 377 378 uint32_t swapped = (out & 0xFFFF0000) >> 16; 379 swapped |= (out & 0x0000FFFF) << 16; 380 return swapped; 381 } 382 case ARM::fixup_arm_thumb_bl: { 383 // The value doesn't encode the low bit (always zero) and is offset by 384 // four. The value is encoded into disjoint bit positions in the destination 385 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit 386 // 387 // BL: xxxxxSIIIIIIIIII xxxxxIIIIIIIIIII 388 // 389 // Note that the halfwords are stored high first, low second; so we need 390 // to transpose the fixup value here to map properly. 391 unsigned isNeg = (int64_t(Value - 4) < 0) ? 1 : 0; 392 uint32_t Binary = 0; 393 Value = 0x3fffff & ((Value - 4) >> 1); 394 Binary = (Value & 0x7ff) << 16; // Low imm11 value. 395 Binary |= (Value & 0x1ffc00) >> 11; // High imm10 value. 396 Binary |= isNeg << 10; // Sign bit. 397 return Binary; 398 } 399 case ARM::fixup_arm_thumb_blx: { 400 // The value doesn't encode the low two bits (always zero) and is offset by 401 // four (see fixup_arm_thumb_cp). The value is encoded into disjoint bit 402 // positions in the destination opcode. x = unchanged, I = immediate value 403 // bit, S = sign extension bit, 0 = zero. 404 // 405 // BLX: xxxxxSIIIIIIIIII xxxxxIIIIIIIIII0 406 // 407 // Note that the halfwords are stored high first, low second; so we need 408 // to transpose the fixup value here to map properly. 409 unsigned isNeg = (int64_t(Value-4) < 0) ? 1 : 0; 410 uint32_t Binary = 0; 411 Value = 0xfffff & ((Value - 2) >> 2); 412 Binary = (Value & 0x3ff) << 17; // Low imm10L value. 413 Binary |= (Value & 0xffc00) >> 10; // High imm10H value. 414 Binary |= isNeg << 10; // Sign bit. 415 return Binary; 416 } 417 case ARM::fixup_arm_thumb_cp: 418 // Offset by 4, and don't encode the low two bits. Two bytes of that 419 // 'off by 4' is implicitly handled by the half-word ordering of the 420 // Thumb encoding, so we only need to adjust by 2 here. 421 return ((Value - 2) >> 2) & 0xff; 422 case ARM::fixup_arm_thumb_cb: { 423 // Offset by 4 and don't encode the lower bit, which is always 0. 424 uint32_t Binary = (Value - 4) >> 1; 425 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3); 426 } 427 case ARM::fixup_arm_thumb_br: 428 // Offset by 4 and don't encode the lower bit, which is always 0. 429 return ((Value - 4) >> 1) & 0x7ff; 430 case ARM::fixup_arm_thumb_bcc: 431 // Offset by 4 and don't encode the lower bit, which is always 0. 432 return ((Value - 4) >> 1) & 0xff; 433 case ARM::fixup_arm_pcrel_10_unscaled: { 434 Value = Value - 8; // ARM fixups offset by an additional word and don't 435 // need to adjust for the half-word ordering. 436 bool isAdd = true; 437 if ((int64_t)Value < 0) { 438 Value = -Value; 439 isAdd = false; 440 } 441 assert ((Value < 256) && "Out of range pc-relative fixup value!"); 442 return Value | (isAdd << 23); 443 } 444 case ARM::fixup_arm_pcrel_10: 445 Value = Value - 4; // ARM fixups offset by an additional word and don't 446 // need to adjust for the half-word ordering. 447 // Fall through. 448 case ARM::fixup_t2_pcrel_10: { 449 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 450 Value = Value - 4; 451 bool isAdd = true; 452 if ((int64_t)Value < 0) { 453 Value = -Value; 454 isAdd = false; 455 } 456 // These values don't encode the low two bits since they're always zero. 457 Value >>= 2; 458 assert ((Value < 256) && "Out of range pc-relative fixup value!"); 459 Value |= isAdd << 23; 460 461 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords 462 // swapped. 463 if (Kind == ARM::fixup_t2_pcrel_10) { 464 uint32_t swapped = (Value & 0xFFFF0000) >> 16; 465 swapped |= (Value & 0x0000FFFF) << 16; 466 return swapped; 467 } 468 469 return Value; 470 } 471 } 472} 473 474namespace { 475 476// FIXME: This should be in a separate file. 477// ELF is an ELF of course... 478class ELFARMAsmBackend : public ARMAsmBackend { 479public: 480 uint8_t OSABI; 481 ELFARMAsmBackend(const Target &T, const StringRef TT, 482 uint8_t _OSABI) 483 : ARMAsmBackend(T, TT), OSABI(_OSABI) { } 484 485 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 486 uint64_t Value) const; 487 488 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 489 return createARMELFObjectWriter(OS, OSABI); 490 } 491}; 492 493// FIXME: Raise this to share code between Darwin and ELF. 494void ELFARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data, 495 unsigned DataSize, uint64_t Value) const { 496 unsigned NumBytes = 4; // FIXME: 2 for Thumb 497 Value = adjustFixupValue(Fixup.getKind(), Value); 498 if (!Value) return; // Doesn't change encoding. 499 500 unsigned Offset = Fixup.getOffset(); 501 502 // For each byte of the fragment that the fixup touches, mask in the bits from 503 // the fixup value. The Value has been "split up" into the appropriate 504 // bitfields above. 505 for (unsigned i = 0; i != NumBytes; ++i) 506 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff); 507} 508 509// FIXME: This should be in a separate file. 510class DarwinARMAsmBackend : public ARMAsmBackend { 511public: 512 const object::mach::CPUSubtypeARM Subtype; 513 DarwinARMAsmBackend(const Target &T, const StringRef TT, 514 object::mach::CPUSubtypeARM st) 515 : ARMAsmBackend(T, TT), Subtype(st) { } 516 517 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 518 return createARMMachObjectWriter(OS, /*Is64Bit=*/false, 519 object::mach::CTM_ARM, 520 Subtype); 521 } 522 523 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 524 uint64_t Value) const; 525 526 virtual bool doesSectionRequireSymbols(const MCSection &Section) const { 527 return false; 528 } 529}; 530 531/// getFixupKindNumBytes - The number of bytes the fixup may change. 532static unsigned getFixupKindNumBytes(unsigned Kind) { 533 switch (Kind) { 534 default: 535 llvm_unreachable("Unknown fixup kind!"); 536 537 case FK_Data_1: 538 case ARM::fixup_arm_thumb_bcc: 539 case ARM::fixup_arm_thumb_cp: 540 case ARM::fixup_thumb_adr_pcrel_10: 541 return 1; 542 543 case FK_Data_2: 544 case ARM::fixup_arm_thumb_br: 545 case ARM::fixup_arm_thumb_cb: 546 return 2; 547 548 case ARM::fixup_arm_pcrel_10_unscaled: 549 case ARM::fixup_arm_ldst_pcrel_12: 550 case ARM::fixup_arm_pcrel_10: 551 case ARM::fixup_arm_adr_pcrel_12: 552 case ARM::fixup_arm_condbranch: 553 case ARM::fixup_arm_uncondbranch: 554 return 3; 555 556 case FK_Data_4: 557 case ARM::fixup_t2_ldst_pcrel_12: 558 case ARM::fixup_t2_condbranch: 559 case ARM::fixup_t2_uncondbranch: 560 case ARM::fixup_t2_pcrel_10: 561 case ARM::fixup_t2_adr_pcrel_12: 562 case ARM::fixup_arm_thumb_bl: 563 case ARM::fixup_arm_thumb_blx: 564 case ARM::fixup_arm_movt_hi16: 565 case ARM::fixup_arm_movw_lo16: 566 case ARM::fixup_arm_movt_hi16_pcrel: 567 case ARM::fixup_arm_movw_lo16_pcrel: 568 case ARM::fixup_t2_movt_hi16: 569 case ARM::fixup_t2_movw_lo16: 570 case ARM::fixup_t2_movt_hi16_pcrel: 571 case ARM::fixup_t2_movw_lo16_pcrel: 572 return 4; 573 } 574} 575 576void DarwinARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data, 577 unsigned DataSize, uint64_t Value) const { 578 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); 579 Value = adjustFixupValue(Fixup.getKind(), Value); 580 if (!Value) return; // Doesn't change encoding. 581 582 unsigned Offset = Fixup.getOffset(); 583 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!"); 584 585 // For each byte of the fragment that the fixup touches, mask in the 586 // bits from the fixup value. 587 for (unsigned i = 0; i != NumBytes; ++i) 588 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff); 589} 590 591} // end anonymous namespace 592 593MCAsmBackend *llvm::createARMAsmBackend(const Target &T, StringRef TT) { 594 Triple TheTriple(TT); 595 596 if (TheTriple.isOSDarwin()) { 597 if (TheTriple.getArchName() == "armv4t" || 598 TheTriple.getArchName() == "thumbv4t") 599 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V4T); 600 else if (TheTriple.getArchName() == "armv5e" || 601 TheTriple.getArchName() == "thumbv5e") 602 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V5TEJ); 603 else if (TheTriple.getArchName() == "armv6" || 604 TheTriple.getArchName() == "thumbv6") 605 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V6); 606 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V7); 607 } 608 609 if (TheTriple.isOSWindows()) 610 assert(0 && "Windows not supported on ARM"); 611 612 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS()); 613 return new ELFARMAsmBackend(T, TT, OSABI); 614} 615